--- /dev/null
+/*\r
+ FreeRTOS.org V4.1.3 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 0\r
+#define configUSE_TICK_HOOK 0\r
+#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 20000000 )\r
+#define configTICK_RATE_HZ ( ( portTickType ) 1000 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 70 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 7000 ) )\r
+#define configMAX_TASK_NAME_LEN ( 10 )\r
+#define configUSE_TRACE_FACILITY 0\r
+#define configUSE_16_BIT_TICKS 0\r
+#define configIDLE_SHOULD_YIELD 0\r
+#define configUSE_CO_ROUTINES 0\r
+\r
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+\r
+#define INCLUDE_vTaskPrioritySet 0\r
+#define INCLUDE_uxTaskPriorityGet 0\r
+#define INCLUDE_vTaskDelete 0\r
+#define INCLUDE_vTaskCleanUpResources 0\r
+#define INCLUDE_vTaskSuspend 0\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+\r
+\r
+\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
--- /dev/null
+#******************************************************************************
+#
+# Makefile - Rules for building the driver library and examples.
+#
+# Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
+#
+# Software License Agreement
+#
+# Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+# exclusively on LMI's Stellaris Family of microcontroller products.
+#
+# The software is owned by LMI and/or its suppliers, and is protected under
+# applicable copyright laws. All rights are reserved. Any use in violation
+# of the foregoing restrictions may subject the user to criminal sanctions
+# under applicable laws, as well as to civil liability for the breach of the
+# terms and conditions of this license.
+#
+# THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+# OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+# LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+# CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+#
+#******************************************************************************
+
+include makedefs
+
+RTOS_SOURCE_DIR=../../Source
+DEMO_SOURCE_DIR=../Common/Minimal
+
+CFLAGS+=-I hw_include -I . -I ${RTOS_SOURCE_DIR}/include -I ${RTOS_SOURCE_DIR}/portable/GCC/ARM_CM3 -I ../Common/include -D GCC_ARMCM3_LM3S102 -D inline=
+
+VPATH=${RTOS_SOURCE_DIR}:${RTOS_SOURCE_DIR}/portable/MemMang:${RTOS_SOURCE_DIR}/portable/GCC/ARM_CM3:${DEMO_SOURCE_DIR}:init:hw_include
+
+OBJS=${COMPILER}/main.o \\r
+ ${COMPILER}/list.o \\r
+ ${COMPILER}/queue.o \\r
+ ${COMPILER}/tasks.o \\r
+ ${COMPILER}/port.o \\r
+ ${COMPILER}/heap_1.o \\r
+ ${COMPILER}/BlockQ.o \\r
+ ${COMPILER}/PollQ.o \\r
+ ${COMPILER}/integer.o \\r
+ ${COMPILER}/semtest.o \\r
+ ${COMPILER}/osram96x16.o\r
+
+INIT_OBJS= ${COMPILER}/startup.o
+
+LIBS= hw_include/libdriver.a
+
+
+#
+# The default rule, which causes init to be built.
+#
+all: ${COMPILER} \
+ ${COMPILER}/RTOSDemo.axf \
+
+#
+# The rule to clean out all the build products
+#
+
+clean:
+ @rm -rf ${COMPILER} ${wildcard *.bin} RTOSDemo.axf
+
+#
+# The rule to create the target directory
+#
+${COMPILER}:
+ @mkdir ${COMPILER}
+
+${COMPILER}/RTOSDemo.axf: ${INIT_OBJS} ${OBJS} ${LIBS}
+SCATTER_RTOSDemo=standalone.ld
+ENTRY_RTOSDemo=ResetISR
+
+#
+#
+# Include the automatically generated dependency files.
+#
+-include ${wildcard ${COMPILER}/*.d} __dummy__
+
+
+
+
+
+
--- /dev/null
+#ifndef DRIVER_LIB_H\r
+#define DRIVER_LIB_H\r
+\r
+#include "DriverLib.h"\r
+#include "hw_adc.h"\r
+#include "hw_comp.h"\r
+#include "hw_flash.h"\r
+#include "hw_gpio.h"\r
+#include "hw_i2c.h"\r
+#include "hw_ints.h"\r
+#include "hw_memmap.h"\r
+#include "hw_nvic.h"\r
+#include "hw_pwm.h"\r
+#include "hw_qei.h"\r
+#include "hw_ssi.h"\r
+#include "hw_sysctl.h"\r
+#include "hw_timer.h"\r
+#include "hw_types.h"\r
+#include "hw_uart.h"\r
+#include "hw_watchdog.h"\r
+#include "osram96x16.h"\r
+#include "adc.h"\r
+#include "comp.h"\r
+#include "cpu.h"\r
+#include "debug.h"\r
+#include "flash.h"\r
+#include "gpio.h"\r
+#include "i2c.h"\r
+#include "interrupt.h"\r
+#include "pwm.h"\r
+#include "qei.h"\r
+#include "ssi.h"\r
+#include "sysctl.h"\r
+#include "systick.h"\r
+#include "timer.h"\r
+#include "uart.h"\r
+#include "watchdog.h"\r
+\r
+#endif\r
--- /dev/null
+IMPORTANT. Read the following LMI Software License Agreement ("Agreement")\r
+completely.\r
+\r
+LUMINARY MICRO SOFTWARE LICENSE AGREEMENT\r
+\r
+ This is a legal agreement between you (either as an individual or as an\r
+authorized representative of your employer) and Luminary Micro, Inc. ("LMI").\r
+It concerns your rights to use this file and any accompanying written materials\r
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+all copies of the Software in your possession or control. Any copies of the\r
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+will continue to be governed by this Agreement. Your prior use will also\r
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+\r
+1. LICENSE GRANT. LMI grants to you, free of charge, the non-exclusive,\r
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+\r
+2. COPYRIGHT. The Software is licensed to you, not sold. LMI owns the\r
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+4. INDEMNITY. You agree to fully defend and indemnify LMI from any and\r
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+related to (1) your use (including your sub-licensee's use, if permitted) of\r
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+\r
+5. HIGH RISK ACTIVITIES. You acknowledge that the Software is not fault\r
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+direct life support machines or weapons systems, in which the failure of\r
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+\r
+6. PRODUCT LABELING. You are not authorized to use any LMI trademarks,\r
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+7. COMPLIANCE WITH LAWS; EXPORT RESTRICTIONS. You must use the Software\r
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+\r
+8. GOVERNMENT USE. Use of the Software and any corresponding\r
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+clause at DFARS 252.227-7013 or subparagraphs (c)(l) and (2) of the Commercial\r
+Computer Software--Restricted Rights at 48 CFR 52.227-19, as applicable.\r
+Manufacturer is Luminary Micro, Inc., 2499 S. Capital of Texas Hwy Ste A-100,\r
+Austin, Texas 78746.\r
+\r
+9. DISCLAIMER OF WARRANTY. TO THE MAXIMUM EXTENT PERMITTED BY LAW, LMI\r
+EXPRESSLY DISCLAIMS ANY WARRANTY FOR THE SOFTWARE. THE SOFTWARE IS PROVIDED\r
+"AS IS", WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING,\r
+WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A\r
+PARTICULAR PURPOSE, OR NON-INFRINGEMENT. YOU ASSUME THE ENTIRE RISK ARISING\r
+OUT OF THE USE OR PERFORMANCE OF THE SOFTWARE, OR ANY SYSTEMS YOU DESIGN USING\r
+THE SOFTWARE (IF ANY). NOTHING IN THIS AGREEMENT MAY BE CONSTRUED AS A\r
+WARRANTY OR REPRESENTATION BY LMI THAT THE SOFTWARE OR ANY DERIVATIVE WORK\r
+DEVELOPED WITH OR INCORPORATING THE SOFTWARE WILL BE FREE FROM INFRINGEMENT OF\r
+THE INTELLECTUAL PROPERTY RIGHTS OF THIRD PARTIES.\r
+\r
+10. LIMITATION OF LIABILITY. IN NO EVENT WILL LMI BE LIABLE, WHETHER IN\r
+CONTRACT, TORT, OR OTHERWISE, FOR ANY INCIDENTAL, SPECIAL, INDIRECT,\r
+CONSEQUENTIAL OR PUNITIVE DAMAGES, INCLUDING, BUT NOT LIMITED TO, DAMAGES FOR\r
+ANY LOSS OF USE, LOSS OF TIME, INCONVENIENCE, COMMERCIAL LOSS, OR LOST PROFITS,\r
+SAVINGS, OR REVENUES TO THE FULL EXTENT SUCH MAY BE DISCLAIMED BY LAW.\r
+\r
+11. CHOICE OF LAW; VENUE; LIMITATIONS. You agree that the statutes and\r
+laws of the United States and the State of Texas, USA, without regard to\r
+conflicts of laws principles, will apply to all matters relating to this\r
+Agreement or the Software, and you agree that any litigation will be subject to\r
+the exclusive jurisdiction of the state or federal courts in Austin, Travis\r
+County, Texas, USA. You agree that regardless of any statute or law to the\r
+contrary, any claim or cause of action arising out of or related to this\r
+Agreement or the Software must be filed within one (1) year after such claim or\r
+cause of action arose or be forever barred.\r
+\r
+12. ENTIRE AGREEMENT. This Agreement constitutes the entire agreement\r
+between you and LMI regarding the subject matter of this Agreement, and\r
+supersedes all prior communications, negotiations, understandings, agreements\r
+or representations, either written or oral, if any. This Agreement may only be\r
+amended in written form, executed by you and LMI.\r
+\r
+13. SEVERABILITY. If any provision of this Agreement is held for any\r
+reason to be invalid or unenforceable, then the remaining provisions of this\r
+Agreement will be unimpaired and, unless a modification or replacement of the\r
+invalid or unenforceable provision is further held to deprive you or LMI of a\r
+material benefit, in which case the Agreement will immediately terminate, the\r
+invalid or unenforceable provision will be replaced with a provision that is\r
+valid and enforceable and that comes closest to the intention underlying the\r
+invalid or unenforceable provision.\r
+\r
+14. NO WAIVER. The waiver by LMI of any breach of any provision of this\r
+Agreement will not operate or be construed as a waiver of any other or a\r
+subsequent breach of the same or a different provision.\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// adc.c - Driver for the ADC.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 991 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \addtogroup adc_api\r
+//! @{\r
+//\r
+//*****************************************************************************\r
+\r
+#include "../hw_adc.h"\r
+#include "../hw_ints.h"\r
+#include "../hw_memmap.h"\r
+#include "../hw_types.h"\r
+#include "adc.h"\r
+#include "debug.h"\r
+#include "interrupt.h"\r
+\r
+//*****************************************************************************\r
+//\r
+// The currently configured software oversampling factor for each of the ADC\r
+// sequencers.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_pucoverssamplefactor) || defined(BUILD_ALL)\r
+unsigned char g_pucOversampleFactor[3];\r
+#else\r
+extern unsigned char g_pucOversampleFactor[3];\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Registers an interrupt handler for an ADC interrupt.\r
+//!\r
+//! \param ulBase is the base address of the ADC module.\r
+//! \param ulSequenceNum is the sample sequence number.\r
+//! \param pfnHandler is a pointer to the function to be called when the\r
+//! ADC sample sequence interrupt occurs.\r
+//!\r
+//! This function sets the handler to be called when a sample sequence\r
+//! interrupt occurs. This will enable the global interrupt in the interrupt\r
+//! controller; the sequence interrupt must be enabled with ADCIntEnable(). It\r
+//! is the interrupt handler's responsibility to clear the interrupt source via\r
+//! ADCIntClear().\r
+//!\r
+//! \sa IntRegister() for important information about registering interrupt\r
+//! handlers.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+ADCIntRegister(unsigned long ulBase, unsigned long ulSequenceNum,\r
+ void (*pfnHandler)(void))\r
+{\r
+ unsigned long ulInt;\r
+\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == ADC_BASE);\r
+ ASSERT(ulSequenceNum < 4);\r
+\r
+ //\r
+ // Determine the interrupt to register based on the sequence number.\r
+ //\r
+ ulInt = INT_ADC0 + ulSequenceNum;\r
+\r
+ //\r
+ // Register the interrupt handler.\r
+ //\r
+ IntRegister(ulInt, pfnHandler);\r
+\r
+ //\r
+ // Enable the timer interrupt.\r
+ //\r
+ IntEnable(ulInt);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Unregisters the interrupt handler for an ADC interrupt.\r
+//!\r
+//! \param ulBase is the base address of the ADC module.\r
+//! \param ulSequenceNum is the sample sequence number.\r
+//!\r
+//! This function unregisters the interrupt handler. This will disable the\r
+//! global interrupt in the interrupt controller; the sequence interrupt must\r
+//! be disabled via ADCIntDisable().\r
+//!\r
+//! \sa IntRegister() for important information about registering interrupt\r
+//! handlers.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+ADCIntUnregister(unsigned long ulBase, unsigned long ulSequenceNum)\r
+{\r
+ unsigned long ulInt;\r
+\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == ADC_BASE);\r
+ ASSERT(ulSequenceNum < 4);\r
+\r
+ //\r
+ // Determine the interrupt to unregister based on the sequence number.\r
+ //\r
+ ulInt = INT_ADC0 + ulSequenceNum;\r
+\r
+ //\r
+ // Disable the interrupt.\r
+ //\r
+ IntDisable(ulInt);\r
+\r
+ //\r
+ // Unregister the interrupt handler.\r
+ //\r
+ IntUnregister(ulInt);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Disables a sample sequence interrupt.\r
+//!\r
+//! \param ulBase is the base address of the ADC module.\r
+//! \param ulSequenceNum is the sample sequence number.\r
+//!\r
+//! This function disables the requested sample sequence interrupt.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+ADCIntDisable(unsigned long ulBase, unsigned long ulSequenceNum)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == ADC_BASE);\r
+ ASSERT(ulSequenceNum < 4);\r
+\r
+ //\r
+ // Disable this sample sequence interrupt.\r
+ //\r
+ HWREG(ulBase + ADC_O_IM) &= ~(1 << ulSequenceNum);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Enables a sample sequence interrupt.\r
+//!\r
+//! \param ulBase is the base address of the ADC module.\r
+//! \param ulSequenceNum is the sample sequence number.\r
+//!\r
+//! This function enables the requested sample sequence interrupt. Any\r
+//! outstanding interrupts are cleared before enabling the sample sequence\r
+//! interrupt.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+ADCIntEnable(unsigned long ulBase, unsigned long ulSequenceNum)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == ADC_BASE);\r
+ ASSERT(ulSequenceNum < 4);\r
+\r
+ //\r
+ // Clear any outstanding interrupts on this sample sequence.\r
+ //\r
+ HWREG(ulBase + ADC_O_ISC) = 1 << ulSequenceNum;\r
+\r
+ //\r
+ // Enable this sample sequence interrupt.\r
+ //\r
+ HWREG(ulBase + ADC_O_IM) |= 1 << ulSequenceNum;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Gets the current interrupt status.\r
+//!\r
+//! \param ulBase is the base address of the ADC module.\r
+//! \param ulSequenceNum is the sample sequence number.\r
+//! \param bMasked is false if the raw interrupt status is required and true if\r
+//! the masked interrupt status is required.\r
+//!\r
+//! This returns the interrupt status for the specified sample sequence.\r
+//! Either the raw interrupt status or the status of interrupts that are\r
+//! allowed to reflect to the processor can be returned.\r
+//!\r
+//! \return The current raw or masked interrupt status.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+unsigned long\r
+ADCIntStatus(unsigned long ulBase, unsigned long ulSequenceNum,\r
+ tBoolean bMasked)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == ADC_BASE);\r
+ ASSERT(ulSequenceNum < 4);\r
+\r
+ //\r
+ // Return either the interrupt status or the raw interrupt status as\r
+ // requested.\r
+ //\r
+ if(bMasked)\r
+ {\r
+ return(HWREG(ulBase + ADC_O_ISC) & (1 << ulSequenceNum));\r
+ }\r
+ else\r
+ {\r
+ return(HWREG(ulBase + ADC_O_RIS) & (1 << ulSequenceNum));\r
+ }\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Clears sample sequence interrupt source.\r
+//!\r
+//! \param ulBase is the base address of the ADC module.\r
+//! \param ulSequenceNum is the sample sequence number.\r
+//!\r
+//! The specified sample sequence interrupt is cleared, so that it no longer\r
+//! asserts. This must be done in the interrupt handler to keep it from being\r
+//! called again immediately upon exit.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+ADCIntClear(unsigned long ulBase, unsigned long ulSequenceNum)\r
+{\r
+ //\r
+ // Check the arugments.\r
+ //\r
+ ASSERT(ulBase == ADC_BASE);\r
+ ASSERT(ulSequenceNum < 4);\r
+\r
+ //\r
+ // Clear the interrupt.\r
+ //\r
+ HWREG(ulBase + ADC_O_ISC) = 1 << ulSequenceNum;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Enables a sample sequence.\r
+//!\r
+//! \param ulBase is the base address of the ADC module.\r
+//! \param ulSequenceNum is the sample sequence number.\r
+//!\r
+//! Allows the specified sample sequence to be captured when its trigger is\r
+//! detected. A sample sequence must be configured before it is enabled.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_sequenceenable) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+ADCSequenceEnable(unsigned long ulBase, unsigned long ulSequenceNum)\r
+{\r
+ //\r
+ // Check the arugments.\r
+ //\r
+ ASSERT(ulBase == ADC_BASE);\r
+ ASSERT(ulSequenceNum < 4);\r
+\r
+ //\r
+ // Enable the specified sequence.\r
+ //\r
+ HWREG(ulBase + ADC_O_ACTSS) |= 1 << ulSequenceNum;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Disables a sample sequence.\r
+//!\r
+//! \param ulBase is the base address of the ADC module.\r
+//! \param ulSequenceNum is the sample sequence number.\r
+//!\r
+//! Prevents the specified sample sequence from being captured when its trigger\r
+//! is detected. A sample sequence should be disabled before it is configured.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_sequencedisable) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+ADCSequenceDisable(unsigned long ulBase, unsigned long ulSequenceNum)\r
+{\r
+ //\r
+ // Check the arugments.\r
+ //\r
+ ASSERT(ulBase == ADC_BASE);\r
+ ASSERT(ulSequenceNum < 4);\r
+\r
+ //\r
+ // Disable the specified sequences.\r
+ //\r
+ HWREG(ulBase + ADC_O_ACTSS) &= ~(1 << ulSequenceNum);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Configures the trigger source and priority of a sample sequence.\r
+//!\r
+//! \param ulBase is the base address of the ADC module.\r
+//! \param ulSequenceNum is the sample sequence number.\r
+//! \param ulTrigger is the trigger source that initiates the sample sequence;\r
+//! must be one of the \b ADC_TRIGGER_* values.\r
+//! \param ulPriority is the relative priority of the sample sequence with\r
+//! respect to the other sample sequences.\r
+//!\r
+//! This function configures the initiation criteria for a sample sequence.\r
+//! Valid sample sequences range from zero to three; sequence zero will capture\r
+//! up to eight samples, sequences one and two will capture up to four samples,\r
+//! and sequence three will capture a single sample. The trigger condition and\r
+//! priority (with respect to other sample sequence execution) is set.\r
+//!\r
+//! The parameter \b ulTrigger can take on the following values:\r
+//!\r
+//! - \b ADC_TRIGGER_PROCESSOR - A trigger generated by the processor, via the\r
+//! ADCProcessorTrigger() function.\r
+//! - \b ADC_TRIGGER_COMP0 - A trigger generated by the first analog\r
+//! comparator; configured with ComparatorConfigure().\r
+//! - \b ADC_TRIGGER_COMP1 - A trigger generated by the second analog\r
+//! comparator; configured with ComparatorConfigure().\r
+//! - \b ADC_TRIGGER_COMP2 - A trigger generated by the third analog\r
+//! comparator; configured with ComparatorConfigure().\r
+//! - \b ADC_TRIGGER_EXTERNAL - A trigger generated by an input from the Port\r
+//! B4 pin.\r
+//! - \b ADC_TRIGGER_TIMER - A trigger generated by a timer; configured with\r
+//! TimerControlTrigger().\r
+//! - \b ADC_TRIGGER_PWM0 - A trigger generated by the first PWM generator;\r
+//! configured with PWMGenIntTrigEnable().\r
+//! - \b ADC_TRIGGER_PWM1 - A trigger generated by the second PWM generator;\r
+//! configured with PWMGenIntTrigEnable().\r
+//! - \b ADC_TRIGGER_PWM2 - A trigger generated by the third PWM generator;\r
+//! configured with PWMGenIntTrigEnable().\r
+//! - \b ADC_TRIGGER_ALWAYS - A trigger that is always asserted, causing the\r
+//! sample sequence to capture repeatedly (so long as\r
+//! there is not a higher priority source active).\r
+//!\r
+//! Note that not all trigger sources are available on all Stellaris family\r
+//! members; consult the data sheet for the device in question to determine the\r
+//! availability of triggers.\r
+//!\r
+//! The parameter \b ulPriority is a value between 0 and 3, where 0 represents\r
+//! the highest priority and 3 the lowest. Note that when programming the\r
+//! priority among a set of sample sequences, each must have unique priority;\r
+//! it is up to the caller to guarantee the uniqueness of the priorities.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_sequenceconfigure) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+ADCSequenceConfigure(unsigned long ulBase, unsigned long ulSequenceNum,\r
+ unsigned long ulTrigger, unsigned long ulPriority)\r
+{\r
+ //\r
+ // Check the arugments.\r
+ //\r
+ ASSERT(ulBase == ADC_BASE);\r
+ ASSERT(ulSequenceNum < 4);\r
+ ASSERT((ulTrigger == ADC_TRIGGER_PROCESSOR) ||\r
+ (ulTrigger == ADC_TRIGGER_COMP0) ||\r
+ (ulTrigger == ADC_TRIGGER_COMP1) ||\r
+ (ulTrigger == ADC_TRIGGER_COMP2) ||\r
+ (ulTrigger == ADC_TRIGGER_EXTERNAL) ||\r
+ (ulTrigger == ADC_TRIGGER_TIMER) ||\r
+ (ulTrigger == ADC_TRIGGER_PWM0) ||\r
+ (ulTrigger == ADC_TRIGGER_PWM1) ||\r
+ (ulTrigger == ADC_TRIGGER_PWM2) ||\r
+ (ulTrigger == ADC_TRIGGER_ALWAYS));\r
+ ASSERT(ulPriority < 4);\r
+\r
+ //\r
+ // Compute the shift for the bits that control this sample sequence.\r
+ //\r
+ ulSequenceNum *= 4;\r
+\r
+ //\r
+ // Set the trigger event for this sample sequence.\r
+ //\r
+ HWREG(ulBase + ADC_O_EMUX) = ((HWREG(ulBase + ADC_O_EMUX) &\r
+ ~(0xf << ulSequenceNum)) |\r
+ ((ulTrigger & 0xf) << ulSequenceNum));\r
+\r
+ //\r
+ // Set the priority for this sample sequence.\r
+ //\r
+ HWREG(ulBase + ADC_O_SSPRI) = ((HWREG(ulBase + ADC_O_SSPRI) &\r
+ ~(0xf << ulSequenceNum)) |\r
+ ((ulPriority & 0x3) << ulSequenceNum));\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Configure a step of the sample sequencer.\r
+//!\r
+//! \param ulBase is the base address of the ADC module.\r
+//! \param ulSequenceNum is the sample sequence number.\r
+//! \param ulStep is the step to be configured.\r
+//! \param ulConfig is the configuration of this step; must be a logical OR of\r
+//! \b ADC_CTL_TS, \b ADC_CTL_IE, \b ADC_CTL_END, \b ADC_CTL_D, and one of the\r
+//! input channel selects (\b ADC_CTL_CH0 through \b ADC_CTL_CH7).\r
+//!\r
+//! This function will set the configuration of the ADC for one step of a\r
+//! sample sequence. The ADC can be configured for single-ended or\r
+//! differential operation (the \b ADC_CTL_D bit selects differential\r
+//! operation when set), the channel to be sampled can be chosen (the\r
+//! \b ADC_CTL_CH0 through \b ADC_CTL_CH7 values), and the internal temperature\r
+//! sensor can be selected (the \b ADC_CTL_TS bit). Additionally, this step\r
+//! can be defined as the last in the sequence (the \b ADC_CTL_END bit) and it\r
+//! can be configured to cause an interrupt when the step is complete (the\r
+//! \b ADC_CTL_IE bit). The configuration is used by the ADC at the\r
+//! appropriate time when the trigger for this sequence occurs.\r
+//!\r
+//! The \b ulStep parameter determines the order in which the samples are\r
+//! captured by the ADC when the trigger occurs. It can range from zero to\r
+//! seven for the first sample sequence, from zero to three for the second and\r
+//! third sample sequence, and can only be zero for the fourth sample sequence.\r
+//!\r
+//! Differential mode only works with adjacent channel pairs (e.g. 0 and 1).\r
+//! The channel select must be the number of the channel pair to sample (e.g.\r
+//! \b ADC_CTL_CH0 for 0 and 1, or \b ADC_CTL_CH1 for 2 and 3) or undefined\r
+//! results will be returned by the ADC. Additionally, if differential mode is\r
+//! selected when the temperature sensor is being sampled, undefined results\r
+//! will be returned by the ADC.\r
+//!\r
+//! It is the responsibility of the caller to ensure that a valid configuration\r
+//! is specified; this function does not check the validity of the specified\r
+//! configuration.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_sequencestepconfigure) || defined(BUILD_ALL) || \\r
+ defined(DOXYGEN)\r
+void\r
+ADCSequenceStepConfigure(unsigned long ulBase, unsigned long ulSequenceNum,\r
+ unsigned long ulStep, unsigned long ulConfig)\r
+{\r
+ //\r
+ // Check the arugments.\r
+ //\r
+ ASSERT(ulBase == ADC_BASE);\r
+ ASSERT(ulSequenceNum < 4);\r
+ ASSERT(((ulSequenceNum == 0) && (ulStep < 8)) ||\r
+ ((ulSequenceNum == 1) && (ulStep < 4)) ||\r
+ ((ulSequenceNum == 2) && (ulStep < 4)) ||\r
+ ((ulSequenceNum == 3) && (ulStep < 1)));\r
+\r
+ //\r
+ // Get the offset of the sequence to be configured.\r
+ //\r
+ ulBase += ADC_O_SEQ + (ADC_O_SEQ_STEP * ulSequenceNum);\r
+\r
+ //\r
+ // Compute the shift for the bits that control this step.\r
+ //\r
+ ulStep *= 4;\r
+\r
+ //\r
+ // Set the analog mux value for this step.\r
+ //\r
+ HWREG(ulBase + ADC_O_X_SSMUX) = ((HWREG(ulBase + ADC_O_X_SSMUX) &\r
+ ~(0x0000000f << ulStep)) |\r
+ ((ulConfig & 0x0f) << ulStep));\r
+\r
+ //\r
+ // Set the control value for this step.\r
+ //\r
+ HWREG(ulBase + ADC_O_X_SSCTL) = ((HWREG(ulBase + ADC_O_X_SSCTL) &\r
+ ~(0x0000000f << ulStep)) |\r
+ (((ulConfig & 0xf0) >> 4) << ulStep));\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Determines if a sample sequence overflow occurred.\r
+//!\r
+//! \param ulBase is the base address of the ADC module.\r
+//! \param ulSequenceNum is the sample sequence number.\r
+//!\r
+//! This determines if a sample sequence overflow has occurred. This will\r
+//! happen if the captured samples are not read from the FIFO before the next\r
+//! trigger occurs.\r
+//!\r
+//! \return Returns zero if there was not an overflow, and non-zero if there\r
+//! was.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_sequenceoverflow) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+long\r
+ADCSequenceOverflow(unsigned long ulBase, unsigned long ulSequenceNum)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == ADC_BASE);\r
+ ASSERT(ulSequenceNum < 4);\r
+\r
+ //\r
+ // Determine if there was an overflow on this sequence.\r
+ //\r
+ return(HWREG(ulBase + ADC_O_OSTAT) & (1 << ulSequenceNum));\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Determines if a sample sequence underflow occurred.\r
+//!\r
+//! \param ulBase is the base address of the ADC module.\r
+//! \param ulSequenceNum is the sample sequence number.\r
+//!\r
+//! This determines if a sample sequence underflow has occurred. This will\r
+//! happen if too many samples are read from the FIFO.\r
+//!\r
+//! \return Returns zero if there was not an underflow, and non-zero if there\r
+//! was.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_sequenceunderflow) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+long\r
+ADCSequenceUnderflow(unsigned long ulBase, unsigned long ulSequenceNum)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == ADC_BASE);\r
+ ASSERT(ulSequenceNum < 4);\r
+\r
+ //\r
+ // Determine if there was an underflow on this sequence.\r
+ //\r
+ return(HWREG(ulBase + ADC_O_USTAT) & (1 << ulSequenceNum));\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Gets the captured data for a sample sequence.\r
+//!\r
+//! \param ulBase is the base address of the ADC module.\r
+//! \param ulSequenceNum is the sample sequence number.\r
+//! \param pulBuffer is the address where the data is stored.\r
+//!\r
+//! This function copies data from the specified sample sequence output FIFO to\r
+//! a memory resident buffer. The number of samples available in the hardware\r
+//! FIFO are copied into the buffer, which is assumed to be large enough to\r
+//! hold that many samples. This will only return the samples that are\r
+//! presently available, which may not be the entire sample sequence if it is\r
+//! in the process of being executed.\r
+//!\r
+//! \return Returns the number of samples copied to the buffer.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_sequencedataget) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+long\r
+ADCSequenceDataGet(unsigned long ulBase, unsigned long ulSequenceNum,\r
+ unsigned long *pulBuffer)\r
+{\r
+ unsigned long ulCount;\r
+\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == ADC_BASE);\r
+ ASSERT(ulSequenceNum < 4);\r
+\r
+ //\r
+ // Get the offset of the sequence to be read.\r
+ //\r
+ ulBase += ADC_O_SEQ + (ADC_O_SEQ_STEP * ulSequenceNum);\r
+\r
+ //\r
+ // Read samples from the FIFO until it is empty.\r
+ //\r
+ ulCount = 0;\r
+ while(!(HWREG(ulBase + ADC_O_X_SSFSTAT) & ADC_SSFSTAT_EMPTY) &&\r
+ (ulCount < 8))\r
+ {\r
+ //\r
+ // Read the FIFO and copy it to the destination.\r
+ //\r
+ *pulBuffer++ = HWREG(ulBase + ADC_O_X_SSFIFO);\r
+\r
+ //\r
+ // Increment the count of samples read.\r
+ //\r
+ ulCount++;\r
+ }\r
+\r
+ //\r
+ // Return the number of samples read.\r
+ //\r
+ return(ulCount);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Causes a processor trigger for a sample sequence.\r
+//!\r
+//! \param ulBase is the base address of the ADC module.\r
+//! \param ulSequenceNum is the sample sequence number.\r
+//!\r
+//! This function triggers a processor-initiated sample sequence if the sample\r
+//! sequence trigger is configured to ADC_TRIGGER_PROCESSOR.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_processortrigger) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+ADCProcessorTrigger(unsigned long ulBase, unsigned long ulSequenceNum)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == ADC_BASE);\r
+ ASSERT(ulSequenceNum < 4);\r
+\r
+ //\r
+ // Generate a processor trigger for this sample sequence.\r
+ //\r
+ HWREG(ulBase + ADC_O_PSSI) = 1 << ulSequenceNum;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Configures the software oversampling factor of the ADC.\r
+//!\r
+//! \param ulBase is the base address of the ADC module.\r
+//! \param ulSequenceNum is the sample sequence number.\r
+//! \param ulFactor is the number of samples to be averaged.\r
+//!\r
+//! This function configures the software oversampling for the ADC, which can\r
+//! be used to provide better resolution on the sampled data. Oversampling is\r
+//! accomplished by averaging multiple samples from the same analog input.\r
+//! Three different oversampling rates are supported; 2x, 4x, and 8x.\r
+//!\r
+//! Oversampling is only supported on the sample sequencers that are more than\r
+//! one sample in depth (i.e. the fourth sample sequencer is not supported).\r
+//! Oversampling by 2x (for example) divides the depth of the sample sequencer\r
+//! by two; so 2x oversampling on the first sample sequencer can only provide\r
+//! four samples per trigger. This also means that 8x oversampling is only\r
+//! available on the first sample sequencer.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_softwareoversampleconfigure) || defined(BUILD_ALL) || \\r
+ defined(DOXYGEN)\r
+void\r
+ADCSoftwareOversampleConfigure(unsigned long ulBase,\r
+ unsigned long ulSequenceNum,\r
+ unsigned long ulFactor)\r
+{\r
+ unsigned long ulValue;\r
+\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == ADC_BASE);\r
+ ASSERT(ulSequenceNum < 3);\r
+ ASSERT(((ulFactor == 2) || (ulFactor == 4) || (ulFactor == 8)) &&\r
+ ((ulSequenceNum == 0) || (ulFactor != 8)));\r
+\r
+ //\r
+ // Convert the oversampling factor to a shift factor.\r
+ //\r
+ for(ulValue = 0, ulFactor >>= 1; ulFactor; ulValue++, ulFactor >>= 1)\r
+ {\r
+ }\r
+\r
+ //\r
+ // Save the sfiht factor.\r
+ //\r
+ g_pucOversampleFactor[ulSequenceNum] = ulValue;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Configures a step of the software oversampled sequencer.\r
+//!\r
+//! \param ulBase is the base address of the ADC module.\r
+//! \param ulSequenceNum is the sample sequence number.\r
+//! \param ulStep is the step to be configured.\r
+//! \param ulConfig is the configuration of this step.\r
+//!\r
+//! This function configures a step of the sample sequencer when using the\r
+//! software oversampling feature. The number of steps available depends on\r
+//! the oversampling factor set by ADCSoftwareOversampleConfigure(). The value\r
+//! of \e ulConfig is the same as defined for ADCSequenceStepConfigure().\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_softwareoversamplestepconfigure) || defined(BUILD_ALL) || \\r
+ defined(DOXYGEN)\r
+void\r
+ADCSoftwareOversampleStepConfigure(unsigned long ulBase,\r
+ unsigned long ulSequenceNum,\r
+ unsigned long ulStep,\r
+ unsigned long ulConfig)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == ADC_BASE);\r
+ ASSERT(ulSequenceNum < 3);\r
+ ASSERT(((ulSequenceNum == 0) &&\r
+ (ulStep < (8 >> g_pucOversampleFactor[ulSequenceNum]))) ||\r
+ (ulStep < (4 >> g_pucOversampleFactor[ulSequenceNum])));\r
+\r
+ //\r
+ // Get the offset of the sequence to be configured.\r
+ //\r
+ ulBase += ADC_O_SEQ + (ADC_O_SEQ_STEP * ulSequenceNum);\r
+\r
+ //\r
+ // Compute the shift for the bits that control this step.\r
+ //\r
+ ulStep *= 4 << g_pucOversampleFactor[ulSequenceNum];\r
+\r
+ //\r
+ // Loop through the hardware steps that make up this step of the software\r
+ // oversampled sequence.\r
+ //\r
+ for(ulSequenceNum = 1 << g_pucOversampleFactor[ulSequenceNum];\r
+ ulSequenceNum; ulSequenceNum--)\r
+ {\r
+ //\r
+ // Set the analog mux value for this step.\r
+ //\r
+ HWREG(ulBase + ADC_O_X_SSMUX) = ((HWREG(ulBase + ADC_O_X_SSMUX) &\r
+ ~(0x0000000f << ulStep)) |\r
+ ((ulConfig & 0x0f) << ulStep));\r
+\r
+ //\r
+ // Set the control value for this step.\r
+ //\r
+ HWREG(ulBase + ADC_O_X_SSCTL) = ((HWREG(ulBase + ADC_O_X_SSCTL) &\r
+ ~(0x0000000f << ulStep)) |\r
+ (((ulConfig & 0xf0) >> 4) << ulStep));\r
+ if(ulSequenceNum != 1)\r
+ {\r
+ HWREG(ulBase + ADC_O_X_SSCTL) &= ~((ADC_SSCTL_IE0 |\r
+ ADC_SSCTL_END0) << ulStep);\r
+ }\r
+\r
+ //\r
+ // Go to the next hardware step.\r
+ //\r
+ ulStep += 4;\r
+ }\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Gets the captured data for a sample sequence using software oversampling.\r
+//!\r
+//! \param ulBase is the base address of the ADC module.\r
+//! \param ulSequenceNum is the sample sequence number.\r
+//! \param pulBuffer is the address where the data is stored.\r
+//! \param ulCount is the number of samples to be read.\r
+//!\r
+//! This function copies data from the specified sample sequence output FIFO to\r
+//! a memory resident buffer with software oversampling applied. The requested\r
+//! number of samples are copied into the data buffer; if there are not enough\r
+//! samples in the hardware FIFO to satisfy this many oversampled data items\r
+//! then incorrect results will be returned. It is the caller's responsibility\r
+//! to read only the samples that are available and wait until enough data is\r
+//! available, for example as a result of receiving an interrupt.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_softwareoversampledataget) || defined(BUILD_ALL) || \\r
+ defined(DOXYGEN)\r
+void\r
+ADCSoftwareOversampleDataGet(unsigned long ulBase, unsigned long ulSequenceNum,\r
+ unsigned long *pulBuffer, unsigned long ulCount)\r
+{\r
+ unsigned long ulIdx, ulAccum;\r
+\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == ADC_BASE);\r
+ ASSERT(ulSequenceNum < 3);\r
+ ASSERT(((ulSequenceNum == 0) &&\r
+ (ulCount < (8 >> g_pucOversampleFactor[ulSequenceNum]))) ||\r
+ (ulCount < (4 >> g_pucOversampleFactor[ulSequenceNum])));\r
+\r
+ //\r
+ // Get the offset of the sequence to be read.\r
+ //\r
+ ulBase += ADC_O_SEQ + (ADC_O_SEQ_STEP * ulSequenceNum);\r
+\r
+ //\r
+ // Read the samples from the FIFO until it is empty.\r
+ //\r
+ while(ulCount--)\r
+ {\r
+ //\r
+ // Compute the sum of the samples.\r
+ //\r
+ ulAccum = 0;\r
+ for(ulIdx = 1 << g_pucOversampleFactor[ulSequenceNum]; ulIdx; ulIdx--)\r
+ {\r
+ //\r
+ // Read the FIFO and add it to the accumulator.\r
+ //\r
+ ulAccum += HWREG(ulBase + ADC_O_X_SSFIFO);\r
+ }\r
+\r
+ //\r
+ // Write the averaged sample to the output buffer.\r
+ //\r
+ *pulBuffer++ = ulAccum >> g_pucOversampleFactor[ulSequenceNum];\r
+ }\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Configures the hardware oversampling factor of the ADC.\r
+//!\r
+//! \param ulBase is the base address of the ADC module.\r
+//! \param ulFactor is the number of samples to be averaged.\r
+//!\r
+//! This function configures the hardware oversampling for the ADC, which can\r
+//! be used to provide better resolution on the sampled data. Oversampling is\r
+//! accomplished by averaging multiple samples from the same analog input. Six\r
+//! different oversampling rates are supported; 2x, 4x, 8x, 16x, 32x, and 64x.\r
+//! Specifying an oversampling factor of zero will disable the hardware\r
+//! oversampler.\r
+//!\r
+//! Hardware oversampling applies uniformly to all sample sequencers. It does\r
+//! not reduce the depth of the sample sequencers like the software\r
+//! oversampling APIs; each sample written into the sample sequence FIFO is a\r
+//! fully oversampled analog input reading.\r
+//!\r
+//! Enabling hardware averaging increases the precision of the ADC at the cost\r
+//! of throughput. For example, enabling 4x oversampling reduces the\r
+//! throughput of a 250 KSps ADC to 62.5 KSps.\r
+//!\r
+//! \note Hardware oversampling is available beginning with Rev C0 of the\r
+//! Stellaris microcontroller.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_hardwareoversampleconfigure) || defined(BUILD_ALL) || \\r
+ defined(DOXYGEN)\r
+void\r
+ADCHardwareOversampleConfigure(unsigned long ulBase,\r
+ unsigned long ulFactor)\r
+{\r
+ unsigned long ulValue;\r
+\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == ADC_BASE);\r
+ ASSERT(((ulFactor == 0) || (ulFactor == 2) || (ulFactor == 4) ||\r
+ (ulFactor == 8) || (ulFactor == 16) || (ulFactor == 32) ||\r
+ (ulFactor == 64)));\r
+\r
+ //\r
+ // Convert the oversampling factor to a shift factor.\r
+ //\r
+ for(ulValue = 0, ulFactor >>= 1; ulFactor; ulValue++, ulFactor >>= 1)\r
+ {\r
+ }\r
+\r
+ //\r
+ // Write the shift factor to the ADC to configure the hardware oversampler.\r
+ //\r
+ HWREG(ulBase + ADC_O_SAC) = ulValue;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Close the Doxygen group.\r
+//! @}\r
+//\r
+//*****************************************************************************\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// adc.h - ADC headers for using the ADC driver functions.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 991 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __ADC_H__\r
+#define __ADC_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to ADCSequenceConfigure as the ulTrigger\r
+// parameter.\r
+//\r
+//*****************************************************************************\r
+#define ADC_TRIGGER_PROCESSOR 0x00000000 // Processor event\r
+#define ADC_TRIGGER_COMP0 0x00000001 // Analog comparator 0 event\r
+#define ADC_TRIGGER_COMP1 0x00000002 // Analog comparator 1 event\r
+#define ADC_TRIGGER_COMP2 0x00000003 // Analog comparator 2 event\r
+#define ADC_TRIGGER_EXTERNAL 0x00000004 // External event\r
+#define ADC_TRIGGER_TIMER 0x00000005 // Timer event\r
+#define ADC_TRIGGER_PWM0 0x00000006 // PWM0 event\r
+#define ADC_TRIGGER_PWM1 0x00000007 // PWM1 event\r
+#define ADC_TRIGGER_PWM2 0x00000008 // PWM2 event\r
+#define ADC_TRIGGER_ALWAYS 0x0000000F // Always event\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to ADCSequenceStepConfigure as the ulConfig\r
+// parameter.\r
+//\r
+//*****************************************************************************\r
+#define ADC_CTL_TS 0x00000080 // Temperature sensor select\r
+#define ADC_CTL_IE 0x00000040 // Interrupt enable\r
+#define ADC_CTL_END 0x00000020 // Sequence end select\r
+#define ADC_CTL_D 0x00000010 // Differential select\r
+#define ADC_CTL_CH0 0x00000000 // Input channel 0\r
+#define ADC_CTL_CH1 0x00000001 // Input channel 1\r
+#define ADC_CTL_CH2 0x00000002 // Input channel 2\r
+#define ADC_CTL_CH3 0x00000003 // Input channel 3\r
+#define ADC_CTL_CH4 0x00000004 // Input channel 4\r
+#define ADC_CTL_CH5 0x00000005 // Input channel 5\r
+#define ADC_CTL_CH6 0x00000006 // Input channel 6\r
+#define ADC_CTL_CH7 0x00000007 // Input channel 7\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void ADCIntRegister(unsigned long ulBase, unsigned long ulSequenceNum,\r
+ void (*pfnHandler)(void));\r
+extern void ADCIntUnregister(unsigned long ulBase,\r
+ unsigned long ulSequenceNum);\r
+extern void ADCIntDisable(unsigned long ulBase, unsigned long ulSequenceNum);\r
+extern void ADCIntEnable(unsigned long ulBase, unsigned long ulSequenceNum);\r
+extern unsigned long ADCIntStatus(unsigned long ulBase,\r
+ unsigned long ulSequenceNum,\r
+ tBoolean bMasked);\r
+extern void ADCIntClear(unsigned long ulBase, unsigned long ulSequenceNum);\r
+extern void ADCSequenceEnable(unsigned long ulBase,\r
+ unsigned long ulSequenceNum);\r
+extern void ADCSequenceDisable(unsigned long ulBase,\r
+ unsigned long ulSequenceNum);\r
+extern void ADCSequenceConfigure(unsigned long ulBase,\r
+ unsigned long ulSequenceNum,\r
+ unsigned long ulTrigger,\r
+ unsigned long ulPriority);\r
+extern void ADCSequenceStepConfigure(unsigned long ulBase,\r
+ unsigned long ulSequenceNum,\r
+ unsigned long ulStep,\r
+ unsigned long ulConfig);\r
+extern long ADCSequenceOverflow(unsigned long ulBase,\r
+ unsigned long ulSequenceNum);\r
+extern long ADCSequenceUnderflow(unsigned long ulBase,\r
+ unsigned long ulSequenceNum);\r
+extern long ADCSequenceDataGet(unsigned long ulBase,\r
+ unsigned long ulSequenceNum,\r
+ unsigned long *pulBuffer);\r
+extern void ADCProcessorTrigger(unsigned long ulBase,\r
+ unsigned long ulSequenceNum);\r
+extern void ADCSoftwareOversampleConfigure(unsigned long ulBase,\r
+ unsigned long ulSequenceNum,\r
+ unsigned long ulFactor);\r
+extern void ADCSoftwareOversampleStepConfigure(unsigned long ulBase,\r
+ unsigned long ulSequenceNum,\r
+ unsigned long ulStep,\r
+ unsigned long ulConfig);\r
+extern void ADCSoftwareOversampleDataGet(unsigned long ulBase,\r
+ unsigned long ulSequenceNum,\r
+ unsigned long *pulBuffer,\r
+ unsigned long ulCount);\r
+extern void ADCHardwareOversampleConfigure(unsigned long ulBase,\r
+ unsigned long ulFactor);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __ADC_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// comp.c - Driver for the analog comparator.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 991 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \addtogroup comp_api\r
+//! @{\r
+//\r
+//*****************************************************************************\r
+\r
+#include "../hw_comp.h"\r
+#include "../hw_ints.h"\r
+#include "../hw_memmap.h"\r
+#include "../hw_types.h"\r
+#include "comp.h"\r
+#include "debug.h"\r
+#include "interrupt.h"\r
+\r
+//*****************************************************************************\r
+//\r
+//! Configures a comparator.\r
+//!\r
+//! \param ulBase is the base address of the comparator module.\r
+//! \param ulComp is the index of the comparator to configure.\r
+//! \param ulConfig is the configuration of the comparator.\r
+//!\r
+//! This function will configure a comparator. The \e ulConfig parameter is\r
+//! the result of a logical OR operation between the \b COMP_TRIG_xxx,\r
+//! \b COMP_INT_xxx, \b COMP_ASRCP_xxx, and \b COMP_OUTPUT_xxx values.\r
+//!\r
+//! The \b COMP_TRIG_xxx term can take on the following values:\r
+//!\r
+//! - \b COMP_TRIG_NONE to have no trigger to the ADC.\r
+//! - \b COMP_TRIG_HIGH to trigger the ADC when the comparator output is high.\r
+//! - \b COMP_TRIG_LOW to trigger the ADC when the comparator output is low.\r
+//! - \b COMP_TRIG_FALL to trigger the ADC when the comparator output goes low.\r
+//! - \b COMP_TRIG_RISE to trigger the ADC when the comparator output goes\r
+//! high.\r
+//! - \b COMP_TRIG_BOTH to trigger the ADC when the comparator output goes low\r
+//! or high.\r
+//!\r
+//! The \b COMP_INT_xxx term can take on the following values:\r
+//!\r
+//! - \b COMP_INT_HIGH to generate an interrupt when the comparator output is\r
+//! high.\r
+//! - \b COMP_INT_LOW to generate an interrupt when the comparator output is\r
+//! low.\r
+//! - \b COMP_INT_FALL to generate an interrupt when the comparator output goes\r
+//! low.\r
+//! - \b COMP_INT_RISE to generate an interrupt when the comparator output goes\r
+//! high.\r
+//! - \b COMP_INT_BOTH to generate an interrupt when the comparator output goes\r
+//! low or high.\r
+//!\r
+//! The \b COMP_ASRCP_xxx term can take on the following values:\r
+//!\r
+//! - \b COMP_ASRCP_PIN to use the dedicated Comp+ pin as the reference\r
+//! voltage.\r
+//! - \b COMP_ASRCP_PIN0 to use the Comp0+ pin as the reference voltage (this\r
+//! the same as \b COMP_ASRCP_PIN for the comparator 0).\r
+//! - \b COMP_ASRCP_REF to use the internally generated voltage as the\r
+//! reference voltage.\r
+//!\r
+//! The \b COMP_OUTPUT_xxx term can take on the following values:\r
+//!\r
+//! - \b COMP_OUTPUT_NONE to disable the output from the comparator to a device\r
+//! pin.\r
+//! - \b COMP_OUTPUT_NORMAL to enable a non-inverted output from the comparator\r
+//! to a device pin.\r
+//! - \b COMP_OUTPUT_INVERT to enable an inverted output from the comparator to\r
+//! a device pin.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_configure) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+ComparatorConfigure(unsigned long ulBase, unsigned long ulComp,\r
+ unsigned long ulConfig)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == COMP_BASE);\r
+ ASSERT(ulComp < 3);\r
+\r
+ //\r
+ // Configure this comparator.\r
+ //\r
+ HWREG(ulBase + (ulComp * 0x20) + COMP_O_ACCTL0) = ulConfig;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Sets the internal reference voltage.\r
+//!\r
+//! \param ulBase is the base address of the comparator module.\r
+//! \param ulRef is the desired reference voltage.\r
+//!\r
+//! This function will set the internal reference voltage value. The voltage\r
+//! is specified as one of the following values:\r
+//!\r
+//! - \b COMP_REF_OFF to turn off the reference voltage\r
+//! - \b COMP_REF_0V to set the reference voltage to 0 V\r
+//! - \b COMP_REF_0_1375V to set the reference voltage to 0.1375 V\r
+//! - \b COMP_REF_0_275V to set the reference voltage to 0.275 V\r
+//! - \b COMP_REF_0_4125V to set the reference voltage to 0.4125 V\r
+//! - \b COMP_REF_0_55V to set the reference voltage to 0.55 V\r
+//! - \b COMP_REF_0_6875V to set the reference voltage to 0.6875 V\r
+//! - \b COMP_REF_0_825V to set the reference voltage to 0.825 V\r
+//! - \b COMP_REF_0_928125V to set the reference voltage to 0.928125 V\r
+//! - \b COMP_REF_0_9625V to set the reference voltage to 0.9625 V\r
+//! - \b COMP_REF_1_03125V to set the reference voltage to 1.03125 V\r
+//! - \b COMP_REF_1_134375V to set the reference voltage to 1.134375 V\r
+//! - \b COMP_REF_1_1V to set the reference voltage to 1.1 V\r
+//! - \b COMP_REF_1_2375V to set the reference voltage to 1.2375 V\r
+//! - \b COMP_REF_1_340625V to set the reference voltage to 1.340625 V\r
+//! - \b COMP_REF_1_375V to set the reference voltage to 1.375 V\r
+//! - \b COMP_REF_1_44375V to set the reference voltage to 1.44375 V\r
+//! - \b COMP_REF_1_5125V to set the reference voltage to 1.5125 V\r
+//! - \b COMP_REF_1_546875V to set the reference voltage to 1.546875 V\r
+//! - \b COMP_REF_1_65V to set the reference voltage to 1.65 V\r
+//! - \b COMP_REF_1_753125V to set the reference voltage to 1.753125 V\r
+//! - \b COMP_REF_1_7875V to set the reference voltage to 1.7875 V\r
+//! - \b COMP_REF_1_85625V to set the reference voltage to 1.85625 V\r
+//! - \b COMP_REF_1_925V to set the reference voltage to 1.925 V\r
+//! - \b COMP_REF_1_959375V to set the reference voltage to 1.959375 V\r
+//! - \b COMP_REF_2_0625V to set the reference voltage to 2.0625 V\r
+//! - \b COMP_REF_2_165625V to set the reference voltage to 2.165625 V\r
+//! - \b COMP_REF_2_26875V to set the reference voltage to 2.26875 V\r
+//! - \b COMP_REF_2_371875V to set the reference voltage to 2.371875 V\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_refset) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+ComparatorRefSet(unsigned long ulBase, unsigned long ulRef)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == COMP_BASE);\r
+\r
+ //\r
+ // Set the voltage reference voltage as requested.\r
+ //\r
+ HWREG(ulBase + COMP_O_REFCTL) = ulRef;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Gets the current comparator output value.\r
+//!\r
+//! \param ulBase is the base address of the comparator module.\r
+//! \param ulComp is the index of the comparator.\r
+//!\r
+//! This function retrieves the current value of the comparator output.\r
+//!\r
+//! \return Returns \b true if the comparator output is high and \b false if\r
+//! the comparator output is low.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_valueget) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+tBoolean\r
+ComparatorValueGet(unsigned long ulBase, unsigned long ulComp)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == COMP_BASE);\r
+ ASSERT(ulComp < 3);\r
+\r
+ //\r
+ // Return the appropriate value based on the comparator's present output\r
+ // value.\r
+ //\r
+ if(HWREG(ulBase + (ulComp * 0x20) + COMP_O_ACSTAT0) & COMP_ACSTAT_OVAL)\r
+ {\r
+ return(true);\r
+ }\r
+ else\r
+ {\r
+ return(false);\r
+ }\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Registers an interrupt handler for the comparator interrupt.\r
+//!\r
+//! \param ulBase is the base address of the comparator module.\r
+//! \param ulComp is the index of the comparator.\r
+//! \param pfnHandler is a pointer to the function to be called when the\r
+//! comparator interrupt occurs.\r
+//!\r
+//! This sets the handler to be called when the comparator interrupt occurs.\r
+//! This will enable the interrupt in the interrupt controller; it is the\r
+//! interrupt-handler's responsibility to clear the interrupt source via\r
+//! ComparatorIntClear().\r
+//!\r
+//! \sa IntRegister() for important information about registering interrupt\r
+//! handlers.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+ComparatorIntRegister(unsigned long ulBase, unsigned long ulComp,\r
+ void (*pfnHandler)(void))\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == COMP_BASE);\r
+ ASSERT(ulComp < 3);\r
+\r
+ //\r
+ // Register the interrupt handler, returning an error if an error occurs.\r
+ //\r
+ IntRegister(INT_COMP0 + ulComp, pfnHandler);\r
+\r
+ //\r
+ // Enable the interrupt in the interrupt controller.\r
+ //\r
+ IntEnable(INT_COMP0 + ulComp);\r
+\r
+ //\r
+ // Enable the comparator interrupt.\r
+ //\r
+ HWREG(ulBase + COMP_O_INTEN) |= 1 << ulComp;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Unregisters an interrupt handler for a comparator interrupt.\r
+//!\r
+//! \param ulBase is the base address of the comparator module.\r
+//! \param ulComp is the index of the comparator.\r
+//!\r
+//! This function will clear the handler to be called when a comparator\r
+//! interrupt occurs. This will also mask off the interrupt in the interrupt\r
+//! controller so that the interrupt handler no longer is called.\r
+//!\r
+//! \sa IntRegister() for important information about registering interrupt\r
+//! handlers.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+ComparatorIntUnregister(unsigned long ulBase, unsigned long ulComp)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == COMP_BASE);\r
+ ASSERT(ulComp < 3);\r
+\r
+ //\r
+ // Disable the comparator interrupt.\r
+ //\r
+ HWREG(ulBase + COMP_O_INTEN) &= ~(1 << ulComp);\r
+\r
+ //\r
+ // Disable the interrupt in the interrupt controller.\r
+ //\r
+ IntDisable(INT_COMP0 + ulComp);\r
+\r
+ //\r
+ // Unregister the interrupt handler.\r
+ //\r
+ IntUnregister(INT_COMP0 + ulComp);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Enables the comparator interrupt.\r
+//!\r
+//! \param ulBase is the base address of the comparator module.\r
+//! \param ulComp is the index of the comparator.\r
+//!\r
+//! This function enables generation of an interrupt from the specified\r
+//! comparator. Only comparators whose interrupts are enabled can be reflected\r
+//! to the processor.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+ComparatorIntEnable(unsigned long ulBase, unsigned long ulComp)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == COMP_BASE);\r
+ ASSERT(ulComp < 3);\r
+\r
+ //\r
+ // Enable the comparator interrupt.\r
+ //\r
+ HWREG(ulBase + COMP_O_INTEN) |= 1 << ulComp;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Disables the comparator interrupt.\r
+//!\r
+//! \param ulBase is the base address of the comparator module.\r
+//! \param ulComp is the index of the comparator.\r
+//!\r
+//! This function disables generation of an interrupt from the specified\r
+//! comparator. Only comparators whose interrupts are enabled can be reflected\r
+//! to the processor.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+ComparatorIntDisable(unsigned long ulBase, unsigned long ulComp)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == COMP_BASE);\r
+ ASSERT(ulComp < 3);\r
+\r
+ //\r
+ // Disable the comparator interrupt.\r
+ //\r
+ HWREG(ulBase + COMP_O_INTEN) &= ~(1 << ulComp);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Gets the current interrupt status.\r
+//!\r
+//! \param ulBase is the base address of the comparator module.\r
+//! \param ulComp is the index of the comparator.\r
+//! \param bMasked is \b false if the raw interrupt status is required and\r
+//! \b true if the masked interrupt status is required.\r
+//!\r
+//! This returns the interrupt status for the comparator. Either the raw or\r
+//! the masked interrupt status can be returned.\r
+//!\r
+//! \return \b true if the interrupt is asserted and \b false if it is not\r
+//! asserted.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+tBoolean\r
+ComparatorIntStatus(unsigned long ulBase, unsigned long ulComp,\r
+ tBoolean bMasked)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == COMP_BASE);\r
+ ASSERT(ulComp < 3);\r
+\r
+ //\r
+ // Return either the interrupt status or the raw interrupt status as\r
+ // requested.\r
+ //\r
+ if(bMasked)\r
+ {\r
+ return(((HWREG(ulBase + COMP_O_MIS) >> ulComp) & 1) ? true : false);\r
+ }\r
+ else\r
+ {\r
+ return(((HWREG(ulBase + COMP_O_RIS) >> ulComp) & 1) ? true : false);\r
+ }\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Clears a comparator interrupt.\r
+//!\r
+//! \param ulBase is the base address of the comparator module.\r
+//! \param ulComp is the index of the comparator.\r
+//!\r
+//! The comparator interrupt is cleared, so that it no longer asserts. This\r
+//! must be done in the interrupt handler to keep it from being called again\r
+//! immediately upon exit. Note that for a level triggered interrupt, the\r
+//! interrupt cannot be cleared until it stops asserting.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+ComparatorIntClear(unsigned long ulBase, unsigned long ulComp)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == COMP_BASE);\r
+ ASSERT(ulComp < 3);\r
+\r
+ //\r
+ // Clear the interrupt.\r
+ //\r
+ HWREG(ulBase + COMP_O_MIS) = 1 << ulComp;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Close the Doxygen group.\r
+//! @}\r
+//\r
+//*****************************************************************************\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// comp.h - Prototypes for the analog comparator driver.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 991 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __COMP_H__\r
+#define __COMP_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to ComparatorConfigure() as the ulConfig\r
+// parameter. For each group (i.e. COMP_TRIG_xxx, COMP_INT_xxx, etc.), one of\r
+// the values may be selected and ORed together will values from the other\r
+// groups.\r
+//\r
+//*****************************************************************************\r
+#define COMP_TRIG_NONE 0x00000000 // No ADC trigger\r
+#define COMP_TRIG_HIGH 0x00000880 // Trigger when high\r
+#define COMP_TRIG_LOW 0x00000800 // Trigger when low\r
+#define COMP_TRIG_FALL 0x00000820 // Trigger on falling edge\r
+#define COMP_TRIG_RISE 0x00000840 // Trigger on rising edge\r
+#define COMP_TRIG_BOTH 0x00000860 // Trigger on both edges\r
+#define COMP_INT_HIGH 0x00000010 // Interrupt when high\r
+#define COMP_INT_LOW 0x00000000 // Interrupt when low\r
+#define COMP_INT_FALL 0x00000004 // Interrupt on falling edge\r
+#define COMP_INT_RISE 0x00000008 // Interrupt on rising edge\r
+#define COMP_INT_BOTH 0x0000000C // Interrupt on both edges\r
+#define COMP_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin\r
+#define COMP_ASRCP_PIN0 0x00000200 // Comp0+ pin\r
+#define COMP_ASRCP_REF 0x00000400 // Internal voltage reference\r
+#define COMP_OUTPUT_NONE 0x00000000 // No comparator output\r
+#define COMP_OUTPUT_NORMAL 0x00000100 // Comparator output normal\r
+#define COMP_OUTPUT_INVERT 0x00000102 // Comparator output inverted\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to ComparatorSetRef() as the ulRef parameter.\r
+//\r
+//*****************************************************************************\r
+#define COMP_REF_OFF 0x00000000 // Turn off the internal reference\r
+#define COMP_REF_0V 0x00000300 // Internal reference of 0V\r
+#define COMP_REF_0_1375V 0x00000301 // Internal reference of 0.1375V\r
+#define COMP_REF_0_275V 0x00000302 // Internal reference of 0.275V\r
+#define COMP_REF_0_4125V 0x00000303 // Internal reference of 0.4125V\r
+#define COMP_REF_0_55V 0x00000304 // Internal reference of 0.55V\r
+#define COMP_REF_0_6875V 0x00000305 // Internal reference of 0.6875V\r
+#define COMP_REF_0_825V 0x00000306 // Internal reference of 0.825V\r
+#define COMP_REF_0_928125V 0x00000201 // Internal reference of 0.928125V\r
+#define COMP_REF_0_9625V 0x00000307 // Internal reference of 0.9625V\r
+#define COMP_REF_1_03125V 0x00000202 // Internal reference of 1.03125V\r
+#define COMP_REF_1_134375V 0x00000203 // Internal reference of 1.134375V\r
+#define COMP_REF_1_1V 0x00000308 // Internal reference of 1.1V\r
+#define COMP_REF_1_2375V 0x00000309 // Internal reference of 1.2375V\r
+#define COMP_REF_1_340625V 0x00000205 // Internal reference of 1.340625V\r
+#define COMP_REF_1_375V 0x0000030A // Internal reference of 1.375V\r
+#define COMP_REF_1_44375V 0x00000206 // Internal reference of 1.44375V\r
+#define COMP_REF_1_5125V 0x0000030B // Internal reference of 1.5125V\r
+#define COMP_REF_1_546875V 0x00000207 // Internal reference of 1.546875V\r
+#define COMP_REF_1_65V 0x0000030C // Internal reference of 1.65V\r
+#define COMP_REF_1_753125V 0x00000209 // Internal reference of 1.753125V\r
+#define COMP_REF_1_7875V 0x0000030D // Internal reference of 1.7875V\r
+#define COMP_REF_1_85625V 0x0000020A // Internal reference of 1.85625V\r
+#define COMP_REF_1_925V 0x0000030E // Internal reference of 1.925V\r
+#define COMP_REF_1_959375V 0x0000020B // Internal reference of 1.959375V\r
+#define COMP_REF_2_0625V 0x0000030F // Internal reference of 2.0625V\r
+#define COMP_REF_2_165625V 0x0000020D // Internal reference of 2.165625V\r
+#define COMP_REF_2_26875V 0x0000020E // Internal reference of 2.26875V\r
+#define COMP_REF_2_371875V 0x0000020F // Internal reference of 2.371875V\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void ComparatorConfigure(unsigned long ulBase, unsigned long ulComp,\r
+ unsigned long ulConfig);\r
+extern void ComparatorRefSet(unsigned long ulBase, unsigned long ulRef);\r
+extern tBoolean ComparatorValueGet(unsigned long ulBase, unsigned long ulComp);\r
+extern void ComparatorIntRegister(unsigned long ulBase, unsigned long ulComp,\r
+ void (*pfnHandler)(void));\r
+extern void ComparatorIntUnregister(unsigned long ulBase,\r
+ unsigned long ulComp);\r
+extern void ComparatorIntEnable(unsigned long ulBase, unsigned long ulComp);\r
+extern void ComparatorIntDisable(unsigned long ulBase, unsigned long ulComp);\r
+extern tBoolean ComparatorIntStatus(unsigned long ulBase, unsigned long ulComp,\r
+ tBoolean bMasked);\r
+extern void ComparatorIntClear(unsigned long ulBase, unsigned long ulComp);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __COMP_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// cpu.h - Prototypes for the CPU instruction wrapper functions.\r
+//\r
+// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 991 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __CPU_H__\r
+#define __CPU_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes.\r
+//\r
+//*****************************************************************************\r
+extern void CPUcpsid(void);\r
+extern void CPUcpsie(void);\r
+extern void CPUwfi(void);\r
+\r
+#endif // __CPU_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// debug.h - Macros for assisting debug of the driver library.\r
+//\r
+// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 991 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __DEBUG_H__\r
+#define __DEBUG_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototype for the function that is called when an invalid argument is passed\r
+// to an API. This is only used when doing a DEBUG build.\r
+//\r
+//*****************************************************************************\r
+extern void __error__(char *pcFilename, unsigned long ulLine);\r
+\r
+//*****************************************************************************\r
+//\r
+// The ASSERT macro, which does the actual assertion checking. Typically, this\r
+// will be for procedure arguments.\r
+//\r
+//*****************************************************************************\r
+#ifdef DEBUG\r
+#define ASSERT(expr) { \\r
+ if(!(expr)) \\r
+ { \\r
+ __error__(__FILE__, __LINE__); \\r
+ } \\r
+ }\r
+#else\r
+#define ASSERT(expr)\r
+#endif\r
+\r
+#endif // __DEBUG_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// flash.c - Driver for programming the on-chip flash.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 991 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \addtogroup flash_api\r
+//! @{\r
+//\r
+//*****************************************************************************\r
+\r
+#include "../hw_flash.h"\r
+#include "../hw_ints.h"\r
+#include "../hw_memmap.h"\r
+#include "../hw_sysctl.h"\r
+#include "../hw_types.h"\r
+#include "debug.h"\r
+#include "flash.h"\r
+#include "interrupt.h"\r
+\r
+//*****************************************************************************\r
+//\r
+//! Gets the number of processor clocks per micro-second.\r
+//!\r
+//! This function returns the number of clocks per micro-second, as presently\r
+//! known by the flash controller.\r
+//!\r
+//! \return Returns the number of processor clocks per micro-second.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_usecget) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+unsigned long\r
+FlashUsecGet(void)\r
+{\r
+ //\r
+ // Return the number of clocks per micro-second.\r
+ //\r
+ return(HWREG(FLASH_USECRL) + 1);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Sets the number of processor clocks per micro-second.\r
+//!\r
+//! \param ulClocks is the number of processor clocks per micro-second.\r
+//!\r
+//! This function is used to tell the flash controller the number of processor\r
+//! clocks per micro-second. This value must be programmed correctly or the\r
+//! flash most likely will not program correctly; it has no affect on reading\r
+//! flash.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_usecset) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+FlashUsecSet(unsigned long ulClocks)\r
+{\r
+ //\r
+ // Set the number of clocks per micro-second.\r
+ //\r
+ HWREG(FLASH_USECRL) = ulClocks - 1;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Erases a block of flash.\r
+//!\r
+//! \param ulAddress is the start address of the flash block to be erased.\r
+//!\r
+//! This function will erase a 1 kB block of the on-chip flash. After erasing,\r
+//! the block will be filled with 0xFF bytes. Read-only and execute-only\r
+//! blocks cannot be erased.\r
+//!\r
+//! This function will not return until the block has been erased.\r
+//!\r
+//! \return Returns 0 on success, or -1 if an invalid block address was\r
+//! specified or the block is write-protected.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_erase) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+long\r
+FlashErase(unsigned long ulAddress)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(!(ulAddress & (FLASH_ERASE_SIZE - 1)));\r
+\r
+ //\r
+ // Clear the flash access interrupt.\r
+ //\r
+ HWREG(FLASH_FCMISC) = FLASH_FCMISC_ACCESS;\r
+\r
+ //\r
+ // Erase the block.\r
+ //\r
+ HWREG(FLASH_FMA) = ulAddress;\r
+ HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_ERASE;\r
+\r
+ //\r
+ // Wait until the word has been programmed.\r
+ //\r
+ while(HWREG(FLASH_FMC) & FLASH_FMC_ERASE)\r
+ {\r
+ }\r
+\r
+ //\r
+ // Return an error if an access violation occurred.\r
+ //\r
+ if(HWREG(FLASH_FCRIS) & FLASH_FCRIS_ACCESS)\r
+ {\r
+ return(-1);\r
+ }\r
+\r
+ //\r
+ // Success.\r
+ //\r
+ return(0);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Programs flash.\r
+//!\r
+//! \param pulData is a pointer to the data to be programmed.\r
+//! \param ulAddress is the starting address in flash to be programmed. Must\r
+//! be a multiple of four.\r
+//! \param ulCount is the number of bytes to be programmed. Must be a multiple\r
+//! of four.\r
+//!\r
+//! This function will program a sequence of words into the on-chip flash.\r
+//! Programming each location consists of the result of an AND operation\r
+//! of the new data and the existing data; in other words bits that contain\r
+//! 1 can remain 1 or be changed to 0, but bits that are 0 cannot be changed\r
+//! to 1. Therefore, a word can be programmed multiple times as long as these\r
+//! rules are followed; if a program operation attempts to change a 0 bit to\r
+//! a 1 bit, that bit will not have its value changed.\r
+//!\r
+//! Since the flash is programmed one word at a time, the starting address and\r
+//! byte count must both be multiples of four. It is up to the caller to\r
+//! verify the programmed contents, if such verification is required.\r
+//!\r
+//! This function will not return until the data has been programmed.\r
+//!\r
+//! \return Returns 0 on success, or -1 if a programming error is encountered.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_program) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+long\r
+FlashProgram(unsigned long *pulData, unsigned long ulAddress,\r
+ unsigned long ulCount)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(!(ulAddress & 3));\r
+ ASSERT(!(ulCount & 3));\r
+\r
+ //\r
+ // Clear the flash access interrupt.\r
+ //\r
+ HWREG(FLASH_FCMISC) = FLASH_FCMISC_ACCESS;\r
+\r
+ //\r
+ // Loop over the words to be programmed.\r
+ //\r
+ while(ulCount)\r
+ {\r
+ //\r
+ // Program the next word.\r
+ //\r
+ HWREG(FLASH_FMA) = ulAddress;\r
+ HWREG(FLASH_FMD) = *pulData;\r
+ HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_WRITE;\r
+\r
+ //\r
+ // Wait until the word has been programmed.\r
+ //\r
+ while(HWREG(FLASH_FMC) & FLASH_FMC_WRITE)\r
+ {\r
+ }\r
+\r
+ //\r
+ // Increment to the next word.\r
+ //\r
+ pulData++;\r
+ ulAddress += 4;\r
+ ulCount -= 4;\r
+ }\r
+\r
+ //\r
+ // Return an error if an access violation occurred.\r
+ //\r
+ if(HWREG(FLASH_FCRIS) & FLASH_FCRIS_ACCESS)\r
+ {\r
+ return(-1);\r
+ }\r
+\r
+ //\r
+ // Success.\r
+ //\r
+ return(0);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Gets the protection setting for a block of flash.\r
+//!\r
+//! \param ulAddress is the start address of the flash block to be queried.\r
+//!\r
+//! This function will get the current protection for the specified 2 kB block\r
+//! of flash. Each block can be read/write, read-only, or execute-only.\r
+//! Read/write blocks can be read, executed, erased, and programmed. Read-only\r
+//! blocks can be read and executed. Execute-only blocks can only be executed;\r
+//! processor and debugger data reads are not allowed.\r
+//!\r
+//! \return Returns the protection setting for this block. See\r
+//! FlashProtectSet() for possible values.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_protectget) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+tFlashProtection\r
+FlashProtectGet(unsigned long ulAddress)\r
+{\r
+ unsigned long ulFMPRE, ulFMPPE;\r
+\r
+ //\r
+ // Check the argument.\r
+ //\r
+ ASSERT(!(ulAddress & (FLASH_PROTECT_SIZE - 1)));\r
+\r
+ //\r
+ // Read the flash protection register and get the bits that apply to the\r
+ // specified block.\r
+ //\r
+ ulFMPRE = HWREG(FLASH_FMPRE);\r
+ ulFMPPE = HWREG(FLASH_FMPPE);\r
+ switch((((ulFMPRE >> (ulAddress / FLASH_PROTECT_SIZE)) &\r
+ FLASH_FMP_BLOCK_0) << 1) |\r
+ ((ulFMPPE >> (ulAddress / FLASH_PROTECT_SIZE)) & FLASH_FMP_BLOCK_0))\r
+ {\r
+ //\r
+ // This block is marked as execute only (i.e. it can not be erased or\r
+ // programmed, and the only reads allowed are via the instruction fecth\r
+ // interface).\r
+ //\r
+ case 0:\r
+ case 1:\r
+ {\r
+ return(FlashExecuteOnly);\r
+ }\r
+\r
+ //\r
+ // This block is marked as read only (i.e. it can not be erased or\r
+ // programmed).\r
+ //\r
+ case 2:\r
+ {\r
+ return(FlashReadOnly);\r
+ }\r
+\r
+ //\r
+ // This block is read/write; it can be read, erased, and programmed.\r
+ //\r
+ case 3:\r
+ default:\r
+ {\r
+ return(FlashReadWrite);\r
+ }\r
+ }\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Sets the protection setting for a block of flash.\r
+//!\r
+//! \param ulAddress is the start address of the flash block to be protected.\r
+//! \param eProtect is the protection to be applied to the block. Can be one\r
+//! of \b FlashReadWrite, \b FlashReadOnly, or \b FlashExecuteOnly.\r
+//!\r
+//! This function will set the protection for the specified 2 kB block of\r
+//! flash. Blocks which are read/write can be made read-only or execute-only.\r
+//! Blocks which are read-only can be made execute-only. Blocks which are\r
+//! execute-only cannot have their protection modified. Attempts to make the\r
+//! block protection less stringent (i.e. read-only to read/write) will result\r
+//! in a failure (and be prevented by the hardware).\r
+//!\r
+//! Changes to the flash protection are maintained only until the next reset.\r
+//! This allows the application to be executed in the desired flash protection\r
+//! environment to check for inappropriate flash access (via the flash\r
+//! interrupt). To make the flash protection permanent, use the\r
+//! FlashProtectSave() function.\r
+//!\r
+//! \return Returns 0 on success, or -1 if an invalid address or an invalid\r
+//! protection was specified.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_protectset) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+long\r
+FlashProtectSet(unsigned long ulAddress, tFlashProtection eProtect)\r
+{\r
+ unsigned long ulProtectRE, ulProtectPE;\r
+\r
+ //\r
+ // Check the argument.\r
+ //\r
+ ASSERT(!(ulAddress & (FLASH_PROTECT_SIZE - 1)));\r
+ ASSERT((eProtect == FlashReadWrite) || (eProtect == FlashReadOnly) ||\r
+ (eProtect == FlashExecuteOnly));\r
+\r
+ //\r
+ // Convert the address into a block number.\r
+ //\r
+ ulAddress /= FLASH_PROTECT_SIZE;\r
+\r
+ //\r
+ // Get the current protection.\r
+ //\r
+ ulProtectRE = HWREG(FLASH_FMPRE);\r
+ ulProtectPE = HWREG(FLASH_FMPPE);\r
+\r
+ //\r
+ // Set the protection based on the requested proection.\r
+ //\r
+ switch(eProtect)\r
+ {\r
+ //\r
+ // Make this block execute only.\r
+ //\r
+ case FlashExecuteOnly:\r
+ {\r
+ //\r
+ // Turn off the read and program bits for this block.\r
+ //\r
+ ulProtectRE &= ~(FLASH_FMP_BLOCK_0 << ulAddress);\r
+ ulProtectPE &= ~(FLASH_FMP_BLOCK_0 << ulAddress);\r
+\r
+ //\r
+ // We're done handling this protection.\r
+ //\r
+ break;\r
+ }\r
+\r
+ //\r
+ // Make this block read only.\r
+ //\r
+ case FlashReadOnly:\r
+ {\r
+ //\r
+ // The block can not be made read only if it is execute only.\r
+ //\r
+ if(((ulProtectRE >> ulAddress) & FLASH_FMP_BLOCK_0) !=\r
+ FLASH_FMP_BLOCK_0)\r
+ {\r
+ return(-1);\r
+ }\r
+\r
+ //\r
+ // Make this block read only.\r
+ //\r
+ ulProtectPE &= ~(FLASH_FMP_BLOCK_0 << ulAddress);\r
+\r
+ //\r
+ // We're done handling this protection.\r
+ //\r
+ break;\r
+ }\r
+\r
+ //\r
+ // Make this block read/write.\r
+ //\r
+ case FlashReadWrite:\r
+ default:\r
+ {\r
+ //\r
+ // The block can not be made read/write if it is not already\r
+ // read/write.\r
+ //\r
+ if((((ulProtectRE >> ulAddress) & FLASH_FMP_BLOCK_0) !=\r
+ FLASH_FMP_BLOCK_0) ||\r
+ (((ulProtectPE >> ulAddress) & FLASH_FMP_BLOCK_0) !=\r
+ FLASH_FMP_BLOCK_0))\r
+ {\r
+ return(-1);\r
+ }\r
+\r
+ //\r
+ // The block is already read/write, so there is nothing to do.\r
+ //\r
+ return(0);\r
+ }\r
+ }\r
+\r
+ //\r
+ // Set the new protection.\r
+ //\r
+ HWREG(FLASH_FMPRE) = ulProtectRE;\r
+ HWREG(FLASH_FMPPE) = ulProtectPE;\r
+\r
+ //\r
+ // Success.\r
+ //\r
+ return(0);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Saves the flash protection settings.\r
+//!\r
+//! This function will make the currently programmed flash protection settings\r
+//! permanent. This is a non-reversible operation; a chip reset or power cycle\r
+//! will not change the flash protection.\r
+//!\r
+//! This function will not return until the protection has been saved.\r
+//!\r
+//! \return Returns 0 on success, or -1 if a hardware error is encountered.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_protectsave) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+long\r
+FlashProtectSave(void)\r
+{\r
+ //\r
+ // Tell the flash controller to write the flash read protection register.\r
+ //\r
+ HWREG(FLASH_FMA) = 0;\r
+ HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_COMT;\r
+\r
+ //\r
+ // Wait until the write has completed.\r
+ //\r
+ while(HWREG(FLASH_FMC) & FLASH_FMC_COMT)\r
+ {\r
+ }\r
+\r
+ //\r
+ // Tell the flash controller to write the flash program protection\r
+ // register.\r
+ //\r
+ HWREG(FLASH_FMA) = 1;\r
+ HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_COMT;\r
+\r
+ //\r
+ // Wait until the write has completed.\r
+ //\r
+ while(HWREG(FLASH_FMC) & FLASH_FMC_COMT)\r
+ {\r
+ }\r
+\r
+ //\r
+ // Success.\r
+ //\r
+ return(0);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Registers an interrupt handler for the flash interrupt.\r
+//!\r
+//! \param pfnHandler is a pointer to the function to be called when the flash\r
+//! interrupt occurs.\r
+//!\r
+//! This sets the handler to be called when the flash interrupt occurs. The\r
+//! flash controller can generate an interrupt when an invalid flash access\r
+//! occurs, such as trying to program or erase a read-only block, or trying to\r
+//! read from an execute-only block. It can also generate an interrupt when a\r
+//! program or erase operation has completed. The interrupt will be\r
+//! automatically enabled when the handler is registered.\r
+//!\r
+//! \sa IntRegister() for important information about registering interrupt\r
+//! handlers.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+FlashIntRegister(void (*pfnHandler)(void))\r
+{\r
+ //\r
+ // Register the interrupt handler, returning an error if an error occurs.\r
+ //\r
+ IntRegister(INT_FLASH, pfnHandler);\r
+\r
+ //\r
+ // Enable the flash interrupt.\r
+ //\r
+ IntEnable(INT_FLASH);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Unregisters the interrupt handler for the flash interrupt.\r
+//!\r
+//! This function will clear the handler to be called when the flash interrupt\r
+//! occurs. This will also mask off the interrupt in the interrupt controller\r
+//! so that the interrupt handler is no longer called.\r
+//!\r
+//! \sa IntRegister() for important information about registering interrupt\r
+//! handlers.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+FlashIntUnregister(void)\r
+{\r
+ //\r
+ // Disable the interrupt.\r
+ //\r
+ IntDisable(INT_FLASH);\r
+\r
+ //\r
+ // Unregister the interrupt handler.\r
+ //\r
+ IntUnregister(INT_FLASH);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Enables individual flash controller interrupt sources.\r
+//!\r
+//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled.\r
+//! Can be any of the \b FLASH_FCIM_PROGRAM or \b FLASH_FCIM_ACCESS values.\r
+//!\r
+//! Enables the indicated flash controller interrupt sources. Only the sources\r
+//! that are enabled can be reflected to the processor interrupt; disabled\r
+//! sources have no effect on the processor.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+FlashIntEnable(unsigned long ulIntFlags)\r
+{\r
+ //\r
+ // Enable the specified interrupts.\r
+ //\r
+ HWREG(FLASH_FCIM) |= ulIntFlags;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Disables individual flash controller interrupt sources.\r
+//!\r
+//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled.\r
+//! Can be any of the \b FLASH_FCIM_PROGRAM or \b FLASH_FCIM_ACCESS values.\r
+//!\r
+//! Disables the indicated flash controller interrupt sources. Only the\r
+//! sources that are enabled can be reflected to the processor interrupt;\r
+//! disabled sources have no effect on the processor.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+FlashIntDisable(unsigned long ulIntFlags)\r
+{\r
+ //\r
+ // Disable the specified interrupts.\r
+ //\r
+ HWREG(FLASH_FCIM) &= ~(ulIntFlags);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Gets the current interrupt status.\r
+//!\r
+//! \param bMasked is false if the raw interrupt status is required and true if\r
+//! the masked interrupt status is required.\r
+//!\r
+//! This returns the interrupt status for the flash controller. Either the raw\r
+//! interrupt status or the status of interrupts that are allowed to reflect to\r
+//! the processor can be returned.\r
+//!\r
+//! \return The current interrupt status, enumerated as a bit field of\r
+//! \b FLASH_FCMISC_PROGRAM and \b FLASH_FCMISC_ACCESS.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_intgetstatus) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+unsigned long\r
+FlashIntGetStatus(tBoolean bMasked)\r
+{\r
+ //\r
+ // Return either the interrupt status or the raw interrupt status as\r
+ // requested.\r
+ //\r
+ if(bMasked)\r
+ {\r
+ return(HWREG(FLASH_FCMISC));\r
+ }\r
+ else\r
+ {\r
+ return(HWREG(FLASH_FCRIS));\r
+ }\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Clears flash controller interrupt sources.\r
+//!\r
+//! \param ulIntFlags is the bit mask of the interrupt sources to be cleared.\r
+//! Can be any of the \b FLASH_FCMISC_PROGRAM or \b FLASH_FCMISC_ACCESS\r
+//! values.\r
+//!\r
+//! The specified flash controller interrupt sources are cleared, so that they\r
+//! no longer assert. This must be done in the interrupt handler to keep it\r
+//! from being called again immediately upon exit.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+FlashIntClear(unsigned long ulIntFlags)\r
+{\r
+ //\r
+ // Clear the flash interrupt.\r
+ //\r
+ HWREG(FLASH_FCMISC) = ulIntFlags;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Close the Doxygen group.\r
+//! @}\r
+//\r
+//*****************************************************************************\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// flash.h - Prototypes for the flash driver.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 991 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __FLASH_H__\r
+#define __FLASH_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to FlashProtectSet(), and returned by\r
+// FlashProtectGet().\r
+//\r
+//*****************************************************************************\r
+typedef enum\r
+{\r
+ FlashReadWrite, // Flash can be read and written\r
+ FlashReadOnly, // Flash can only be read\r
+ FlashExecuteOnly // Flash can only be executed\r
+}\r
+tFlashProtection;\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern unsigned long FlashUsecGet(void);\r
+extern void FlashUsecSet(unsigned long ulClocks);\r
+extern long FlashErase(unsigned long ulAddress);\r
+extern long FlashProgram(unsigned long *pulData, unsigned long ulAddress,\r
+ unsigned long ulCount);\r
+extern tFlashProtection FlashProtectGet(unsigned long ulAddress);\r
+extern long FlashProtectSet(unsigned long ulAddress,\r
+ tFlashProtection eProtect);\r
+extern long FlashProtectSave(void);\r
+extern void FlashIntRegister(void (*pfnHandler)(void));\r
+extern void FlashIntUnregister(void);\r
+extern void FlashIntEnable(unsigned long ulIntFlags);\r
+extern void FlashIntDisable(unsigned long ulIntFlags);\r
+extern unsigned long FlashIntGetStatus(tBoolean bMasked);\r
+extern void FlashIntClear(unsigned long ulIntFlags);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __FLASH_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// gpio.c - API for GPIO ports\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 991 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \addtogroup gpio_api\r
+//! @{\r
+//\r
+//*****************************************************************************\r
+\r
+#include "../hw_gpio.h"\r
+#include "../hw_ints.h"\r
+#include "../hw_memmap.h"\r
+#include "../hw_types.h"\r
+#include "debug.h"\r
+#include "gpio.h"\r
+#include "interrupt.h"\r
+\r
+//*****************************************************************************\r
+//\r
+//! \internal\r
+//! Get GPIO interrupt number.\r
+//!\r
+//! \param ulPort base address of the selected GPIO port\r
+//!\r
+//! Given a GPIO base address, returns the corresponding interrupt number.\r
+//!\r
+//! \return Returns a GPIO interrupt number, or -1 if \e ulPort is invalid.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_getintnumber) || defined(BUILD_ALL)\r
+long\r
+GPIOGetIntNumber(unsigned long ulPort)\r
+{\r
+ unsigned int ulInt;\r
+\r
+ //\r
+ // Determine the GPIO interrupt number for the given module.\r
+ //\r
+ switch(ulPort)\r
+ {\r
+ case GPIO_PORTA_BASE:\r
+ {\r
+ ulInt = INT_GPIOA;\r
+ break;\r
+ }\r
+\r
+ case GPIO_PORTB_BASE:\r
+ {\r
+ ulInt = INT_GPIOB;\r
+ break;\r
+ }\r
+\r
+ case GPIO_PORTC_BASE:\r
+ {\r
+ ulInt = INT_GPIOC;\r
+ break;\r
+ }\r
+\r
+ case GPIO_PORTD_BASE:\r
+ {\r
+ ulInt = INT_GPIOD;\r
+ break;\r
+ }\r
+\r
+ case GPIO_PORTE_BASE:\r
+ {\r
+ ulInt = INT_GPIOE;\r
+ break;\r
+ }\r
+\r
+ default:\r
+ {\r
+ return(-1);\r
+ }\r
+ }\r
+\r
+ //\r
+ // Return GPIO interrupt number.\r
+ //\r
+ return(ulInt);\r
+}\r
+#else\r
+extern long GPIOGetIntNumber(unsigned long ulPort);\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Sets the direction and mode of the specified pins of the selected\r
+//! GPIO port.\r
+//!\r
+//! \param ulPort base address of the selected GPIO port\r
+//! \param ucPins bit-packed representation of the specified pins\r
+//! \param ulPinIO pin direction and/or mode\r
+//!\r
+//! This function will set the specified pins on the selected GPIO port\r
+//! as either an input or output under software control, or it will set the\r
+//! pin to be under hardware control.\r
+//!\r
+//! The parameter \e ulPinIO is an enumerated data type that can be one of\r
+//! the following values:\r
+//!\r
+//! - \b GPIO_DIR_MODE_IN\r
+//! - \b GPIO_DIR_MODE_OUT\r
+//! - \b GPIO_DIR_MODE_HW\r
+//!\r
+//! where \b GPIO_DIR_MODE_IN specifies that the pin will be programmed as\r
+//! a software controlled input, \b GPIO_DIR_MODE_OUT specifies that the pin\r
+//! will be programmed as a software controlled output, and\r
+//! \b GPIO_DIR_MODE_HW specifies that the pin will be placed under\r
+//! hardware control.\r
+//!\r
+//! The pins are specified using a bit-packed byte, where each bit that is\r
+//! set identifies the pin to be accessed, and where bit 0 of the byte\r
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, etc.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_dirmodeset) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+GPIODirModeSet(unsigned long ulPort, unsigned char ucPins,\r
+ unsigned long ulPinIO)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) ||\r
+ (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) ||\r
+ (ulPort == GPIO_PORTE_BASE));\r
+ ASSERT((ulPinIO == GPIO_DIR_MODE_IN) || (ulPinIO == GPIO_DIR_MODE_OUT) ||\r
+ (ulPinIO == GPIO_DIR_MODE_HW));\r
+\r
+ //\r
+ // Set the pin direction and mode.\r
+ //\r
+ HWREG(ulPort + GPIO_O_DIR) = ((ulPinIO & 1) ?\r
+ (HWREG(ulPort + GPIO_O_DIR) | ucPins) :\r
+ (HWREG(ulPort + GPIO_O_DIR) & ~(ucPins)));\r
+ HWREG(ulPort + GPIO_O_AFSEL) = ((ulPinIO & 2) ?\r
+ (HWREG(ulPort + GPIO_O_AFSEL) | ucPins) :\r
+ (HWREG(ulPort + GPIO_O_AFSEL) &\r
+ ~(ucPins)));\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Gets the direction and mode of a specified pin of the selected\r
+//! GPIO port.\r
+//!\r
+//! \param ulPort base address of the selected GPIO port\r
+//! \param ucPin pin number of the specified pin, relative to the selected\r
+//! GPIO port.\r
+//!\r
+//! This function gets the direction and control mode for a specified pin on\r
+//! the selected GPIO port. The pin can be configured as either an input or\r
+//! output under software control, or it can be under hardware control. The\r
+//! type of control and direction are returned as an enumerated data type.\r
+//!\r
+//! \return Returns one of the enumerated data types described for\r
+//! GPIODirModeSet().\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_dirmodeget) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+unsigned long\r
+GPIODirModeGet(unsigned long ulPort, unsigned char ucPin)\r
+{\r
+ unsigned long ulDir, ulAFSEL;\r
+\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) ||\r
+ (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) ||\r
+ (ulPort == GPIO_PORTE_BASE));\r
+ ASSERT(ucPin < 8);\r
+\r
+ //\r
+ // Convert from a pin number to a bit position.\r
+ //\r
+ ucPin = 1 << ucPin;\r
+\r
+ //\r
+ // Return the pin direction and mode.\r
+ //\r
+ ulDir = HWREG(ulPort + GPIO_O_DIR);\r
+ ulAFSEL = HWREG(ulPort + GPIO_O_AFSEL);\r
+ return(((ulDir & ucPin) ? 1 : 0) | ((ulAFSEL & ucPin) ? 2 : 0));\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Sets the interrupt type for the specified pins of the selected GPIO\r
+//! port.\r
+//!\r
+//! \param ulPort base address of the selected GPIO port\r
+//! \param ucPins bit-packed representation of the specified pins\r
+//! \param ulIntType specifies the type of interrupt trigger mechanism\r
+//!\r
+//! This function sets up the various interrupt trigger mechanisms for the\r
+//! specified pins on the selected GPIO port.\r
+//!\r
+//! The parameter \e ulIntType is an enumerated data type that can be one of\r
+//! the following values:\r
+//!\r
+//! - \b GPIO_FALLING_EDGE\r
+//! - \b GPIO_RISING_EDGE\r
+//! - \b GPIO_BOTH_EDGES\r
+//! - \b GPIO_LOW_LEVEL\r
+//! - \b GPIO_HIGH_LEVEL\r
+//!\r
+//! where the different values describe the interrupt detection mechanism\r
+//! (edge or level) and the particular triggering event (falling, rising,\r
+//! or both edges for edge detect, low or high for level detect).\r
+//!\r
+//! The pins are specified using a bit-packed byte, where each bit that is\r
+//! set identifies the pin to be accessed, and where bit 0 of the byte\r
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, etc.\r
+//!\r
+//! \note In order to avoid any spurious interrupts, the user must\r
+//! ensure that the GPIO inputs remain stable for the duration of\r
+//! this function.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_inttypeset) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins,\r
+ unsigned long ulIntType)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) ||\r
+ (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) ||\r
+ (ulPort == GPIO_PORTE_BASE));\r
+ ASSERT((ulIntType == GPIO_FALLING_EDGE) ||\r
+ (ulIntType == GPIO_RISING_EDGE) ||\r
+ (ulIntType == GPIO_BOTH_EDGES) ||\r
+ (ulIntType == GPIO_LOW_LEVEL) ||\r
+ (ulIntType == GPIO_HIGH_LEVEL));\r
+\r
+ //\r
+ // Set the pin interrupt type.\r
+ //\r
+ HWREG(ulPort + GPIO_O_IBE) = ((ulIntType & 1) ?\r
+ (HWREG(ulPort + GPIO_O_IBE) | ucPins) :\r
+ (HWREG(ulPort + GPIO_O_IBE) & ~(ucPins)));\r
+ HWREG(ulPort + GPIO_O_IS) = ((ulIntType & 2) ?\r
+ (HWREG(ulPort + GPIO_O_IS) | ucPins) :\r
+ (HWREG(ulPort + GPIO_O_IS) & ~(ucPins)));\r
+ HWREG(ulPort + GPIO_O_IEV) = ((ulIntType & 4) ?\r
+ (HWREG(ulPort + GPIO_O_IEV) | ucPins) :\r
+ (HWREG(ulPort + GPIO_O_IEV) & ~(ucPins)));\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Gets the interrupt type for the specified pin of the selected GPIO\r
+//! port.\r
+//!\r
+//! \param ulPort base address of the selected GPIO port\r
+//! \param ucPin pin number of the specified pin, relative to the selected\r
+//! GPIO port.\r
+//!\r
+//! This function gets the interrupt type for a specified pin on the selected\r
+//! GPIO port. The pin can be configured as a falling edge, rising edge, or\r
+//! both edge detected interrupt, or it can be configured as a low level or\r
+//! high level detected interrupt. The type of interrupt detection mechanism\r
+//! is returned as an enumerated data type.\r
+//!\r
+//! \return Returns one of the enumerated data types described for\r
+//! GPIOIntTypeSet().\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_inttypeget) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+unsigned long\r
+GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin)\r
+{\r
+ unsigned long ulIBE, ulIS, ulIEV;\r
+\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) ||\r
+ (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) ||\r
+ (ulPort == GPIO_PORTE_BASE));\r
+ ASSERT(ucPin < 8);\r
+\r
+ //\r
+ // Convert from a pin number to a bit position.\r
+ //\r
+ ucPin = 1 << ucPin;\r
+\r
+ //\r
+ // Return the pin interrupt type.\r
+ //\r
+ ulIBE = HWREG(ulPort + GPIO_O_IBE);\r
+ ulIS = HWREG(ulPort + GPIO_O_IS);\r
+ ulIEV = HWREG(ulPort + GPIO_O_IEV);\r
+ return(((ulIBE & ucPin) ? 1 : 0) | ((ulIS & ucPin) ? 2 : 0) |\r
+ ((ulIEV & ucPin) ? 4 : 0));\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Sets the pad configuration for the specified pins of the selected GPIO\r
+//! port.\r
+//!\r
+//! \param ulPort is the base address of the GPIO port.\r
+//! \param ucPins bit-packed representation of the specified pins.\r
+//! \param ulStrength specifies the output drive strength.\r
+//! \param ulPinType specifies the pin type.\r
+//!\r
+//! This function sets the drive strength and type for the specified pins\r
+//! on the selected GPIO port. For pins configured as input ports, the\r
+//! pad is configured as requested, but the only real effect on the input\r
+//! is the configuration of the pull-up or pull-down termination.\r
+//!\r
+//! The parameter \e ulStrength can be one of the following values:\r
+//!\r
+//! - \b GPIO_STRENGTH_2MA\r
+//! - \b GPIO_STRENGTH_4MA\r
+//! - \b GPIO_STRENGTH_8MA\r
+//! - \b GPIO_STRENGTH_8MA_SC\r
+//!\r
+//! where \b GPIO_STRENGTH_xMA specifies either 2, 4, or 8 mA output drive\r
+//! strength, and \b GPIO_OUT_STRENGTH_8MA_SC specifies 8 mA output drive with\r
+//! slew control.\r
+//!\r
+//! The parameter \e ulPinType can be one of the following values:\r
+//!\r
+//! - \b GPIO_PIN_TYPE_STD\r
+//! - \b GPIO_PIN_TYPE_STD_WPU\r
+//! - \b GPIO_PIN_TYPE_STD_WPD\r
+//! - \b GPIO_PIN_TYPE_OD\r
+//! - \b GPIO_PIN_TYPE_OD_WPU\r
+//! - \b GPIO_PIN_TYPE_OD_WPD\r
+//! - \b GPIO_PIN_TYPE_ANALOG\r
+//!\r
+//! where \b GPIO_PIN_TYPE_STD* specifies a push-pull pin, \b GPIO_PIN_TYPE_OD*\r
+//! specifies an open-drain pin, \b *_WPU specifies a weak pull-up, \b *_WPD\r
+//! specifies a weak pull-down, and \b GPIO_PIN_TYPE_ANALOG specifies an\r
+//! analog input (for the comparators).\r
+//!\r
+//! The pins are specified using a bit-packed byte, where each bit that is\r
+//! set identifies the pin to be accessed, and where bit 0 of the byte\r
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, etc.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_padconfigset) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins,\r
+ unsigned long ulStrength, unsigned long ulPinType)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) ||\r
+ (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) ||\r
+ (ulPort == GPIO_PORTE_BASE));\r
+ ASSERT((ulStrength == GPIO_STRENGTH_2MA) ||\r
+ (ulStrength == GPIO_STRENGTH_4MA) ||\r
+ (ulStrength == GPIO_STRENGTH_8MA) ||\r
+ (ulStrength == GPIO_STRENGTH_8MA_SC));\r
+ ASSERT((ulPinType == GPIO_PIN_TYPE_STD) ||\r
+ (ulPinType == GPIO_PIN_TYPE_STD_WPU) ||\r
+ (ulPinType == GPIO_PIN_TYPE_STD_WPD) ||\r
+ (ulPinType == GPIO_PIN_TYPE_OD) ||\r
+ (ulPinType == GPIO_PIN_TYPE_OD_WPU) ||\r
+ (ulPinType == GPIO_PIN_TYPE_OD_WPD) ||\r
+ (ulPinType == GPIO_PIN_TYPE_ANALOG))\r
+\r
+ //\r
+ // Set the output drive strength.\r
+ //\r
+ HWREG(ulPort + GPIO_O_DR2R) = ((ulStrength & 1) ?\r
+ (HWREG(ulPort + GPIO_O_DR2R) | ucPins) :\r
+ (HWREG(ulPort + GPIO_O_DR2R) & ~(ucPins)));\r
+ HWREG(ulPort + GPIO_O_DR4R) = ((ulStrength & 2) ?\r
+ (HWREG(ulPort + GPIO_O_DR4R) | ucPins) :\r
+ (HWREG(ulPort + GPIO_O_DR4R) & ~(ucPins)));\r
+ HWREG(ulPort + GPIO_O_DR8R) = ((ulStrength & 4) ?\r
+ (HWREG(ulPort + GPIO_O_DR8R) | ucPins) :\r
+ (HWREG(ulPort + GPIO_O_DR8R) & ~(ucPins)));\r
+ HWREG(ulPort + GPIO_O_SLR) = ((ulStrength & 8) ?\r
+ (HWREG(ulPort + GPIO_O_SLR) | ucPins) :\r
+ (HWREG(ulPort + GPIO_O_SLR) & ~(ucPins)));\r
+\r
+ //\r
+ // Set the pin type.\r
+ //\r
+ HWREG(ulPort + GPIO_O_ODR) = ((ulPinType & 1) ?\r
+ (HWREG(ulPort + GPIO_O_ODR) | ucPins) :\r
+ (HWREG(ulPort + GPIO_O_ODR) & ~(ucPins)));\r
+ HWREG(ulPort + GPIO_O_PUR) = ((ulPinType & 2) ?\r
+ (HWREG(ulPort + GPIO_O_PUR) | ucPins) :\r
+ (HWREG(ulPort + GPIO_O_PUR) & ~(ucPins)));\r
+ HWREG(ulPort + GPIO_O_PDR) = ((ulPinType & 4) ?\r
+ (HWREG(ulPort + GPIO_O_PDR) | ucPins) :\r
+ (HWREG(ulPort + GPIO_O_PDR) & ~(ucPins)));\r
+ HWREG(ulPort + GPIO_O_DEN) = ((ulPinType & 8) ?\r
+ (HWREG(ulPort + GPIO_O_DEN) | ucPins) :\r
+ (HWREG(ulPort + GPIO_O_DEN) & ~(ucPins)));\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Gets the pad configuration for the specified pin of the selected GPIO\r
+//! port.\r
+//!\r
+//! \param ulPort base address of the selected GPIO port\r
+//! \param ucPin pin number of the specified pin, relative to the selected\r
+//! GPIO port.\r
+//! \param pulStrength pointer to storage for the output drive strength\r
+//! \param pulPinType pointer to storage for the output drive type\r
+//!\r
+//! This function gets the pad configuration for a specified pin on the\r
+//! selected GPIO port. The values returned in \e eStrength and \e eOutType\r
+//! correspond to the values used in GPIOPadConfigSet(). This function also\r
+//! works for pins configured as input pins; however, the only meaningful\r
+//! data returned is whether the pin is terminated with a pull-up or\r
+//! down resistor.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_padconfigget) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin,\r
+ unsigned long *pulStrength, unsigned long *pulPinType)\r
+{\r
+ unsigned long ulTemp1, ulTemp2, ulTemp3, ulTemp4;\r
+\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) ||\r
+ (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) ||\r
+ (ulPort == GPIO_PORTE_BASE));\r
+ ASSERT(ucPin < 8);\r
+\r
+ //\r
+ // Convert from a pin number to a bit position.\r
+ //\r
+ ucPin = (1 << ucPin);\r
+\r
+ //\r
+ // Get the drive strength for this pin.\r
+ //\r
+ ulTemp1 = HWREG(ulPort + GPIO_O_DR2R);\r
+ ulTemp2 = HWREG(ulPort + GPIO_O_DR4R);\r
+ ulTemp3 = HWREG(ulPort + GPIO_O_DR8R);\r
+ ulTemp4 = HWREG(ulPort + GPIO_O_SLR);\r
+ *pulStrength = (((ulTemp1 & ucPin) ? 1 : 0) | ((ulTemp2 & ucPin) ? 2 : 0) |\r
+ ((ulTemp3 & ucPin) ? 4 : 0) | ((ulTemp4 & ucPin) ? 8 : 0));\r
+\r
+ //\r
+ // Get the pin type.\r
+ //\r
+ ulTemp1 = HWREG(ulPort + GPIO_O_ODR);\r
+ ulTemp2 = HWREG(ulPort + GPIO_O_PUR);\r
+ ulTemp3 = HWREG(ulPort + GPIO_O_PDR);\r
+ ulTemp4 = HWREG(ulPort + GPIO_O_DEN);\r
+ *pulPinType = (((ulTemp1 & ucPin) ? 1 : 0) | ((ulTemp2 & ucPin) ? 2 : 0) |\r
+ ((ulTemp3 & ucPin) ? 4 : 0) | ((ulTemp4 & ucPin) ? 8 : 0));\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Enables interrupts for the specified pins of the selected GPIO port.\r
+//!\r
+//! \param ulPort base address of the selected GPIO port\r
+//! \param ucPins bit-packed representation of the specified pins\r
+//!\r
+//! Unmasks the interrupt for the specified pins.\r
+//!\r
+//! The pins are specified using a bit-packed byte, where each bit that is\r
+//! set identifies the pin to be accessed, and where bit 0 of the byte\r
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, etc.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_pinintenable) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) ||\r
+ (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) ||\r
+ (ulPort == GPIO_PORTE_BASE));\r
+\r
+ //\r
+ // Enable the interrupts.\r
+ //\r
+ HWREG(ulPort + GPIO_O_IM) |= ucPins;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Disables interrupts for the specified pins of the selected GPIO port.\r
+//!\r
+//! \param ulPort base address of the selected GPIO port\r
+//! \param ucPins bit-packed representation of the specified pins\r
+//!\r
+//! Masks the interrupt for the specified pins.\r
+//!\r
+//! The pins are specified using a bit-packed byte, where each bit that is\r
+//! set identifies the pin to be accessed, and where bit 0 of the byte\r
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, etc.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_pinintdisable) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) ||\r
+ (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) ||\r
+ (ulPort == GPIO_PORTE_BASE));\r
+\r
+ //\r
+ // Disable the interrupts.\r
+ //\r
+ HWREG(ulPort + GPIO_O_IM) &= ~(ucPins);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Gets interrupt status for all the pins of the selected GPIO port.\r
+//!\r
+//! \param ulPort base address of the selected GPIO port\r
+//! \param bMasked specifies whether masked or raw interrupt\r
+//! status is returned\r
+//!\r
+//! If \e bMasked is set as \b true, then the masked interrupt status is\r
+//! returned; otherwise, the raw interrupt status will be returned.\r
+//!\r
+//! \return Returns a bit-packed byte, where each bit that is set identifies\r
+//! an active masked or raw interrupt, and where bit 0 of the byte\r
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, etc. Bits\r
+//! 31:8 should be ignored.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_pinintstatus) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+long\r
+GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) ||\r
+ (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) ||\r
+ (ulPort == GPIO_PORTE_BASE));\r
+\r
+ //\r
+ // Return the interrupt status.\r
+ //\r
+ if(bMasked)\r
+ {\r
+ return(HWREG(ulPort + GPIO_O_MIS));\r
+ }\r
+ else\r
+ {\r
+ return(HWREG(ulPort + GPIO_O_RIS));\r
+ }\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Clears the interrupt for the specified pins of the selected GPIO port.\r
+//!\r
+//! \param ulPort base address of the selected GPIO port\r
+//! \param ucPins bit-packed representation of the specified pins\r
+//!\r
+//! Clears the interrupt for the specified pins.\r
+//!\r
+//! The pins are specified using a bit-packed byte, where each bit that is\r
+//! set identifies the pin to be accessed, and where bit 0 of the byte\r
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, etc.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_pinintclear) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) ||\r
+ (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) ||\r
+ (ulPort == GPIO_PORTE_BASE));\r
+\r
+ //\r
+ // Clear the interrupts.\r
+ //\r
+ HWREG(ulPort + GPIO_O_ICR) = ucPins;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Registers an interrupt handler for the selected GPIO port.\r
+//!\r
+//! \param ulPort base address of the selected GPIO port\r
+//! \param pfIntHandler pointer to the GPIO port interrupt handling function\r
+//!\r
+//! This function will ensure that the interrupt handler specified by \e\r
+//! pfIntHandler is called when an interrupt is detected from the selected\r
+//! GPIO port. This function will also enable the corresponding GPIO\r
+//! interrupt in the interrupt controller; individual pin interrupts and\r
+//! interrupt sources must be enabled with GPIOPinIntEnable().\r
+//!\r
+//! \sa IntRegister() for important information about registering interrupt\r
+//! handlers.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_portintregister) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+GPIOPortIntRegister(unsigned long ulPort, void (*pfIntHandler)(void))\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) ||\r
+ (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) ||\r
+ (ulPort == GPIO_PORTE_BASE));\r
+\r
+ //\r
+ // Get the interrupt number associated with the specified GPIO.\r
+ //\r
+ ulPort = GPIOGetIntNumber(ulPort);\r
+\r
+ //\r
+ // Register the interrupt handler.\r
+ //\r
+ IntRegister(ulPort, pfIntHandler);\r
+\r
+ //\r
+ // Enable the GPIO interrupt.\r
+ //\r
+ IntEnable(ulPort);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Removes an interrupt handler for the selected GPIO port.\r
+//!\r
+//! \param ulPort base address of the selected GPIO port\r
+//!\r
+//! This function will unregister the interrupt handler for the specified\r
+//! GPIO port. This function will also disable the corresponding\r
+//! GPIO port interrupt in the interrupt controller; individual GPIO interrupts\r
+//! and interrupt sources must be disabled with GPIOPinIntDisable().\r
+//!\r
+//! \sa IntRegister() for important information about registering interrupt\r
+//! handlers.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_portintunregister) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+GPIOPortIntUnregister(unsigned long ulPort)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) ||\r
+ (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) ||\r
+ (ulPort == GPIO_PORTE_BASE));\r
+\r
+ //\r
+ // Get the interrupt number associated with the specified GPIO.\r
+ //\r
+ ulPort = GPIOGetIntNumber(ulPort);\r
+\r
+ //\r
+ // Disable the GPIO interrupt.\r
+ //\r
+ IntDisable(ulPort);\r
+\r
+ //\r
+ // Unregister the interrupt handler.\r
+ //\r
+ IntUnregister(ulPort);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Reads the values present at the specified pins of the selected GPIO port.\r
+//!\r
+//! \param ulPort base address of the selected GPIO port\r
+//! \param ucPins bit-packed representation of the specified pins\r
+//!\r
+//! The values at the specified pins are read, as specified by \e ucPins.\r
+//! Values are returned for both input and output pins, and the value\r
+//! for pins that are not specified by \e ucPins are set to 0.\r
+//!\r
+//! The pins are specified using a bit-packed byte, where each bit that is\r
+//! set identifies the pin to be accessed, and where bit 0 of the byte\r
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, etc.\r
+//!\r
+//! \return Returns a bit-packed byte providing the state of the specified\r
+//! pin, where bit 0 of the byte represents GPIO port pin 0, bit 1 represents\r
+//! GPIO port pin 1, etc. Any bit that is not specified by \e ucPins\r
+//! is returned as a 0. Bits 31:8 should be ignored.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_pinread) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+long\r
+GPIOPinRead(unsigned long ulPort, unsigned char ucPins)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) ||\r
+ (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) ||\r
+ (ulPort == GPIO_PORTE_BASE));\r
+\r
+ //\r
+ // Return the pin value(s).\r
+ //\r
+ return(HWREG(ulPort + (GPIO_O_DATA + (ucPins << 2))));\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Writes a value at the specified pins of the selected GPIO port.\r
+//!\r
+//! \param ulPort base address of the selected GPIO port\r
+//! \param ucPins bit-packed representation of the specified pins\r
+//! \param ucVal value to write to the specified pins\r
+//!\r
+//! Writes the corresponding bit values to the output pins specified\r
+//! by \e ucPins. Writing to a pin configured as an input pin has no\r
+//! effect.\r
+//!\r
+//! The pins are specified using a bit-packed byte, where each bit that is\r
+//! set identifies the pin to be accessed, and where bit 0 of the byte\r
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, etc.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_pinwrite) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+GPIOPinWrite(unsigned long ulPort, unsigned char ucPins, unsigned char ucVal)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) ||\r
+ (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) ||\r
+ (ulPort == GPIO_PORTE_BASE));\r
+\r
+ //\r
+ // Write the pins.\r
+ //\r
+ HWREG(ulPort + (GPIO_O_DATA + (ucPins << 2))) = ucVal;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Configures pin(s) for use as an analog comparator input.\r
+//!\r
+//! \param ulPort base address of the selected GPIO port\r
+//! \param ucPins bit-packed representation of the specified pins\r
+//!\r
+//! The analog comparator input pins must be properly configured for the analog\r
+//! comparator to function correctly. This function provides the proper\r
+//! configuration for those pins.\r
+//!\r
+//! \note This cannot be used to turn any pin into an analog comparator input;\r
+//! it only configures an analog comparator pin for proper operation.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_pintypecomparator) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) ||\r
+ (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) ||\r
+ (ulPort == GPIO_PORTE_BASE));\r
+\r
+ //\r
+ // Make the pin(s) be inputs.\r
+ //\r
+ GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_IN);\r
+\r
+ //\r
+ // Set the pad(s) for analog operation.\r
+ //\r
+ GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_ANALOG);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Configures pin(s) for use by the I2C peripheral.\r
+//!\r
+//! \param ulPort base address of the selected GPIO port\r
+//! \param ucPins bit-packed representation of the specified pins\r
+//!\r
+//! The I2C pins must be properly configured for the I2C peripheral to function\r
+//! correctly. This function provides the proper configuration for those pins.\r
+//!\r
+//! \note This cannot be used to turn any pin into an I2C pin; it only\r
+//! configures an I2C pin for proper operation.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_pintypei2c) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) ||\r
+ (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) ||\r
+ (ulPort == GPIO_PORTE_BASE));\r
+\r
+ //\r
+ // Make the pin(s) be peripheral controlled.\r
+ //\r
+ GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW);\r
+\r
+ //\r
+ // Set the pad(s) for open-drain operation with a weak pull-up.\r
+ //\r
+ GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_OD_WPU);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Configures pin(s) for use by the PWM peripheral.\r
+//!\r
+//! \param ulPort base address of the selected GPIO port\r
+//! \param ucPins bit-packed representation of the specified pins\r
+//!\r
+//! The PWM pins must be properly configured for the PWM peripheral to function\r
+//! correctly. This function provides a typical configuration for those pins;\r
+//! other configurations may work as well depending upon the board setup (for\r
+//! example, using the on-chip pull-ups).\r
+//!\r
+//! \note This cannot be used to turn any pin into a PWM pin; it only\r
+//! configures a PWM pin for proper operation.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_pintypepwm) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+GPIOPinTypePWM(unsigned long ulPort, unsigned char ucPins)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) ||\r
+ (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) ||\r
+ (ulPort == GPIO_PORTE_BASE));\r
+\r
+ //\r
+ // Make the pin(s) be peripheral controlled.\r
+ //\r
+ GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW);\r
+\r
+ //\r
+ // Set the pad(s) for standard push-pull operation.\r
+ //\r
+ GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Configures pin(s) for use by the QEI peripheral.\r
+//!\r
+//! \param ulPort base address of the selected GPIO port\r
+//! \param ucPins bit-packed representation of the specified pins\r
+//!\r
+//! The QEI pins must be properly configured for the QEI peripheral to function\r
+//! correctly. This function provides a typical configuration for those pins;\r
+//! other configurations may work as well depending upon the board setup (for\r
+//! example, not using the on-chip pull-ups).\r
+//!\r
+//! \note This cannot be used to turn any pin into a QEI pin; it only\r
+//! configures a QEI pin for proper operation.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_pintypeqei) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+GPIOPinTypeQEI(unsigned long ulPort, unsigned char ucPins)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) ||\r
+ (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) ||\r
+ (ulPort == GPIO_PORTE_BASE));\r
+\r
+ //\r
+ // Make the pin(s) be peripheral controlled.\r
+ //\r
+ GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW);\r
+\r
+ //\r
+ // Set the pad(s) for standard push-pull operation with a weak pull-up.\r
+ //\r
+ GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD_WPU);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Configures pin(s) for use by the SSI peripheral.\r
+//!\r
+//! \param ulPort base address of the selected GPIO port\r
+//! \param ucPins bit-packed representation of the specified pins\r
+//!\r
+//! The SSI pins must be properly configured for the SSI peripheral to function\r
+//! correctly. This function provides a typical configuration for those pins;\r
+//! other configurations may work as well depending upon the board setup (for\r
+//! example, using the on-chip pull-ups).\r
+//!\r
+//! \note This cannot be used to turn any pin into a SSI pin; it only\r
+//! configures a SSI pin for proper operation.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_pintypessi) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) ||\r
+ (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) ||\r
+ (ulPort == GPIO_PORTE_BASE));\r
+\r
+ //\r
+ // Make the pin(s) be peripheral controlled.\r
+ //\r
+ GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW);\r
+\r
+ //\r
+ // Set the pad(s) for standard push-pull operation.\r
+ //\r
+ GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Configures pin(s) for use by the Timer peripheral.\r
+//!\r
+//! \param ulPort base address of the selected GPIO port\r
+//! \param ucPins bit-packed representation of the specified pins\r
+//!\r
+//! The CCP pins must be properly configured for the timer peripheral to\r
+//! function correctly. This function provides a typical configuration for\r
+//! those pins; other configurations may work as well depending upon the board\r
+//! setup (for example, using the on-chip pull-ups).\r
+//!\r
+//! \note This cannot be used to turn any pin into a timer pin; it only\r
+//! configures a timer pin for proper operation.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_pintypetimer) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) ||\r
+ (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) ||\r
+ (ulPort == GPIO_PORTE_BASE));\r
+\r
+ //\r
+ // Make the pin(s) be peripheral controlled.\r
+ //\r
+ GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW);\r
+\r
+ //\r
+ // Set the pad(s) for standard push-pull operation.\r
+ //\r
+ GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Configures pin(s) for use by the UART peripheral.\r
+//!\r
+//! \param ulPort base address of the selected GPIO port\r
+//! \param ucPins bit-packed representation of the specified pins\r
+//!\r
+//! The UART pins must be properly configured for the UART peripheral to\r
+//! function correctly. This function provides a typical configuration for\r
+//! those pins; other configurations may work as well depending upon the board\r
+//! setup (for example, using the on-chip pull-ups).\r
+//!\r
+//! \note This cannot be used to turn any pin into a UART pin; it only\r
+//! configures a UART pin for proper operation.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_pintypeuart) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) ||\r
+ (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) ||\r
+ (ulPort == GPIO_PORTE_BASE));\r
+\r
+ //\r
+ // Make the pin(s) be peripheral controlled.\r
+ //\r
+ GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW);\r
+\r
+ //\r
+ // Set the pad(s) for standard push-pull operation.\r
+ //\r
+ GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Close the Doxygen group.\r
+//! @}\r
+//\r
+//*****************************************************************************\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// gpio.h - Defines and Macros for GPIO API.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 991 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __GPIO_H__\r
+#define __GPIO_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// The following values define the bit field for the ucPins argument to several\r
+// of the APIs.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_PIN_0 0x00000001 // GPIO pin 0\r
+#define GPIO_PIN_1 0x00000002 // GPIO pin 1\r
+#define GPIO_PIN_2 0x00000004 // GPIO pin 2\r
+#define GPIO_PIN_3 0x00000008 // GPIO pin 3\r
+#define GPIO_PIN_4 0x00000010 // GPIO pin 4\r
+#define GPIO_PIN_5 0x00000020 // GPIO pin 5\r
+#define GPIO_PIN_6 0x00000040 // GPIO pin 6\r
+#define GPIO_PIN_7 0x00000080 // GPIO pin 7\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to GPIODirModeSet as the ulPinIO parameter, and\r
+// returned from GPIODirModeGet.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input\r
+#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output\r
+#define GPIO_DIR_MODE_HW 0x00000002 // Pin is a peripheral function\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, and\r
+// returned from GPIOIntTypeGet.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge\r
+#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge\r
+#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges\r
+#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level\r
+#define GPIO_HIGH_LEVEL 0x00000007 // Interrupt on high level\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to GPIOPadConfigSet as the ulStrength parameter,\r
+// and returned by GPIOPadConfigGet in the *pulStrength parameter.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_STRENGTH_2MA 0x00000001 // 2mA drive strength\r
+#define GPIO_STRENGTH_4MA 0x00000002 // 4mA drive strength\r
+#define GPIO_STRENGTH_8MA 0x00000004 // 8mA drive strength\r
+#define GPIO_STRENGTH_8MA_SC 0x0000000C // 8mA drive with slew rate control\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to GPIOPadConfigSet as the ulPadType parameter,\r
+// and returned by GPIOPadConfigGet in the *pulPadType parameter.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_PIN_TYPE_STD 0x00000008 // Push-pull\r
+#define GPIO_PIN_TYPE_STD_WPU 0x0000000A // Push-pull with weak pull-up\r
+#define GPIO_PIN_TYPE_STD_WPD 0x0000000C // Push-pull with weak pull-down\r
+#define GPIO_PIN_TYPE_OD 0x00000009 // Open-drain\r
+#define GPIO_PIN_TYPE_OD_WPU 0x0000000B // Open-drain with weak pull-up\r
+#define GPIO_PIN_TYPE_OD_WPD 0x0000000D // Open-drain with weak pull-down\r
+#define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void GPIODirModeSet(unsigned long ulPort, unsigned char ucPins,\r
+ unsigned long ulPinIO);\r
+extern unsigned long GPIODirModeGet(unsigned long ulPort, unsigned char ucPin);\r
+extern void GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins,\r
+ unsigned long ulIntType);\r
+extern unsigned long GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin);\r
+extern void GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins,\r
+ unsigned long ulStrength,\r
+ unsigned long ulPadType);\r
+extern void GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin,\r
+ unsigned long *pulStrength,\r
+ unsigned long *pulPadType);\r
+extern void GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins);\r
+extern long GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked);\r
+extern void GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPortIntRegister(unsigned long ulPort,\r
+ void (*pfIntHandler)(void));\r
+extern void GPIOPortIntUnregister(unsigned long ulPort);\r
+extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins,\r
+ unsigned char ucVal);\r
+extern void GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinTypePWM(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinTypeQEI(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __GPIO_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_adc.h - Macros used when accessing the ADC hardware.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 991 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_ADC_H__\r
+#define __HW_ADC_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the ADC registers.\r
+//\r
+//*****************************************************************************\r
+#define ADC_O_ACTSS 0x00000000 // Active sample register\r
+#define ADC_O_RIS 0x00000004 // Raw interrupt status register\r
+#define ADC_O_IM 0x00000008 // Interrupt mask register\r
+#define ADC_O_ISC 0x0000000C // Interrupt status/clear register\r
+#define ADC_O_OSTAT 0x00000010 // Overflow status register\r
+#define ADC_O_EMUX 0x00000014 // Event multiplexer select reg.\r
+#define ADC_O_USTAT 0x00000018 // Underflow status register\r
+#define ADC_O_SSPRI 0x00000020 // Channel priority register\r
+#define ADC_O_PSSI 0x00000028 // Processor sample initiate reg.\r
+#define ADC_O_SAC 0x00000030 // Sample Averaging Control reg.\r
+#define ADC_O_SSMUX0 0x00000040 // Multiplexer select 0 register\r
+#define ADC_O_SSCTL0 0x00000044 // Sample sequence control 0 reg.\r
+#define ADC_O_SSFIFO0 0x00000048 // Result FIFO 0 register\r
+#define ADC_O_SSFSTAT0 0x0000004C // FIFO 0 status register\r
+#define ADC_O_SSMUX1 0x00000060 // Multiplexer select 1 register\r
+#define ADC_O_SSCTL1 0x00000064 // Sample sequence control 1 reg.\r
+#define ADC_O_SSFIFO1 0x00000068 // Result FIFO 1 register\r
+#define ADC_O_SSFSTAT1 0x0000006C // FIFO 1 status register\r
+#define ADC_O_SSMUX2 0x00000080 // Multiplexer select 2 register\r
+#define ADC_O_SSCTL2 0x00000084 // Sample sequence control 2 reg.\r
+#define ADC_O_SSFIFO2 0x00000088 // Result FIFO 2 register\r
+#define ADC_O_SSFSTAT2 0x0000008C // FIFO 2 status register\r
+#define ADC_O_SSMUX3 0x000000A0 // Multiplexer select 3 register\r
+#define ADC_O_SSCTL3 0x000000A4 // Sample sequence control 3 reg.\r
+#define ADC_O_SSFIFO3 0x000000A8 // Result FIFO 3 register\r
+#define ADC_O_SSFSTAT3 0x000000AC // FIFO 3 status register\r
+#define ADC_O_TMLB 0x00000100 // Test mode loopback register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the ADC sequence registers.\r
+//\r
+//*****************************************************************************\r
+#define ADC_O_SEQ 0x00000040 // Offset to the first sequence\r
+#define ADC_O_SEQ_STEP 0x00000020 // Increment to the next sequence\r
+#define ADC_O_X_SSMUX 0x00000000 // Multiplexer select register\r
+#define ADC_O_X_SSCTL 0x00000004 // Sample sequence control register\r
+#define ADC_O_X_SSFIFO 0x00000008 // Result FIFO register\r
+#define ADC_O_X_SSFSTAT 0x0000000C // FIFO status register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_ACTSS register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_ACTSS_ASEN3 0x00000008 // Sample sequence 3 enable\r
+#define ADC_ACTSS_ASEN2 0x00000004 // Sample sequence 2 enable\r
+#define ADC_ACTSS_ASEN1 0x00000002 // Sample sequence 1 enable\r
+#define ADC_ACTSS_ASEN0 0x00000001 // Sample sequence 0 enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_RIS register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_RIS_INR3 0x00000008 // Sample sequence 3 interrupt\r
+#define ADC_RIS_INR2 0x00000004 // Sample sequence 2 interrupt\r
+#define ADC_RIS_INR1 0x00000002 // Sample sequence 1 interrupt\r
+#define ADC_RIS_INR0 0x00000001 // Sample sequence 0 interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_IM register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_IM_MASK3 0x00000008 // Sample sequence 3 mask\r
+#define ADC_IM_MASK2 0x00000004 // Sample sequence 2 mask\r
+#define ADC_IM_MASK1 0x00000002 // Sample sequence 1 mask\r
+#define ADC_IM_MASK0 0x00000001 // Sample sequence 0 mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_ISC register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_ISC_IN3 0x00000008 // Sample sequence 3 interrupt\r
+#define ADC_ISC_IN2 0x00000004 // Sample sequence 2 interrupt\r
+#define ADC_ISC_IN1 0x00000002 // Sample sequence 1 interrupt\r
+#define ADC_ISC_IN0 0x00000001 // Sample sequence 0 interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_OSTAT register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_OSTAT_OV3 0x00000008 // Sample sequence 3 overflow\r
+#define ADC_OSTAT_OV2 0x00000004 // Sample sequence 2 overflow\r
+#define ADC_OSTAT_OV1 0x00000002 // Sample sequence 1 overflow\r
+#define ADC_OSTAT_OV0 0x00000001 // Sample sequence 0 overflow\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_EMUX register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_EMUX_EM3_MASK 0x0000F000 // Event mux 3 mask\r
+#define ADC_EMUX_EM3_PROCESSOR 0x00000000 // Processor event\r
+#define ADC_EMUX_EM3_COMP0 0x00001000 // Analog comparator 0 event\r
+#define ADC_EMUX_EM3_COMP1 0x00002000 // Analog comparator 1 event\r
+#define ADC_EMUX_EM3_COMP2 0x00003000 // Analog comparator 2 event\r
+#define ADC_EMUX_EM3_EXTERNAL 0x00004000 // External event\r
+#define ADC_EMUX_EM3_TIMER 0x00005000 // Timer event\r
+#define ADC_EMUX_EM3_PWM0 0x00006000 // PWM0 event\r
+#define ADC_EMUX_EM3_PWM1 0x00007000 // PWM1 event\r
+#define ADC_EMUX_EM3_PWM2 0x00008000 // PWM2 event\r
+#define ADC_EMUX_EM3_ALWAYS 0x0000F000 // Always event\r
+#define ADC_EMUX_EM2_MASK 0x00000F00 // Event mux 2 mask\r
+#define ADC_EMUX_EM2_PROCESSOR 0x00000000 // Processor event\r
+#define ADC_EMUX_EM2_COMP0 0x00000100 // Analog comparator 0 event\r
+#define ADC_EMUX_EM2_COMP1 0x00000200 // Analog comparator 1 event\r
+#define ADC_EMUX_EM2_COMP2 0x00000300 // Analog comparator 2 event\r
+#define ADC_EMUX_EM2_EXTERNAL 0x00000400 // External event\r
+#define ADC_EMUX_EM2_TIMER 0x00000500 // Timer event\r
+#define ADC_EMUX_EM2_PWM0 0x00000600 // PWM0 event\r
+#define ADC_EMUX_EM2_PWM1 0x00000700 // PWM1 event\r
+#define ADC_EMUX_EM2_PWM2 0x00000800 // PWM2 event\r
+#define ADC_EMUX_EM2_ALWAYS 0x00000F00 // Always event\r
+#define ADC_EMUX_EM1_MASK 0x000000F0 // Event mux 1 mask\r
+#define ADC_EMUX_EM1_PROCESSOR 0x00000000 // Processor event\r
+#define ADC_EMUX_EM1_COMP0 0x00000010 // Analog comparator 0 event\r
+#define ADC_EMUX_EM1_COMP1 0x00000020 // Analog comparator 1 event\r
+#define ADC_EMUX_EM1_COMP2 0x00000030 // Analog comparator 2 event\r
+#define ADC_EMUX_EM1_EXTERNAL 0x00000040 // External event\r
+#define ADC_EMUX_EM1_TIMER 0x00000050 // Timer event\r
+#define ADC_EMUX_EM1_PWM0 0x00000060 // PWM0 event\r
+#define ADC_EMUX_EM1_PWM1 0x00000070 // PWM1 event\r
+#define ADC_EMUX_EM1_PWM2 0x00000080 // PWM2 event\r
+#define ADC_EMUX_EM1_ALWAYS 0x000000F0 // Always event\r
+#define ADC_EMUX_EM0_MASK 0x0000000F // Event mux 0 mask\r
+#define ADC_EMUX_EM0_PROCESSOR 0x00000000 // Processor event\r
+#define ADC_EMUX_EM0_COMP0 0x00000001 // Analog comparator 0 event\r
+#define ADC_EMUX_EM0_COMP1 0x00000002 // Analog comparator 1 event\r
+#define ADC_EMUX_EM0_COMP2 0x00000003 // Analog comparator 2 event\r
+#define ADC_EMUX_EM0_EXTERNAL 0x00000004 // External event\r
+#define ADC_EMUX_EM0_TIMER 0x00000005 // Timer event\r
+#define ADC_EMUX_EM0_PWM0 0x00000006 // PWM0 event\r
+#define ADC_EMUX_EM0_PWM1 0x00000007 // PWM1 event\r
+#define ADC_EMUX_EM0_PWM2 0x00000008 // PWM2 event\r
+#define ADC_EMUX_EM0_ALWAYS 0x0000000F // Always event\r
+#define ADC_EMUX_EM0_SHIFT 0 // The shift for the first event\r
+#define ADC_EMUX_EM1_SHIFT 4 // The shift for the second event\r
+#define ADC_EMUX_EM2_SHIFT 8 // The shift for the third event\r
+#define ADC_EMUX_EM3_SHIFT 12 // The shift for the fourth event\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_USTAT register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_USTAT_UV3 0x00000008 // Sample sequence 3 underflow\r
+#define ADC_USTAT_UV2 0x00000004 // Sample sequence 2 underflow\r
+#define ADC_USTAT_UV1 0x00000002 // Sample sequence 1 underflow\r
+#define ADC_USTAT_UV0 0x00000001 // Sample sequence 0 underflow\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_SSPRI register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_SSPRI_SS3_MASK 0x00003000 // Sequencer 3 priority mask\r
+#define ADC_SSPRI_SS3_1ST 0x00000000 // First priority\r
+#define ADC_SSPRI_SS3_2ND 0x00001000 // Second priority\r
+#define ADC_SSPRI_SS3_3RD 0x00002000 // Third priority\r
+#define ADC_SSPRI_SS3_4TH 0x00003000 // Fourth priority\r
+#define ADC_SSPRI_SS2_MASK 0x00000300 // Sequencer 2 priority mask\r
+#define ADC_SSPRI_SS2_1ST 0x00000000 // First priority\r
+#define ADC_SSPRI_SS2_2ND 0x00000100 // Second priority\r
+#define ADC_SSPRI_SS2_3RD 0x00000200 // Third priority\r
+#define ADC_SSPRI_SS2_4TH 0x00000300 // Fourth priority\r
+#define ADC_SSPRI_SS1_MASK 0x00000030 // Sequencer 1 priority mask\r
+#define ADC_SSPRI_SS1_1ST 0x00000000 // First priority\r
+#define ADC_SSPRI_SS1_2ND 0x00000010 // Second priority\r
+#define ADC_SSPRI_SS1_3RD 0x00000020 // Third priority\r
+#define ADC_SSPRI_SS1_4TH 0x00000030 // Fourth priority\r
+#define ADC_SSPRI_SS0_MASK 0x00000003 // Sequencer 0 priority mask\r
+#define ADC_SSPRI_SS0_1ST 0x00000000 // First priority\r
+#define ADC_SSPRI_SS0_2ND 0x00000001 // Second priority\r
+#define ADC_SSPRI_SS0_3RD 0x00000002 // Third priority\r
+#define ADC_SSPRI_SS0_4TH 0x00000003 // Fourth priority\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_PSSI register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_PSSI_SS3 0x00000008 // Trigger sample sequencer 3\r
+#define ADC_PSSI_SS2 0x00000004 // Trigger sample sequencer 2\r
+#define ADC_PSSI_SS1 0x00000002 // Trigger sample sequencer 1\r
+#define ADC_PSSI_SS0 0x00000001 // Trigger sample sequencer 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_SAC register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_SAC_AVG_OFF 0x00000000 // No hardware oversampling\r
+#define ADC_SAC_AVG_2X 0x00000001 // 2x hardware oversampling\r
+#define ADC_SAC_AVG_4X 0x00000002 // 4x hardware oversampling\r
+#define ADC_SAC_AVG_8X 0x00000003 // 8x hardware oversampling\r
+#define ADC_SAC_AVG_16X 0x00000004 // 16x hardware oversampling\r
+#define ADC_SAC_AVG_32X 0x00000005 // 32x hardware oversampling\r
+#define ADC_SAC_AVG_64X 0x00000006 // 64x hardware oversampling\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_SSMUX0, ADC_SSMUX1,\r
+// ADC_SSMUX2, and ADC_SSMUX3 registers. Not all fields are present in all\r
+// registers.\r
+//\r
+//*****************************************************************************\r
+#define ADC_SSMUX_MUX7_MASK 0x70000000 // 8th mux select mask\r
+#define ADC_SSMUX_MUX6_MASK 0x07000000 // 7th mux select mask\r
+#define ADC_SSMUX_MUX5_MASK 0x00700000 // 6th mux select mask\r
+#define ADC_SSMUX_MUX4_MASK 0x00070000 // 5th mux select mask\r
+#define ADC_SSMUX_MUX3_MASK 0x00007000 // 4th mux select mask\r
+#define ADC_SSMUX_MUX2_MASK 0x00000700 // 3rd mux select mask\r
+#define ADC_SSMUX_MUX1_MASK 0x00000070 // 2nd mux select mask\r
+#define ADC_SSMUX_MUX0_MASK 0x00000007 // 1st mux select mask\r
+#define ADC_SSMUX_MUX7_SHIFT 28\r
+#define ADC_SSMUX_MUX6_SHIFT 24\r
+#define ADC_SSMUX_MUX5_SHIFT 20\r
+#define ADC_SSMUX_MUX4_SHIFT 16\r
+#define ADC_SSMUX_MUX3_SHIFT 12\r
+#define ADC_SSMUX_MUX2_SHIFT 8\r
+#define ADC_SSMUX_MUX1_SHIFT 4\r
+#define ADC_SSMUX_MUX0_SHIFT 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_SSCTL0, ADC_SSCTL1,\r
+// ADC_SSCTL2, and ADC_SSCTL3 registers. Not all fields are present in all\r
+// registers.\r
+//\r
+//*****************************************************************************\r
+#define ADC_SSCTL_TS7 0x80000000 // 8th temperature sensor select\r
+#define ADC_SSCTL_IE7 0x40000000 // 8th interrupt enable\r
+#define ADC_SSCTL_END7 0x20000000 // 8th sequence end select\r
+#define ADC_SSCTL_D7 0x10000000 // 8th differential select\r
+#define ADC_SSCTL_TS6 0x08000000 // 7th temperature sensor select\r
+#define ADC_SSCTL_IE6 0x04000000 // 7th interrupt enable\r
+#define ADC_SSCTL_END6 0x02000000 // 7th sequence end select\r
+#define ADC_SSCTL_D6 0x01000000 // 7th differential select\r
+#define ADC_SSCTL_TS5 0x00800000 // 6th temperature sensor select\r
+#define ADC_SSCTL_IE5 0x00400000 // 6th interrupt enable\r
+#define ADC_SSCTL_END5 0x00200000 // 6th sequence end select\r
+#define ADC_SSCTL_D5 0x00100000 // 6th differential select\r
+#define ADC_SSCTL_TS4 0x00080000 // 5th temperature sensor select\r
+#define ADC_SSCTL_IE4 0x00040000 // 5th interrupt enable\r
+#define ADC_SSCTL_END4 0x00020000 // 5th sequence end select\r
+#define ADC_SSCTL_D4 0x00010000 // 5th differential select\r
+#define ADC_SSCTL_TS3 0x00008000 // 4th temperature sensor select\r
+#define ADC_SSCTL_IE3 0x00004000 // 4th interrupt enable\r
+#define ADC_SSCTL_END3 0x00002000 // 4th sequence end select\r
+#define ADC_SSCTL_D3 0x00001000 // 4th differential select\r
+#define ADC_SSCTL_TS2 0x00000800 // 3rd temperature sensor select\r
+#define ADC_SSCTL_IE2 0x00000400 // 3rd interrupt enable\r
+#define ADC_SSCTL_END2 0x00000200 // 3rd sequence end select\r
+#define ADC_SSCTL_D2 0x00000100 // 3rd differential select\r
+#define ADC_SSCTL_TS1 0x00000080 // 2nd temperature sensor select\r
+#define ADC_SSCTL_IE1 0x00000040 // 2nd interrupt enable\r
+#define ADC_SSCTL_END1 0x00000020 // 2nd sequence end select\r
+#define ADC_SSCTL_D1 0x00000010 // 2nd differential select\r
+#define ADC_SSCTL_TS0 0x00000008 // 1st temperature sensor select\r
+#define ADC_SSCTL_IE0 0x00000004 // 1st interrupt enable\r
+#define ADC_SSCTL_END0 0x00000002 // 1st sequence end select\r
+#define ADC_SSCTL_D0 0x00000001 // 1st differential select\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_SSFIFO0, ADC_SSFIFO1,\r
+// ADC_SSFIFO2, and ADC_SSFIFO3 registers.\r
+//\r
+//*****************************************************************************\r
+#define ADC_SSFIFO_DATA_MASK 0x000003FF // Sample data\r
+#define ADC_SSFIFO_DATA_SHIFT 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_SSFSTAT0, ADC_SSFSTAT1,\r
+// ADC_SSFSTAT2, and ADC_SSFSTAT3 registers.\r
+//\r
+//*****************************************************************************\r
+#define ADC_SSFSTAT_FULL 0x00001000 // FIFO is full\r
+#define ADC_SSFSTAT_EMPTY 0x00000100 // FIFO is empty\r
+#define ADC_SSFSTAT_HPTR 0x000000F0 // FIFO head pointer\r
+#define ADC_SSFSTAT_TPTR 0x0000000F // FIFO tail pointer\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_TMLB register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_TMLB_LB 0x00000001 // Loopback control signals\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the loopback ADC data.\r
+//\r
+//*****************************************************************************\r
+#define ADC_LB_CNT_MASK 0x000003C0 // Sample counter mask\r
+#define ADC_LB_CONT 0x00000020 // Continuation sample\r
+#define ADC_LB_DIFF 0x00000010 // Differential sample\r
+#define ADC_LB_TS 0x00000008 // Temperature sensor sample\r
+#define ADC_LB_MUX_MASK 0x00000007 // Input channel number mask\r
+#define ADC_LB_CNT_SHIFT 6 // Sample counter shift\r
+#define ADC_LB_MUX_SHIFT 0 // Input channel number shift\r
+\r
+#endif // __HW_ADC_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_comp.h - Macros used when accessing the comparator hardware.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 991 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_COMP_H__\r
+#define __HW_COMP_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the comparator registers.\r
+//\r
+//*****************************************************************************\r
+#define COMP_O_MIS 0x00000000 // Interrupt status register\r
+#define COMP_O_RIS 0x00000004 // Raw interrupt status register\r
+#define COMP_O_INTEN 0x00000008 // Interrupt enable register\r
+#define COMP_O_REFCTL 0x00000010 // Reference voltage control reg.\r
+#define COMP_O_ACSTAT0 0x00000020 // Comp0 status register\r
+#define COMP_O_ACCTL0 0x00000024 // Comp0 control register\r
+#define COMP_O_ACSTAT1 0x00000040 // Comp1 status register\r
+#define COMP_O_ACCTL1 0x00000044 // Comp1 control register\r
+#define COMP_O_ACSTAT2 0x00000060 // Comp2 status register\r
+#define COMP_O_ACCTL2 0x00000064 // Comp2 control register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the COMP_MIS, COMP_RIS, and\r
+// COMP_INTEN registers.\r
+//\r
+//*****************************************************************************\r
+#define COMP_INT_2 0x00000004 // Comp2 interrupt\r
+#define COMP_INT_1 0x00000002 // Comp1 interrupt\r
+#define COMP_INT_0 0x00000001 // Comp0 interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the COMP_REFCTL register.\r
+//\r
+//*****************************************************************************\r
+#define COMP_REFCTL_EN 0x00000200 // Reference voltage enable\r
+#define COMP_REFCTL_RNG 0x00000100 // Reference voltage range\r
+#define COMP_REFCTL_VREF_MASK 0x0000000F // Reference voltage select mask\r
+#define COMP_REFCTL_VREF_SHIFT 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the COMP_ACSTAT0, COMP_ACSTAT1, and\r
+// COMP_ACSTAT2 registers.\r
+//\r
+//*****************************************************************************\r
+#define COMP_ACSTAT_OVAL 0x00000002 // Comparator output value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the COMP_ACCTL0, COMP_ACCTL1, and\r
+// COMP_ACCTL2 registers.\r
+//\r
+//*****************************************************************************\r
+#define COMP_ACCTL_TMASK 0x00000800 // Trigger enable\r
+#define COMP_ACCTL_ASRCP_MASK 0x00000600 // Vin+ source select mask\r
+#define COMP_ACCTL_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin\r
+#define COMP_ACCTL_ASRCP_PIN0 0x00000200 // Comp0+ pin\r
+#define COMP_ACCTL_ASRCP_REF 0x00000400 // Internal voltage reference\r
+#define COMP_ACCTL_ASRCP_RES 0x00000600 // Reserved\r
+#define COMP_ACCTL_OEN 0x00000100 // Comparator output enable\r
+#define COMP_ACCTL_TSVAL 0x00000080 // Trigger polarity select\r
+#define COMP_ACCTL_TSEN_MASK 0x00000060 // Trigger sense mask\r
+#define COMP_ACCTL_TSEN_LEVEL 0x00000000 // Trigger is level sense\r
+#define COMP_ACCTL_TSEN_FALL 0x00000020 // Trigger is falling edge\r
+#define COMP_ACCTL_TSEN_RISE 0x00000040 // Trigger is rising edge\r
+#define COMP_ACCTL_TSEN_BOTH 0x00000060 // Trigger is both edges\r
+#define COMP_ACCTL_ISLVAL 0x00000010 // Interrupt polarity select\r
+#define COMP_ACCTL_ISEN_MASK 0x0000000C // Interrupt sense mask\r
+#define COMP_ACCTL_ISEN_LEVEL 0x00000000 // Interrupt is level sense\r
+#define COMP_ACCTL_ISEN_FALL 0x00000004 // Interrupt is falling edge\r
+#define COMP_ACCTL_ISEN_RISE 0x00000008 // Interrupt is rising edge\r
+#define COMP_ACCTL_ISEN_BOTH 0x0000000C // Interrupt is both edges\r
+#define COMP_ACCTL_CINV 0x00000002 // Comparator output invert\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the reset values for the comparator registers.\r
+//\r
+//*****************************************************************************\r
+#define COMP_RV_MIS 0x00000000 // Interrupt status register\r
+#define COMP_RV_RIS 0x00000000 // Raw interrupt status register\r
+#define COMP_RV_INTEN 0x00000000 // Interrupt enable register\r
+#define COMP_RV_REFCTL 0x00000000 // Reference voltage control reg.\r
+#define COMP_RV_ACSTAT0 0x00000000 // Comp0 status register\r
+#define COMP_RV_ACCTL0 0x00000000 // Comp0 control register\r
+#define COMP_RV_ACSTAT1 0x00000000 // Comp1 status register\r
+#define COMP_RV_ACCTL1 0x00000000 // Comp1 control register\r
+#define COMP_RV_ACSTAT2 0x00000000 // Comp2 status register\r
+#define COMP_RV_ACCTL2 0x00000000 // Comp2 control register\r
+\r
+#endif // __HW_COMP_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_flash.h - Macros used when accessing the flash controller.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 991 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_FLASH_H__\r
+#define __HW_FLASH_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the FLASH registers.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_FMA 0x400FD000 // Memory address register\r
+#define FLASH_FMD 0x400FD004 // Memory data register\r
+#define FLASH_FMC 0x400FD008 // Memory control register\r
+#define FLASH_FCRIS 0x400FD00c // Raw interrupt status register\r
+#define FLASH_FCIM 0x400FD010 // Interrupt mask register\r
+#define FLASH_FCMISC 0x400FD014 // Interrupt status register\r
+#define FLASH_FMPRE 0x400FE130 // FLASH read protect register\r
+#define FLASH_FMPPE 0x400FE134 // FLASH program protect register\r
+#define FLASH_USECRL 0x400FE140 // uSec reload register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the FLASH_FMC register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_FMC_WRKEY_MASK 0xFFFF0000 // FLASH write key mask\r
+#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key\r
+#define FLASH_FMC_COMT 0x00000008 // Commit user register\r
+#define FLASH_FMC_MERASE 0x00000004 // Mass erase FLASH\r
+#define FLASH_FMC_ERASE 0x00000002 // Erase FLASH page\r
+#define FLASH_FMC_WRITE 0x00000001 // Write FLASH word\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the FLASH_FCRIS register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_FCRIS_PROGRAM 0x00000002 // Programming status\r
+#define FLASH_FCRIS_ACCESS 0x00000001 // Invalid access status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the FLASH_FCIM register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_FCIM_PROGRAM 0x00000002 // Programming mask\r
+#define FLASH_FCIM_ACCESS 0x00000001 // Invalid access mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the FLASH_FMIS register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_FCMISC_PROGRAM 0x00000002 // Programming status\r
+#define FLASH_FCMISC_ACCESS 0x00000001 // Invalid access status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the FLASH_FMPRE and FLASH_FMPPE\r
+// registers.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_FMP_BLOCK_31 0x80000000 // Enable for block 31\r
+#define FLASH_FMP_BLOCK_30 0x40000000 // Enable for block 30\r
+#define FLASH_FMP_BLOCK_29 0x20000000 // Enable for block 29\r
+#define FLASH_FMP_BLOCK_28 0x10000000 // Enable for block 28\r
+#define FLASH_FMP_BLOCK_27 0x08000000 // Enable for block 27\r
+#define FLASH_FMP_BLOCK_26 0x04000000 // Enable for block 26\r
+#define FLASH_FMP_BLOCK_25 0x02000000 // Enable for block 25\r
+#define FLASH_FMP_BLOCK_24 0x01000000 // Enable for block 24\r
+#define FLASH_FMP_BLOCK_23 0x00800000 // Enable for block 23\r
+#define FLASH_FMP_BLOCK_22 0x00400000 // Enable for block 22\r
+#define FLASH_FMP_BLOCK_21 0x00200000 // Enable for block 21\r
+#define FLASH_FMP_BLOCK_20 0x00100000 // Enable for block 20\r
+#define FLASH_FMP_BLOCK_19 0x00080000 // Enable for block 19\r
+#define FLASH_FMP_BLOCK_18 0x00040000 // Enable for block 18\r
+#define FLASH_FMP_BLOCK_17 0x00020000 // Enable for block 17\r
+#define FLASH_FMP_BLOCK_16 0x00010000 // Enable for block 16\r
+#define FLASH_FMP_BLOCK_15 0x00008000 // Enable for block 15\r
+#define FLASH_FMP_BLOCK_14 0x00004000 // Enable for block 14\r
+#define FLASH_FMP_BLOCK_13 0x00002000 // Enable for block 13\r
+#define FLASH_FMP_BLOCK_12 0x00001000 // Enable for block 12\r
+#define FLASH_FMP_BLOCK_11 0x00000800 // Enable for block 11\r
+#define FLASH_FMP_BLOCK_10 0x00000400 // Enable for block 10\r
+#define FLASH_FMP_BLOCK_9 0x00000200 // Enable for block 9\r
+#define FLASH_FMP_BLOCK_8 0x00000100 // Enable for block 8\r
+#define FLASH_FMP_BLOCK_7 0x00000080 // Enable for block 7\r
+#define FLASH_FMP_BLOCK_6 0x00000040 // Enable for block 6\r
+#define FLASH_FMP_BLOCK_5 0x00000020 // Enable for block 5\r
+#define FLASH_FMP_BLOCK_4 0x00000010 // Enable for block 4\r
+#define FLASH_FMP_BLOCK_3 0x00000008 // Enable for block 3\r
+#define FLASH_FMP_BLOCK_2 0x00000004 // Enable for block 2\r
+#define FLASH_FMP_BLOCK_1 0x00000002 // Enable for block 1\r
+#define FLASH_FMP_BLOCK_0 0x00000001 // Enable for block 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the FLASH_USECRL register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_USECRL_MASK 0x000000FF // Clock per uSec\r
+#define FLASH_USECRL_SHIFT 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The erase size is the size of the FLASH block that is erased by an erase\r
+// operation, and the protect size is the size of the FLASH block that is\r
+// protected by each protection register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_ERASE_SIZE 0x00000400\r
+#define FLASH_PROTECT_SIZE 0x00000800\r
+\r
+#endif // __HW_FLASH_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_gpio.h - Defines and Macros for GPIO hardware.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 991 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_GPIO_H__\r
+#define __HW_GPIO_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// GPIO Register Offsets.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_O_DATA 0x00000000 // Data register.\r
+#define GPIO_O_DIR 0x00000400 // Data direction register.\r
+#define GPIO_O_IS 0x00000404 // Interrupt sense register.\r
+#define GPIO_O_IBE 0x00000408 // Interrupt both edges register.\r
+#define GPIO_O_IEV 0x0000040C // Intterupt event register.\r
+#define GPIO_O_IM 0x00000410 // Interrupt mask register.\r
+#define GPIO_O_RIS 0x00000414 // Raw interrupt status register.\r
+#define GPIO_O_MIS 0x00000418 // Masked interrupt status reg.\r
+#define GPIO_O_ICR 0x0000041C // Interrupt clear register.\r
+#define GPIO_O_AFSEL 0x00000420 // Mode control select register.\r
+#define GPIO_O_DR2R 0x00000500 // 2ma drive select register.\r
+#define GPIO_O_DR4R 0x00000504 // 4ma drive select register.\r
+#define GPIO_O_DR8R 0x00000508 // 8ma drive select register.\r
+#define GPIO_O_ODR 0x0000050C // Open drain select register.\r
+#define GPIO_O_PUR 0x00000510 // Pull up select register.\r
+#define GPIO_O_PDR 0x00000514 // Pull down select register.\r
+#define GPIO_O_SLR 0x00000518 // Slew rate control enable reg.\r
+#define GPIO_O_DEN 0x0000051C // Digital input enable register.\r
+#define GPIO_O_PeriphID4 0x00000FD0 //\r
+#define GPIO_O_PeriphID5 0x00000FD4 //\r
+#define GPIO_O_PeriphID6 0x00000FD8 //\r
+#define GPIO_O_PeriphID7 0x00000FDC //\r
+#define GPIO_O_PeriphID0 0x00000FE0 //\r
+#define GPIO_O_PeriphID1 0x00000FE4 //\r
+#define GPIO_O_PeriphID2 0x00000FE8 //\r
+#define GPIO_O_PeriphID3 0x00000FEC //\r
+#define GPIO_O_PCellID0 0x00000FF0 //\r
+#define GPIO_O_PCellID1 0x00000FF4 //\r
+#define GPIO_O_PCellID2 0x00000FF8 //\r
+#define GPIO_O_PCellID3 0x00000FFC //\r
+\r
+//*****************************************************************************\r
+//\r
+// GPIO Register reset values.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_RV_DATA 0x00000000 // Data register reset value.\r
+#define GPIO_RV_DIR 0x00000000 // Data direction reg RV.\r
+#define GPIO_RV_IS 0x00000000 // Interrupt sense reg RV.\r
+#define GPIO_RV_IBE 0x00000000 // Interrupt both edges reg RV.\r
+#define GPIO_RV_IEV 0x00000000 // Intterupt event reg RV.\r
+#define GPIO_RV_IM 0x00000000 // Interrupt mask reg RV.\r
+#define GPIO_RV_RIS 0x00000000 // Raw interrupt status reg RV.\r
+#define GPIO_RV_MIS 0x00000000 // Masked interrupt status reg RV.\r
+#define GPIO_RV_IC 0x00000000 // Interrupt clear reg RV.\r
+#define GPIO_RV_AFSEL 0x00000000 // Mode control select reg RV.\r
+#define GPIO_RV_DR2R 0x000000FF // 2ma drive select reg RV.\r
+#define GPIO_RV_DR4R 0x00000000 // 4ma drive select reg RV.\r
+#define GPIO_RV_DR8R 0x00000000 // 8ma drive select reg RV.\r
+#define GPIO_RV_ODR 0x00000000 // Open drain select reg RV.\r
+#define GPIO_RV_PUR 0x000000FF // Pull up select reg RV.\r
+#define GPIO_RV_PDR 0x00000000 // Pull down select reg RV.\r
+#define GPIO_RV_SLR 0x00000000 // Slew rate control enable reg RV.\r
+#define GPIO_RV_DEN 0x000000FF // Digital input enable reg RV.\r
+#define GPIO_RV_PeriphID4 0x00000000 //\r
+#define GPIO_RV_PeriphID5 0x00000000 //\r
+#define GPIO_RV_PeriphID6 0x00000000 //\r
+#define GPIO_RV_PeriphID7 0x00000000 //\r
+#define GPIO_RV_PeriphID0 0x00000061 //\r
+#define GPIO_RV_PeriphID1 0x00000010 //\r
+#define GPIO_RV_PeriphID2 0x00000004 //\r
+#define GPIO_RV_PeriphID3 0x00000000 //\r
+#define GPIO_RV_PCellID0 0x0000000D //\r
+#define GPIO_RV_PCellID1 0x000000F0 //\r
+#define GPIO_RV_PCellID2 0x00000005 //\r
+#define GPIO_RV_PCellID3 0x000000B1 //\r
+\r
+#endif // __HW_GPIO_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_i2c.h - Macros used when accessing the I2C master and slave hardware.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 991 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_I2C_H__\r
+#define __HW_I2C_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following defines the offset between the I2C master and slave registers.\r
+//\r
+//*****************************************************************************\r
+#define I2C_O_SLAVE 0x00000800 // Offset from master to slave\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the I2C master registers.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_O_SA 0x00000000 // Slave address register\r
+#define I2C_MASTER_O_CS 0x00000004 // Control and Status register\r
+#define I2C_MASTER_O_DR 0x00000008 // Data register\r
+#define I2C_MASTER_O_TPR 0x0000000C // Timer period register\r
+#define I2C_MASTER_O_IMR 0x00000010 // Interrupt mask register\r
+#define I2C_MASTER_O_RIS 0x00000014 // Raw interrupt status register\r
+#define I2C_MASTER_O_MIS 0x00000018 // Masked interrupt status reg\r
+#define I2C_MASTER_O_MICR 0x0000001c // Interrupt clear register\r
+#define I2C_MASTER_O_CR 0x00000020 // Configuration register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the I2C slave registers.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_O_OAR 0x00000000 // Own address register\r
+#define I2C_SLAVE_O_CSR 0x00000004 // Control/Status register\r
+#define I2C_SLAVE_O_DR 0x00000008 // Data register\r
+#define I2C_SLAVE_O_IM 0x0000000C // Interrupt mask register\r
+#define I2C_SLAVE_O_RIS 0x00000010 // Raw interrupt status register\r
+#define I2C_SLAVE_O_MIS 0x00000014 // Masked interrupt status reg\r
+#define I2C_SLAVE_O_SICR 0x00000018 // Interrupt clear register\r
+\r
+//*****************************************************************************\r
+//\r
+// The followng define the bit fields in the I2C master slave address register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_SA_SA_MASK 0x000000FE // Slave address\r
+#define I2C_MASTER_SA_RS 0x00000001 // Receive/send\r
+#define I2C_MASTER_SA_SA_SHIFT 1\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Master Control and Status\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_CS_ACK 0x00000008 // Acknowlegde\r
+#define I2C_MASTER_CS_STOP 0x00000004 // Stop\r
+#define I2C_MASTER_CS_START 0x00000002 // Start\r
+#define I2C_MASTER_CS_RUN 0x00000001 // Run\r
+#define I2C_MASTER_CS_BUS_BUSY 0x00000040 // Bus busy\r
+#define I2C_MASTER_CS_IDLE 0x00000020 // Idle\r
+#define I2C_MASTER_CS_ARB_LOST 0x00000010 // Lost arbitration\r
+#define I2C_MASTER_CS_DATA_ACK 0x00000008 // Data byte not acknowledged\r
+#define I2C_MASTER_CS_ADDR_ACK 0x00000004 // Address byte not acknowledged\r
+#define I2C_MASTER_CS_ERROR 0x00000002 // Error occurred\r
+#define I2C_MASTER_CS_BUSY 0x00000001 // Controller is TX/RX data\r
+#define I2C_MASTER_CS_ERR_MASK 0x0000001C\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define values used in determining the contents of the I2C\r
+// Master Timer Period register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_TPR_SCL_HP 0x00000004 // SCL high period\r
+#define I2C_MASTER_TPR_SCL_LP 0x00000006 // SCL low period\r
+#define I2C_MASTER_TPR_SCL (I2C_MASTER_TPR_SCL_HP + I2C_MASTER_TPR_SCL_LP)\r
+#define I2C_SCL_STANDARD 100000 // SCL standard frequency\r
+#define I2C_SCL_FAST 400000 // SCL fast frequency\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Master Interrupt Mask\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_IMR_IM 0x00000001 // Master interrupt mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Master Raw Interrupt Status\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_RIS_RIS 0x00000001 // Master raw interrupt status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Master Masked Interrupt\r
+// Status register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_MIS_MIS 0x00000001 // Master masked interrupt status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Master Interrupt Clear\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_MICR_IC 0x00000001 // Master interrupt clear\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Master Configuration\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_CR_SFE 0x00000020 // Slave function enable\r
+#define I2C_MASTER_CR_MFE 0x00000010 // Master function enable\r
+#define I2C_MASTER_CR_LPBK 0x00000001 // Loopback enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Slave Own Address register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_SOAR_OAR_MASK 0x0000007F // Slave address\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Slave Control/Status\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_CSR_DA 0x00000001 // Enable the device\r
+#define I2C_SLAVE_CSR_TREQ 0x00000002 // Transmit request received\r
+#define I2C_SLAVE_CSR_RREQ 0x00000001 // Receive data from I2C master\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Slave Interrupt Mask\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_IMR_IM 0x00000001 // Slave interrupt mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Slave Raw Interrupt Status\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_RIS_RIS 0x00000001 // Slave raw interrupt status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Slave Masked Interrupt\r
+// Status register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_MIS_MIS 0x00000001 // Slave masked interrupt status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Slave Interrupt Clear\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_SICR_IC 0x00000001 // Slave interrupt clear\r
+\r
+#endif // __HW_I2C_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_ints.h - Macros that define the interrupt assignment on Stellaris.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 991 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_INTS_H__\r
+#define __HW_INTS_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the fault assignments.\r
+//\r
+//*****************************************************************************\r
+#define FAULT_NMI 2 // NMI fault\r
+#define FAULT_HARD 3 // Hard fault\r
+#define FAULT_MPU 4 // MPU fault\r
+#define FAULT_BUS 5 // Bus fault\r
+#define FAULT_USAGE 6 // Usage fault\r
+#define FAULT_SVCALL 11 // SVCall\r
+#define FAULT_DEBUG 12 // Debug monitor\r
+#define FAULT_PENDSV 14 // PendSV\r
+#define FAULT_SYSTICK 15 // System Tick\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the interrupt assignments.\r
+//\r
+//*****************************************************************************\r
+#define INT_GPIOA 16 // GPIO Port A\r
+#define INT_GPIOB 17 // GPIO Port B\r
+#define INT_GPIOC 18 // GPIO Port C\r
+#define INT_GPIOD 19 // GPIO Port D\r
+#define INT_GPIOE 20 // GPIO Port E\r
+#define INT_UART0 21 // UART0 Rx and Tx\r
+#define INT_UART1 22 // UART1 Rx and Tx\r
+#define INT_SSI 23 // SSI Rx and Tx\r
+#define INT_I2C 24 // I2C Master and Slave\r
+#define INT_PWM_FAULT 25 // PWM Fault\r
+#define INT_PWM0 26 // PWM Generator 0\r
+#define INT_PWM1 27 // PWM Generator 1\r
+#define INT_PWM2 28 // PWM Generator 2\r
+#define INT_QEI 29 // Quadrature Encoder\r
+#define INT_ADC0 30 // ADC Sequence 0\r
+#define INT_ADC1 31 // ADC Sequence 1\r
+#define INT_ADC2 32 // ADC Sequence 2\r
+#define INT_ADC3 33 // ADC Sequence 3\r
+#define INT_WATCHDOG 34 // Watchdog timer\r
+#define INT_TIMER0A 35 // Timer 0 subtimer A\r
+#define INT_TIMER0B 36 // Timer 0 subtimer B\r
+#define INT_TIMER1A 37 // Timer 1 subtimer A\r
+#define INT_TIMER1B 38 // Timer 1 subtimer B\r
+#define INT_TIMER2A 39 // Timer 2 subtimer A\r
+#define INT_TIMER2B 40 // Timer 2 subtimer B\r
+#define INT_COMP0 41 // Analog Comparator 0\r
+#define INT_COMP1 42 // Analog Comparator 1\r
+#define INT_COMP2 43 // Analog Comparator 2\r
+#define INT_SYSCTL 44 // System Control (PLL, OSC, BO)\r
+#define INT_FLASH 45 // FLASH Control\r
+\r
+//*****************************************************************************\r
+//\r
+// The total number of interrupts.\r
+//\r
+//*****************************************************************************\r
+#define NUM_INTERRUPTS 46\r
+\r
+//*****************************************************************************\r
+//\r
+// The total number of priority levels.\r
+//\r
+//*****************************************************************************\r
+#define NUM_PRIORITY 8\r
+#define NUM_PRIORITY_BITS 3\r
+\r
+#endif // __HW_INTS_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_memmap.h - Macros defining the memory map of Stellaris.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 991 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_MEMMAP_H__\r
+#define __HW_MEMMAP_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the base address of the memories and peripherals.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_BASE 0x00000000 // FLASH memory\r
+#define SRAM_BASE 0x20000000 // SRAM memory\r
+#define WATCHDOG_BASE 0x40000000 // Watchdog\r
+#define GPIO_PORTA_BASE 0x40004000 // GPIO Port A\r
+#define GPIO_PORTB_BASE 0x40005000 // GPIO Port B\r
+#define GPIO_PORTC_BASE 0x40006000 // GPIO Port C\r
+#define GPIO_PORTD_BASE 0x40007000 // GPIO Port D\r
+#define SSI_BASE 0x40008000 // SSI\r
+#define UART0_BASE 0x4000C000 // UART0\r
+#define UART1_BASE 0x4000D000 // UART1\r
+#define I2C_MASTER_BASE 0x40020000 // I2C Master\r
+#define I2C_SLAVE_BASE 0x40020800 // I2C Slave\r
+#define GPIO_PORTE_BASE 0x40024000 // GPIO Port E\r
+#define PWM_BASE 0x40028000 // PWM\r
+#define QEI_BASE 0x4002C000 // QEI\r
+#define TIMER0_BASE 0x40030000 // Timer0\r
+#define TIMER1_BASE 0x40031000 // Timer1\r
+#define TIMER2_BASE 0x40032000 // Timer2\r
+#define ADC_BASE 0x40038000 // ADC\r
+#define COMP_BASE 0x4003C000 // Analog comparators\r
+#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller\r
+#define SYSCTL_BASE 0x400FE000 // System Control\r
+#define ITM_BASE 0xE0000000 // Instrumentation Trace Macrocell\r
+#define DWT_BASE 0xE0001000 // Data Watchpoint and Trace\r
+#define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint\r
+#define NVIC_BASE 0xE000E000 // Nested Vectored Interrupt Ctrl\r
+#define TPIU_BASE 0xE0040000 // Trace Port Interface Unit\r
+\r
+#endif // __HW_MEMMAP_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_nvic.h - Macros used when accessing the NVIC hardware.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 991 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_NVIC_H__\r
+#define __HW_NVIC_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the addresses of the NVIC registers.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg.\r
+#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status Reg.\r
+#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register\r
+#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register\r
+#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg.\r
+#define NVIC_EN0 0xE000E100 // IRQ 0 to 31 Set Enable Register\r
+#define NVIC_DIS0 0xE000E180 // IRQ 0 to 31 Clear Enable Reg.\r
+#define NVIC_PEND0 0xE000E200 // IRQ 0 to 31 Set Pending Register\r
+#define NVIC_UNPEND0 0xE000E280 // IRQ 0 to 31 Clear Pending Reg.\r
+#define NVIC_ACTIVE0 0xE000E300 // IRQ 0 to 31 Active Register\r
+#define NVIC_PRI0 0xE000E400 // IRQ 0 to 3 Priority Register\r
+#define NVIC_PRI1 0xE000E404 // IRQ 4 to 7 Priority Register\r
+#define NVIC_PRI2 0xE000E408 // IRQ 8 to 11 Priority Register\r
+#define NVIC_PRI3 0xE000E40C // IRQ 12 to 15 Priority Register\r
+#define NVIC_PRI4 0xE000E410 // IRQ 16 to 19 Priority Register\r
+#define NVIC_PRI5 0xE000E414 // IRQ 20 to 23 Priority Register\r
+#define NVIC_PRI6 0xE000E418 // IRQ 24 to 27 Priority Register\r
+#define NVIC_PRI7 0xE000E41C // IRQ 28 to 31 Priority Register\r
+#define NVIC_CPUID 0xE000ED00 // CPUID Base Register\r
+#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control State Register\r
+#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset Register\r
+#define NVIC_APINT 0xE000ED0C // App. Int & Reset Control Reg.\r
+#define NVIC_SYS_CTRL 0xE000ED10 // System Control Register\r
+#define NVIC_CFG_CTRL 0xE000ED14 // Configuration Control Register\r
+#define NVIC_SYS_PRI1 0xE000ED18 // Sys. Handlers 4 to 7 Priority\r
+#define NVIC_SYS_PRI2 0xE000ED1C // Sys. Handlers 8 to 11 Priority\r
+#define NVIC_SYS_PRI3 0xE000ED20 // Sys. Handlers 12 to 15 Priority\r
+#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State\r
+#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status Reg.\r
+#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status Register\r
+#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register\r
+#define NVIC_MM_ADDR 0xE000ED34 // Mem Manage Address Register\r
+#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address Register\r
+#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type Register\r
+#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control Register\r
+#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number Register\r
+#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address Register\r
+#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute & Size Reg.\r
+#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg.\r
+#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select\r
+#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data\r
+#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control\r
+#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt Reg.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_INT_TYPE register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32)\r
+#define NVIC_INT_TYPE_LINES_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_ST_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_ST_CTRL_COUNT 0x00010000 // Count flag\r
+#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source\r
+#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt enable\r
+#define NVIC_ST_CTRL_ENABLE 0x00000001 // Counter mode\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_ST_RELOAD register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_ST_RELOAD_M 0x00FFFFFF // Counter load value\r
+#define NVIC_ST_RELOAD_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_ST_CURRENT register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_ST_CURRENT_M 0x00FFFFFF // Counter current value\r
+#define NVIC_ST_CURRENT_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_ST_CAL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock\r
+#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew\r
+#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value\r
+#define NVIC_ST_CAL_ONEMS_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_EN0 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable\r
+#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable\r
+#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable\r
+#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable\r
+#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable\r
+#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable\r
+#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable\r
+#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable\r
+#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable\r
+#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable\r
+#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable\r
+#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable\r
+#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable\r
+#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable\r
+#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable\r
+#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable\r
+#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable\r
+#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable\r
+#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable\r
+#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable\r
+#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable\r
+#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable\r
+#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable\r
+#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable\r
+#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable\r
+#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable\r
+#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable\r
+#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable\r
+#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable\r
+#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable\r
+#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable\r
+#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_DIS0 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable\r
+#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable\r
+#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable\r
+#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable\r
+#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable\r
+#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable\r
+#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable\r
+#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable\r
+#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable\r
+#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable\r
+#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable\r
+#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable\r
+#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable\r
+#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable\r
+#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable\r
+#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable\r
+#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable\r
+#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable\r
+#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable\r
+#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable\r
+#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable\r
+#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable\r
+#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable\r
+#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable\r
+#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable\r
+#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable\r
+#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable\r
+#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable\r
+#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable\r
+#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable\r
+#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable\r
+#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PEND0 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend\r
+#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend\r
+#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend\r
+#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend\r
+#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend\r
+#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend\r
+#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend\r
+#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend\r
+#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend\r
+#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend\r
+#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend\r
+#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend\r
+#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend\r
+#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend\r
+#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend\r
+#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend\r
+#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend\r
+#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend\r
+#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend\r
+#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend\r
+#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend\r
+#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend\r
+#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend\r
+#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend\r
+#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend\r
+#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend\r
+#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend\r
+#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend\r
+#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend\r
+#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend\r
+#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend\r
+#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_UNPEND0 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend\r
+#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend\r
+#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend\r
+#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend\r
+#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend\r
+#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend\r
+#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend\r
+#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend\r
+#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend\r
+#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend\r
+#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend\r
+#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend\r
+#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend\r
+#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend\r
+#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend\r
+#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend\r
+#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend\r
+#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend\r
+#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend\r
+#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend\r
+#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend\r
+#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend\r
+#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend\r
+#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend\r
+#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend\r
+#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend\r
+#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend\r
+#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend\r
+#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend\r
+#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend\r
+#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend\r
+#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_ACTIVE0 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active\r
+#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active\r
+#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active\r
+#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active\r
+#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active\r
+#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active\r
+#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active\r
+#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active\r
+#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active\r
+#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active\r
+#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active\r
+#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active\r
+#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active\r
+#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active\r
+#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active\r
+#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active\r
+#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active\r
+#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active\r
+#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active\r
+#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active\r
+#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active\r
+#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active\r
+#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active\r
+#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active\r
+#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active\r
+#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active\r
+#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active\r
+#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active\r
+#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active\r
+#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active\r
+#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active\r
+#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI0 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI0_INT3_M 0xFF000000 // Interrupt 3 priority mask\r
+#define NVIC_PRI0_INT2_M 0x00FF0000 // Interrupt 2 priority mask\r
+#define NVIC_PRI0_INT1_M 0x0000FF00 // Interrupt 1 priority mask\r
+#define NVIC_PRI0_INT0_M 0x000000FF // Interrupt 0 priority mask\r
+#define NVIC_PRI0_INT3_S 24\r
+#define NVIC_PRI0_INT2_S 16\r
+#define NVIC_PRI0_INT1_S 8\r
+#define NVIC_PRI0_INT0_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI1 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI1_INT7_M 0xFF000000 // Interrupt 7 priority mask\r
+#define NVIC_PRI1_INT6_M 0x00FF0000 // Interrupt 6 priority mask\r
+#define NVIC_PRI1_INT5_M 0x0000FF00 // Interrupt 5 priority mask\r
+#define NVIC_PRI1_INT4_M 0x000000FF // Interrupt 4 priority mask\r
+#define NVIC_PRI1_INT7_S 24\r
+#define NVIC_PRI1_INT6_S 16\r
+#define NVIC_PRI1_INT5_S 8\r
+#define NVIC_PRI1_INT4_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI2 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI2_INT11_M 0xFF000000 // Interrupt 11 priority mask\r
+#define NVIC_PRI2_INT10_M 0x00FF0000 // Interrupt 10 priority mask\r
+#define NVIC_PRI2_INT9_M 0x0000FF00 // Interrupt 9 priority mask\r
+#define NVIC_PRI2_INT8_M 0x000000FF // Interrupt 8 priority mask\r
+#define NVIC_PRI2_INT11_S 24\r
+#define NVIC_PRI2_INT10_S 16\r
+#define NVIC_PRI2_INT9_S 8\r
+#define NVIC_PRI2_INT8_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI3 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI3_INT15_M 0xFF000000 // Interrupt 15 priority mask\r
+#define NVIC_PRI3_INT14_M 0x00FF0000 // Interrupt 14 priority mask\r
+#define NVIC_PRI3_INT13_M 0x0000FF00 // Interrupt 13 priority mask\r
+#define NVIC_PRI3_INT12_M 0x000000FF // Interrupt 12 priority mask\r
+#define NVIC_PRI3_INT15_S 24\r
+#define NVIC_PRI3_INT14_S 16\r
+#define NVIC_PRI3_INT13_S 8\r
+#define NVIC_PRI3_INT12_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI4 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI4_INT19_M 0xFF000000 // Interrupt 19 priority mask\r
+#define NVIC_PRI4_INT18_M 0x00FF0000 // Interrupt 18 priority mask\r
+#define NVIC_PRI4_INT17_M 0x0000FF00 // Interrupt 17 priority mask\r
+#define NVIC_PRI4_INT16_M 0x000000FF // Interrupt 16 priority mask\r
+#define NVIC_PRI4_INT19_S 24\r
+#define NVIC_PRI4_INT18_S 16\r
+#define NVIC_PRI4_INT17_S 8\r
+#define NVIC_PRI4_INT16_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI5 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI5_INT23_M 0xFF000000 // Interrupt 23 priority mask\r
+#define NVIC_PRI5_INT22_M 0x00FF0000 // Interrupt 22 priority mask\r
+#define NVIC_PRI5_INT21_M 0x0000FF00 // Interrupt 21 priority mask\r
+#define NVIC_PRI5_INT20_M 0x000000FF // Interrupt 20 priority mask\r
+#define NVIC_PRI5_INT23_S 24\r
+#define NVIC_PRI5_INT22_S 16\r
+#define NVIC_PRI5_INT21_S 8\r
+#define NVIC_PRI5_INT20_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI6 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI6_INT27_M 0xFF000000 // Interrupt 27 priority mask\r
+#define NVIC_PRI6_INT26_M 0x00FF0000 // Interrupt 26 priority mask\r
+#define NVIC_PRI6_INT25_M 0x0000FF00 // Interrupt 25 priority mask\r
+#define NVIC_PRI6_INT24_M 0x000000FF // Interrupt 24 priority mask\r
+#define NVIC_PRI6_INT27_S 24\r
+#define NVIC_PRI6_INT26_S 16\r
+#define NVIC_PRI6_INT25_S 8\r
+#define NVIC_PRI6_INT24_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI7 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI7_INT31_M 0xFF000000 // Interrupt 31 priority mask\r
+#define NVIC_PRI7_INT30_M 0x00FF0000 // Interrupt 30 priority mask\r
+#define NVIC_PRI7_INT29_M 0x0000FF00 // Interrupt 29 priority mask\r
+#define NVIC_PRI7_INT28_M 0x000000FF // Interrupt 28 priority mask\r
+#define NVIC_PRI7_INT31_S 24\r
+#define NVIC_PRI7_INT30_S 16\r
+#define NVIC_PRI7_INT29_S 8\r
+#define NVIC_PRI7_INT28_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_CPUID register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer\r
+#define NVIC_CPUID_VAR_M 0x00F00000 // Variant\r
+#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Processor part number\r
+#define NVIC_CPUID_REV_M 0x0000000F // Revision\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_INT_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_INT_CTRL_NMI_SET 0x80000000 // Pend a NMI\r
+#define NVIC_INT_CTRL_PEND_SV 0x10000000 // Pend a PendSV\r
+#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // Unpend a PendSV\r
+#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug interrupt handling\r
+#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Debug interrupt pending\r
+#define NVIC_INT_CTRL_VEC_PEN_M 0x003FF000 // Highest pending exception\r
+#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to base\r
+#define NVIC_INT_CTRL_VEC_ACT_M 0x000003FF // Current active exception\r
+#define NVIC_INT_CTRL_VEC_PEN_S 12\r
+#define NVIC_INT_CTRL_VEC_ACT_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_VTABLE register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_VTABLE_BASE 0x20000000 // Vector table base\r
+#define NVIC_VTABLE_OFFSET_M 0x1FFFFF00 // Vector table offset\r
+#define NVIC_VTABLE_OFFSET_S 8\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_APINT register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Vector key mask\r
+#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key\r
+#define NVIC_APINT_ENDIANESS 0x00008000 // Data endianess\r
+#define NVIC_APINT_PRIGROUP_M 0x00000700 // Priority group\r
+#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split\r
+#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split\r
+#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split\r
+#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split\r
+#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split\r
+#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split\r
+#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split\r
+#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split\r
+#define NVIC_APINT_SYSRESETREQ 0x00000004 // System reset request\r
+#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear active NMI/fault info\r
+#define NVIC_APINT_VECT_RESET 0x00000001 // System reset\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_SYS_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wakeup on pend\r
+#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep sleep enable\r
+#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR exit\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_CFG_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore bus fault in NMI/fault\r
+#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on divide by 0\r
+#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on unaligned access\r
+#define NVIC_CFG_CTRL_DEEP_PEND 0x00000004 // Allow deep interrupt trigger\r
+#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow main interrupt trigger\r
+#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread state control\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_SYS_PRI1 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_SYS_PRI1_RES_M 0xFF000000 // Priority of reserved handler\r
+#define NVIC_SYS_PRI1_USAGE_M 0x00FF0000 // Priority of usage fault handler\r
+#define NVIC_SYS_PRI1_BUS_M 0x0000FF00 // Priority of bus fault handler\r
+#define NVIC_SYS_PRI1_MEM_M 0x000000FF // Priority of mem manage handler\r
+#define NVIC_SYS_PRI1_USAGE_S 16\r
+#define NVIC_SYS_PRI1_BUS_S 8\r
+#define NVIC_SYS_PRI1_MEM_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_SYS_PRI2 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_SYS_PRI2_SVC_M 0xFF000000 // Priority of SVCall handler\r
+#define NVIC_SYS_PRI2_RES_M 0x00FFFFFF // Priority of reserved handlers\r
+#define NVIC_SYS_PRI2_SVC_S 24\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_SYS_PRI3 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_SYS_PRI3_TICK_M 0xFF000000 // Priority of Sys Tick handler\r
+#define NVIC_SYS_PRI3_PENDSV_M 0x00FF0000 // Priority of PendSV handler\r
+#define NVIC_SYS_PRI3_RES_M 0x0000FF00 // Priority of reserved handler\r
+#define NVIC_SYS_PRI3_DEBUG_M 0x000000FF // Priority of debug handler\r
+#define NVIC_SYS_PRI3_TICK_S 24\r
+#define NVIC_SYS_PRI3_PENDSV_S 16\r
+#define NVIC_SYS_PRI3_DEBUG_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_SYS_HND_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage fault enable\r
+#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus fault enable\r
+#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Mem manage fault enable\r
+#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVCall is pended\r
+#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus fault is pended\r
+#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // Sys tick is active\r
+#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV is active\r
+#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Monitor is active\r
+#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVCall is active\r
+#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage fault is active\r
+#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus fault is active\r
+#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Mem manage is active\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_FAULT_STAT register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide by zero fault\r
+#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned access fault\r
+#define NVIC_FAULT_STAT_NOCP 0x00080000 // No coprocessor fault\r
+#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC fault\r
+#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid state fault\r
+#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined instruction fault\r
+#define NVIC_FAULT_STAT_BFARV 0x00008000 // BFAR is valid\r
+#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack bus fault\r
+#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack bus fault\r
+#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise data bus error\r
+#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise data bus error\r
+#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction bus fault\r
+#define NVIC_FAULT_STAT_MMARV 0x00000080 // MMAR is valid\r
+#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack access violation\r
+#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack access violation\r
+#define NVIC_FAULT_STAT_DERR 0x00000002 // Data access violation\r
+#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction access violation\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_HFAULT_STAT register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug event\r
+#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Cannot execute fault handler\r
+#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector table read fault\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_DEBUG_STAT register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted\r
+#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch\r
+#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match\r
+#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction\r
+#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_MM_ADDR register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_MM_ADDR_M 0xFFFFFFFF // Data fault address\r
+#define NVIC_MM_ADDR_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_FAULT_ADDR register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Data bus fault address\r
+#define NVIC_FAULT_ADDR_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_EXC_STACK register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_EXC_STACK_DEEP 0x00000001 // Exception stack\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_EXC_NUM register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_EXC_NUM_M 0x000003FF // Exception number\r
+#define NVIC_EXC_NUM_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_COPRO register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_COPRO_15_M 0xC0000000 // Coprocessor 15 access mask\r
+#define NVIC_COPRO_15_DENIED 0x00000000 // Coprocessor 15 access denied\r
+#define NVIC_COPRO_15_PRIV 0x40000000 // Coprocessor 15 privileged addess\r
+#define NVIC_COPRO_15_FULL 0xC0000000 // Coprocessor 15 full access\r
+#define NVIC_COPRO_14_M 0x30000000 // Coprocessor 14 access mask\r
+#define NVIC_COPRO_14_DENIED 0x00000000 // Coprocessor 14 access denied\r
+#define NVIC_COPRO_14_PRIV 0x10000000 // Coprocessor 14 privileged addess\r
+#define NVIC_COPRO_14_FULL 0x30000000 // Coprocessor 14 full access\r
+#define NVIC_COPRO_13_M 0x0C000000 // Coprocessor 13 access mask\r
+#define NVIC_COPRO_13_DENIED 0x00000000 // Coprocessor 13 access denied\r
+#define NVIC_COPRO_13_PRIV 0x04000000 // Coprocessor 13 privileged addess\r
+#define NVIC_COPRO_13_FULL 0x0C000000 // Coprocessor 13 full access\r
+#define NVIC_COPRO_12_M 0x03000000 // Coprocessor 12 access mask\r
+#define NVIC_COPRO_12_DENIED 0x00000000 // Coprocessor 12 access denied\r
+#define NVIC_COPRO_12_PRIV 0x01000000 // Coprocessor 12 privileged addess\r
+#define NVIC_COPRO_12_FULL 0x03000000 // Coprocessor 12 full access\r
+#define NVIC_COPRO_11_M 0x00C00000 // Coprocessor 11 access mask\r
+#define NVIC_COPRO_11_DENIED 0x00000000 // Coprocessor 11 access denied\r
+#define NVIC_COPRO_11_PRIV 0x00400000 // Coprocessor 11 privileged addess\r
+#define NVIC_COPRO_11_FULL 0x00C00000 // Coprocessor 11 full access\r
+#define NVIC_COPRO_10_M 0x00300000 // Coprocessor 10 access mask\r
+#define NVIC_COPRO_10_DENIED 0x00000000 // Coprocessor 10 access denied\r
+#define NVIC_COPRO_10_PRIV 0x00100000 // Coprocessor 10 privileged addess\r
+#define NVIC_COPRO_10_FULL 0x00300000 // Coprocessor 10 full access\r
+#define NVIC_COPRO_9_M 0x000C0000 // Coprocessor 9 access mask\r
+#define NVIC_COPRO_9_DENIED 0x00000000 // Coprocessor 9 access denied\r
+#define NVIC_COPRO_9_PRIV 0x00040000 // Coprocessor 9 privileged addess\r
+#define NVIC_COPRO_9_FULL 0x000C0000 // Coprocessor 9 full access\r
+#define NVIC_COPRO_8_M 0x00030000 // Coprocessor 8 access mask\r
+#define NVIC_COPRO_8_DENIED 0x00000000 // Coprocessor 8 access denied\r
+#define NVIC_COPRO_8_PRIV 0x00010000 // Coprocessor 8 privileged addess\r
+#define NVIC_COPRO_8_FULL 0x00030000 // Coprocessor 8 full access\r
+#define NVIC_COPRO_7_M 0x0000C000 // Coprocessor 7 access mask\r
+#define NVIC_COPRO_7_DENIED 0x00000000 // Coprocessor 7 access denied\r
+#define NVIC_COPRO_7_PRIV 0x00004000 // Coprocessor 7 privileged addess\r
+#define NVIC_COPRO_7_FULL 0x0000C000 // Coprocessor 7 full access\r
+#define NVIC_COPRO_6_M 0x00003000 // Coprocessor 6 access mask\r
+#define NVIC_COPRO_6_DENIED 0x00000000 // Coprocessor 6 access denied\r
+#define NVIC_COPRO_6_PRIV 0x00001000 // Coprocessor 6 privileged addess\r
+#define NVIC_COPRO_6_FULL 0x00003000 // Coprocessor 6 full access\r
+#define NVIC_COPRO_5_M 0x00000C00 // Coprocessor 5 access mask\r
+#define NVIC_COPRO_5_DENIED 0x00000000 // Coprocessor 5 access denied\r
+#define NVIC_COPRO_5_PRIV 0x00000400 // Coprocessor 5 privileged addess\r
+#define NVIC_COPRO_5_FULL 0x00000C00 // Coprocessor 5 full access\r
+#define NVIC_COPRO_4_M 0x00000300 // Coprocessor 4 access mask\r
+#define NVIC_COPRO_4_DENIED 0x00000000 // Coprocessor 4 access denied\r
+#define NVIC_COPRO_4_PRIV 0x00000100 // Coprocessor 4 privileged addess\r
+#define NVIC_COPRO_4_FULL 0x00000300 // Coprocessor 4 full access\r
+#define NVIC_COPRO_3_M 0x000000C0 // Coprocessor 3 access mask\r
+#define NVIC_COPRO_3_DENIED 0x00000000 // Coprocessor 3 access denied\r
+#define NVIC_COPRO_3_PRIV 0x00000040 // Coprocessor 3 privileged addess\r
+#define NVIC_COPRO_3_FULL 0x000000C0 // Coprocessor 3 full access\r
+#define NVIC_COPRO_2_M 0x00000030 // Coprocessor 2 access mask\r
+#define NVIC_COPRO_2_DENIED 0x00000000 // Coprocessor 2 access denied\r
+#define NVIC_COPRO_2_PRIV 0x00000010 // Coprocessor 2 privileged addess\r
+#define NVIC_COPRO_2_FULL 0x00000030 // Coprocessor 2 full access\r
+#define NVIC_COPRO_1_M 0x0000000C // Coprocessor 1 access mask\r
+#define NVIC_COPRO_1_DENIED 0x00000000 // Coprocessor 1 access denied\r
+#define NVIC_COPRO_1_PRIV 0x00000004 // Coprocessor 1 privileged addess\r
+#define NVIC_COPRO_1_FULL 0x0000000C // Coprocessor 1 full access\r
+#define NVIC_COPRO_0_M 0x00000003 // Coprocessor 0 access mask\r
+#define NVIC_COPRO_0_DENIED 0x00000000 // Coprocessor 0 access denied\r
+#define NVIC_COPRO_0_PRIV 0x00000001 // Coprocessor 0 privileged addess\r
+#define NVIC_COPRO_0_FULL 0x00000003 // Coprocessor 0 full access\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_MPU_TYPE register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I regions\r
+#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D regions\r
+#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or unified MPU\r
+#define NVIC_MPU_TYPE_IREGION_S 16\r
+#define NVIC_MPU_TYPE_DREGION_S 8\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_MPU_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU enabled during faults\r
+#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_MPU_NUMBER register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_MPU_NUMBER_M 0x000000FF // MPU region to access\r
+#define NVIC_MPU_NUMBER_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_MPU_BASE register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_MPU_BASE_ADDR_M 0xFFFFFF00 // Base address\r
+#define NVIC_MPU_BASE_VALID 0x00000010 // Region number valid\r
+#define NVIC_MPU_BASE_REGION_M 0x0000000F // Region number\r
+#define NVIC_MPU_BASE_ADDR_S 8\r
+#define NVIC_MPU_BASE_REGION_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_MPU_ATTR register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_MPU_ATTR_ATTRS 0xFFFF0000 // Attributes\r
+#define NVIC_MPU_ATTR_SRD 0x0000FF00 // Sub-region disable\r
+#define NVIC_MPU_ATTR_SZENABLE 0x000000FF // Region size\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_DBG_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask\r
+#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key\r
+#define NVIC_DBG_CTRL_MON_PEND 0x00008000 // Pend the monitor\r
+#define NVIC_DBG_CTRL_MON_REQ 0x00004000 // Monitor request\r
+#define NVIC_DBG_CTRL_MON_EN 0x00002000 // Debug monitor enable\r
+#define NVIC_DBG_CTRL_MONSTEP 0x00001000 // Monitor step the core\r
+#define NVIC_DBG_CTRL_S_SLEEP 0x00000400 // Core is sleeping\r
+#define NVIC_DBG_CTRL_S_HALT 0x00000200 // Core status on halt\r
+#define NVIC_DBG_CTRL_S_REGRDY 0x00000100 // Register read/write available\r
+#define NVIC_DBG_CTRL_S_LOCKUP 0x00000080 // Core is locked up\r
+#define NVIC_DBG_CTRL_C_RESET 0x00000010 // Reset the core\r
+#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping\r
+#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core\r
+#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core\r
+#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_DBG_XFER register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read\r
+#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register\r
+#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0\r
+#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1\r
+#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2\r
+#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3\r
+#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4\r
+#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5\r
+#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6\r
+#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7\r
+#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8\r
+#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9\r
+#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10\r
+#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11\r
+#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12\r
+#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13\r
+#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14\r
+#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15\r
+#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register\r
+#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP\r
+#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP\r
+#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP\r
+#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_DBG_DATA register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache\r
+#define NVIC_DBG_DATA_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_DBG_INT register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault\r
+#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors\r
+#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error\r
+#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state\r
+#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check\r
+#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error\r
+#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault\r
+#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status\r
+#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset\r
+#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending\r
+#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_SW_TRIG register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_SW_TRIG_INTID_M 0x000003FF // Interrupt to trigger\r
+#define NVIC_SW_TRIG_INTID_S 0\r
+\r
+#endif // __HW_NVIC_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_pwm.h - Defines and Macros for Pulse Width Modulation (PWM) ports\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 991 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_PWM_H__\r
+#define __HW_PWM_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM Module Register Offsets.\r
+//\r
+//*****************************************************************************\r
+#define PWM_O_CTL 0x00000000 // PWM Master Control register\r
+#define PWM_O_SYNC 0x00000004 // PWM Time Base Sync register\r
+#define PWM_O_ENABLE 0x00000008 // PWM Output Enable register\r
+#define PWM_O_INVERT 0x0000000C // PWM Output Inversion register\r
+#define PWM_O_FAULT 0x00000010 // PWM Output Fault register\r
+#define PWM_O_INTEN 0x00000014 // PWM Interrupt Enable register\r
+#define PWM_O_RIS 0x00000018 // PWM Interrupt Raw Status reg.\r
+#define PWM_O_ISC 0x0000001C // PWM Interrupt Status register\r
+#define PWM_O_STATUS 0x00000020 // PWM Status register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the PWM Master Control register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_CTL_GLOBAL_SYNC2 0x00000004 // Global sync generator 2\r
+#define PWM_CTL_GLOBAL_SYNC1 0x00000002 // Global sync generator 1\r
+#define PWM_CTL_GLOBAL_SYNC0 0x00000001 // Global sync generator 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the PWM Time Base Sync register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_SYNC_SYNC2 0x00000004 // Reset generator 2 counter\r
+#define PWM_SYNC_SYNC1 0x00000002 // Reset generator 1 counter\r
+#define PWM_SYNC_SYNC0 0x00000001 // Reset generator 0 counter\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the PWM Output Enable register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_ENABLE_PWM5EN 0x00000020 // PWM5 pin enable\r
+#define PWM_ENABLE_PWM4EN 0x00000010 // PWM4 pin enable\r
+#define PWM_ENABLE_PWM3EN 0x00000008 // PWM3 pin enable\r
+#define PWM_ENABLE_PWM2EN 0x00000004 // PWM2 pin enable\r
+#define PWM_ENABLE_PWM1EN 0x00000002 // PWM1 pin enable\r
+#define PWM_ENABLE_PWM0EN 0x00000001 // PWM0 pin enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the PWM Inversion register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_INVERT_PWM5INV 0x00000020 // PWM5 pin invert\r
+#define PWM_INVERT_PWM4INV 0x00000010 // PWM4 pin invert\r
+#define PWM_INVERT_PWM3INV 0x00000008 // PWM3 pin invert\r
+#define PWM_INVERT_PWM2INV 0x00000004 // PWM2 pin invert\r
+#define PWM_INVERT_PWM1INV 0x00000002 // PWM1 pin invert\r
+#define PWM_INVERT_PWM0INV 0x00000001 // PWM0 pin invert\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the PWM Fault register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_FAULT_FAULT5 0x00000020 // PWM5 pin fault\r
+#define PWM_FAULT_FAULT4 0x00000010 // PWM5 pin fault\r
+#define PWM_FAULT_FAULT3 0x00000008 // PWM5 pin fault\r
+#define PWM_FAULT_FAULT2 0x00000004 // PWM5 pin fault\r
+#define PWM_FAULT_FAULT1 0x00000002 // PWM5 pin fault\r
+#define PWM_FAULT_FAULT0 0x00000001 // PWM5 pin fault\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM Interrupt Register bit definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_INT_INTFAULT 0x00010000 // Fault interrupt pending\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the PWM Status register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_STATUS_FAULT 0x00000001 // Fault status\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM Generator standard offsets.\r
+//\r
+//*****************************************************************************\r
+#define PWM_GEN_0_OFFSET 0x00000040 // PWM0 base\r
+#define PWM_GEN_1_OFFSET 0x00000080 // PWM1 base\r
+#define PWM_GEN_2_OFFSET 0x000000C0 // PWM2 base\r
+\r
+#define PWM_O_X_CTL 0x00000000 // Gen Control Reg\r
+#define PWM_O_X_INTEN 0x00000004 // Gen Int/Trig Enable Reg\r
+#define PWM_O_X_RIS 0x00000008 // Gen Raw Int Status Reg\r
+#define PWM_O_X_ISC 0x0000000C // Gen Int Status Reg\r
+#define PWM_O_X_LOAD 0x00000010 // Gen Load Reg\r
+#define PWM_O_X_COUNT 0x00000014 // Gen Counter Reg\r
+#define PWM_O_X_CMPA 0x00000018 // Gen Compare A Reg\r
+#define PWM_O_X_CMPB 0x0000001C // Gen Compare B Reg\r
+#define PWM_O_X_GENA 0x00000020 // Gen Generator A Ctrl Reg\r
+#define PWM_O_X_GENB 0x00000024 // Gen Generator B Ctrl Reg\r
+#define PWM_O_X_DBCTL 0x00000028 // Gen Dead Band Ctrl Reg\r
+#define PWM_O_X_DBRISE 0x0000002C // Gen DB Rising Edge Delay Reg\r
+#define PWM_O_X_DBFALL 0x00000030 // Gen DB Falling Edge Delay Reg\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM_X Control Register bit definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_X_CTL_ENABLE 0x00000001 // Master enable for gen block\r
+#define PWM_X_CTL_MODE 0x00000002 // Counter mode, down or up/down\r
+#define PWM_X_CTL_DEBUG 0x00000004 // Debug mode\r
+#define PWM_X_CTL_LOADUPD 0x00000008 // Update mode for the load reg\r
+#define PWM_X_CTL_CMPAUPD 0x00000010 // Update mode for comp A reg\r
+#define PWM_X_CTL_CMPBUPD 0x00000020 // Update mode for comp B reg\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM_X Interrupt/Trigger Enable Register bit definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_X_INTEN_INTCNTZERO 0x00000001 // Int if COUNT = 0\r
+#define PWM_X_INTEN_INTCNTLOAD 0x00000002 // Int if COUNT = LOAD\r
+#define PWM_X_INTEN_INTCMPAU 0x00000004 // Int if COUNT = CMPA U\r
+#define PWM_X_INTEN_INTCMPAD 0x00000008 // Int if COUNT = CMPA D\r
+#define PWM_X_INTEN_INTCMPBU 0x00000010 // Int if COUNT = CMPA U\r
+#define PWM_X_INTEN_INTCMPBD 0x00000020 // Int if COUNT = CMPA D\r
+#define PWM_X_INTEN_TRCNTZERO 0x00000100 // Trig if COUNT = 0\r
+#define PWM_X_INTEN_TRCNTLOAD 0x00000200 // Trig if COUNT = LOAD\r
+#define PWM_X_INTEN_TRCMPAU 0x00000400 // Trig if COUNT = CMPA U\r
+#define PWM_X_INTEN_TRCMPAD 0x00000800 // Trig if COUNT = CMPA D\r
+#define PWM_X_INTEN_TRCMPBU 0x00001000 // Trig if COUNT = CMPA U\r
+#define PWM_X_INTEN_TRCMPBD 0x00002000 // Trig if COUNT = CMPA D\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM_X Raw Interrupt Status Register bit definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_X_RIS_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 int\r
+#define PWM_X_RIS_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD int\r
+#define PWM_X_RIS_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U int\r
+#define PWM_X_RIS_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D int\r
+#define PWM_X_RIS_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U int\r
+#define PWM_X_RIS_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D int\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM_X Interrupt Status Register bit definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_X_INT_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 received\r
+#define PWM_X_INT_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD rcvd\r
+#define PWM_X_INT_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U rcvd\r
+#define PWM_X_INT_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D rcvd\r
+#define PWM_X_INT_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U rcvd\r
+#define PWM_X_INT_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D rcvd\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM_X Generator A/B Control Register bit definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_X_GEN_Y_ACTZERO 0x00000003 // Act PWM_X_COUNT = 0\r
+#define PWM_X_GEN_Y_ACTLOAD 0x0000000C // Act PWM_X_COUNT = PWM_X_LOAD\r
+#define PWM_X_GEN_Y_ACTCMPAU 0x00000030 // Act PWM_X_COUNT = PWM_X_CMPA U\r
+#define PWM_X_GEN_Y_ACTCMPAD 0x000000C0 // Act PWM_X_COUNT = PWM_X_CMPA D\r
+#define PWM_X_GEN_Y_ACTCMPBU 0x00000300 // Act PWM_X_COUNT = PWM_X_CMPB U\r
+#define PWM_X_GEN_Y_ACTCMPBD 0x00000C00 // Act PWM_X_COUNT = PWM_X_CMPB D\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM_X Generator A/B Control Register action definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_GEN_ACT_NONE 0x0 // Do nothing\r
+#define PWM_GEN_ACT_INV 0x1 // Invert the output signal\r
+#define PWM_GEN_ACT_ZERO 0x2 // Set the output signal to zero\r
+#define PWM_GEN_ACT_ONE 0x3 // Set the output signal to one\r
+#define PWM_GEN_ACT_ZERO_SHIFT 0 // Shift amount for the zero action\r
+#define PWM_GEN_ACT_LOAD_SHIFT 2 // Shift amount for the load action\r
+#define PWM_GEN_ACT_A_UP_SHIFT 4 // Shift amount for the A up action\r
+#define PWM_GEN_ACT_A_DN_SHIFT 6 // Shift amount for the A dn action\r
+#define PWM_GEN_ACT_B_UP_SHIFT 8 // Shift amount for the B up action\r
+#define PWM_GEN_ACT_B_DN_SHIFT 10 // Shift amount for the B dn action\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM_X Dead Band Control Register bit definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_DBCTL_ENABLE 0x00000001 // Enable dead band insertion\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM Register reset values.\r
+//\r
+//*****************************************************************************\r
+#define PWM_RV_CTL 0x00000000 // Master control of the PWM module\r
+#define PWM_RV_SYNC 0x00000000 // Counter synch for PWM generators\r
+#define PWM_RV_ENABLE 0x00000000 // Master enable for the PWM\r
+ // output pins\r
+#define PWM_RV_INVERT 0x00000000 // Inversion control for\r
+ // PWM output pins\r
+#define PWM_RV_FAULT 0x00000000 // Fault handling for the PWM\r
+ // output pins\r
+#define PWM_RV_INTEN 0x00000000 // Interrupt enable\r
+#define PWM_RV_RIS 0x00000000 // Raw interrupt status\r
+#define PWM_RV_ISC 0x00000000 // Interrupt status and clearing\r
+#define PWM_RV_STATUS 0x00000000 // Status\r
+#define PWM_RV_X_CTL 0x00000000 // Master control of the PWM\r
+ // generator block\r
+#define PWM_RV_X_INTEN 0x00000000 // Interrupt and trigger enable\r
+#define PWM_RV_X_RIS 0x00000000 // Raw interrupt status\r
+#define PWM_RV_X_ISC 0x00000000 // Interrupt status and clearing\r
+#define PWM_RV_X_LOAD 0x00000000 // The load value for the counter\r
+#define PWM_RV_X_COUNT 0x00000000 // The current counter value\r
+#define PWM_RV_X_CMPA 0x00000000 // The comparator A value\r
+#define PWM_RV_X_CMPB 0x00000000 // The comparator B value\r
+#define PWM_RV_X_GENA 0x00000000 // Controls PWM generator A\r
+#define PWM_RV_X_GENB 0x00000000 // Controls PWM generator B\r
+#define PWM_RV_X_DBCTL 0x00000000 // Control the dead band generator\r
+#define PWM_RV_X_DBRISE 0x00000000 // The dead band rising edge delay\r
+ // count\r
+#define PWM_RV_X_DBFALL 0x00000000 // The dead band falling edge delay\r
+ // count\r
+\r
+#endif // __HW_PWM_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_qei.h - Macros used when accessing the QEI hardware.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 991 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_QEI_H__\r
+#define __HW_QEI_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the QEI registers.\r
+//\r
+//*****************************************************************************\r
+#define QEI_O_CTL 0x00000000 // Configuration and control reg.\r
+#define QEI_O_STAT 0x00000004 // Status register\r
+#define QEI_O_POS 0x00000008 // Current position register\r
+#define QEI_O_MAXPOS 0x0000000C // Maximum position register\r
+#define QEI_O_LOAD 0x00000010 // Velocity timer load register\r
+#define QEI_O_TIME 0x00000014 // Velocity timer register\r
+#define QEI_O_COUNT 0x00000018 // Velocity pulse count register\r
+#define QEI_O_SPEED 0x0000001C // Velocity speed register\r
+#define QEI_O_INTEN 0x00000020 // Interrupt enable register\r
+#define QEI_O_RIS 0x00000024 // Raw interrupt status register\r
+#define QEI_O_ISC 0x00000028 // Interrupt status register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_CTL register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_CTL_STALLEN 0x00001000 // Stall enable\r
+#define QEI_CTL_INVI 0x00000800 // Invert Index input\r
+#define QEI_CTL_INVB 0x00000400 // Invert PhB input\r
+#define QEI_CTL_INVA 0x00000200 // Invert PhA input\r
+#define QEI_CTL_VELDIV_M 0x000001C0 // Velocity predivider mask\r
+#define QEI_CTL_VELDIV_1 0x00000000 // Predivide by 1\r
+#define QEI_CTL_VELDIV_2 0x00000040 // Predivide by 2\r
+#define QEI_CTL_VELDIV_4 0x00000080 // Predivide by 4\r
+#define QEI_CTL_VELDIV_8 0x000000C0 // Predivide by 8\r
+#define QEI_CTL_VELDIV_16 0x00000100 // Predivide by 16\r
+#define QEI_CTL_VELDIV_32 0x00000140 // Predivide by 32\r
+#define QEI_CTL_VELDIV_64 0x00000180 // Predivide by 64\r
+#define QEI_CTL_VELDIV_128 0x000001C0 // Predivide by 128\r
+#define QEI_CTL_VELEN 0x00000020 // Velocity enable\r
+#define QEI_CTL_RESMODE 0x00000010 // Position counter reset mode\r
+#define QEI_CTL_CAPMODE 0x00000008 // Edge capture mode\r
+#define QEI_CTL_SIGMODE 0x00000004 // Encoder signaling mode\r
+#define QEI_CTL_SWAP 0x00000002 // Swap input signals\r
+#define QEI_CTL_ENABLE 0x00000001 // QEI enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_STAT register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_STAT_DIRECTION 0x00000002 // Direction of rotation\r
+#define QEI_STAT_ERROR 0x00000001 // Signalling error detected\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_POS register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_POS_M 0xFFFFFFFF // Current encoder position\r
+#define QEI_POS_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_MAXPOS register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_MAXPOS_M 0xFFFFFFFF // Maximum encoder position\r
+#define QEI_MAXPOS_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_LOAD register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_LOAD_M 0xFFFFFFFF // Velocity timer load value\r
+#define QEI_LOAD_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_TIME register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_TIME_M 0xFFFFFFFF // Velocity timer current value\r
+#define QEI_TIME_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_COUNT register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_COUNT_M 0xFFFFFFFF // Encoder running pulse count\r
+#define QEI_COUNT_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_SPEED register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_SPEED_M 0xFFFFFFFF // Encoder pulse count\r
+#define QEI_SPEED_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_INTEN register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_INTEN_ERROR 0x00000008 // Phase error detected\r
+#define QEI_INTEN_DIR 0x00000004 // Direction change\r
+#define QEI_INTEN_TIMER 0x00000002 // Velocity timer expired\r
+#define QEI_INTEN_INDEX 0x00000001 // Index pulse detected\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_RIS register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_RIS_ERROR 0x00000008 // Phase error detected\r
+#define QEI_RIS_DIR 0x00000004 // Direction change\r
+#define QEI_RIS_TIMER 0x00000002 // Velocity timer expired\r
+#define QEI_RIS_INDEX 0x00000001 // Index pulse detected\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_ISC register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_INT_ERROR 0x00000008 // Phase error detected\r
+#define QEI_INT_DIR 0x00000004 // Direction change\r
+#define QEI_INT_TIMER 0x00000002 // Velocity timer expired\r
+#define QEI_INT_INDEX 0x00000001 // Index pulse detected\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the reset values for the QEI registers.\r
+//\r
+//*****************************************************************************\r
+#define QEI_RV_CTL 0x00000000 // Configuration and control reg.\r
+#define QEI_RV_STAT 0x00000000 // Status register\r
+#define QEI_RV_POS 0x00000000 // Current position register\r
+#define QEI_RV_MAXPOS 0x00000000 // Maximum position register\r
+#define QEI_RV_LOAD 0x00000000 // Velocity timer load register\r
+#define QEI_RV_TIME 0x00000000 // Velocity timer register\r
+#define QEI_RV_COUNT 0x00000000 // Velocity pulse count register\r
+#define QEI_RV_SPEED 0x00000000 // Velocity speed register\r
+#define QEI_RV_INTEN 0x00000000 // Interrupt enable register\r
+#define QEI_RV_RIS 0x00000000 // Raw interrupt status register\r
+#define QEI_RV_ISC 0x00000000 // Interrupt status register\r
+\r
+#endif // __HW_QEI_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_ssi.h - Macros used when accessing the SSI hardware.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 991 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_SSI_H__\r
+#define __HW_SSI_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the SSI registers.\r
+//\r
+//*****************************************************************************\r
+#define SSI_O_CR0 0x00000000 // Control register 0\r
+#define SSI_O_CR1 0x00000004 // Control register 1\r
+#define SSI_O_DR 0x00000008 // Data register\r
+#define SSI_O_SR 0x0000000C // Status register\r
+#define SSI_O_CPSR 0x00000010 // Clock prescale register\r
+#define SSI_O_IM 0x00000014 // Int mask set and clear register\r
+#define SSI_O_RIS 0x00000018 // Raw interrupt register\r
+#define SSI_O_MIS 0x0000001C // Masked interrupt register\r
+#define SSI_O_ICR 0x00000020 // Interrupt clear register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SSI Control register 0.\r
+//\r
+//*****************************************************************************\r
+#define SSI_CR0_SCR 0x0000FF00 // Serial clock rate\r
+#define SSI_CR0_SPH 0x00000080 // SSPCLKOUT phase\r
+#define SSI_CR0_SPO 0x00000040 // SSPCLKOUT polarity\r
+#define SSI_CR0_FRF_MASK 0x00000030 // Frame format mask\r
+#define SSI_CR0_FRF_MOTO 0x00000000 // Motorola SPI frame format\r
+#define SSI_CR0_FRF_TI 0x00000010 // TI sync serial frame format\r
+#define SSI_CR0_FRF_NMW 0x00000020 // National Microwire frame format\r
+#define SSI_CR0_DSS 0x0000000F // Data size select\r
+#define SSI_CR0_DSS_4 0x00000003 // 4 bit data\r
+#define SSI_CR0_DSS_5 0x00000004 // 5 bit data\r
+#define SSI_CR0_DSS_6 0x00000005 // 6 bit data\r
+#define SSI_CR0_DSS_7 0x00000006 // 7 bit data\r
+#define SSI_CR0_DSS_8 0x00000007 // 8 bit data\r
+#define SSI_CR0_DSS_9 0x00000008 // 9 bit data\r
+#define SSI_CR0_DSS_10 0x00000009 // 10 bit data\r
+#define SSI_CR0_DSS_11 0x0000000A // 11 bit data\r
+#define SSI_CR0_DSS_12 0x0000000B // 12 bit data\r
+#define SSI_CR0_DSS_13 0x0000000C // 13 bit data\r
+#define SSI_CR0_DSS_14 0x0000000D // 14 bit data\r
+#define SSI_CR0_DSS_15 0x0000000E // 15 bit data\r
+#define SSI_CR0_DSS_16 0x0000000F // 16 bit data\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SSI Control register 1.\r
+//\r
+//*****************************************************************************\r
+#define SSI_CR1_SOD 0x00000008 // Slave mode output disable\r
+#define SSI_CR1_MS 0x00000004 // Master or slave mode select\r
+#define SSI_CR1_SSE 0x00000002 // Sync serial port enable\r
+#define SSI_CR1_LBM 0x00000001 // Loopback mode\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SSI Status register.\r
+//\r
+//*****************************************************************************\r
+#define SSI_SR_BSY 0x00000010 // SSI busy\r
+#define SSI_SR_RFF 0x00000008 // RX FIFO full\r
+#define SSI_SR_RNE 0x00000004 // RX FIFO not empty\r
+#define SSI_SR_TNF 0x00000002 // TX FIFO not full\r
+#define SSI_SR_TFE 0x00000001 // TX FIFO empty\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SSI clock prescale register.\r
+//\r
+//*****************************************************************************\r
+#define SSI_CPSR_CPSDVSR_MASK 0x000000FF // Clock prescale\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define information concerning the SSI Data register.\r
+//\r
+//*****************************************************************************\r
+#define TX_FIFO_SIZE (8) // Number of entries in the TX FIFO\r
+#define RX_FIFO_SIZE (8) // Number of entries in the RX FIFO\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the interrupt mask set and clear,\r
+// raw interrupt, masked interrupt, and interrupt clear registers.\r
+//\r
+//*****************************************************************************\r
+#define SSI_INT_TXFF 0x00000008 // TX FIFO interrupt\r
+#define SSI_INT_RXFF 0x00000004 // RX FIFO interrupt\r
+#define SSI_INT_RXTO 0x00000002 // RX timeout interrupt\r
+#define SSI_INT_RXOR 0x00000001 // RX overrun interrupt\r
+\r
+#endif // __HW_SSI_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_sysctl.h - Macros used when accessing the system control hardware.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 991 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_SYSCTL_H__\r
+#define __HW_SYSCTL_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the system control registers.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DID0 0x400fe000 // Device identification register 0\r
+#define SYSCTL_DID1 0x400fe004 // Device identification register 1\r
+#define SYSCTL_DC0 0x400fe008 // Device capabilities register 0\r
+#define SYSCTL_DC1 0x400fe010 // Device capabilities register 1\r
+#define SYSCTL_DC2 0x400fe014 // Device capabilities register 2\r
+#define SYSCTL_DC3 0x400fe018 // Device capabilities register 3\r
+#define SYSCTL_DC4 0x400fe01C // Device capabilities register 4\r
+#define SYSCTL_PBORCTL 0x400fe030 // POR/BOR reset control register\r
+#define SYSCTL_LDOPCTL 0x400fe034 // LDO power control register\r
+#define SYSCTL_SRCR0 0x400fe040 // Software reset control reg 0\r
+#define SYSCTL_SRCR1 0x400fe044 // Software reset control reg 1\r
+#define SYSCTL_SRCR2 0x400fe048 // Software reset control reg 2\r
+#define SYSCTL_RIS 0x400fe050 // Raw interrupt status register\r
+#define SYSCTL_IMC 0x400fe054 // Interrupt mask/control register\r
+#define SYSCTL_MISC 0x400fe058 // Interrupt status register\r
+#define SYSCTL_RESC 0x400fe05c // Reset cause register\r
+#define SYSCTL_RCC 0x400fe060 // Run-mode clock config register\r
+#define SYSCTL_PLLCFG 0x400fe064 // PLL configuration register\r
+#define SYSCTL_RCGC0 0x400fe100 // Run-mode clock gating register 0\r
+#define SYSCTL_RCGC1 0x400fe104 // Run-mode clock gating register 1\r
+#define SYSCTL_RCGC2 0x400fe108 // Run-mode clock gating register 2\r
+#define SYSCTL_SCGC0 0x400fe110 // Sleep-mode clock gating reg 0\r
+#define SYSCTL_SCGC1 0x400fe114 // Sleep-mode clock gating reg 1\r
+#define SYSCTL_SCGC2 0x400fe118 // Sleep-mode clock gating reg 2\r
+#define SYSCTL_DCGC0 0x400fe120 // Deep Sleep-mode clock gate reg 0\r
+#define SYSCTL_DCGC1 0x400fe124 // Deep Sleep-mode clock gate reg 1\r
+#define SYSCTL_DCGC2 0x400fe128 // Deep Sleep-mode clock gate reg 2\r
+#define SYSCTL_CLKVCLR 0x400fe150 // Clock verifcation clear register\r
+#define SYSCTL_LDOARST 0x400fe160 // LDO reset control register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DID0 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DID0_VER_MASK 0x70000000 // DID0 version mask\r
+#define SYSCTL_DID0_VER_0 0x00000000 // DID0 version 0\r
+#define SYSCTL_DID0_MAJ_MASK 0x0000FF00 // Major revision mask\r
+#define SYSCTL_DID0_MAJ_A 0x00000000 // Major revision A\r
+#define SYSCTL_DID0_MAJ_B 0x00000100 // Major revision B\r
+#define SYSCTL_DID0_MIN_MASK 0x000000FF // Minor revision mask\r
+#define SYSCTL_DID0_MIN_0 0x00000000 // Minor revision 0\r
+#define SYSCTL_DID0_MIN_1 0x00000001 // Minor revision 1\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DID1 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DID1_VER_MASK 0xF0000000 // Register version mask\r
+#define SYSCTL_DID1_FAM_MASK 0x0F000000 // Family mask\r
+#define SYSCTL_DID1_FAM_S 0x00000000 // Stellaris family\r
+#define SYSCTL_DID1_PRTNO_MASK 0x00FF0000 // Part number mask\r
+#define SYSCTL_DID1_PRTNO_101 0x00010000 // LM3S101\r
+#define SYSCTL_DID1_PRTNO_102 0x00020000 // LM3S102\r
+#define SYSCTL_DID1_PRTNO_301 0x00110000 // LM3S301\r
+#define SYSCTL_DID1_PRTNO_310 0x00120000 // LM3S310\r
+#define SYSCTL_DID1_PRTNO_315 0x00130000 // LM3S315\r
+#define SYSCTL_DID1_PRTNO_316 0x00140000 // LM3S316\r
+#define SYSCTL_DID1_PRTNO_328 0x00150000 // LM3S328\r
+#define SYSCTL_DID1_PRTNO_601 0x00210000 // LM3S601\r
+#define SYSCTL_DID1_PRTNO_610 0x00220000 // LM3S610\r
+#define SYSCTL_DID1_PRTNO_611 0x00230000 // LM3S611\r
+#define SYSCTL_DID1_PRTNO_612 0x00240000 // LM3S612\r
+#define SYSCTL_DID1_PRTNO_613 0x00250000 // LM3S613\r
+#define SYSCTL_DID1_PRTNO_615 0x00260000 // LM3S615\r
+#define SYSCTL_DID1_PRTNO_628 0x00270000 // LM3S628\r
+#define SYSCTL_DID1_PRTNO_801 0x00310000 // LM3S801\r
+#define SYSCTL_DID1_PRTNO_811 0x00320000 // LM3S811\r
+#define SYSCTL_DID1_PRTNO_812 0x00330000 // LM3S812\r
+#define SYSCTL_DID1_PRTNO_815 0x00340000 // LM3S815\r
+#define SYSCTL_DID1_PRTNO_828 0x00350000 // LM3S828\r
+#define SYSCTL_DID1_TEMP_MASK 0x000000E0 // Temperature range mask\r
+#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temp range (0..70C)\r
+#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temp range (-40..85C)\r
+#define SYSCTL_DID1_PKG_MASK 0x00000018 // Package mask\r
+#define SYSCTL_DID1_PKG_28SOIC 0x00000000 // 28-pin SOIC\r
+#define SYSCTL_DID1_PKG_48QFP 0x00000008 // 48-pin QFP\r
+#define SYSCTL_DID1_ROHS 0x00000004 // Part is RoHS compliant\r
+#define SYSCTL_DID1_QUAL_MASK 0x00000003 // Qualification status mask\r
+#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering sample (unqualified)\r
+#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot production (unqualified)\r
+#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully qualified\r
+#define SYSCTL_DID1_PRTNO_SHIFT 16\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DC0 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DC0_SRAMSZ_MASK 0xFFFF0000 // SRAM size mask\r
+#define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 // 2kB of SRAM\r
+#define SYSCTL_DC0_SRAMSZ_4KB 0x000F0000 // 4kB of SRAM\r
+#define SYSCTL_DC0_SRAMSZ_8KB 0x001F0000 // 8kB of SRAM\r
+#define SYSCTL_DC0_FLASHSZ_MASK 0x0000FFFF // Flash size mask\r
+#define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 // 8kB of flash\r
+#define SYSCTL_DC0_FLASHSZ_16KB 0x00000007 // 16kB of flash\r
+#define SYSCTL_DC0_FLASHSZ_32KB 0x0000000F // 32kB of flash\r
+#define SYSCTL_DC0_FLASHSZ_64KB 0x0000001F // 64kB of flash\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DC1 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DC1_PWM 0x00100000 // PWM module present\r
+#define SYSCTL_DC1_ADC 0x00010000 // ADC module present\r
+#define SYSCTL_DC1_SYSDIV_MASK 0x0000F000 // Minimum system divider mask\r
+#define SYSCTL_DC1_ADCSPD_MASK 0x00000F00 // ADC speed mask\r
+#define SYSCTL_DC1_ADCSPD_1M 0x00000300 // 1Msps ADC\r
+#define SYSCTL_DC1_ADCSPD_500K 0x00000200 // 500Ksps ADC\r
+#define SYSCTL_DC1_ADCSPD_250K 0x00000100 // 250Ksps ADC\r
+#define SYSCTL_DC1_ADCSPD_125K 0x00000000 // 125Ksps ADC\r
+#define SYSCTL_DC1_MPU 0x00000080 // Cortex M3 MPU present\r
+#define SYSCTL_DC1_TEMP 0x00000020 // Temperature sensor present\r
+#define SYSCTL_DC1_PLL 0x00000010 // PLL present\r
+#define SYSCTL_DC1_WDOG 0x00000008 // Watchdog present\r
+#define SYSCTL_DC1_SWO 0x00000004 // Serial wire output present\r
+#define SYSCTL_DC1_SWD 0x00000002 // Serial wire debug present\r
+#define SYSCTL_DC1_JTAG 0x00000001 // JTAG debug present\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DC2 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DC2_COMP2 0x04000000 // Analog comparator 2 present\r
+#define SYSCTL_DC2_COMP1 0x02000000 // Analog comparator 1 present\r
+#define SYSCTL_DC2_COMP0 0x01000000 // Analog comparator 0 present\r
+#define SYSCTL_DC2_TIMER2 0x00040000 // Timer 2 present\r
+#define SYSCTL_DC2_TIMER1 0x00020000 // Timer 1 present\r
+#define SYSCTL_DC2_TIMER0 0x00010000 // Timer 0 present\r
+#define SYSCTL_DC2_I2C 0x00001000 // I2C present\r
+#define SYSCTL_DC2_QEI 0x00000100 // QEI present\r
+#define SYSCTL_DC2_SSI 0x00000010 // SSI present\r
+#define SYSCTL_DC2_UART1 0x00000002 // UART 1 present\r
+#define SYSCTL_DC2_UART0 0x00000001 // UART 0 present\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DC3 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DC3_32KHZ 0x80000000 // 32kHz pin present\r
+#define SYSCTL_DC3_CCP5 0x20000000 // CCP5 pin present\r
+#define SYSCTL_DC3_CCP4 0x10000000 // CCP4 pin present\r
+#define SYSCTL_DC3_CCP3 0x08000000 // CCP3 pin present\r
+#define SYSCTL_DC3_CCP2 0x04000000 // CCP2 pin present\r
+#define SYSCTL_DC3_CCP1 0x02000000 // CCP1 pin present\r
+#define SYSCTL_DC3_CCP0 0x01000000 // CCP0 pin present\r
+#define SYSCTL_DC3_ADC7 0x00800000 // ADC7 pin present\r
+#define SYSCTL_DC3_ADC6 0x00400000 // ADC6 pin present\r
+#define SYSCTL_DC3_ADC5 0x00200000 // ADC5 pin present\r
+#define SYSCTL_DC3_ADC4 0x00100000 // ADC4 pin present\r
+#define SYSCTL_DC3_ADC3 0x00080000 // ADC3 pin present\r
+#define SYSCTL_DC3_ADC2 0x00040000 // ADC2 pin present\r
+#define SYSCTL_DC3_ADC1 0x00020000 // ADC1 pin present\r
+#define SYSCTL_DC3_ADC0 0x00010000 // ADC0 pin present\r
+#define SYSCTL_DC3_C2O 0x00004000 // C2o pin present\r
+#define SYSCTL_DC3_C2PLUS 0x00002000 // C2+ pin present\r
+#define SYSCTL_DC3_C2MINUS 0x00001000 // C2- pin present\r
+#define SYSCTL_DC3_C1O 0x00000800 // C1o pin present\r
+#define SYSCTL_DC3_C1PLUS 0x00000400 // C1+ pin present\r
+#define SYSCTL_DC3_C1MINUS 0x00000200 // C1- pin present\r
+#define SYSCTL_DC3_C0O 0x00000100 // C0o pin present\r
+#define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ pin present\r
+#define SYSCTL_DC3_C0MINUS 0x00000040 // C0- pin present\r
+#define SYSCTL_DC3_PWM5 0x00000020 // PWM5 pin present\r
+#define SYSCTL_DC3_PWM4 0x00000010 // PWM4 pin present\r
+#define SYSCTL_DC3_PWM3 0x00000008 // PWM3 pin present\r
+#define SYSCTL_DC3_PWM2 0x00000004 // PWM2 pin present\r
+#define SYSCTL_DC3_PWM1 0x00000002 // PWM1 pin present\r
+#define SYSCTL_DC3_PWM0 0x00000001 // PWM0 pin present\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DC4 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DC4_GPIOE 0x00000010 // GPIO port E present\r
+#define SYSCTL_DC4_GPIOD 0x00000008 // GPIO port D present\r
+#define SYSCTL_DC4_GPIOC 0x00000004 // GPIO port C present\r
+#define SYSCTL_DC4_GPIOB 0x00000002 // GPIO port B present\r
+#define SYSCTL_DC4_GPIOA 0x00000001 // GPIO port A present\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_PBORCTL register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_PBORCTL_BOR_MASK 0x0000FFFC // BOR wait timer\r
+#define SYSCTL_PBORCTL_BORIOR 0x00000002 // BOR interrupt or reset\r
+#define SYSCTL_PBORCTL_BORWT 0x00000001 // BOR wait and check for noise\r
+#define SYSCTL_PBORCTL_BOR_SH 2\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_LDOPCTL register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_LDOPCTL_MASK 0x0000003F // Voltage adjust mask\r
+#define SYSCTL_LDOPCTL_2_25V 0x00000005 // LDO output of 2.25V\r
+#define SYSCTL_LDOPCTL_2_30V 0x00000004 // LDO output of 2.30V\r
+#define SYSCTL_LDOPCTL_2_35V 0x00000003 // LDO output of 2.35V\r
+#define SYSCTL_LDOPCTL_2_40V 0x00000002 // LDO output of 2.40V\r
+#define SYSCTL_LDOPCTL_2_45V 0x00000001 // LDO output of 2.45V\r
+#define SYSCTL_LDOPCTL_2_50V 0x00000000 // LDO output of 2.50V\r
+#define SYSCTL_LDOPCTL_2_55V 0x0000001F // LDO output of 2.55V\r
+#define SYSCTL_LDOPCTL_2_60V 0x0000001E // LDO output of 2.60V\r
+#define SYSCTL_LDOPCTL_2_65V 0x0000001D // LDO output of 2.65V\r
+#define SYSCTL_LDOPCTL_2_70V 0x0000001C // LDO output of 2.70V\r
+#define SYSCTL_LDOPCTL_2_75V 0x0000001B // LDO output of 2.75V\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_SRCR0, SYSCTL_RCGC0,\r
+// SYSCTL_SCGC0, and SYSCTL_DCGC0 registers.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_SET0_PWM 0x00100000 // PWM module\r
+#define SYSCTL_SET0_ADC 0x00010000 // ADC module\r
+#define SYSCTL_SET0_ADCSPD_MASK 0x00000F00 // ADC speed mask\r
+#define SYSCTL_SET0_ADCSPD_1M 0x00000300 // 1Msps ADC\r
+#define SYSCTL_SET0_ADCSPD_500K 0x00000200 // 500Ksps ADC\r
+#define SYSCTL_SET0_ADCSPD_250K 0x00000100 // 250Ksps ADC\r
+#define SYSCTL_SET0_ADCSPD_125K 0x00000000 // 125Ksps ADC\r
+#define SYSCTL_SET0_WDOG 0x00000008 // Watchdog module\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_SRCR1, SYSCTL_RCGC1,\r
+// SYSCTL_SCGC1, and SYSCTL_DCGC1 registers.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_SET1_COMP2 0x04000000 // Analog comparator module 2\r
+#define SYSCTL_SET1_COMP1 0x02000000 // Analog comparator module 1\r
+#define SYSCTL_SET1_COMP0 0x01000000 // Analog comparator module 0\r
+#define SYSCTL_SET1_TIMER2 0x00040000 // Timer module 2\r
+#define SYSCTL_SET1_TIMER1 0x00020000 // Timer module 1\r
+#define SYSCTL_SET1_TIMER0 0x00010000 // Timer module 0\r
+#define SYSCTL_SET1_I2C 0x00001000 // I2C module\r
+#define SYSCTL_SET1_QEI 0x00000100 // QEI module\r
+#define SYSCTL_SET1_SSI 0x00000010 // SSI module\r
+#define SYSCTL_SET1_UART1 0x00000002 // UART module 1\r
+#define SYSCTL_SET1_UART0 0x00000001 // UART module 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_SRCR2, SYSCTL_RCGC2,\r
+// SYSCTL_SCGC2, and SYSCTL_DCGC2 registers.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_SET2_GPIOE 0x00000010 // GPIO E module\r
+#define SYSCTL_SET2_GPIOD 0x00000008 // GPIO D module\r
+#define SYSCTL_SET2_GPIOC 0x00000004 // GPIO C module\r
+#define SYSCTL_SET2_GPIOB 0x00000002 // GPIO B module\r
+#define SYSCTL_SET2_GPIOA 0x00000001 // GIPO A module\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_RIS, SYSCTL_IMC, and\r
+// SYSCTL_IMS registers.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt\r
+#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt\r
+#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int\r
+#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int\r
+#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt\r
+#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt\r
+#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_RESC register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_RESC_LDO 0x00000020 // LDO power OK lost reset\r
+#define SYSCTL_RESC_SW 0x00000010 // Software reset\r
+#define SYSCTL_RESC_WDOG 0x00000008 // Watchdog reset\r
+#define SYSCTL_RESC_BOR 0x00000004 // Brown-out reset\r
+#define SYSCTL_RESC_POR 0x00000002 // Power on reset\r
+#define SYSCTL_RESC_EXT 0x00000001 // External reset\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_RCC register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_RCC_ACG 0x08000000 // Automatic clock gating\r
+#define SYSCTL_RCC_SYSDIV_MASK 0x07800000 // System clock divider\r
+#define SYSCTL_RCC_SYSDIV_2 0x00800000 // System clock /2\r
+#define SYSCTL_RCC_SYSDIV_3 0x01000000 // System clock /3\r
+#define SYSCTL_RCC_SYSDIV_4 0x01800000 // System clock /4\r
+#define SYSCTL_RCC_SYSDIV_5 0x02000000 // System clock /5\r
+#define SYSCTL_RCC_SYSDIV_6 0x02800000 // System clock /6\r
+#define SYSCTL_RCC_SYSDIV_7 0x03000000 // System clock /7\r
+#define SYSCTL_RCC_SYSDIV_8 0x03800000 // System clock /8\r
+#define SYSCTL_RCC_SYSDIV_9 0x04000000 // System clock /9\r
+#define SYSCTL_RCC_SYSDIV_10 0x04800000 // System clock /10\r
+#define SYSCTL_RCC_SYSDIV_11 0x05000000 // System clock /11\r
+#define SYSCTL_RCC_SYSDIV_12 0x05800000 // System clock /12\r
+#define SYSCTL_RCC_SYSDIV_13 0x06000000 // System clock /13\r
+#define SYSCTL_RCC_SYSDIV_14 0x06800000 // System clock /14\r
+#define SYSCTL_RCC_SYSDIV_15 0x07000000 // System clock /15\r
+#define SYSCTL_RCC_SYSDIV_16 0x07800000 // System clock /16\r
+#define SYSCTL_RCC_USE_SYSDIV 0x00400000 // Use sytem clock divider\r
+#define SYSCTL_RCC_USE_PWMDIV 0x00100000 // Use PWM clock divider\r
+#define SYSCTL_RCC_PWMDIV_MASK 0x000E0000 // PWM clock divider\r
+#define SYSCTL_RCC_PWMDIV_2 0x00000000 // PWM clock /2\r
+#define SYSCTL_RCC_PWMDIV_4 0x00020000 // PWM clock /4\r
+#define SYSCTL_RCC_PWMDIV_8 0x00040000 // PWM clock /8\r
+#define SYSCTL_RCC_PWMDIV_16 0x00060000 // PWM clock /16\r
+#define SYSCTL_RCC_PWMDIV_32 0x00080000 // PWM clock /32\r
+#define SYSCTL_RCC_PWMDIV_64 0x000A0000 // PWM clock /64\r
+#define SYSCTL_RCC_PWRDN 0x00002000 // PLL power down\r
+#define SYSCTL_RCC_OE 0x00001000 // PLL output enable\r
+#define SYSCTL_RCC_BYPASS 0x00000800 // PLL bypass\r
+#define SYSCTL_RCC_PLLVER 0x00000400 // PLL verification timer enable\r
+#define SYSCTL_RCC_XTAL_MASK 0x000003C0 // Crystal attached to main osc\r
+#define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100 // Using a 3.579545MHz crystal\r
+#define SYSCTL_RCC_XTAL_3_68MHz 0x00000140 // Using a 3.6864MHz crystal\r
+#define SYSCTL_RCC_XTAL_4MHz 0x00000180 // Using a 4MHz crystal\r
+#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // Using a 4.096MHz crystal\r
+#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // Using a 4.9152MHz crystal\r
+#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // Using a 5MHz crystal\r
+#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // Using a 5.12MHz crystal\r
+#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // Using a 6MHz crystal\r
+#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // Using a 6.144MHz crystal\r
+#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // Using a 7.3728MHz crystal\r
+#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // Using a 8MHz crystal\r
+#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // Using a 8.192MHz crystal\r
+#define SYSCTL_RCC_OSCSRC_MASK 0x00000030 // Oscillator input select\r
+#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // Use the main oscillator\r
+#define SYSCTL_RCC_OSCSRC_INT 0x00000010 // Use the internal oscillator\r
+#define SYSCTL_RCC_OSCSRC_INT4 0x00000020 // Use the internal oscillator / 4\r
+#define SYSCTL_RCC_IOSCVER 0x00000008 // Int. osc. verification timer en\r
+#define SYSCTL_RCC_MOSCVER 0x00000004 // Main osc. verification timer en\r
+#define SYSCTL_RCC_IOSCDIS 0x00000002 // Internal oscillator disable\r
+#define SYSCTL_RCC_MOSCDIS 0x00000001 // Main oscillator disable\r
+#define SYSCTL_RCC_SYSDIV_SHIFT 23 // Shift to the SYSDIV field\r
+#define SYSCTL_RCC_PWMDIV_SHIFT 17 // Shift to the PWMDIV field\r
+#define SYSCTL_RCC_XTAL_SHIFT 6 // Shift to the XTAL field\r
+#define SYSCTL_RCC_OSCSRC_SHIFT 4 // Shift to the OSCSRC field\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_PLLCFG register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_PLLCFG_OD_MASK 0x0000C000 // Output divider\r
+#define SYSCTL_PLLCFG_OD_1 0x00000000 // Output divider is 1\r
+#define SYSCTL_PLLCFG_OD_2 0x00004000 // Output divider is 2\r
+#define SYSCTL_PLLCFG_OD_4 0x00008000 // Output divider is 4\r
+#define SYSCTL_PLLCFG_F_MASK 0x00003FE0 // PLL multiplier\r
+#define SYSCTL_PLLCFG_R_MASK 0x0000001F // Input predivider\r
+#define SYSCTL_PLLCFG_F_SHIFT 5\r
+#define SYSCTL_PLLCFG_R_SHIFT 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_CLKVCLR register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_CLKVCLR_CLR 0x00000001 // Clear clock verification fault\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_LDOARST register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_LDOARST_ARST 0x00000001 // Allow LDO to reset device\r
+\r
+#endif // __HW_SYSCTL_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_timer.h - Defines and macros used when accessing the timer.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 991 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_TIMER_H__\r
+#define __HW_TIMER_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the timer registers.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_O_CFG 0x00000000 // Configuration register\r
+#define TIMER_O_TAMR 0x00000004 // TimerA mode register\r
+#define TIMER_O_TBMR 0x00000008 // TimerB mode register\r
+#define TIMER_O_CTL 0x0000000C // Control register\r
+#define TIMER_O_IMR 0x00000018 // Interrupt mask register\r
+#define TIMER_O_RIS 0x0000001C // Interrupt status register\r
+#define TIMER_O_MIS 0x00000020 // Masked interrupt status reg.\r
+#define TIMER_O_ICR 0x00000024 // Interrupt clear register\r
+#define TIMER_O_TAILR 0x00000028 // TimerA interval load register\r
+#define TIMER_O_TBILR 0x0000002C // TimerB interval load register\r
+#define TIMER_O_TAMATCHR 0x00000030 // TimerA match register\r
+#define TIMER_O_TBMATCHR 0x00000034 // TimerB match register\r
+#define TIMER_O_TAPR 0x00000038 // TimerA prescale register\r
+#define TIMER_O_TBPR 0x0000003C // TimerB prescale register\r
+#define TIMER_O_TAPMR 0x00000040 // TimerA prescale match register\r
+#define TIMER_O_TBPMR 0x00000044 // TimerB prescale match register\r
+#define TIMER_O_TAR 0x00000048 // TimerA register\r
+#define TIMER_O_TBR 0x0000004C // TimerB register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the reset values of the timer registers.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_RV_CFG 0x00000000 // Configuration register RV\r
+#define TIMER_RV_TAMR 0x00000000 // TimerA mode register RV\r
+#define TIMER_RV_TBMR 0x00000000 // TimerB mode register RV\r
+#define TIMER_RV_CTL 0x00000000 // Control register RV\r
+#define TIMER_RV_IMR 0x00000000 // Interrupt mask register RV\r
+#define TIMER_RV_RIS 0x00000000 // Interrupt status register RV\r
+#define TIMER_RV_MIS 0x00000000 // Masked interrupt status reg RV\r
+#define TIMER_RV_ICR 0x00000000 // Interrupt clear register RV\r
+#define TIMER_RV_TAILR 0xFFFFFFFF // TimerA interval load reg RV\r
+#define TIMER_RV_TBILR 0x0000FFFF // TimerB interval load reg RV\r
+#define TIMER_RV_TAMATCHR 0xFFFFFFFF // TimerA match register RV\r
+#define TIMER_RV_TBMATCHR 0x0000FFFF // TimerB match register RV\r
+#define TIMER_RV_TAPR 0x00000000 // TimerA prescale register RV\r
+#define TIMER_RV_TBPR 0x00000000 // TimerB prescale register RV\r
+#define TIMER_RV_TAPMR 0x00000000 // TimerA prescale match reg RV\r
+#define TIMER_RV_TBPMR 0x00000000 // TimerB prescale match regi RV\r
+#define TIMER_RV_TAR 0xFFFFFFFF // TimerA register RV\r
+#define TIMER_RV_TBR 0x0000FFFF // TimerB register RV\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_CFG register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_CFG_CFG_MSK 0x00000007 // Configuration options mask\r
+#define TIMER_CFG_16_BIT 0x00000004 // Two 16 bit timers\r
+#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32 bit RTC\r
+#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32 bit timer\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_TnMR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TNMR_TNAMS 0x00000008 // Alternate mode select\r
+#define TIMER_TNMR_TNCMR 0x00000004 // Capture mode - count or time\r
+#define TIMER_TNMR_TNTMR_MSK 0x00000003 // Timer mode mask\r
+#define TIMER_TNMR_TNTMR_CAP 0x00000003 // Mode - capture\r
+#define TIMER_TNMR_TNTMR_PERIOD 0x00000002 // Mode - periodic\r
+#define TIMER_TNMR_TNTMR_1_SHOT 0x00000001 // Mode - one shot\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_CTL register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_CTL_TBPWML 0x00004000 // TimerB PWM output level invert\r
+#define TIMER_CTL_TBOTE 0x00002000 // TimerB output trigger enable\r
+#define TIMER_CTL_TBEVENT_MSK 0x00000C00 // TimerB event mode mask\r
+#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // TimerB event mode - both edges\r
+#define TIMER_CTL_TBEVENT_NEG 0x00000400 // TimerB event mode - neg edge\r
+#define TIMER_CTL_TBEVENT_POS 0x00000000 // TimerB event mode - pos edge\r
+#define TIMER_CTL_TBSTALL 0x00000200 // TimerB stall enable\r
+#define TIMER_CTL_TBEN 0x00000100 // TimerB enable\r
+#define TIMER_CTL_TAPWML 0x00000040 // TimerA PWM output level invert\r
+#define TIMER_CTL_TAOTE 0x00000020 // TimerA output trigger enable\r
+#define TIMER_CTL_RTCEN 0x00000010 // RTC counter enable\r
+#define TIMER_CTL_TAEVENT_MSK 0x0000000C // TimerA event mode mask\r
+#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // TimerA event mode - both edges\r
+#define TIMER_CTL_TAEVENT_NEG 0x00000004 // TimerA event mode - neg edge\r
+#define TIMER_CTL_TAEVENT_POS 0x00000000 // TimerA event mode - pos edge\r
+#define TIMER_CTL_TASTALL 0x00000002 // TimerA stall enable\r
+#define TIMER_CTL_TAEN 0x00000001 // TimerA enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_IMR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_IMR_CBEIM 0x00000400 // CaptureB event interrupt mask\r
+#define TIMER_IMR_CBMIM 0x00000200 // CaptureB match interrupt mask\r
+#define TIMER_IMR_TBTOIM 0x00000100 // TimerB time out interrupt mask\r
+#define TIMER_IMR_RTCIM 0x00000008 // RTC interrupt mask\r
+#define TIMER_IMR_CAEIM 0x00000004 // CaptureA event interrupt mask\r
+#define TIMER_IMR_CAMIM 0x00000002 // CaptureA match interrupt mask\r
+#define TIMER_IMR_TATOIM 0x00000001 // TimerA time out interrupt mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_RIS register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_RIS_CBERIS 0x00000400 // CaptureB event raw int status\r
+#define TIMER_RIS_CBMRIS 0x00000200 // CaptureB match raw int status\r
+#define TIMER_RIS_TBTORIS 0x00000100 // TimerB time out raw int status\r
+#define TIMER_RIS_RTCRIS 0x00000008 // RTC raw int status\r
+#define TIMER_RIS_CAERIS 0x00000004 // CaptureA event raw int status\r
+#define TIMER_RIS_CAMRIS 0x00000002 // CaptureA match raw int status\r
+#define TIMER_RIS_TATORIS 0x00000001 // TimerA time out raw int status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_MIS register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_RIS_CBEMIS 0x00000400 // CaptureB event masked int status\r
+#define TIMER_RIS_CBMMIS 0x00000200 // CaptureB match masked int status\r
+#define TIMER_RIS_TBTOMIS 0x00000100 // TimerB time out masked int stat\r
+#define TIMER_RIS_RTCMIS 0x00000008 // RTC masked int status\r
+#define TIMER_RIS_CAEMIS 0x00000004 // CaptureA event masked int status\r
+#define TIMER_RIS_CAMMIS 0x00000002 // CaptureA match masked int status\r
+#define TIMER_RIS_TATOMIS 0x00000001 // TimerA time out masked int stat\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_ICR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_ICR_CBECINT 0x00000400 // CaptureB event interrupt clear\r
+#define TIMER_ICR_CBMCINT 0x00000200 // CaptureB match interrupt clear\r
+#define TIMER_ICR_TBTOCINT 0x00000100 // TimerB time out interrupt clear\r
+#define TIMER_ICR_RTCCINT 0x00000008 // RTC interrupt clear\r
+#define TIMER_ICR_CAECINT 0x00000004 // CaptureA event interrupt clear\r
+#define TIMER_ICR_CAMCINT 0x00000002 // CaptureA match interrupt clear\r
+#define TIMER_ICR_TATOCINT 0x00000001 // TimerA time out interrupt clear\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_TAILR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TAILR_TAILRH 0xFFFF0000 // TimerB load val in 32 bit mode\r
+#define TIMER_TAILR_TAILRL 0x0000FFFF // TimerA interval load value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following defines the bit fields in the TIMER_TBILR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TBILR_TBILRL 0x0000FFFF // TimerB interval load value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_TAMATCHR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TAMATCHR_TAMRH 0xFFFF0000 // TimerB match val in 32 bit mode\r
+#define TIMER_TAMATCHR_TAMRL 0x0000FFFF // TimerA match value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following defines the bit fields in the TIMER_TBMATCHR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TBMATCHR_TBMRL 0x0000FFFF // TimerB match load value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following defines the bit fields in the TIMER_TnPR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TNPR_TNPSR 0x000000FF // TimerN prescale value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following defines the bit fields in the TIMER_TnPMR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TNPMR_TNPSMR 0x000000FF // TimerN prescale match value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_TAR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TAR_TARH 0xFFFF0000 // TimerB val in 32 bit mode\r
+#define TIMER_TAR_TARL 0x0000FFFF // TimerA value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following defines the bit fields in the TIMER_TBR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TBR_TBRL 0x0000FFFF // TimerB value\r
+\r
+#endif // __HW_TIMER_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_types.h - Common types and macros.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 991 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_TYPES_H__\r
+#define __HW_TYPES_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// Define a boolean type, and values for true and false.\r
+//\r
+//*****************************************************************************\r
+typedef unsigned char tBoolean;\r
+\r
+#ifndef true\r
+#define true 1\r
+#endif\r
+\r
+#ifndef false\r
+#define false 0\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Macros for hardware access, both direct and via the bit-band region.\r
+//\r
+//*****************************************************************************\r
+#define HWREG(x) \\r
+ (*((volatile unsigned long *)(x)))\r
+#define HWREGH(x) \\r
+ (*((volatile unsigned short *)(x)))\r
+#define HWREGB(x) \\r
+ (*((volatile unsigned char *)(x)))\r
+#define HWREGBITW(x, b) \\r
+ HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \\r
+ (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))\r
+#define HWREGBITH(x, b) \\r
+ HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \\r
+ (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))\r
+#define HWREGBITB(x, b) \\r
+ HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \\r
+ (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))\r
+\r
+#endif // __HW_TYPES_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_uart.h - Macros and defines used when accessing the UART hardware\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 991 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_UART_H__\r
+#define __HW_UART_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// UART Register Offsets.\r
+//\r
+//*****************************************************************************\r
+#define UART_O_DR 0x00000000 // Data Register\r
+#define UART_O_RSR 0x00000004 // Receive Status Register (read)\r
+#define UART_O_ECR 0x00000004 // Error Clear Register (write)\r
+#define UART_O_FR 0x00000018 // Flag Register (read only)\r
+#define UART_O_IBRD 0x00000024 // Integer Baud Rate Divisor Reg\r
+#define UART_O_FBRD 0x00000028 // Fractional Baud Rate Divisor Reg\r
+#define UART_O_LCR_H 0x0000002C // Line Control Register, HIGH byte\r
+#define UART_O_CTL 0x00000030 // Control Register\r
+#define UART_O_IFLS 0x00000034 // Interrupt FIFO Level Select Reg\r
+#define UART_O_IM 0x00000038 // Interrupt Mask Set/Clear Reg\r
+#define UART_O_RIS 0x0000003C // Raw Interrupt Status Register\r
+#define UART_O_MIS 0x00000040 // Masked Interrupt Status Register\r
+#define UART_O_ICR 0x00000044 // Interrupt Clear Register\r
+#define UART_O_PeriphID4 0x00000FD0 //\r
+#define UART_O_PeriphID5 0x00000FD4 //\r
+#define UART_O_PeriphID6 0x00000FD8 //\r
+#define UART_O_PeriphID7 0x00000FDC //\r
+#define UART_O_PeriphID0 0x00000FE0 //\r
+#define UART_O_PeriphID1 0x00000FE4 //\r
+#define UART_O_PeriphID2 0x00000FE8 //\r
+#define UART_O_PeriphID3 0x00000FEC //\r
+#define UART_O_PCellID0 0x00000FF0 //\r
+#define UART_O_PCellID1 0x00000FF4 //\r
+#define UART_O_PCellID2 0x00000FF8 //\r
+#define UART_O_PCellID3 0x00000FFC //\r
+\r
+//*****************************************************************************\r
+//\r
+// Data Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_DR_OE 0x00000800 // Overrun Error\r
+#define UART_DR_BE 0x00000400 // Break Error\r
+#define UART_DR_PE 0x00000200 // Parity Error\r
+#define UART_DR_FE 0x00000100 // Framing Error\r
+#define UART_DR_DATA_MASK 0x000000FF // UART data\r
+\r
+//*****************************************************************************\r
+//\r
+// Receive Status Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_RSR_OE 0x00000008 // Overrun Error\r
+#define UART_RSR_BE 0x00000004 // Break Error\r
+#define UART_RSR_PE 0x00000002 // Parity Error\r
+#define UART_RSR_FE 0x00000001 // Framing Error\r
+\r
+//*****************************************************************************\r
+//\r
+// Flag Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_FR_TXFE 0x00000080 // TX FIFO Empty\r
+#define UART_FR_RXFF 0x00000040 // RX FIFO Full\r
+#define UART_FR_TXFF 0x00000020 // TX FIFO Full\r
+#define UART_FR_RXFE 0x00000010 // RX FIFO Empty\r
+#define UART_FR_BUSY 0x00000008 // UART Busy\r
+\r
+//*****************************************************************************\r
+//\r
+// Integer baud-rate divisor\r
+//\r
+//*****************************************************************************\r
+#define UART_IBRD_DIVINT_MASK 0x0000FFFF // Integer baud-rate divisor\r
+\r
+//*****************************************************************************\r
+//\r
+// Fractional baud-rate divisor\r
+//\r
+//*****************************************************************************\r
+#define UART_FBRD_DIVFRAC_MASK 0x0000003F // Fractional baud-rate divisor\r
+\r
+//*****************************************************************************\r
+//\r
+// Line Control Register High bits\r
+//\r
+//*****************************************************************************\r
+#define UART_LCR_H_SPS 0x00000080 // Stick Parity Select\r
+#define UART_LCR_H_WLEN 0x00000060 // Word length\r
+#define UART_LCR_H_WLEN_8 0x00000060 // 8 bit data\r
+#define UART_LCR_H_WLEN_7 0x00000040 // 7 bit data\r
+#define UART_LCR_H_WLEN_6 0x00000020 // 6 bit data\r
+#define UART_LCR_H_WLEN_5 0x00000000 // 5 bit data\r
+#define UART_LCR_H_FEN 0x00000010 // Enable FIFO\r
+#define UART_LCR_H_STP2 0x00000008 // Two Stop Bits Select\r
+#define UART_LCR_H_EPS 0x00000004 // Even Parity Select\r
+#define UART_LCR_H_PEN 0x00000002 // Parity Enable\r
+#define UART_LCR_H_BRK 0x00000001 // Send Break\r
+\r
+//*****************************************************************************\r
+//\r
+// Control Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_CTL_RXE 0x00000200 // Receive Enable\r
+#define UART_CTL_TXE 0x00000100 // Transmit Enable\r
+#define UART_CTL_LBE 0x00000080 // Loopback Enable\r
+#define UART_CTL_UARTEN 0x00000001 // UART Enable\r
+\r
+//*****************************************************************************\r
+//\r
+// Interrupt FIFO Level Select Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_IFLS_RX1_8 0x00000000 // 1/8 Full\r
+#define UART_IFLS_RX2_8 0x00000010 // 1/4 Full\r
+#define UART_IFLS_RX4_8 0x00000020 // 1/2 Full\r
+#define UART_IFLS_RX6_8 0x00000030 // 3/4 Full\r
+#define UART_IFLS_RX7_8 0x00000040 // 7/8 Full\r
+#define UART_IFLS_TX1_8 0x00000000 // 1/8 Full\r
+#define UART_IFLS_TX2_8 0x00000001 // 1/4 Full\r
+#define UART_IFLS_TX4_8 0x00000002 // 1/2 Full\r
+#define UART_IFLS_TX6_8 0x00000003 // 3/4 Full\r
+#define UART_IFLS_TX7_8 0x00000004 // 7/8 Full\r
+\r
+//*****************************************************************************\r
+//\r
+// Interrupt Mask Set/Clear Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_IM_OEIM 0x00000400 // Overrun Error Interrupt Mask\r
+#define UART_IM_BEIM 0x00000200 // Break Error Interrupt Mask\r
+#define UART_IM_PEIM 0x00000100 // Parity Error Interrupt Mask\r
+#define UART_IM_FEIM 0x00000080 // Framing Error Interrupt Mask\r
+#define UART_IM_RTIM 0x00000040 // Receive Timeout Interrupt Mask\r
+#define UART_IM_TXIM 0x00000020 // Transmit Interrupt Mask\r
+#define UART_IM_RXIM 0x00000010 // Receive Interrupt Mask\r
+\r
+//*****************************************************************************\r
+//\r
+// Raw Interrupt Status Register\r
+//\r
+//*****************************************************************************\r
+#define UART_RIS_OERIS 0x00000400 // Overrun Error Interrupt Status\r
+#define UART_RIS_BERIS 0x00000200 // Break Error Interrupt Status\r
+#define UART_RIS_PERIS 0x00000100 // Parity Error Interrupt Status\r
+#define UART_RIS_FERIS 0x00000080 // Framing Error Interrupt Status\r
+#define UART_RIS_RTRIS 0x00000040 // Receive Timeout Interrupt Status\r
+#define UART_RIS_TXRIS 0x00000020 // Transmit Interrupt Status\r
+#define UART_RIS_RXRIS 0x00000010 // Receive Interrupt Status\r
+\r
+//*****************************************************************************\r
+//\r
+// Masked Interrupt Status Register\r
+//\r
+//*****************************************************************************\r
+#define UART_MIS_OEMIS 0x00000400 // Overrun Error Interrupt Status\r
+#define UART_MIS_BEMIS 0x00000200 // Break Error Interrupt Status\r
+#define UART_MIS_PEMIS 0x00000100 // Parity Error Interrupt Status\r
+#define UART_MIS_FEMIS 0x00000080 // Framing Error Interrupt Status\r
+#define UART_MIS_RTMIS 0x00000040 // Receive Timeout Interrupt Status\r
+#define UART_MIS_TXMIS 0x00000020 // Transmit Interrupt Status\r
+#define UART_MIS_RXMIS 0x00000010 // Receive Interrupt Status\r
+\r
+//*****************************************************************************\r
+//\r
+// Interrupt Clear Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear\r
+#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear\r
+#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear\r
+#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear\r
+#define UART_ICR_RTIC 0x00000040 // Receive Timeout Interrupt Clear\r
+#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear\r
+#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear\r
+\r
+#define UART_RSR_ANY (UART_RSR_OE | \\r
+ UART_RSR_BE | \\r
+ UART_RSR_PE | \\r
+ UART_RSR_FE)\r
+\r
+//*****************************************************************************\r
+//\r
+// Reset Values for UART Registers.\r
+//\r
+//*****************************************************************************\r
+#define UART_RV_DR 0x00000000\r
+#define UART_RV_RSR 0x00000000\r
+#define UART_RV_ECR 0x00000000\r
+#define UART_RV_FR 0x00000090\r
+#define UART_RV_IBRD 0x00000000\r
+#define UART_RV_FBRD 0x00000000\r
+#define UART_RV_LCR_H 0x00000000\r
+#define UART_RV_CTL 0x00000300\r
+#define UART_RV_IFLS 0x00000012\r
+#define UART_RV_IM 0x00000000\r
+#define UART_RV_RIS 0x00000000\r
+#define UART_RV_MIS 0x00000000\r
+#define UART_RV_ICR 0x00000000\r
+#define UART_RV_PeriphID4 0x00000000\r
+#define UART_RV_PeriphID5 0x00000000\r
+#define UART_RV_PeriphID6 0x00000000\r
+#define UART_RV_PeriphID7 0x00000000\r
+#define UART_RV_PeriphID0 0x00000011\r
+#define UART_RV_PeriphID1 0x00000000\r
+#define UART_RV_PeriphID2 0x00000018\r
+#define UART_RV_PeriphID3 0x00000001\r
+#define UART_RV_PCellID0 0x0000000D\r
+#define UART_RV_PCellID1 0x000000F0\r
+#define UART_RV_PCellID2 0x00000005\r
+#define UART_RV_PCellID3 0x000000B1\r
+\r
+#endif // __HW_UART_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 991 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_WATCHDOG_H__\r
+#define __HW_WATCHDOG_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the Watchdog Timer registers.\r
+//\r
+//*****************************************************************************\r
+#define WDT_O_LOAD 0x00000000 // Load register\r
+#define WDT_O_VALUE 0x00000004 // Current value register\r
+#define WDT_O_CTL 0x00000008 // Control register\r
+#define WDT_O_ICR 0x0000000C // Interrupt clear register\r
+#define WDT_O_RIS 0x00000010 // Raw interrupt status register\r
+#define WDT_O_MIS 0x00000014 // Masked interrupt status register\r
+#define WDT_O_TEST 0x00000418 // Test register\r
+#define WDT_O_LOCK 0x00000C00 // Lock register\r
+#define WDT_O_PeriphID4 0x00000FD0 //\r
+#define WDT_O_PeriphID5 0x00000FD4 //\r
+#define WDT_O_PeriphID6 0x00000FD8 //\r
+#define WDT_O_PeriphID7 0x00000FDC //\r
+#define WDT_O_PeriphID0 0x00000FE0 //\r
+#define WDT_O_PeriphID1 0x00000FE4 //\r
+#define WDT_O_PeriphID2 0x00000FE8 //\r
+#define WDT_O_PeriphID3 0x00000FEC //\r
+#define WDT_O_PCellID0 0x00000FF0 //\r
+#define WDT_O_PCellID1 0x00000FF4 //\r
+#define WDT_O_PCellID2 0x00000FF8 //\r
+#define WDT_O_PCellID3 0x00000FFC //\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the WDT_CTL register.\r
+//\r
+//*****************************************************************************\r
+#define WDT_CTL_RESEN 0x00000002 // Enable reset output\r
+#define WDT_CTL_INTEN 0x00000001 // Enable the WDT counter and int\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the WDT_ISR, WDT_RIS, and WDT_MIS\r
+// registers.\r
+//\r
+//*****************************************************************************\r
+#define WDT_INT_TIMEOUT 0x00000001 // Watchdog timer expired\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the WDT_TEST register.\r
+//\r
+//*****************************************************************************\r
+#define WDT_TEST_STALL 0x00000100 // Watchdog stall enable\r
+#ifndef DEPRECATED\r
+#define WDT_TEST_STALL_EN 0x00000100 // Watchdog stall enable\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the WDT_LOCK register.\r
+//\r
+//*****************************************************************************\r
+#define WDT_LOCK_LOCKED 0x00000001 // Watchdog timer is locked\r
+#define WDT_LOCK_UNLOCKED 0x00000000 // Watchdog timer is unlocked\r
+#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the reset values for the WDT registers.\r
+//\r
+//*****************************************************************************\r
+#define WDT_RV_LOAD 0xFFFFFFFF // Load register\r
+#define WDT_RV_VALUE 0xFFFFFFFF // Current value register\r
+#define WDT_RV_CTL 0x00000000 // Control register\r
+#define WDT_RV_RIS 0x00000000 // Raw interrupt status register\r
+#define WDT_RV_MIS 0x00000000 // Masked interrupt status register\r
+#define WDT_RV_LOCK 0x00000000 // Lock register\r
+#define WDT_RV_PeriphID4 0x00000000 //\r
+#define WDT_RV_PeriphID5 0x00000000 //\r
+#define WDT_RV_PeriphID6 0x00000000 //\r
+#define WDT_RV_PeriphID7 0x00000000 //\r
+#define WDT_RV_PeriphID0 0x00000005 //\r
+#define WDT_RV_PeriphID1 0x00000018 //\r
+#define WDT_RV_PeriphID2 0x00000018 //\r
+#define WDT_RV_PeriphID3 0x00000001 //\r
+#define WDT_RV_PCellID0 0x0000000D //\r
+#define WDT_RV_PCellID1 0x000000F0 //\r
+#define WDT_RV_PCellID2 0x00000005 //\r
+#define WDT_RV_PCellID3 0x000000B1 //\r
+\r
+#endif // __HW_WATCHDOG_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// i2c.c - Driver for Inter-IC (I2C) bus block.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 991 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \addtogroup i2c_api\r
+//! @{\r
+//\r
+//*****************************************************************************\r
+\r
+#include "../hw_i2c.h"\r
+#include "../hw_ints.h"\r
+#include "../hw_memmap.h"\r
+#include "../hw_types.h"\r
+#include "debug.h"\r
+#include "i2c.h"\r
+#include "interrupt.h"\r
+#include "sysctl.h"\r
+\r
+//*****************************************************************************\r
+//\r
+//! Initializes the I2C Master block.\r
+//!\r
+//! \param ulBase base address of the I2C Master module\r
+//! \param bFast set up for fast data transfers\r
+//!\r
+//! This function initializes operation of the I2C Master block. Upon\r
+//! successful initialization of the I2C block, this function will have\r
+//! set the bus speed for the master, and will have enabled the I2C Master\r
+//! block.\r
+//!\r
+//! If the parameter \e bFast is \b true, then the master block will be\r
+//! set up to transfer data at 400 kbps; otherwise, it will be set up to\r
+//! transfer data at 100 kbps.\r
+//!\r
+//! The I2C clocking is dependent upon the system clock rate returned by\r
+//! SysCtlClockGet(); if it does not return the correct system clock rate then\r
+//! the I2C clock rate will be incorrect.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_masterinit) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+I2CMasterInit(unsigned long ulBase, tBoolean bFast)\r
+{\r
+ unsigned long ulSysClk;\r
+ unsigned long ulSCLFreq;\r
+ unsigned long ulTPR;\r
+\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == I2C_MASTER_BASE);\r
+\r
+ //\r
+ // Must enable the device before doing anything else.\r
+ //\r
+ I2CMasterEnable(ulBase);\r
+\r
+ //\r
+ // Get the system clock speed.\r
+ //\r
+ ulSysClk = SysCtlClockGet();\r
+\r
+ //\r
+ // Get the desired SCL speed.\r
+ //\r
+ if(bFast == true)\r
+ {\r
+ ulSCLFreq = I2C_SCL_FAST;\r
+ }\r
+ else\r
+ {\r
+ ulSCLFreq = I2C_SCL_STANDARD;\r
+ }\r
+\r
+ //\r
+ // Compute the clock divider that achieves the fastest speed less than or\r
+ // equal to the desired speed. The numerator is biases to favor a larger\r
+ // clock divider so that the resulting clock is always less than or equal\r
+ // to the desired clock, never greater.\r
+ //\r
+ ulTPR = (((ulSysClk + (2 * I2C_MASTER_TPR_SCL * ulSCLFreq) - 1) /\r
+ (2 * I2C_MASTER_TPR_SCL * ulSCLFreq)) - 1);\r
+ HWREG(ulBase + I2C_MASTER_O_TPR) = ulTPR;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Initializes the I2C Slave block.\r
+//!\r
+//! \param ulBase base address of the I2C Slave module\r
+//! \param ucSlaveAddr 7-bit slave address\r
+//!\r
+//! This function initializes operation of the I2C Slave block. Upon\r
+//! successful initialization of the I2C blocks, this function will have\r
+//! set the slave address and have enabled the I2C Slave block.\r
+//!\r
+//! The parameter \e ucSlaveAddr is the value that will be compared\r
+//! against the slave address sent by an I2C master.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_slaveinit) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == I2C_SLAVE_BASE);\r
+ ASSERT(!(ucSlaveAddr & 0x80));\r
+\r
+ //\r
+ // Must enable the device before doing anything else.\r
+ //\r
+ I2CSlaveEnable(ulBase);\r
+\r
+ //\r
+ // Set up the slave address.\r
+ //\r
+ HWREG(ulBase + I2C_SLAVE_O_OAR) = ucSlaveAddr;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Enables the I2C Master block.\r
+//!\r
+//! \param ulBase base address of the I2C Master module\r
+//!\r
+//! This will enable operation of the I2C Master block.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_masterenable) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+I2CMasterEnable(unsigned long ulBase)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == I2C_MASTER_BASE);\r
+\r
+ //\r
+ // Enable the master block.\r
+ //\r
+ HWREG(ulBase + I2C_MASTER_O_CR) |= I2C_MASTER_CR_MFE;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Enables the I2C Slave block.\r
+//!\r
+//! \param ulBase base address of the I2C Slave module\r
+//!\r
+//! This will enable operation of the I2C Slave block.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_slaveenable) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+I2CSlaveEnable(unsigned long ulBase)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == I2C_SLAVE_BASE);\r
+\r
+ //\r
+ // Enable the clock to the slave block.\r
+ //\r
+ HWREG(ulBase - I2C_O_SLAVE + I2C_MASTER_O_CR) |= I2C_MASTER_CR_SFE;\r
+\r
+ //\r
+ // Enable the slave.\r
+ //\r
+ HWREG(ulBase + I2C_SLAVE_O_CSR) = I2C_SLAVE_CSR_DA;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Disables the I2C master block.\r
+//!\r
+//! \param ulBase base address of the I2C Master module\r
+//!\r
+//! This will disable operation of the I2C master block.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_masterdisable) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+I2CMasterDisable(unsigned long ulBase)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == I2C_MASTER_BASE);\r
+\r
+ //\r
+ // Disable the master block.\r
+ //\r
+ HWREG(ulBase + I2C_MASTER_O_CR) &= ~(I2C_MASTER_CR_MFE);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Disables the I2C slave block.\r
+//!\r
+//! \param ulBase base address of the I2C Slave module\r
+//!\r
+//! This will disable operation of the I2C slave block.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_slavedisable) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+I2CSlaveDisable(unsigned long ulBase)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == I2C_SLAVE_BASE);\r
+\r
+ //\r
+ // Disable the slave.\r
+ //\r
+ HWREG(ulBase + I2C_SLAVE_O_CSR) = 0;\r
+\r
+ //\r
+ // Disable the clock to the slave block.\r
+ //\r
+ HWREG(ulBase - I2C_O_SLAVE + I2C_MASTER_O_CR) &= ~(I2C_MASTER_CR_SFE);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Registers an interrupt handler for the I2C module\r
+//!\r
+//! \param ulBase base address of the I2C module\r
+//! \param pfnHandler is a pointer to the function to be called when the\r
+//! synchronous serial interface interrupt occurs.\r
+//!\r
+//! This sets the handler to be called when an I2C interrupt occurs. This\r
+//! will enable the global interrupt in the interrupt controller; specific I2C\r
+//! interrupts must be enabled via I2CMasterIntEnable() and\r
+//! I2CSlaveIntEnable(). If necessary, it is the interrupt handler's\r
+//! responsibility to clear the interrupt source via I2CMasterIntClear() and\r
+//! I2CSlaveIntClear().\r
+//!\r
+//! \sa IntRegister() for important information about registering interrupt\r
+//! handlers.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+I2CIntRegister(unsigned long ulBase, void (*pfnHandler)(void))\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == I2C_MASTER_BASE);\r
+\r
+ //\r
+ // Register the interrupt handler, returning an error if an error occurs.\r
+ //\r
+ IntRegister(INT_I2C, pfnHandler);\r
+\r
+ //\r
+ // Enable the I2C interrupt.\r
+ //\r
+ IntEnable(INT_I2C);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Unregisters an interrupt handler for the I2C module.\r
+//!\r
+//! \param ulBase base address of the I2C module\r
+//!\r
+//! This function will clear the handler to be called when an I2C\r
+//! interrupt occurs. This will also mask off the interrupt in the interrupt\r
+//! controller so that the interrupt handler no longer is called.\r
+//!\r
+//! \sa IntRegister() for important information about registering interrupt\r
+//! handlers.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+I2CIntUnregister(unsigned long ulBase)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == I2C_MASTER_BASE);\r
+\r
+ //\r
+ // Disable the interrupt.\r
+ //\r
+ IntDisable(INT_I2C);\r
+\r
+ //\r
+ // Unregister the interrupt handler.\r
+ //\r
+ IntUnregister(INT_I2C);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Enables the I2C Master interrupt.\r
+//!\r
+//! \param ulBase base address of the I2C Master module\r
+//!\r
+//! Enables the I2C Master interrupt source.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_masterintenable) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+I2CMasterIntEnable(unsigned long ulBase)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == I2C_MASTER_BASE);\r
+\r
+ //\r
+ // Enable the master interrupt.\r
+ //\r
+ HWREG(ulBase + I2C_MASTER_O_IMR) = 1;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Enables the I2C Slave interrupt.\r
+//!\r
+//! \param ulBase base address of the I2C Slave module\r
+//!\r
+//! Enables the I2C Slave interrupt source.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_slaveintenable) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+I2CSlaveIntEnable(unsigned long ulBase)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == I2C_SLAVE_BASE);\r
+\r
+ //\r
+ // Enable the slave interrupt.\r
+ //\r
+ HWREG(ulBase + I2C_SLAVE_O_IM) = 1;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Disables the I2C Master interrupt.\r
+//!\r
+//! \param ulBase base address of the I2C Master module\r
+//!\r
+//! Disables the I2C Master interrupt source.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_masterintdisable) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+I2CMasterIntDisable(unsigned long ulBase)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == I2C_MASTER_BASE);\r
+\r
+ //\r
+ // Disable the master interrupt.\r
+ //\r
+ HWREG(ulBase + I2C_MASTER_O_IMR) = 0;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Disables the I2C Slave interrupt.\r
+//!\r
+//! \param ulBase base address of the I2C Slave module\r
+//!\r
+//! Disables the I2C Slave interrupt source.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_slaveintdisable) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+I2CSlaveIntDisable(unsigned long ulBase)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == I2C_SLAVE_BASE);\r
+\r
+ //\r
+ // Disable the slave interrupt.\r
+ //\r
+ HWREG(ulBase + I2C_SLAVE_O_IM) = 0;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Gets the current I2C Master interrupt status.\r
+//!\r
+//! \param ulBase base address of the I2C Master module\r
+//! \param bMasked is false if the raw interrupt status is requested and\r
+//! true if the masked interrupt status is requested.\r
+//!\r
+//! This returns the interrupt status for the I2C Master module.\r
+//! Either the raw interrupt status or the status of interrupts that are\r
+//! allowed to reflect to the processor can be returned.\r
+//!\r
+//! \return The current interrupt status, returned as \b true if active\r
+//! or \b false if not active.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_masterintstatus) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+tBoolean\r
+I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == I2C_MASTER_BASE);\r
+\r
+ //\r
+ // Return either the interrupt status or the raw interrupt status as\r
+ // requested.\r
+ //\r
+ if(bMasked)\r
+ {\r
+ return((HWREG(ulBase + I2C_MASTER_O_MIS)) ? true : false);\r
+ }\r
+ else\r
+ {\r
+ return((HWREG(ulBase + I2C_MASTER_O_RIS)) ? true : false);\r
+ }\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Gets the current I2C Slave interrupt status.\r
+//!\r
+//! \param ulBase base address of the I2C Slave module\r
+//! \param bMasked is false if the raw interrupt status is requested and\r
+//! true if the masked interrupt status is requested.\r
+//!\r
+//! This returns the interrupt status for the I2C Slave module.\r
+//! Either the raw interrupt status or the status of interrupts that are\r
+//! allowed to reflect to the processor can be returned.\r
+//!\r
+//! \return The current interrupt status, returned as \b true if active\r
+//! or \b false if not active.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_slaveintstatus) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+tBoolean\r
+I2CSlaveIntStatus(unsigned long ulBase, tBoolean bMasked)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == I2C_SLAVE_BASE);\r
+\r
+ //\r
+ // Return either the interrupt status or the raw interrupt status as\r
+ // requested.\r
+ //\r
+ if(bMasked)\r
+ {\r
+ return((HWREG(ulBase + I2C_SLAVE_O_MIS)) ? true : false);\r
+ }\r
+ else\r
+ {\r
+ return((HWREG(ulBase + I2C_SLAVE_O_RIS)) ? true : false);\r
+ }\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Clears I2C Master interrupt sources.\r
+//!\r
+//! \param ulBase base address of the I2C Master module\r
+//!\r
+//! The I2C Master interrupt source is cleared, so that it no longer asserts.\r
+//! This must be done in the interrupt handler to keep it from being called\r
+//! again immediately upon exit.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_masterintclear) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+I2CMasterIntClear(unsigned long ulBase)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == I2C_MASTER_BASE);\r
+\r
+ //\r
+ // Clear the I2C master interrupt source.\r
+ //\r
+ HWREG(ulBase + I2C_MASTER_O_MICR) = I2C_MASTER_MICR_IC;\r
+\r
+ //\r
+ // Workaround for I2C master interrupt clear errata for rev B Stellaris\r
+ // devices. For later devices, this write is ignored and therefore\r
+ // harmless (other than the slight performance hit).\r
+ //\r
+ HWREG(ulBase + I2C_MASTER_O_MIS) = I2C_MASTER_MICR_IC;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Clears I2C Slave interrupt sources.\r
+//!\r
+//! \param ulBase base address of the I2C Slave module\r
+//!\r
+//! The I2C Slave interrupt source is cleared, so that it no longer asserts.\r
+//! This must be done in the interrupt handler to keep it from being called\r
+//! again immediately upon exit.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_slaveintclear) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+I2CSlaveIntClear(unsigned long ulBase)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == I2C_SLAVE_BASE);\r
+\r
+ //\r
+ // Clear the I2C slave interrupt source.\r
+ //\r
+ HWREG(ulBase + I2C_SLAVE_O_SICR) = I2C_SLAVE_SICR_IC;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Sets the address that the I2C Master will place on the bus.\r
+//!\r
+//! \param ulBase base address of the I2C Master module\r
+//! \param ucSlaveAddr 7-bit slave address\r
+//! \param bReceive flag indicating the type of communication with the slave\r
+//!\r
+//! This function will set the address that the I2C Master will place on the\r
+//! bus when initiating a transaction. When the parameter \e bReceive is set\r
+//! to \b true, the address will indicate that the I2C Master is initiating\r
+//! a read from the slave; otherwise the address will indicate that the I2C\r
+//! Master is initiating a write to the slave.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_masterslaveaddrset) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+I2CMasterSlaveAddrSet(unsigned long ulBase, unsigned char ucSlaveAddr,\r
+ tBoolean bReceive)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == I2C_MASTER_BASE);\r
+ ASSERT(!(ucSlaveAddr & 0x80));\r
+\r
+ //\r
+ // Set the address of the slave with which the master will communicate.\r
+ //\r
+ HWREG(ulBase + I2C_MASTER_O_SA) = (ucSlaveAddr << 1) | bReceive;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Indicates whether or not the I2C Master is busy.\r
+//!\r
+//! \param ulBase base address of the I2C Master module\r
+//!\r
+//! This function returns an indication of whether or not the I2C Master is\r
+//! busy transmitting or receiving data.\r
+//!\r
+//! \return Returns \b true if the I2C Master is busy; otherwise, returns\r
+//! \b false.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_masterbusy) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+tBoolean\r
+I2CMasterBusy(unsigned long ulBase)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == I2C_MASTER_BASE);\r
+\r
+ //\r
+ // Return the busy status.\r
+ //\r
+ if(HWREG(ulBase + I2C_MASTER_O_CS) & I2C_MASTER_CS_BUSY)\r
+ {\r
+ return(true);\r
+ }\r
+ else\r
+ {\r
+ return(false);\r
+ }\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Indicates whether or not the I2C bus is busy.\r
+//!\r
+//! \param ulBase base address of the I2C Master module\r
+//!\r
+//! This function returns an indication of whether or not the I2C bus is\r
+//! busy. This function can be used in a multi-master environment to\r
+//! determine if another master is currently using the bus.\r
+//!\r
+//! \return Returns \b true if the I2C bus is busy; otherwise, returns\r
+//! \b false.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_masterbusbusy) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+tBoolean\r
+I2CMasterBusBusy(unsigned long ulBase)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == I2C_MASTER_BASE);\r
+\r
+ //\r
+ // Return the bus busy status.\r
+ //\r
+ if(HWREG(ulBase + I2C_MASTER_O_CS) & I2C_MASTER_CS_BUS_BUSY)\r
+ {\r
+ return(true);\r
+ }\r
+ else\r
+ {\r
+ return(false);\r
+ }\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Controls the state of the I2C Master module.\r
+//!\r
+//! \param ulBase base address of the I2C Master module\r
+//! \param ulCmd command to be issued to the I2C Master module\r
+//!\r
+//! This function is used to control the state of the Master module send and\r
+//! receive operations. The parameter \e ucCmd can be one of the following\r
+//! values:\r
+//!\r
+//! - I2C_MASTER_CMD_SINGLE_SEND\r
+//! - I2C_MASTER_CMD_SINGLE_RECEIVE\r
+//! - I2C_MASTER_CMD_BURST_SEND_START\r
+//! - I2C_MASTER_CMD_BURST_SEND_CONT\r
+//! - I2C_MASTER_CMD_BURST_SEND_FINISH\r
+//! - I2C_MASTER_CMD_BURST_SEND_ERROR_STOP\r
+//! - I2C_MASTER_CMD_BURST_RECEIVE_START\r
+//! - I2C_MASTER_CMD_BURST_RECEIVE_CONT\r
+//! - I2C_MASTER_CMD_BURST_RECEIVE_FINISH\r
+//! - I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_mastercontrol) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+I2CMasterControl(unsigned long ulBase, unsigned long ulCmd)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == I2C_MASTER_BASE);\r
+ ASSERT((ulCmd == I2C_MASTER_CMD_SINGLE_SEND) ||\r
+ (ulCmd == I2C_MASTER_CMD_SINGLE_RECEIVE) ||\r
+ (ulCmd == I2C_MASTER_CMD_BURST_SEND_START) ||\r
+ (ulCmd == I2C_MASTER_CMD_BURST_SEND_CONT) ||\r
+ (ulCmd == I2C_MASTER_CMD_BURST_SEND_FINISH) ||\r
+ (ulCmd == I2C_MASTER_CMD_BURST_SEND_ERROR_STOP) ||\r
+ (ulCmd == I2C_MASTER_CMD_BURST_RECEIVE_START) ||\r
+ (ulCmd == I2C_MASTER_CMD_BURST_RECEIVE_CONT) ||\r
+ (ulCmd == I2C_MASTER_CMD_BURST_RECEIVE_FINISH) ||\r
+ (ulCmd == I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP));\r
+\r
+ //\r
+ // Send the command.\r
+ //\r
+ HWREG(ulBase + I2C_MASTER_O_CS) = ulCmd;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Gets the error status of the I2C Master module.\r
+//!\r
+//! \param ulBase base address of the I2C Master module\r
+//!\r
+//! This function is used to obtain the error status of the Master module\r
+//! send and receive operations. It returns one of the following values:\r
+//!\r
+//! - I2C_MASTER_ERR_NONE\r
+//! - I2C_MASTER_ERR_ADDR_ACK\r
+//! - I2C_MASTER_ERR_DATA_ACK\r
+//! - I2C_MASTER_ERR_ARB_LOST\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_mastererr) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+unsigned long\r
+I2CMasterErr(unsigned long ulBase)\r
+{\r
+ unsigned long ulErr;\r
+\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == I2C_MASTER_BASE);\r
+\r
+ //\r
+ // Get the raw error state\r
+ //\r
+ ulErr = HWREG(ulBase + I2C_MASTER_O_CS);\r
+\r
+ //\r
+ // If the I2C master is busy, then all the other bit are invalid, and\r
+ // don't have an error to report.\r
+ //\r
+ if(ulErr & I2C_MASTER_CS_BUSY)\r
+ {\r
+ return(I2C_MASTER_ERR_NONE);\r
+ }\r
+\r
+ //\r
+ // Check for errors.\r
+ //\r
+ if(ulErr & I2C_MASTER_CS_ERROR)\r
+ {\r
+ return(ulErr & (I2C_MASTER_CS_ERR_MASK));\r
+ }\r
+ else\r
+ {\r
+ return(I2C_MASTER_ERR_NONE);\r
+ }\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Transmits a byte from the I2C Master.\r
+//!\r
+//! \param ulBase base address of the I2C Master module\r
+//! \param ucData data to be transmitted from the I2C Master\r
+//!\r
+//! This function will place the supplied data into I2C Master Data Register.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_masterdataput) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+I2CMasterDataPut(unsigned long ulBase, unsigned char ucData)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == I2C_MASTER_BASE);\r
+\r
+ //\r
+ // Write the byte.\r
+ //\r
+ HWREG(ulBase + I2C_MASTER_O_DR) = ucData;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Receives a byte that has been sent to the I2C Master.\r
+//!\r
+//! \param ulBase base address of the I2C Master module\r
+//!\r
+//! This function reads a byte of data from the I2C Master Data Register.\r
+//!\r
+//! \return Returns the byte received from by the I2C Master, cast as an\r
+//! unsigned long.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_masterdataget) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+unsigned long\r
+I2CMasterDataGet(unsigned long ulBase)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == I2C_MASTER_BASE);\r
+\r
+ //\r
+ // Read a byte.\r
+ //\r
+ return(HWREG(ulBase + I2C_MASTER_O_DR));\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Gets the I2C Slave module status\r
+//!\r
+//! \param ulBase base address of the I2C Slave module\r
+//!\r
+//! This function will return the action requested from a master, if any. The\r
+//! possible values returned are:\r
+//!\r
+//! - I2C_SLAVE_ACT_NONE\r
+//! - I2C_SLAVE_ACT_RREQ\r
+//! - I2C_SLAVE_ACT_TREQ\r
+//!\r
+//! where I2C_SLAVE_ACT_NONE means that no action has been requested of the\r
+//! I2C Slave module, I2C_SLAVE_ACT_RREQ means that an I2C master has sent\r
+//! data to the I2C Slave module, and I2C_SLAVE_ACT_TREQ means that an I2C\r
+//! master has requested that the I2C Slave module send data.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_slavestatus) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+unsigned long\r
+I2CSlaveStatus(unsigned long ulBase)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == I2C_SLAVE_BASE);\r
+\r
+ //\r
+ // Return the slave status.\r
+ //\r
+ return(HWREG(ulBase + I2C_SLAVE_O_CSR));\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Transmits a byte from the I2C Slave.\r
+//!\r
+//! \param ulBase base address of the I2C Slave module\r
+//! \param ucData data to be transmitted from the I2C Slave\r
+//!\r
+//! This function will place the supplied data into I2C Slave Data Register.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_slavedataput) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+I2CSlaveDataPut(unsigned long ulBase, unsigned char ucData)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == I2C_SLAVE_BASE);\r
+\r
+ //\r
+ // Write the byte.\r
+ //\r
+ HWREG(ulBase + I2C_SLAVE_O_DR) = ucData;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Receives a byte that has been sent to the I2C Slave.\r
+//!\r
+//! \param ulBase base address of the I2C Slave module\r
+//!\r
+//! This function reads a byte of data from the I2C Slave Data Register.\r
+//!\r
+//! \return Returns the byte received from by the I2C Slave, cast as an\r
+//! unsigned long.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_slavedataget) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+unsigned long\r
+I2CSlaveDataGet(unsigned long ulBase)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == I2C_SLAVE_BASE);\r
+\r
+ //\r
+ // Read a byte.\r
+ //\r
+ return(HWREG(ulBase + I2C_SLAVE_O_DR));\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Close the Doxygen group.\r
+//! @}\r
+//\r
+//*****************************************************************************\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// i2c.h - Prototypes for the I2C Driver.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 991 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __I2C_H__\r
+#define __I2C_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Defines for the API.\r
+//\r
+//*****************************************************************************\r
+//*****************************************************************************\r
+//\r
+// Interrupt defines.\r
+//\r
+//*****************************************************************************\r
+#define I2C_INT_MASTER 0x00000001\r
+#define I2C_INT_SLAVE 0x00000002\r
+\r
+//*****************************************************************************\r
+//\r
+// I2C Master commands.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_CMD_SINGLE_SEND \\r
+ (I2C_MASTER_CS_STOP | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_SINGLE_RECEIVE \\r
+ (I2C_MASTER_CS_STOP | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_BURST_SEND_START \\r
+ (I2C_MASTER_CS_START | I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_BURST_SEND_CONT \\r
+ (I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_BURST_SEND_FINISH \\r
+ (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \\r
+ (I2C_MASTER_CS_STOP)\r
+#define I2C_MASTER_CMD_BURST_RECEIVE_START \\r
+ (I2C_MASTER_CS_ACK | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_BURST_RECEIVE_CONT \\r
+ (I2C_MASTER_CS_ACK | I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH \\r
+ (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \\r
+ (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN)\r
+\r
+//*****************************************************************************\r
+//\r
+// I2C Master error status.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_ERR_NONE 0\r
+#define I2C_MASTER_ERR_ADDR_ACK 0x00000004\r
+#define I2C_MASTER_ERR_DATA_ACK 0x00000008\r
+#define I2C_MASTER_ERR_ARB_LOST 0x00000010\r
+\r
+//*****************************************************************************\r
+//\r
+// I2C Slave action requests\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_ACT_NONE 0\r
+#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data\r
+#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data\r
+\r
+//*****************************************************************************\r
+// Miscellaneous I2C driver definitions.\r
+//*****************************************************************************\r
+#define I2C_MASTER_MAX_RETRIES 1000 // Number of retries\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void I2CIntRegister(unsigned long ulBase, void(fnHandler)(void));\r
+extern void I2CIntUnregister(unsigned long ulBase);\r
+extern tBoolean I2CMasterBusBusy(unsigned long ulBase);\r
+extern tBoolean I2CMasterBusy(unsigned long ulBase);\r
+extern void I2CMasterControl(unsigned long ulBase, unsigned long ulCmd);\r
+extern unsigned long I2CMasterDataGet(unsigned long ulBase);\r
+extern void I2CMasterDataPut(unsigned long ulBase, unsigned char ucData);\r
+extern void I2CMasterDisable(unsigned long ulBase);\r
+extern void I2CMasterEnable(unsigned long ulBase);\r
+extern unsigned long I2CMasterErr(unsigned long ulBase);\r
+extern void I2CMasterInit(unsigned long ulBase, tBoolean bFast);\r
+extern void I2CMasterIntClear(unsigned long ulBase);\r
+extern void I2CMasterIntDisable(unsigned long ulBase);\r
+extern void I2CMasterIntEnable(unsigned long ulBase);\r
+extern tBoolean I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern void I2CMasterSlaveAddrSet(unsigned long ulBase,\r
+ unsigned char ucSlaveAddr,\r
+ tBoolean bReceive);\r
+extern unsigned long I2CSlaveDataGet(unsigned long ulBase);\r
+extern void I2CSlaveDataPut(unsigned long ulBase, unsigned char ucData);\r
+extern void I2CSlaveDisable(unsigned long ulBase);\r
+extern void I2CSlaveEnable(unsigned long ulBase);\r
+extern void I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr);\r
+extern void I2CSlaveIntClear(unsigned long ulBase);\r
+extern void I2CSlaveIntDisable(unsigned long ulBase);\r
+extern void I2CSlaveIntEnable(unsigned long ulBase);\r
+extern tBoolean I2CSlaveIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern unsigned long I2CSlaveStatus(unsigned long ulBase);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __I2C_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// interrupt.c - Driver for the NVIC Interrupt Controller.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 991 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \addtogroup interrupt_api\r
+//! @{\r
+//\r
+//*****************************************************************************\r
+\r
+#include "../hw_ints.h"\r
+#include "../hw_nvic.h"\r
+#include "../hw_types.h"\r
+#include "cpu.h"\r
+#include "debug.h"\r
+#include "interrupt.h"\r
+\r
+//*****************************************************************************\r
+//\r
+// This is a mapping between priority grouping encodings and the number of\r
+// preemption priority bits.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_pulpriority) || defined(BUILD_ALL)\r
+const unsigned long g_pulPriority[] =\r
+{\r
+ NVIC_APINT_PRIGROUP_0_8, NVIC_APINT_PRIGROUP_1_7, NVIC_APINT_PRIGROUP_2_6,\r
+ NVIC_APINT_PRIGROUP_3_5, NVIC_APINT_PRIGROUP_4_4, NVIC_APINT_PRIGROUP_5_3,\r
+ NVIC_APINT_PRIGROUP_6_2, NVIC_APINT_PRIGROUP_7_1\r
+};\r
+#else\r
+extern const unsigned long g_pulPriority[];\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// This is a mapping between interrupt number and the register that contains\r
+// the priority encoding for that interrupt.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_pulregs) || defined(BUILD_ALL)\r
+const unsigned long g_pulRegs[12] =\r
+{\r
+ 0, NVIC_SYS_PRI1, NVIC_SYS_PRI2, NVIC_SYS_PRI3, NVIC_PRI0, NVIC_PRI1,\r
+ NVIC_PRI2, NVIC_PRI3, NVIC_PRI4, NVIC_PRI5, NVIC_PRI6, NVIC_PRI7\r
+};\r
+#else\r
+extern const unsigned long g_pulRegs[12];\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! \internal\r
+//! The default interrupt handler.\r
+//!\r
+//! This is the default interrupt handler for all interrupts. It simply loops\r
+//! forever so that the system state is preserved for observation by a\r
+//! debugger. Since interrupts should be disabled before unregistering the\r
+//! corresponding handler, this should never be called.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_defaulthandler) || defined(BUILD_ALL)\r
+void\r
+IntDefaultHandler(void)\r
+{\r
+ //\r
+ // Go into an infinite loop.\r
+ //\r
+ while(1)\r
+ {\r
+ }\r
+}\r
+#else\r
+extern void IntDefaultHandler(void);\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// The processor vector table.\r
+//\r
+// This contains a list of the handlers for the various interrupt sources in\r
+// the system. The layout of this list is defined by the hardware; assertion\r
+// of an interrupt causes the processor to start executing directly at the\r
+// address given in the corresponding location in this list.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_vtable) || defined(BUILD_ALL)\r
+#ifdef ewarm\r
+__no_init void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) @ "VTABLE";\r
+#else\r
+__attribute__((section("vtable")))\r
+void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void);\r
+#endif\r
+#else\r
+extern void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void);\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Enables the processor interrupt.\r
+//!\r
+//! Allows the processor to respond to interrupts. This does not affect the\r
+//! set of interrupts enabled in the interrupt controller; it just gates the\r
+//! single interrupt from the controller to the processor.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_masterenable) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+IntMasterEnable(void)\r
+{\r
+ //\r
+ // Enable processor interrupts.\r
+ //\r
+ CPUcpsie();\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Disables the processor interrupt.\r
+//!\r
+//! Prevents the processor from receiving interrupts. This does not affect the\r
+//! set of interrupts enabled in the interrupt controller; it just gates the\r
+//! single interrupt from the controller to the processor.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_masterdisable) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+IntMasterDisable(void)\r
+{\r
+ //\r
+ // Disable processor interrupts.\r
+ //\r
+ CPUcpsid();\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Registers a function to be called when an interrupt occurs.\r
+//!\r
+//! \param ulInterrupt specifies the interrupt in question.\r
+//! \param pfnHandler is a pointer to the function to be called.\r
+//!\r
+//! This function is used to specify the handler function to be called when the\r
+//! given interrupt is asserted to the processor. When the interrupt occurs,\r
+//! if it is enabled (via IntEnable()), the handler function will be called in\r
+//! interrupt context. Since the handler function can preempt other code, care\r
+//! must be taken to protect memory or peripherals that are accessed by the\r
+//! handler and other non-handler code.\r
+//!\r
+//! \note The use of this function (directly or indirectly via a peripheral\r
+//! driver interrupt register function) moves the interrupt vector table from\r
+//! flash to SRAM. Therefore, care must be taken when linking the application\r
+//! to ensure that the SRAM vector table is located at the beginning of SRAM;\r
+//! otherwise NVIC will not look in the correct portion of memory for the\r
+//! vector table (it requires the vector table be on a 1 kB memory alignment).\r
+//! Normally, the SRAM vector table is so placed via the use of linker scripts;\r
+//! some tool chains, such as the evaluation version of RV-MDK, do not support\r
+//! linker scripts and therefore will not produce a valid executable. See the\r
+//! discussion of compile-time versus run-time interrupt handler registration\r
+//! in the introduction to this chapter.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_register) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void))\r
+{\r
+ unsigned long ulIdx;\r
+\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulInterrupt < NUM_INTERRUPTS);\r
+\r
+ //\r
+ // Make sure that the RAM vector table is correctly aligned.\r
+ //\r
+ ASSERT(((unsigned long)g_pfnRAMVectors & 0x000003ff) == 0);\r
+\r
+ //\r
+ // See if the RAM vector table has been initialized.\r
+ //\r
+ if(HWREG(NVIC_VTABLE) != (unsigned long)g_pfnRAMVectors)\r
+ {\r
+ //\r
+ // Copy the vector table from the beginning of FLASH to the RAM vector\r
+ // table.\r
+ //\r
+ for(ulIdx = 0; ulIdx < NUM_INTERRUPTS; ulIdx++)\r
+ {\r
+ g_pfnRAMVectors[ulIdx] = (void (*)(void))HWREG(ulIdx * 4);\r
+ }\r
+\r
+ //\r
+ // Point NVIC at the RAM vector table.\r
+ //\r
+ HWREG(NVIC_VTABLE) = (unsigned long)g_pfnRAMVectors;\r
+ }\r
+\r
+ //\r
+ // Save the interrupt handler.\r
+ //\r
+ g_pfnRAMVectors[ulInterrupt] = pfnHandler;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Unregisters the function to be called when an interrupt occurs.\r
+//!\r
+//! \param ulInterrupt specifies the interrupt in question.\r
+//!\r
+//! This function is used to indicate that no handler should be called when the\r
+//! given interrupt is asserted to the processor. The interrupt source will be\r
+//! automatically disabled (via IntDisable()) if necessary.\r
+//!\r
+//! \sa IntRegister() for important information about registering interrupt\r
+//! handlers.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_unregister) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+IntUnregister(unsigned long ulInterrupt)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulInterrupt < NUM_INTERRUPTS);\r
+\r
+ //\r
+ // Reset the interrupt handler.\r
+ //\r
+ g_pfnRAMVectors[ulInterrupt] = IntDefaultHandler;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Sets the priority grouping of the interrupt controller.\r
+//!\r
+//! \param ulBits specifies the number of bits of preemptable priority.\r
+//!\r
+//! This function specifies the split between preemptable priority levels and\r
+//! subpriority levels in the interrupt priority specification. The range of\r
+//! the grouping values are dependent upon the hardware implementation; on\r
+//! the Stellaris family it can range from 0 to 3.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_prioritygroupingset) || defined(BUILD_ALL) || \\r
+ defined(DOXYGEN)\r
+void\r
+IntPriorityGroupingSet(unsigned long ulBits)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBits < NUM_PRIORITY_BITS);\r
+\r
+ //\r
+ // Set the priority grouping.\r
+ //\r
+ HWREG(NVIC_APINT) = NVIC_APINT_VECTKEY | g_pulPriority[ulBits];\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Gets the priority grouping of the interrupt controller.\r
+//!\r
+//! This function returns the split between preemptable priority levels and\r
+//! subpriority levels in the interrupt priority specification.\r
+//!\r
+//! \return The number of bits of preemptable priority.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_prioritygroupingget) || defined(BUILD_ALL) || \\r
+ defined(DOXYGEN)\r
+unsigned long\r
+IntPriorityGroupingGet(void)\r
+{\r
+ unsigned long ulLoop, ulValue;\r
+\r
+ //\r
+ // Read the priority grouping.\r
+ //\r
+ ulValue = HWREG(NVIC_APINT) & NVIC_APINT_PRIGROUP_M;\r
+\r
+ //\r
+ // Loop through the priority grouping values.\r
+ //\r
+ for(ulLoop = 0; ulLoop < 8; ulLoop++)\r
+ {\r
+ //\r
+ // Stop looping if this value matches.\r
+ //\r
+ if(ulValue == g_pulPriority[ulLoop])\r
+ {\r
+ break;\r
+ }\r
+ }\r
+\r
+ //\r
+ // Return the number of priority bits.\r
+ //\r
+ return(ulLoop);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Sets the priority of an interrupt.\r
+//!\r
+//! \param ulInterrupt specifies the interrupt in question.\r
+//! \param ucPriority specifies the priority of the interrupt.\r
+//!\r
+//! This function is used to set the priority of an interrupt. When multiple\r
+//! interrupts are asserted simultaneously, the ones with the highest priority\r
+//! are processed before the lower priority interrupts. Smaller numbers\r
+//! correspond to higher interrupt priorities; priority 0 is the highest\r
+//! interrupt priority.\r
+//!\r
+//! The hardware priority mechanism will only look at the upper N bits of the\r
+//! priority level (where N is 3 for the Stellaris family), so any\r
+//! prioritization must be performed in those bits. The remaining bits can be\r
+//! used to sub-prioritize the interrupt sources, and may be used by the\r
+//! hardware priority mechanism on a future part. This arrangement allows\r
+//! priorities to migrate to different NVIC implementations without changing\r
+//! the gross prioritization of the interrupts.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_priorityset) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+IntPrioritySet(unsigned long ulInterrupt, unsigned char ucPriority)\r
+{\r
+ unsigned long ulTemp;\r
+\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulInterrupt >= 4) && (ulInterrupt < NUM_INTERRUPTS));\r
+\r
+ //\r
+ // Set the interrupt priority.\r
+ //\r
+ ulTemp = HWREG(g_pulRegs[ulInterrupt >> 2]);\r
+ ulTemp &= ~(0xFF << (8 * (ulInterrupt & 3)));\r
+ ulTemp |= ucPriority << (8 * (ulInterrupt & 3));\r
+ HWREG(g_pulRegs[ulInterrupt >> 2]) = ulTemp;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Gets the priority of an interrupt.\r
+//!\r
+//! \param ulInterrupt specifies the interrupt in question.\r
+//!\r
+//! This function gets the priority of an interrupt. See IntPrioritySet() for\r
+//! a definition of the priority value.\r
+//!\r
+//! \return Returns the interrupt priority, or -1 if an invalid interrupt was\r
+//! specified.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_priorityget) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+long\r
+IntPriorityGet(unsigned long ulInterrupt)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulInterrupt >= 4) && (ulInterrupt < NUM_INTERRUPTS));\r
+\r
+ //\r
+ // Return the interrupt priority.\r
+ //\r
+ return((HWREG(g_pulRegs[ulInterrupt >> 2]) >> (8 * (ulInterrupt & 3))) &\r
+ 0xFF);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Enables an interrupt.\r
+//!\r
+//! \param ulInterrupt specifies the interrupt to be enabled.\r
+//!\r
+//! The specified interrupt is enabled in the interrupt controller. Other\r
+//! enables for the interrupt (such as at the peripheral level) are unaffected\r
+//! by this function.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_enable) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+IntEnable(unsigned long ulInterrupt)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulInterrupt < NUM_INTERRUPTS);\r
+\r
+ //\r
+ // Determine the interrupt to enable.\r
+ //\r
+ if(ulInterrupt == FAULT_MPU)\r
+ {\r
+ //\r
+ // Enable the MemManage interrupt.\r
+ //\r
+ HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_MEM;\r
+ }\r
+ else if(ulInterrupt == FAULT_BUS)\r
+ {\r
+ //\r
+ // Enable the bus fault interrupt.\r
+ //\r
+ HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_BUS;\r
+ }\r
+ else if(ulInterrupt == FAULT_USAGE)\r
+ {\r
+ //\r
+ // Enable the usage fault interrupt.\r
+ //\r
+ HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_USAGE;\r
+ }\r
+ else if(ulInterrupt == FAULT_SYSTICK)\r
+ {\r
+ //\r
+ // Enable the System Tick interrupt.\r
+ //\r
+ HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN;\r
+ }\r
+ else if(ulInterrupt >= INT_GPIOA)\r
+ {\r
+ //\r
+ // Enable the general interrupt.\r
+ //\r
+ HWREG(NVIC_EN0) = 1 << (ulInterrupt - INT_GPIOA);\r
+ }\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Disables an interrupt.\r
+//!\r
+//! \param ulInterrupt specifies the interrupt to be disabled.\r
+//!\r
+//! The specified interrupt is disabled in the interrupt controller. Other\r
+//! enables for the interrupt (such as at the peripheral level) are unaffected\r
+//! by this function.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_disable) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+IntDisable(unsigned long ulInterrupt)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulInterrupt < NUM_INTERRUPTS);\r
+\r
+ //\r
+ // Determine the interrupt to disable.\r
+ //\r
+ if(ulInterrupt == FAULT_MPU)\r
+ {\r
+ //\r
+ // Disable the MemManage interrupt.\r
+ //\r
+ HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_MEM);\r
+ }\r
+ else if(ulInterrupt == FAULT_BUS)\r
+ {\r
+ //\r
+ // Disable the bus fault interrupt.\r
+ //\r
+ HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_BUS);\r
+ }\r
+ else if(ulInterrupt == FAULT_USAGE)\r
+ {\r
+ //\r
+ // Disable the usage fault interrupt.\r
+ //\r
+ HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_USAGE);\r
+ }\r
+ else if(ulInterrupt == FAULT_SYSTICK)\r
+ {\r
+ //\r
+ // Disable the System Tick interrupt.\r
+ //\r
+ HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN);\r
+ }\r
+ else if(ulInterrupt >= INT_GPIOA)\r
+ {\r
+ //\r
+ // Disable the general interrupt.\r
+ //\r
+ HWREG(NVIC_DIS0) = 1 << (ulInterrupt - INT_GPIOA);\r
+ }\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Close the Doxygen group.\r
+//! @}\r
+//\r
+//*****************************************************************************\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// interrupt.h - Prototypes for the NVIC Interrupt Controller Driver.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 991 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __INTERRUPT_H__\r
+#define __INTERRUPT_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void IntMasterEnable(void);\r
+extern void IntMasterDisable(void);\r
+extern void IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void));\r
+extern void IntUnregister(unsigned long ulInterrupt);\r
+extern void IntPriorityGroupingSet(unsigned long ulBits);\r
+extern unsigned long IntPriorityGroupingGet(void);\r
+extern void IntPrioritySet(unsigned long ulInterrupt,\r
+ unsigned char ucPriority);\r
+extern long IntPriorityGet(unsigned long ulInterrupt);\r
+extern void IntEnable(unsigned long ulInterrupt);\r
+extern void IntDisable(unsigned long ulInterrupt);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __INTERRUPT_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// osram96x16.c - Driver for the OSRAM 96x16 graphical OLED display.\r
+//\r
+// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 1049 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \addtogroup ev_lm3s811_api\r
+//! @{\r
+//\r
+//*****************************************************************************\r
+\r
+#include "hw_i2c.h"\r
+#include "hw_memmap.h"\r
+#include "hw_sysctl.h"\r
+#include "hw_types.h"\r
+#include "debug.h"\r
+#include "gpio.h"\r
+#include "i2c.h"\r
+#include "sysctl.h"\r
+#include "osram96x16.h"\r
+\r
+//*****************************************************************************\r
+//\r
+// The I2C slave address of the SSD0303 controller on the OLED display.\r
+//\r
+//*****************************************************************************\r
+#define SSD0303_ADDR 0x3d\r
+\r
+//*****************************************************************************\r
+//\r
+// A 5x7 font (in a 6x8 cell, where the sixth column is omitted from this\r
+// table) for displaying text on the OLED display. The data is organized as\r
+// bytes from the left column to the right column, with each byte containing\r
+// the top row in the LSB and the bottom row in the MSB.\r
+//\r
+//*****************************************************************************\r
+static const unsigned char g_pucFont[95][5] =\r
+{\r
+ { 0x00, 0x00, 0x00, 0x00, 0x00 }, // " "\r
+ { 0x00, 0x00, 0x4f, 0x00, 0x00 }, // !\r
+ { 0x00, 0x07, 0x00, 0x07, 0x00 }, // "\r
+ { 0x14, 0x7f, 0x14, 0x7f, 0x14 }, // #\r
+ { 0x24, 0x2a, 0x7f, 0x2a, 0x12 }, // $\r
+ { 0x23, 0x13, 0x08, 0x64, 0x62 }, // %\r
+ { 0x36, 0x49, 0x55, 0x22, 0x50 }, // &\r
+ { 0x00, 0x05, 0x03, 0x00, 0x00 }, // '\r
+ { 0x00, 0x1c, 0x22, 0x41, 0x00 }, // (\r
+ { 0x00, 0x41, 0x22, 0x1c, 0x00 }, // )\r
+ { 0x14, 0x08, 0x3e, 0x08, 0x14 }, // *\r
+ { 0x08, 0x08, 0x3e, 0x08, 0x08 }, // +\r
+ { 0x00, 0x50, 0x30, 0x00, 0x00 }, // ,\r
+ { 0x08, 0x08, 0x08, 0x08, 0x08 }, // -\r
+ { 0x00, 0x60, 0x60, 0x00, 0x00 }, // .\r
+ { 0x20, 0x10, 0x08, 0x04, 0x02 }, // /\r
+ { 0x3e, 0x51, 0x49, 0x45, 0x3e }, // 0\r
+ { 0x00, 0x42, 0x7f, 0x40, 0x00 }, // 1\r
+ { 0x42, 0x61, 0x51, 0x49, 0x46 }, // 2\r
+ { 0x21, 0x41, 0x45, 0x4b, 0x31 }, // 3\r
+ { 0x18, 0x14, 0x12, 0x7f, 0x10 }, // 4\r
+ { 0x27, 0x45, 0x45, 0x45, 0x39 }, // 5\r
+ { 0x3c, 0x4a, 0x49, 0x49, 0x30 }, // 6\r
+ { 0x01, 0x71, 0x09, 0x05, 0x03 }, // 7\r
+ { 0x36, 0x49, 0x49, 0x49, 0x36 }, // 8\r
+ { 0x06, 0x49, 0x49, 0x29, 0x1e }, // 9\r
+ { 0x00, 0x36, 0x36, 0x00, 0x00 }, // :\r
+ { 0x00, 0x56, 0x36, 0x00, 0x00 }, // ;\r
+ { 0x08, 0x14, 0x22, 0x41, 0x00 }, // <\r
+ { 0x14, 0x14, 0x14, 0x14, 0x14 }, // =\r
+ { 0x00, 0x41, 0x22, 0x14, 0x08 }, // >\r
+ { 0x02, 0x01, 0x51, 0x09, 0x06 }, // ?\r
+ { 0x32, 0x49, 0x79, 0x41, 0x3e }, // @\r
+ { 0x7e, 0x11, 0x11, 0x11, 0x7e }, // A\r
+ { 0x7f, 0x49, 0x49, 0x49, 0x36 }, // B\r
+ { 0x3e, 0x41, 0x41, 0x41, 0x22 }, // C\r
+ { 0x7f, 0x41, 0x41, 0x22, 0x1c }, // D\r
+ { 0x7f, 0x49, 0x49, 0x49, 0x41 }, // E\r
+ { 0x7f, 0x09, 0x09, 0x09, 0x01 }, // F\r
+ { 0x3e, 0x41, 0x49, 0x49, 0x7a }, // G\r
+ { 0x7f, 0x08, 0x08, 0x08, 0x7f }, // H\r
+ { 0x00, 0x41, 0x7f, 0x41, 0x00 }, // I\r
+ { 0x20, 0x40, 0x41, 0x3f, 0x01 }, // J\r
+ { 0x7f, 0x08, 0x14, 0x22, 0x41 }, // K\r
+ { 0x7f, 0x40, 0x40, 0x40, 0x40 }, // L\r
+ { 0x7f, 0x02, 0x0c, 0x02, 0x7f }, // M\r
+ { 0x7f, 0x04, 0x08, 0x10, 0x7f }, // N\r
+ { 0x3e, 0x41, 0x41, 0x41, 0x3e }, // O\r
+ { 0x7f, 0x09, 0x09, 0x09, 0x06 }, // P\r
+ { 0x3e, 0x41, 0x51, 0x21, 0x5e }, // Q\r
+ { 0x7f, 0x09, 0x19, 0x29, 0x46 }, // R\r
+ { 0x46, 0x49, 0x49, 0x49, 0x31 }, // S\r
+ { 0x01, 0x01, 0x7f, 0x01, 0x01 }, // T\r
+ { 0x3f, 0x40, 0x40, 0x40, 0x3f }, // U\r
+ { 0x1f, 0x20, 0x40, 0x20, 0x1f }, // V\r
+ { 0x3f, 0x40, 0x38, 0x40, 0x3f }, // W\r
+ { 0x63, 0x14, 0x08, 0x14, 0x63 }, // X\r
+ { 0x07, 0x08, 0x70, 0x08, 0x07 }, // Y\r
+ { 0x61, 0x51, 0x49, 0x45, 0x43 }, // Z\r
+ { 0x00, 0x7f, 0x41, 0x41, 0x00 }, // [\r
+ { 0x02, 0x04, 0x08, 0x10, 0x20 }, // "\"\r
+ { 0x00, 0x41, 0x41, 0x7f, 0x00 }, // ]\r
+ { 0x04, 0x02, 0x01, 0x02, 0x04 }, // ^\r
+ { 0x40, 0x40, 0x40, 0x40, 0x40 }, // _\r
+ { 0x00, 0x01, 0x02, 0x04, 0x00 }, // `\r
+ { 0x20, 0x54, 0x54, 0x54, 0x78 }, // a\r
+ { 0x7f, 0x48, 0x44, 0x44, 0x38 }, // b\r
+ { 0x38, 0x44, 0x44, 0x44, 0x20 }, // c\r
+ { 0x38, 0x44, 0x44, 0x48, 0x7f }, // d\r
+ { 0x38, 0x54, 0x54, 0x54, 0x18 }, // e\r
+ { 0x08, 0x7e, 0x09, 0x01, 0x02 }, // f\r
+ { 0x0c, 0x52, 0x52, 0x52, 0x3e }, // g\r
+ { 0x7f, 0x08, 0x04, 0x04, 0x78 }, // h\r
+ { 0x00, 0x44, 0x7d, 0x40, 0x00 }, // i\r
+ { 0x20, 0x40, 0x44, 0x3d, 0x00 }, // j\r
+ { 0x7f, 0x10, 0x28, 0x44, 0x00 }, // k\r
+ { 0x00, 0x41, 0x7f, 0x40, 0x00 }, // l\r
+ { 0x7c, 0x04, 0x18, 0x04, 0x78 }, // m\r
+ { 0x7c, 0x08, 0x04, 0x04, 0x78 }, // n\r
+ { 0x38, 0x44, 0x44, 0x44, 0x38 }, // o\r
+ { 0x7c, 0x14, 0x14, 0x14, 0x08 }, // p\r
+ { 0x08, 0x14, 0x14, 0x18, 0x7c }, // q\r
+ { 0x7c, 0x08, 0x04, 0x04, 0x08 }, // r\r
+ { 0x48, 0x54, 0x54, 0x54, 0x20 }, // s\r
+ { 0x04, 0x3f, 0x44, 0x40, 0x20 }, // t\r
+ { 0x3c, 0x40, 0x40, 0x20, 0x7c }, // u\r
+ { 0x1c, 0x20, 0x40, 0x20, 0x1c }, // v\r
+ { 0x3c, 0x40, 0x30, 0x40, 0x3c }, // w\r
+ { 0x44, 0x28, 0x10, 0x28, 0x44 }, // x\r
+ { 0x0c, 0x50, 0x50, 0x50, 0x3c }, // y\r
+ { 0x44, 0x64, 0x54, 0x4c, 0x44 }, // z\r
+ { 0x00, 0x08, 0x36, 0x41, 0x00 }, // {\r
+ { 0x00, 0x00, 0x7f, 0x00, 0x00 }, // |\r
+ { 0x00, 0x41, 0x36, 0x08, 0x00 }, // }\r
+ { 0x02, 0x01, 0x02, 0x04, 0x02 }, // ~\r
+};\r
+\r
+//*****************************************************************************\r
+//\r
+// The sequence of commands used to initialize the SSD0303 controller. Each\r
+// command is described as follows: there is a byte specifying the number of\r
+// bytes in the I2C transfer, followed by that many bytes of command data.\r
+//\r
+//*****************************************************************************\r
+static const unsigned char g_pucOSRAMInit[] =\r
+{\r
+ //\r
+ // Turn off the panel\r
+ //\r
+ 0x04, 0x80, 0xae, 0x80, 0xe3,\r
+\r
+ //\r
+ // Set lower column address\r
+ //\r
+ 0x04, 0x80, 0x04, 0x80, 0xe3,\r
+\r
+ //\r
+ // Set higher column address\r
+ //\r
+ 0x04, 0x80, 0x12, 0x80, 0xe3,\r
+\r
+ //\r
+ // Set contrast control register\r
+ //\r
+ 0x06, 0x80, 0x81, 0x80, 0x2b, 0x80, 0xe3,\r
+\r
+ //\r
+ // Set segment re-map\r
+ //\r
+ 0x04, 0x80, 0xa1, 0x80, 0xe3,\r
+\r
+ //\r
+ // Set display start line\r
+ //\r
+ 0x04, 0x80, 0x40, 0x80, 0xe3,\r
+\r
+ //\r
+ // Set display offset\r
+ //\r
+ 0x06, 0x80, 0xd3, 0x80, 0x00, 0x80, 0xe3,\r
+\r
+ //\r
+ // Set multiplex ratio\r
+ //\r
+ 0x06, 0x80, 0xa8, 0x80, 0x0f, 0x80, 0xe3,\r
+\r
+ //\r
+ // Set the display to normal mode\r
+ //\r
+ 0x04, 0x80, 0xa4, 0x80, 0xe3,\r
+\r
+ //\r
+ // Non-inverted display\r
+ //\r
+ 0x04, 0x80, 0xa6, 0x80, 0xe3,\r
+\r
+ //\r
+ // Set the page address\r
+ //\r
+ 0x04, 0x80, 0xb0, 0x80, 0xe3,\r
+\r
+ //\r
+ // Set COM output scan direction\r
+ //\r
+ 0x04, 0x80, 0xc8, 0x80, 0xe3,\r
+\r
+ //\r
+ // Set display clock divide ratio/oscillator frequency\r
+ //\r
+ 0x06, 0x80, 0xd5, 0x80, 0x72, 0x80, 0xe3,\r
+\r
+ //\r
+ // Enable mono mode\r
+ //\r
+ 0x06, 0x80, 0xd8, 0x80, 0x00, 0x80, 0xe3,\r
+\r
+ //\r
+ // Set pre-charge period\r
+ //\r
+ 0x06, 0x80, 0xd9, 0x80, 0x22, 0x80, 0xe3,\r
+\r
+ //\r
+ // Set COM pins hardware configuration\r
+ //\r
+ 0x06, 0x80, 0xda, 0x80, 0x12, 0x80, 0xe3,\r
+\r
+ //\r
+ // Set VCOM deslect level\r
+ //\r
+ 0x06, 0x80, 0xdb, 0x80, 0x0f, 0x80, 0xe3,\r
+\r
+ //\r
+ // Set DC-DC on\r
+ //\r
+ 0x06, 0x80, 0xad, 0x80, 0x8b, 0x80, 0xe3,\r
+\r
+ //\r
+ // Turn on the panel\r
+ //\r
+ 0x04, 0x80, 0xaf, 0x80, 0xe3,\r
+};\r
+\r
+//*****************************************************************************\r
+//\r
+// The inter-byte delay required by the SSD0303 OLED controller.\r
+//\r
+//*****************************************************************************\r
+static unsigned long g_ulDelay;\r
+\r
+//*****************************************************************************\r
+//\r
+//! \internal\r
+//!\r
+//! Provide a small delay.\r
+//!\r
+//! \param ulCount is the number of delay loop iterations to perform.\r
+//!\r
+//! Since the SSD0303 controller needs a delay between bytes written to it over\r
+//! the I2C bus, this function provides a means of generating that delay. It\r
+//! is written in assembly to keep the delay consistent across tool chains,\r
+//! avoiding the need to tune the delay based on the tool chain in use.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(ewarm)\r
+static void\r
+OSRAMDelay(unsigned long ulCount)\r
+{\r
+ __asm(" subs r0, #1\n"\r
+ " bne OSRAMDelay\n"\r
+ " bx lr");\r
+}\r
+#endif\r
+#if defined(gcc)\r
+static void __attribute__((naked))\r
+OSRAMDelay(unsigned long ulCount)\r
+{\r
+ __asm(" subs r0, #1\n"\r
+ " bne OSRAMDelay\n"\r
+ " bx lr");\r
+}\r
+#endif\r
+#if defined(rvmdk) || defined(__ARMCC_VERSION)\r
+__asm void\r
+OSRAMDelay(unsigned long ulCount)\r
+{\r
+ subs r0, #1;\r
+ bne OSRAMDelay;\r
+ bx lr;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! \internal\r
+//!\r
+//! Start a transfer to the SSD0303 controller.\r
+//!\r
+//! \param ucChar is the first byte to be written to the controller.\r
+//!\r
+//! This function will start a transfer to the SSD0303 controller via the I2C\r
+//! bus.\r
+//!\r
+//! The data is written in a polled fashion; this function will not return\r
+//! until the byte has been written to the controller.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+static void\r
+OSRAMWriteFirst(unsigned char ucChar)\r
+{\r
+ //\r
+ // Set the slave address.\r
+ //\r
+ I2CMasterSlaveAddrSet(I2C_MASTER_BASE, SSD0303_ADDR, false);\r
+\r
+ //\r
+ // Write the first byte to the controller.\r
+ //\r
+ I2CMasterDataPut(I2C_MASTER_BASE, ucChar);\r
+\r
+ //\r
+ // Start the transfer.\r
+ //\r
+ I2CMasterControl(I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_SEND_START);\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! \internal\r
+//!\r
+//! Write a byte to the SSD0303 controller.\r
+//!\r
+//! \param ucChar is the byte to be transmitted to the controller.\r
+//!\r
+//! This function continues a transfer to the SSD0303 controller by writing\r
+//! another byte over the I2C bus. This must only be called after calling\r
+//! OSRAMWriteFirst(), but before calling OSRAMWriteFinal().\r
+//!\r
+//! The data is written in a polled faashion; this function will not return\r
+//! until the byte has been written to the controller.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+static void\r
+OSRAMWriteByte(unsigned char ucChar)\r
+{\r
+ //\r
+ // Wait until the current byte has been transferred.\r
+ //\r
+ while(I2CMasterIntStatus(I2C_MASTER_BASE, false) == 0)\r
+ {\r
+ }\r
+\r
+ //\r
+ // Provide the required inter-byte delay.\r
+ //\r
+ OSRAMDelay(g_ulDelay);\r
+\r
+ //\r
+ // Write the next byte to the controller.\r
+ //\r
+ I2CMasterDataPut(I2C_MASTER_BASE, ucChar);\r
+\r
+ //\r
+ // Continue the transfer.\r
+ //\r
+ I2CMasterControl(I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_SEND_CONT);\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! \internal\r
+//!\r
+//! Write a sequence of bytes to the SSD0303 controller.\r
+//!\r
+//! This function continues a transfer to the SSD0303 controller by writing a\r
+//! sequence of bytes over the I2C bus. This must only be called after calling\r
+//! OSRAMWriteFirst(), but before calling OSRAMWriteFinal().\r
+//!\r
+//! The data is written in a polled fashion; this function will not return\r
+//! until the entire byte sequence has been written to the controller.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+static void\r
+OSRAMWriteArray(const unsigned char *pucBuffer, unsigned long ulCount)\r
+{\r
+ //\r
+ // Loop while there are more bytes left to be transferred.\r
+ //\r
+ while(ulCount != 0)\r
+ {\r
+ //\r
+ // Wait until the current byte has been transferred.\r
+ //\r
+ while(I2CMasterIntStatus(I2C_MASTER_BASE, false) == 0)\r
+ {\r
+ }\r
+\r
+ //\r
+ // Provide the required inter-byte delay.\r
+ //\r
+ OSRAMDelay(g_ulDelay);\r
+\r
+ //\r
+ // Write the next byte to the controller.\r
+ //\r
+ I2CMasterDataPut(I2C_MASTER_BASE, *pucBuffer++);\r
+ ulCount--;\r
+\r
+ //\r
+ // Continue the transfer.\r
+ //\r
+ I2CMasterControl(I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_SEND_CONT);\r
+ }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! \internal\r
+//!\r
+//! Finish a transfer to the SSD0303 controller.\r
+//!\r
+//! \param ucChar is the final byte to be written to the controller.\r
+//!\r
+//! This function will finish a transfer to the SSD0303 controller via the I2C\r
+//! bus. This must only be called after calling OSRAMWriteFirst().\r
+//!\r
+//! The data is written in a polled fashion; this function will not return\r
+//! until the byte has been written to the controller.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+static void\r
+OSRAMWriteFinal(unsigned char ucChar)\r
+{\r
+ //\r
+ // Wait until the current byte has been transferred.\r
+ //\r
+ while(I2CMasterIntStatus(I2C_MASTER_BASE, false) == 0)\r
+ {\r
+ }\r
+\r
+ //\r
+ // Provide the required inter-byte delay.\r
+ //\r
+ OSRAMDelay(g_ulDelay);\r
+\r
+ //\r
+ // Write the final byte to the controller.\r
+ //\r
+ I2CMasterDataPut(I2C_MASTER_BASE, ucChar);\r
+\r
+ //\r
+ // Finish the transfer.\r
+ //\r
+ I2CMasterControl(I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_SEND_FINISH);\r
+\r
+ //\r
+ // Wait until the final byte has been transferred.\r
+ //\r
+ while(I2CMasterIntStatus(I2C_MASTER_BASE, false) == 0)\r
+ {\r
+ }\r
+\r
+ //\r
+ // Provide the required inter-byte delay.\r
+ //\r
+ OSRAMDelay(g_ulDelay);\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Clears the OLED display.\r
+//!\r
+//! This function will clear the display. All pixels in the display will be\r
+//! turned off.\r
+//!\r
+//! This function is contained in <tt>osram96x16.c</tt>, with\r
+//! <tt>osram96x16.h</tt> containing the API definition for use by\r
+//! applications.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+OSRAMClear(void)\r
+{\r
+ static const unsigned char pucRow1[] =\r
+ {\r
+ 0xb0, 0x80, 0x04, 0x80, 0x12, 0x40\r
+ };\r
+ static const unsigned char pucRow2[] =\r
+ {\r
+ 0xb1, 0x80, 0x04, 0x80, 0x12, 0x40\r
+ };\r
+ unsigned long ulIdx;\r
+\r
+ //\r
+ // Move the display cursor to the first column of the first row.\r
+ //\r
+ OSRAMWriteFirst(0x80);\r
+ OSRAMWriteArray(pucRow1, sizeof(pucRow1));\r
+\r
+ //\r
+ // Fill this row with zeros.\r
+ //\r
+ for(ulIdx = 0; ulIdx < 95; ulIdx++)\r
+ {\r
+ OSRAMWriteByte(0x00);\r
+ }\r
+ OSRAMWriteFinal(0x00);\r
+\r
+ //\r
+ // Move the display cursor to the first column of the second row.\r
+ //\r
+ OSRAMWriteFirst(0x80);\r
+ OSRAMWriteArray(pucRow2, sizeof(pucRow2));\r
+\r
+ //\r
+ // Fill this row with zeros.\r
+ //\r
+ for(ulIdx = 0; ulIdx < 95; ulIdx++)\r
+ {\r
+ OSRAMWriteByte(0x00);\r
+ }\r
+ OSRAMWriteFinal(0x00);\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Displays a string on the OLED display.\r
+//!\r
+//! \param pcStr is a pointer to the string to display.\r
+//! \param ulX is the horizontal position to display the string, specified in\r
+//! columns from the left edge of the display.\r
+//! \param ulY is the vertical position to display the string, specified in\r
+//! eight scan line blocks from the top of the display (i.e. only 0 and 1 are\r
+//! valid).\r
+//!\r
+//! This function will draw a string on the display. Only the ASCII characters\r
+//! between 32 (space) and 126 (tilde) are supported; other characters will\r
+//! result in random data being draw on the display (based on whatever appears\r
+//! before/after the font in memory). The font is mono-spaced, so characters\r
+//! such as "i" and "l" have more white space around them than characters such\r
+//! as "m" or "w".\r
+//!\r
+//! If the drawing of the string reaches the right edge of the display, no more\r
+//! characters will be drawn. Therefore, special care is not required to avoid\r
+//! supplying a string that is "too long" to display.\r
+//!\r
+//! This function is contained in <tt>osram96x16.c</tt>, with\r
+//! <tt>osram96x16.h</tt> containing the API definition for use by\r
+//! applications.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+OSRAMStringDraw(const char *pcStr, unsigned long ulX, unsigned long ulY)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulX < 96);\r
+ ASSERT(ulY < 2);\r
+\r
+ //\r
+ // Move the display cursor to the requested position on the display.\r
+ //\r
+ OSRAMWriteFirst(0x80);\r
+ OSRAMWriteByte((ulY == 0) ? 0xb0 : 0xb1);\r
+ OSRAMWriteByte(0x80);\r
+ OSRAMWriteByte((ulX + 36) & 0x0f);\r
+ OSRAMWriteByte(0x80);\r
+ OSRAMWriteByte(0x10 | (((ulX + 36) >> 4) & 0x0f));\r
+ OSRAMWriteByte(0x40);\r
+\r
+ //\r
+ // Loop while there are more characters in the string.\r
+ //\r
+ while(*pcStr != 0)\r
+ {\r
+ //\r
+ // See if there is enough space on the display for this entire\r
+ // character.\r
+ //\r
+ if(ulX <= 90)\r
+ {\r
+ //\r
+ // Write the contents of this character to the display.\r
+ //\r
+ OSRAMWriteArray(g_pucFont[*pcStr - ' '], 5);\r
+\r
+ //\r
+ // See if this is the last character to display (either because the\r
+ // right edge has been reached or because there are no more\r
+ // characters).\r
+ //\r
+ if((ulX == 90) || (pcStr[1] == 0))\r
+ {\r
+ //\r
+ // Write the final column of the display.\r
+ //\r
+ OSRAMWriteFinal(0x00);\r
+\r
+ //\r
+ // The string has been displayed.\r
+ //\r
+ return;\r
+ }\r
+\r
+ //\r
+ // Write the inter-character padding column.\r
+ //\r
+ OSRAMWriteByte(0x00);\r
+ }\r
+ else\r
+ {\r
+ //\r
+ // Write the portion of the character that will fit onto the\r
+ // display.\r
+ //\r
+ OSRAMWriteArray(g_pucFont[*pcStr - ' '], 95 - ulX);\r
+ OSRAMWriteFinal(g_pucFont[*pcStr - ' '][95 - ulX]);\r
+\r
+ //\r
+ // The string has been displayed.\r
+ //\r
+ return;\r
+ }\r
+\r
+ //\r
+ // Advance to the next character.\r
+ //\r
+ pcStr++;\r
+\r
+ //\r
+ // Increment the X coordinate by the six columns that were just\r
+ // written.\r
+ //\r
+ ulX += 6;\r
+ }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Displays an image on the OLED display.\r
+//!\r
+//! \param pucImage is a pointer to the image data.\r
+//! \param ulX is the horizontal position to display this image, specified in\r
+//! columns from the left edge of the display.\r
+//! \param ulY is the vertical position to display this image, specified in\r
+//! eight scan line blocks from the top of the display (i.e. only 0 and 1 are\r
+//! valid).\r
+//! \param ulWidth is the width of the image, specified in columns.\r
+//! \param ulHeight is the height of the image, specified in eight row blocks\r
+//! (i.e. only 1 and 2 are valid).\r
+//!\r
+//! This function will display a bitmap graphic on the display. The image to\r
+//! be displayed must be a multiple of eight scan lines high (i.e. one row) and\r
+//! will be drawn at a vertical position that is a multiple of eight scan lines\r
+//! (i.e. scan line zero or scan line eight, corresponding to row zero or row\r
+//! one).\r
+//!\r
+//! The image data is organized with the first row of image data appearing left\r
+//! to right, followed immediately by the second row of image data. Each byte\r
+//! contains the data for the eight scan lines of the column, with the top scan\r
+//! line being in the least significant bit of the byte and the bottom scan\r
+//! line being in the most significant bit of the byte.\r
+//!\r
+//! For example, an image four columns wide and sixteen scan lines tall would\r
+//! be arranged as follows (showing how the eight bytes of the image would\r
+//! appear on the display):\r
+//!\r
+//! \verbatim\r
+//! +-------+ +-------+ +-------+ +-------+\r
+//! | | 0 | | | 0 | | | 0 | | | 0 |\r
+//! | B | 1 | | B | 1 | | B | 1 | | B | 1 |\r
+//! | y | 2 | | y | 2 | | y | 2 | | y | 2 |\r
+//! | t | 3 | | t | 3 | | t | 3 | | t | 3 |\r
+//! | e | 4 | | e | 4 | | e | 4 | | e | 4 |\r
+//! | | 5 | | | 5 | | | 5 | | | 5 |\r
+//! | 0 | 6 | | 1 | 6 | | 2 | 6 | | 3 | 6 |\r
+//! | | 7 | | | 7 | | | 7 | | | 7 |\r
+//! +-------+ +-------+ +-------+ +-------+\r
+//!\r
+//! +-------+ +-------+ +-------+ +-------+\r
+//! | | 0 | | | 0 | | | 0 | | | 0 |\r
+//! | B | 1 | | B | 1 | | B | 1 | | B | 1 |\r
+//! | y | 2 | | y | 2 | | y | 2 | | y | 2 |\r
+//! | t | 3 | | t | 3 | | t | 3 | | t | 3 |\r
+//! | e | 4 | | e | 4 | | e | 4 | | e | 4 |\r
+//! | | 5 | | | 5 | | | 5 | | | 5 |\r
+//! | 4 | 6 | | 5 | 6 | | 6 | 6 | | 7 | 6 |\r
+//! | | 7 | | | 7 | | | 7 | | | 7 |\r
+//! +-------+ +-------+ +-------+ +-------+\r
+//! \endverbatim\r
+//!\r
+//! This function is contained in <tt>osram96x16.c</tt>, with\r
+//! <tt>osram96x16.h</tt> containing the API definition for use by\r
+//! applications.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+OSRAMImageDraw(const unsigned char *pucImage, unsigned long ulX,\r
+ unsigned long ulY, unsigned long ulWidth,\r
+ unsigned long ulHeight)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulX < 96);\r
+ ASSERT(ulY < 2);\r
+ ASSERT((ulX + ulWidth) <= 96);\r
+ ASSERT((ulY + ulHeight) <= 2);\r
+\r
+ //\r
+ // The first 36 columns of the LCD buffer are not displayed, so increment\r
+ // the X coorddinate by 36 to account for the non-displayed frame buffer\r
+ // memory.\r
+ //\r
+ ulX += 36;\r
+\r
+ //\r
+ // Loop while there are more rows to display.\r
+ //\r
+ while(ulHeight--)\r
+ {\r
+ //\r
+ // Write the starting address within this row.\r
+ //\r
+ OSRAMWriteFirst(0x80);\r
+ OSRAMWriteByte((ulY == 0) ? 0xb0 : 0xb1);\r
+ OSRAMWriteByte(0x80);\r
+ OSRAMWriteByte(ulX & 0x0f);\r
+ OSRAMWriteByte(0x80);\r
+ OSRAMWriteByte(0x10 | ((ulX >> 4) & 0x0f));\r
+ OSRAMWriteByte(0x40);\r
+\r
+ //\r
+ // Write this row of image data.\r
+ //\r
+ OSRAMWriteArray(pucImage, ulWidth - 1);\r
+ OSRAMWriteFinal(pucImage[ulWidth - 1]);\r
+\r
+ //\r
+ // Advance to the next row of the image.\r
+ //\r
+ pucImage += ulWidth;\r
+ ulY++;\r
+ }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Initialize the OLED display.\r
+//!\r
+//! \param bFast is a boolean that is \e true if the I2C interface should be\r
+//! run at 400 kbps and \e false if it should be run at 100 kbps.\r
+//!\r
+//! This function initializes the I2C interface to the OLED display and\r
+//! configures the SSD0303 controller on the panel.\r
+//!\r
+//! This function is contained in <tt>osram96x16.c</tt>, with\r
+//! <tt>osram96x16.h</tt> containing the API definition for use by\r
+//! applications.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+OSRAMInit(tBoolean bFast)\r
+{\r
+ unsigned long ulIdx;\r
+\r
+ //\r
+ // Enable the I2C and GPIO port B blocks as they are needed by this driver.\r
+ //\r
+ SysCtlPeripheralEnable(SYSCTL_PERIPH_I2C);\r
+ SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB);\r
+\r
+ //\r
+ // Configure the I2C SCL and SDA pins for I2C operation.\r
+ //\r
+ GPIOPinTypeI2C(GPIO_PORTB_BASE, GPIO_PIN_2 | GPIO_PIN_3);\r
+\r
+ //\r
+ // Initialize the I2C master.\r
+ //\r
+ I2CMasterInit(I2C_MASTER_BASE, bFast);\r
+\r
+ //\r
+ // Compute the inter-byte delay for the SSD0303 controller. This delay is\r
+ // dependent upon the I2C bus clock rate; the slower the clock the longer\r
+ // the delay required.\r
+ //\r
+ // The derivation of this formula is based on a measured delay of\r
+ // OSRAMDelay(1700) for a 100 kHz I2C bus with the CPU running at 50 MHz\r
+ // (referred to as C). To scale this to the delay for a different CPU\r
+ // speed (since this is just a CPU-based delay loop) is:\r
+ //\r
+ // f(CPU)\r
+ // C * ----------\r
+ // 50,000,000\r
+ //\r
+ // To then scale this to the actual I2C rate (since it won't always be\r
+ // precisely 100 kHz):\r
+ //\r
+ // f(CPU) 100,000\r
+ // C * ---------- * -------\r
+ // 50,000,000 f(I2C)\r
+ //\r
+ // This equation will give the inter-byte delay required for any\r
+ // configuration of the I2C master. But, as arranged it is impossible to\r
+ // directly compute in 32-bit arithmetic (without loosing a lot of\r
+ // accuracy). So, the equation is simplified.\r
+ //\r
+ // Since f(I2C) is generated by dividing down from f(CPU), replace it with\r
+ // the equivalent (where TPR is the value programmed into the Master Timer\r
+ // Period Register of the I2C master, with the 1 added back):\r
+ //\r
+ // 100,000\r
+ // f(CPU) -------\r
+ // C * ---------- * f(CPU)\r
+ // 50,000,000 ------------\r
+ // 2 * 10 * TPR\r
+ //\r
+ // Inverting the dividend in the last term:\r
+ //\r
+ // f(CPU) 100,000 * 2 * 10 * TPR\r
+ // C * ---------- * ----------------------\r
+ // 50,000,000 f(CPU)\r
+ //\r
+ // The f(CPU) now cancels out.\r
+ //\r
+ // 100,000 * 2 * 10 * TPR\r
+ // C * ----------------------\r
+ // 50,000,000\r
+ //\r
+ // Since there are no clock frequencies left in the equation, this equation\r
+ // also works for 400 kHz bus operation as well, since the 100,000 in the\r
+ // numerator becomes 400,000 but C is 1/4, which cancel out each other.\r
+ // Reducing the constants gives:\r
+ //\r
+ // TPR TPR TPR\r
+ // C * --- = 1700 * --- = 340 * --- = 68 * TPR\r
+ // 25 25 5\r
+ //\r
+ // Note that the constant C is actually a bit larger than it needs to be in\r
+ // order to provide some safety margin.\r
+ //\r
+ g_ulDelay = 68 * (HWREG(I2C_MASTER_BASE + I2C_MASTER_O_TPR) + 1);\r
+\r
+ //\r
+ // Initialize the SSD0303 controller. Loop through the initialization\r
+ // sequence doing a single I2C transfer for each command.\r
+ //\r
+ for(ulIdx = 0; ulIdx < sizeof(g_pucOSRAMInit);\r
+ ulIdx += g_pucOSRAMInit[ulIdx] + 1)\r
+ {\r
+ //\r
+ // Send this command.\r
+ //\r
+ OSRAMWriteFirst(g_pucOSRAMInit[ulIdx + 1]);\r
+ OSRAMWriteArray(g_pucOSRAMInit + ulIdx + 2, g_pucOSRAMInit[ulIdx] - 2);\r
+ OSRAMWriteFinal(g_pucOSRAMInit[ulIdx + g_pucOSRAMInit[ulIdx]]);\r
+ }\r
+\r
+ //\r
+ // Clear the frame buffer.\r
+ //\r
+ OSRAMClear();\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Turns on the OLED display.\r
+//!\r
+//! This function will turn on the OLED display, causing it to display the\r
+//! contents of its internal frame buffer.\r
+//!\r
+//! This function is contained in <tt>osram96x16.c</tt>, with\r
+//! <tt>osram96x16.h</tt> containing the API definition for use by\r
+//! applications.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+OSRAMDisplayOn(void)\r
+{\r
+ unsigned long ulIdx;\r
+\r
+ //\r
+ // Re-initialize the SSD0303 controller. Loop through the initialization\r
+ // sequence doing a single I2C transfer for each command.\r
+ //\r
+ for(ulIdx = 0; ulIdx < sizeof(g_pucOSRAMInit);\r
+ ulIdx += g_pucOSRAMInit[ulIdx] + 1)\r
+ {\r
+ //\r
+ // Send this command.\r
+ //\r
+ OSRAMWriteFirst(g_pucOSRAMInit[ulIdx + 1]);\r
+ OSRAMWriteArray(g_pucOSRAMInit + ulIdx + 2, g_pucOSRAMInit[ulIdx] - 2);\r
+ OSRAMWriteFinal(g_pucOSRAMInit[ulIdx + g_pucOSRAMInit[ulIdx]]);\r
+ }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Turns off the OLED display.\r
+//!\r
+//! This function will turn off the OLED display. This will stop the scanning\r
+//! of the panel and turn off the on-chip DC-DC converter, preventing damage to\r
+//! the panel due to burn-in (it has similar characters to a CRT in this\r
+//! respect).\r
+//!\r
+//! This function is contained in <tt>osram96x16.c</tt>, with\r
+//! <tt>osram96x16.h</tt> containing the API definition for use by\r
+//! applications.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+OSRAMDisplayOff(void)\r
+{\r
+ //\r
+ // Turn off the DC-DC converter and the display.\r
+ //\r
+ OSRAMWriteFirst(0x80);\r
+ OSRAMWriteByte(0xae);\r
+ OSRAMWriteByte(0x80);\r
+ OSRAMWriteByte(0xad);\r
+ OSRAMWriteByte(0x80);\r
+ OSRAMWriteFinal(0x8a);\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+// Close the Doxygen group.\r
+//! @}\r
+//\r
+//*****************************************************************************\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// osram96x16.h - Prototypes for the driver for the OSRAM 96x16 graphical OLED\r
+// display.\r
+//\r
+// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 991 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __OSRAM96X16_H__\r
+#define __OSRAM96X16_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the driver APIs.\r
+//\r
+//*****************************************************************************\r
+extern void OSRAMClear(void);\r
+extern void OSRAMStringDraw(const char *pcStr, unsigned long ulX,\r
+ unsigned long ulY);\r
+extern void OSRAMImageDraw(const unsigned char *pucImage, unsigned long ulX,\r
+ unsigned long ulY, unsigned long ulWidth,\r
+ unsigned long ulHeight);\r
+extern void OSRAMInit(tBoolean bFast);\r
+extern void OSRAMDisplayOn(void);\r
+extern void OSRAMDisplayOff(void);\r
+\r
+#endif // __OSRAM96X16_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// pwm.c - API for the PWM modules\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 991 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \addtogroup pwm_api\r
+//! @{\r
+//\r
+//*****************************************************************************\r
+\r
+#include "../hw_ints.h"\r
+#include "../hw_memmap.h"\r
+#include "../hw_pwm.h"\r
+#include "../hw_types.h"\r
+#include "debug.h"\r
+#include "interrupt.h"\r
+#include "pwm.h"\r
+\r
+//*****************************************************************************\r
+//\r
+// Misc macros for manipulating the encoded generator and output defines used\r
+// by the API.\r
+//\r
+//*****************************************************************************\r
+#define PWM_GEN_BADDR(_mod_, _gen_) \\r
+ ((_mod_) + (_gen_))\r
+#define PWM_OUT_BADDR(_mod_, _out_) \\r
+ ((_mod_) + ((_out_) & 0xFFFFFFC0))\r
+#define PWM_IS_OUTPUT_ODD(_out_) \\r
+ ((_out_) & 0x00000001)\r
+\r
+//*****************************************************************************\r
+//\r
+//! Configures a PWM generator.\r
+//!\r
+//! \param ulBase is the base address of the PWM module.\r
+//! \param ulGen is the PWM generator to configure. Must be one of\r
+//! \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2.\r
+//! \param ulConfig is the configuration for the PWM generator.\r
+//!\r
+//! This function is used to set the mode of operation for a PWM generator.\r
+//! The counting mode, synchronization mode, and debug behavior are all\r
+//! configured. After configuration, the generator is left in the disabled\r
+//! state.\r
+//!\r
+//! A PWM generator can count in two different modes: count down mode or count\r
+//! up/down mode. In count down mode, it will count from a value down to zero,\r
+//! and then reset to the preset value. This will produce left-aligned PWM\r
+//! signals (i.e. the rising edge of the two PWM signals produced by the\r
+//! generator will occur at the same time). In count up/down mode, it will\r
+//! count up from zero to the preset value, count back down to zero, and then\r
+//! repeat the process. This will produce center-aligned PWM signals (i.e. the\r
+//! middle of the high/low period of the PWM signals produced by the generator\r
+//! will occur at the same time).\r
+//!\r
+//! When the PWM generator parameters (period and pulse width) are modified,\r
+//! their affect on the output PWM signals can be delayed. In synchronous\r
+//! mode, the parameter updates are not applied until a synchronization event\r
+//! occurs. This allows multiple parameters to be modified and take affect\r
+//! simultaneously, instead of one at a time. Additionally, parameters to\r
+//! multiple PWM generators in synchronous mode can be updated simultaneously,\r
+//! allowing them to be treated as if they were a unified generator. In\r
+//! non-synchronous mode, the parameter updates are not delayed until a\r
+//! synchronization event. In either mode, the parameter updates only occur\r
+//! when the counter is at zero to help prevent oddly formed PWM signals during\r
+//! the update (i.e. a PWM pulse that is too short or too long).\r
+//!\r
+//! The PWM generator can either pause or continue running when the processor\r
+//! is stopped via the debugger. If configured to pause, it will continue to\r
+//! count until it reaches zero, at which point it will pause until the\r
+//! processor is restarted. If configured to continue running, it will keep\r
+//! counting as if nothing had happened.\r
+//!\r
+//! The \b ulConfig parameter contains the desired configuration. It is the\r
+//! logical OR of the following: \b PWM_GEN_MODE_DOWN or\r
+//! \b PWM_GEN_MODE_UP_DOWN to specify the counting mode, \b PWM_GEN_MODE_SYNC\r
+//! or \b PWM_GEN_MODE_NO_SYNC to specify the synchronization mode, and\r
+//! \b PWM_GEN_MODE_DBG_RUN or \b PWM_GEN_MODE_DBG_STOP to specify the debug\r
+//! behavior.\r
+//!\r
+//! \note Changes to the counter mode will affect the period of the PWM signals\r
+//! produced. PWMGenPeriodSet() and PWMPulseWidthSet() should be called after\r
+//! any changes to the counter mode of a generator.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_genconfigure) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+PWMGenConfigure(unsigned long ulBase, unsigned long ulGen,\r
+ unsigned long ulConfig)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == PWM_BASE);\r
+ ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) ||\r
+ (ulGen == PWM_GEN_2));\r
+\r
+ //\r
+ // Compute the generator's base address.\r
+ //\r
+ ulGen = PWM_GEN_BADDR(ulBase, ulGen);\r
+\r
+ //\r
+ // Change the global configuration of the generator.\r
+ //\r
+ HWREG(ulGen + PWM_O_X_CTL) = ((HWREG(ulGen + PWM_O_X_CTL) &\r
+ ~(PWM_X_CTL_MODE | PWM_X_CTL_DEBUG |\r
+ PWM_X_CTL_LOADUPD | PWM_X_CTL_CMPAUPD |\r
+ PWM_X_CTL_CMPBUPD)) | ulConfig);\r
+\r
+ //\r
+ // Set the individual PWM generator controls.\r
+ //\r
+ if(ulConfig & PWM_X_CTL_MODE)\r
+ {\r
+ //\r
+ // In up/down count mode, set the signal high on up count comparison\r
+ // and low on down count comparison (i.e. center align the signals).\r
+ //\r
+ HWREG(ulGen + PWM_O_X_GENA) = ((PWM_GEN_ACT_ONE <<\r
+ PWM_GEN_ACT_A_UP_SHIFT) |\r
+ (PWM_GEN_ACT_ZERO <<\r
+ PWM_GEN_ACT_A_DN_SHIFT));\r
+ HWREG(ulGen + PWM_O_X_GENB) = ((PWM_GEN_ACT_ONE <<\r
+ PWM_GEN_ACT_B_UP_SHIFT) |\r
+ (PWM_GEN_ACT_ZERO <<\r
+ PWM_GEN_ACT_B_DN_SHIFT));\r
+ }\r
+ else\r
+ {\r
+ //\r
+ // In down count mode, set the signal high on load and low on count\r
+ // comparison (i.e. left align the signals).\r
+ //\r
+ HWREG(ulGen + PWM_O_X_GENA) = ((PWM_GEN_ACT_ONE <<\r
+ PWM_GEN_ACT_LOAD_SHIFT) |\r
+ (PWM_GEN_ACT_ZERO <<\r
+ PWM_GEN_ACT_A_DN_SHIFT));\r
+ HWREG(ulGen + PWM_O_X_GENB) = ((PWM_GEN_ACT_ONE <<\r
+ PWM_GEN_ACT_LOAD_SHIFT) |\r
+ (PWM_GEN_ACT_ZERO <<\r
+ PWM_GEN_ACT_B_DN_SHIFT));\r
+ }\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Set the period of a PWM generator.\r
+//!\r
+//! \param ulBase is the base address of the PWM module.\r
+//! \param ulGen is the PWM generator to be modified. Must be one of\r
+//! \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2.\r
+//! \param ulPeriod specifies the period of PWM generator output, measured\r
+//! in clock ticks.\r
+//!\r
+//! This function sets the period of the specified PWM generator block, where\r
+//! the period of the generator block is defined as the number of \b PWM \r
+//! clock ticks between pulses on the generator block \b zero signal.\r
+//!\r
+//! \note Any subsequent calls made to this function before an update occurs\r
+//! will cause the previous values to be overwritten.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_genperiodset) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+PWMGenPeriodSet(unsigned long ulBase, unsigned long ulGen,\r
+ unsigned long ulPeriod)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == PWM_BASE);\r
+ ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) ||\r
+ (ulGen == PWM_GEN_2));\r
+\r
+ //\r
+ // Compute the generator's base address.\r
+ //\r
+ ulGen = PWM_GEN_BADDR(ulBase, ulGen);\r
+\r
+ //\r
+ // Set the reload register based on the mode.\r
+ //\r
+ if(HWREG(ulGen + PWM_O_X_CTL) & PWM_X_CTL_MODE)\r
+ {\r
+ //\r
+ // In up/down count mode, set the reload register to half the requested\r
+ // period.\r
+ //\r
+ ASSERT((ulPeriod / 2) < 65536);\r
+ HWREG(ulGen + PWM_O_X_LOAD) = ulPeriod / 2;\r
+ }\r
+ else\r
+ {\r
+ //\r
+ // In down count mode, set the reload register to the requested period\r
+ // minus one.\r
+ //\r
+ ASSERT((ulPeriod <= 65536) && (ulPeriod != 0));\r
+ HWREG(ulGen + PWM_O_X_LOAD) = ulPeriod - 1;\r
+ }\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Gets the period of a PWM generator block.\r
+//!\r
+//! \param ulBase is the base address of the PWM module.\r
+//! \param ulGen is the PWM generator to query. Must be one of\r
+//! \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2.\r
+//!\r
+//! This function gets the period of the specified PWM generator block. The\r
+//! period of the generator block is defined as the number of \b PWM clock\r
+//! ticks between pulses on the generator block \b zero signal.\r
+//!\r
+//! If the update of the counter for the specified PWM generator has yet\r
+//! to be completed, the value returned may not be the active period. The\r
+//! value returned is the programmed period, measured in \b PWM clock ticks.\r
+//!\r
+//! \return Returns the programmed period of the specified generator block\r
+//! in \b PWM clock ticks.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_genperiodget) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+unsigned long\r
+PWMGenPeriodGet(unsigned long ulBase, unsigned long ulGen)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == PWM_BASE);\r
+ ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) ||\r
+ (ulGen == PWM_GEN_2));\r
+\r
+ //\r
+ // Compute the generator's base address.\r
+ //\r
+ ulGen = PWM_GEN_BADDR(ulBase, ulGen);\r
+\r
+ //\r
+ // Figure out the counter mode.\r
+ //\r
+ if(HWREG(ulGen + PWM_O_X_CTL) & PWM_X_CTL_MODE)\r
+ {\r
+ //\r
+ // The period is twice the reload register value.\r
+ //\r
+ return(HWREG(ulGen + PWM_O_X_LOAD) * 2);\r
+ }\r
+ else\r
+ {\r
+ //\r
+ // The period is the reload register value plus one.\r
+ //\r
+ return(HWREG(ulGen + PWM_O_X_LOAD) + 1);\r
+ }\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Enables the timer/counter for a PWM generator block.\r
+//!\r
+//! \param ulBase is the base address of the PWM module.\r
+//! \param ulGen is the PWM generator to be enabled. Must be one of\r
+//! \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2.\r
+//!\r
+//! This function allows the \b PWM clock to drive the timer/counter for the\r
+//! specified generator block.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_genenable) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+PWMGenEnable(unsigned long ulBase, unsigned long ulGen)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == PWM_BASE);\r
+ ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) ||\r
+ (ulGen == PWM_GEN_2));\r
+\r
+ //\r
+ // Enable the PWM generator.\r
+ //\r
+ HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_CTL) |= PWM_X_CTL_ENABLE;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Disables the timer/counter for a PWM generator block.\r
+//!\r
+//! \param ulBase is the base address of the PWM module.\r
+//! \param ulGen is the PWM generator to be disabled. Must be one of\r
+//! \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2.\r
+//!\r
+//! This function blocks the \b PWM clock from driving the timer/counter for \r
+//! the specified generator block.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_gendisable) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+PWMGenDisable(unsigned long ulBase, unsigned long ulGen)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == PWM_BASE);\r
+ ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) ||\r
+ (ulGen == PWM_GEN_2));\r
+\r
+ //\r
+ // Disable the PWM generator.\r
+ //\r
+ HWREG(PWM_GEN_BADDR(ulBase, + ulGen) + PWM_O_X_CTL) &= ~(PWM_X_CTL_ENABLE);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Sets the pulse width for the specified PWM output.\r
+//!\r
+//! \param ulBase is the base address of the PWM module.\r
+//! \param ulPWMOut is the PWM output to modify. Must be one of \b PWM_OUT_0,\r
+//! \b PWM_OUT_1, \b PWM_OUT_2, \b PWM_OUT_3, \b PWM_OUT_4, or \b PWM_OUT_5.\r
+//! \param ulWidth specifies the width of the positive portion of the pulse.\r
+//!\r
+//! This function sets the pulse width for the specified PWM output, where the\r
+//! pulse width is defined as the number of \b PWM clock ticks.\r
+//!\r
+//! \note Any subsequent calls made to this function before an update occurs\r
+//! will cause the previous values to be overwritten.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_pulsewidthset) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+PWMPulseWidthSet(unsigned long ulBase, unsigned long ulPWMOut,\r
+ unsigned long ulWidth)\r
+{\r
+ unsigned long ulGenBase, ulReg;\r
+\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == PWM_BASE);\r
+ ASSERT((ulPWMOut == PWM_OUT_0) || (ulPWMOut == PWM_OUT_1) ||\r
+ (ulPWMOut == PWM_OUT_2) || (ulPWMOut == PWM_OUT_3) ||\r
+ (ulPWMOut == PWM_OUT_4) || (ulPWMOut == PWM_OUT_5));\r
+\r
+ //\r
+ // Compute the generator's base address.\r
+ //\r
+ ulGenBase = PWM_OUT_BADDR(ulBase, ulPWMOut);\r
+\r
+ //\r
+ // If the counter is in up/down count mode, divide the width by two.\r
+ //\r
+ if(HWREG(ulGenBase + PWM_O_X_CTL) & PWM_X_CTL_MODE)\r
+ {\r
+ ulWidth /= 2;\r
+ }\r
+\r
+ //\r
+ // Get the period.\r
+ //\r
+ ulReg = HWREG(ulGenBase + PWM_O_X_LOAD);\r
+\r
+ //\r
+ // Make sure the width is not too large.\r
+ //\r
+ ASSERT(ulWidth < ulReg);\r
+\r
+ //\r
+ // Compute the compare value.\r
+ //\r
+ ulReg = ulReg - ulWidth;\r
+\r
+ //\r
+ // Write to the appropriate registers.\r
+ //\r
+ if(PWM_IS_OUTPUT_ODD(ulPWMOut))\r
+ {\r
+ HWREG(ulGenBase + PWM_O_X_CMPB) = ulReg;\r
+ }\r
+ else\r
+ {\r
+ HWREG(ulGenBase + PWM_O_X_CMPA) = ulReg;\r
+ }\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Gets the pulse width of a PWM output.\r
+//!\r
+//! \param ulBase is the base address of the PWM module.\r
+//! \param ulPWMOut is the PWM output to query. Must be one of \b PWM_OUT_0,\r
+//! \b PWM_OUT_1, \b PWM_OUT_2, \b PWM_OUT_3, \b PWM_OUT_4, or \b PWM_OUT_5.\r
+//!\r
+//! This function gets the currently programmed pulse width for the\r
+//! specified PWM output. If the update of the comparator for the specified\r
+//! output has yet to be completed, the value returned may not be the active\r
+//! pulse width. The value returned is the programmed pulse width, measured\r
+//! in \b PWM clock ticks.\r
+//!\r
+//! \return Returns the width of the pulse in \b PWM clock ticks.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_pulsewidthget) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+unsigned long\r
+PWMPulseWidthGet(unsigned long ulBase, unsigned long ulPWMOut)\r
+{\r
+ unsigned long ulGenBase, ulReg, ulLoad;\r
+\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == PWM_BASE);\r
+ ASSERT((ulPWMOut == PWM_OUT_0) || (ulPWMOut == PWM_OUT_1) ||\r
+ (ulPWMOut == PWM_OUT_2) || (ulPWMOut == PWM_OUT_3) ||\r
+ (ulPWMOut == PWM_OUT_4) || (ulPWMOut == PWM_OUT_5));\r
+\r
+ //\r
+ // Compute the generator's base address.\r
+ //\r
+ ulGenBase = PWM_OUT_BADDR(ulBase, ulPWMOut);\r
+\r
+ //\r
+ // Then compute the pulse width. If mode is UpDown, set\r
+ // width = (load-compare)*2. Otherwise, set width = load - compare\r
+ //\r
+ ulLoad = HWREG(ulGenBase + PWM_O_X_LOAD);\r
+ if(PWM_IS_OUTPUT_ODD(ulPWMOut))\r
+ {\r
+ ulReg = HWREG(ulGenBase + PWM_O_X_CMPB);\r
+ }\r
+ else\r
+ {\r
+ ulReg = HWREG(ulGenBase + PWM_O_X_CMPA);\r
+ }\r
+ ulReg = ulLoad - ulReg;\r
+\r
+ //\r
+ // If in up/down count mode, double the pulse width.\r
+ //\r
+ if(HWREG(ulGenBase + PWM_O_X_CTL) & PWM_X_CTL_MODE)\r
+ {\r
+ ulReg = ulReg * 2;\r
+ }\r
+\r
+ //\r
+ // Return the pulse width.\r
+ //\r
+ return(ulReg);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Enables the PWM dead band output, and sets the dead band delays.\r
+//!\r
+//! \param ulBase is the base address of the PWM module.\r
+//! \param ulGen is the PWM generator to modify. Must be one of\r
+//! \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2.\r
+//! \param usRise specifies the width of delay from the rising edge.\r
+//! \param usFall specifies the width of delay from the falling edge.\r
+//!\r
+//! This function sets the dead bands for the specified PWM generator,\r
+//! where the dead bands are defined as the number of \b PWM clock ticks\r
+//! from the rising or falling edge of the generator's \b OutA signal.\r
+//! Note that this function causes the coupling of \b OutB to \b OutA.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_deadbandenable) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+PWMDeadBandEnable(unsigned long ulBase, unsigned long ulGen,\r
+ unsigned short usRise, unsigned short usFall)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == PWM_BASE);\r
+ ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) ||\r
+ (ulGen == PWM_GEN_2));\r
+ ASSERT(usRise < 4096);\r
+ ASSERT(usFall < 4096);\r
+\r
+ //\r
+ // Compute the generator's base address.\r
+ //\r
+ ulGen = PWM_GEN_BADDR(ulBase, ulGen);\r
+\r
+ //\r
+ // Write the dead band delay values.\r
+ //\r
+ HWREG(ulGen + PWM_O_X_DBRISE) = usRise;\r
+ HWREG(ulGen + PWM_O_X_DBFALL) = usFall;\r
+\r
+ //\r
+ // Enable the deadband functionality.\r
+ //\r
+ HWREG(ulGen + PWM_O_X_DBCTL) |= PWM_DBCTL_ENABLE;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Disables the PWM dead band output.\r
+//!\r
+//! \param ulBase is the base address of the PWM module.\r
+//! \param ulGen is the PWM generator to modify. Must be one of\r
+//! \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2.\r
+//!\r
+//! This function disables the dead band mode for the specified PWM generator.\r
+//! Doing so decouples the \b OutA and \b OutB signals.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_deadbanddisable) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+PWMDeadBandDisable(unsigned long ulBase, unsigned long ulGen)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == PWM_BASE);\r
+ ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) ||\r
+ (ulGen == PWM_GEN_2));\r
+\r
+ //\r
+ // Disable the deadband functionality.\r
+ //\r
+ HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_DBCTL) &= ~(PWM_DBCTL_ENABLE);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Synchronizes all pending updates.\r
+//!\r
+//! \param ulBase is the base address of the PWM module.\r
+//! \param ulGenBits are the PWM generator blocks to be updated. Must be the\r
+//! logical OR of any of \b PWM_GEN_0_BIT, \b PWM_GEN_1_BIT, or\r
+//! \b PWM_GEN_2_BIT.\r
+//!\r
+//! For the selected PWM generators, this function causes all queued updates to\r
+//! the period or pulse width to be applied the next time the corresponding\r
+//! counter becomes zero.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_syncupdate) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+PWMSyncUpdate(unsigned long ulBase, unsigned long ulGenBits)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == PWM_BASE);\r
+ ASSERT(!(ulGenBits & ~(PWM_GEN_0_BIT | PWM_GEN_1_BIT | PWM_GEN_2_BIT)));\r
+\r
+ //\r
+ // Update the PWM timing registers.\r
+ //\r
+ HWREG(ulBase + PWM_O_CTL) = ulGenBits;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Synchronizes the counters in one or multiple PWM generator blocks.\r
+//!\r
+//! \param ulBase is the base address of the PWM module.\r
+//! \param ulGenBits are the PWM generator blocks to be synchronized. Must be\r
+//! the logical OR of any of \b PWM_GEN_0_BIT, \b PWM_GEN_1_BIT, or\r
+//! \b PWM_GEN_2_BIT.\r
+//!\r
+//! For the selected PWM module, this function synchronizes the time base\r
+//! of the generator blocks by causing the specified generator counters to be\r
+//! reset to zero.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_synctimebase) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+PWMSyncTimeBase(unsigned long ulBase, unsigned long ulGenBits)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == PWM_BASE);\r
+ ASSERT(!(ulGenBits & ~(PWM_GEN_0_BIT | PWM_GEN_1_BIT | PWM_GEN_2_BIT)));\r
+\r
+ //\r
+ // Synchronize the counters in the specified generators by writing to\r
+ // the module's synchronization register.\r
+ //\r
+ HWREG(ulBase + PWM_O_SYNC) = ulGenBits;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Enables or disables PWM outputs.\r
+//!\r
+//! \param ulBase is the base address of the PWM module.\r
+//! \param ulPWMOutBits are the PWM outputs to be modified. Must be the\r
+//! logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, \b PWM_OUT_2_BIT,\r
+//! \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, or \b PWM_OUT_5_BIT.\r
+//! \param bEnable determines if the signal is enabled or disabled.\r
+//!\r
+//! This function is used to enable or disable the selected PWM outputs. The\r
+//! outputs are selected using the parameter \e ulPWMOutBits. The parameter\r
+//! \e bEnable determines the state of the selected outputs. If \e bEnable is\r
+//! \b true, then the selected PWM outputs are enabled, or placed in the active\r
+//! state. If \e bEnable is \b false, then the selected outputs are disabled,\r
+//! or placed in the inactive state.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_outputstate) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+PWMOutputState(unsigned long ulBase, unsigned long ulPWMOutBits,\r
+ tBoolean bEnable)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == PWM_BASE);\r
+ ASSERT(!(ulPWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT |\r
+ PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT)));\r
+\r
+ //\r
+ // Read the module's ENABLE output control register, and set or clear\r
+ // the requested bits.\r
+ //\r
+ if(bEnable == true)\r
+ {\r
+ HWREG(ulBase + PWM_O_ENABLE) |= ulPWMOutBits;\r
+ }\r
+ else\r
+ {\r
+ HWREG(ulBase + PWM_O_ENABLE) &= ~(ulPWMOutBits);\r
+ }\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Selects the inversion mode for PWM outputs.\r
+//!\r
+//! \param ulBase is the base address of the PWM module.\r
+//! \param ulPWMOutBits are the PWM outputs to be modified. Must be the\r
+//! logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, \b PWM_OUT_2_BIT,\r
+//! \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, or \b PWM_OUT_5_BIT.\r
+//! \param bInvert determines if the signal is inverted or passed through.\r
+//!\r
+//! This function is used to select the inversion mode for the selected PWM\r
+//! outputs. The outputs are selected using the parameter \e ulPWMOutBits.\r
+//! The parameter \e bInvert determines the inversion mode for the selected\r
+//! outputs. If \e bInvert is \b true, this function will cause the specified\r
+//! PWM output signals to be inverted, or made active low. If \e bInvert is\r
+//! \b false, the specified output will be passed through as is, or be made\r
+//! active high.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_outputinvert) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+PWMOutputInvert(unsigned long ulBase, unsigned long ulPWMOutBits,\r
+ tBoolean bInvert)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == PWM_BASE);\r
+ ASSERT(!(ulPWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT |\r
+ PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT)));\r
+\r
+ //\r
+ // Read the module's INVERT output control register, and set or clear\r
+ // the requested bits.\r
+ //\r
+ if(bInvert == true)\r
+ {\r
+ HWREG(ulBase + PWM_O_INVERT) |= ulPWMOutBits;\r
+ }\r
+ else\r
+ {\r
+ HWREG(ulBase + PWM_O_INVERT) &= ~(ulPWMOutBits);\r
+ }\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Specifies the state of PWM outputs in response to a fault condition.\r
+//!\r
+//! \param ulBase is the base address of the PWM module.\r
+//! \param ulPWMOutBits are the PWM outputs to be modified. Must be the\r
+//! logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, \b PWM_OUT_2_BIT,\r
+//! \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, or \b PWM_OUT_5_BIT.\r
+//! \param bFaultKill determines if the signal is killed or passed through\r
+//! during an active fault condition.\r
+//!\r
+//! This function sets the fault handling characteristics of the selected PWM\r
+//! outputs. The outputs are selected using the parameter \e ulPWMOutBits.\r
+//! The parameter \e bFaultKill determines the fault handling characteristics\r
+//! for the selected outputs. If \e bFaultKill is \b true, then the selected\r
+//! outputs will be made inactive. If \e bFaultKill is \b false, then the\r
+//! selected outputs are unaffected by the detected fault.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_outputfault) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+PWMOutputFault(unsigned long ulBase, unsigned long ulPWMOutBits,\r
+ tBoolean bFaultKill)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == PWM_BASE);\r
+ ASSERT(!(ulPWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT |\r
+ PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT)));\r
+\r
+ //\r
+ // Read the module's FAULT output control register, and set or clear\r
+ // the requested bits.\r
+ //\r
+ if(bFaultKill == true)\r
+ {\r
+ HWREG(ulBase + PWM_O_FAULT) |= ulPWMOutBits;\r
+ }\r
+ else\r
+ {\r
+ HWREG(ulBase + PWM_O_FAULT) &= ~(ulPWMOutBits);\r
+ }\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Registers an interrupt handler for the specified PWM generator block.\r
+//!\r
+//! \param ulBase is the base address of the PWM module.\r
+//! \param ulGen is the PWM generator in question.\r
+//! \param pfnIntHandler is a pointer to the function to be called when the PWM\r
+//! generator interrupt occurs.\r
+//!\r
+//! This function will ensure that the interrupt handler specified by\r
+//! \e pfnIntHandler is called when an interrupt is detected for the specified\r
+//! PWM generator block. This function will also enable the corresponding\r
+//! PWM generator interrupt in the interrupt controller; individual generator\r
+//! interrupts and interrupt sources must be enabled with PWMIntEnable() and\r
+//! PWMGenIntTrigEnable().\r
+//!\r
+//! \sa IntRegister() for important information about registering interrupt\r
+//! handlers.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_genintregister) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+PWMGenIntRegister(unsigned long ulBase, unsigned long ulGen,\r
+ void (*pfnIntHandler)(void))\r
+{\r
+ unsigned long ulInt;\r
+\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == PWM_BASE);\r
+ ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) ||\r
+ (ulGen == PWM_GEN_2));\r
+\r
+ //\r
+ // Get the interrupt number associated with the specified generator.\r
+ //\r
+ ulInt = INT_PWM0 + (ulGen >> 6) - 1;\r
+\r
+ //\r
+ // Register the interrupt handler.\r
+ //\r
+ IntRegister(ulInt, pfnIntHandler);\r
+\r
+ //\r
+ // Enable the PWMx interrupt.\r
+ //\r
+ IntEnable(ulInt);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Removes an interrupt handler for the specified PWM generator block.\r
+//!\r
+//! \param ulBase is the base address of the PWM module.\r
+//! \param ulGen is the PWM generator in question.\r
+//!\r
+//! This function will unregister the interrupt handler for the specified\r
+//! PWM generator block. This function will also disable the corresponding\r
+//! PWM generator interrupt in the interrupt controller; individual generator\r
+//! interrupts and interrupt sources must be disabled with PWMIntDisable() and\r
+//! PWMGenIntTrigDisable().\r
+//!\r
+//! \sa IntRegister() for important information about registering interrupt\r
+//! handlers.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_genintunregister) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+PWMGenIntUnregister(unsigned long ulBase, unsigned long ulGen)\r
+{\r
+ unsigned long ulInt;\r
+\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == PWM_BASE);\r
+ ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) ||\r
+ (ulGen == PWM_GEN_2));\r
+\r
+ //\r
+ // Get the interrupt number associated with the specified generator.\r
+ //\r
+ ulInt = INT_PWM0 + (ulGen >> 6) - 1;\r
+\r
+ //\r
+ // Disable the PWMx interrupt.\r
+ //\r
+ IntDisable(ulInt);\r
+\r
+ //\r
+ // Unregister the interrupt handler.\r
+ //\r
+ IntUnregister(ulInt);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Registers an interrupt handler for a fault condition detected in a PWM\r
+//! module.\r
+//!\r
+//! \param ulBase is the base address of the PWM module.\r
+//! \param pfnIntHandler is a pointer to the function to be called when the PWM\r
+//! fault interrupt occurs.\r
+//!\r
+//! This function will ensure that the interrupt handler specified by\r
+//! \e pfnIntHandler is called when a fault interrupt is detected for the\r
+//! selected PWM module. This function will also enable the PWM fault\r
+//! interrupt in the NVIC; the PWM fault interrupt must also be enabled at the\r
+//! module level using PWMIntEnable().\r
+//!\r
+//! \sa IntRegister() for important information about registering interrupt\r
+//! handlers.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_faultintregister) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+PWMFaultIntRegister(unsigned long ulBase, void (*pfnIntHandler)(void))\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == PWM_BASE);\r
+\r
+ //\r
+ // Register the interrupt handler, returning an error if one occurs.\r
+ //\r
+ IntRegister(INT_PWM_FAULT, pfnIntHandler);\r
+\r
+ //\r
+ // Enable the PWM fault interrupt.\r
+ //\r
+ IntEnable(INT_PWM_FAULT);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Removes the PWM fault condition interrupt handler.\r
+//!\r
+//! \param ulBase is the base address of the PWM module.\r
+//!\r
+//! This function will remove the interrupt handler for a PWM fault interrupt\r
+//! from the selected PWM module. This function will also disable the PWM\r
+//! fault interrupt in the NVIC; the PWM fault interrupt must also be disabled\r
+//! at the module level using PWMIntDisable().\r
+//!\r
+//! \sa IntRegister() for important information about registering interrupt\r
+//! handlers.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_faultintunregister) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+PWMFaultIntUnregister(unsigned long ulBase)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == PWM_BASE);\r
+\r
+ //\r
+ // Disable the PWM fault interrupt.\r
+ //\r
+ IntDisable(INT_PWM_FAULT);\r
+\r
+ //\r
+ // Unregister the interrupt handler, returning an error if one occurs.\r
+ //\r
+ IntUnregister(INT_PWM_FAULT);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Enables interrupts and triggers for the specified PWM generator block.\r
+//!\r
+//! \param ulBase is the base address of the PWM module.\r
+//! \param ulGen is the PWM generator to have interrupts and triggers enabled.\r
+//! Must be one of \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2.\r
+//! \param ulIntTrig specifies the interrupts and triggers to be enabled.\r
+//!\r
+//! Unmasks the specified interrupt(s) and trigger(s) by setting the\r
+//! specified bits of the interrupt/trigger enable register for the specified\r
+//! PWM generator. The defined values for the bits are as follows:\r
+//!\r
+//! - PWM_INT_CNT_ZERO\r
+//! - PWM_INT_CNT_LOAD\r
+//! - PWM_INT_CMP_AU\r
+//! - PWM_INT_CMP_AD\r
+//! - PWM_INT_CMP_BU\r
+//! - PWM_INT_CMP_BD\r
+//! - PWM_TR_CNT_ZERO\r
+//! - PWM_TR_CNT_LOAD\r
+//! - PWM_TR_CMP_AU\r
+//! - PWM_TR_CMP_AD\r
+//! - PWM_TR_CMP_BU\r
+//! - PWM_TR_CMP_BD\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_geninttrigenable) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+PWMGenIntTrigEnable(unsigned long ulBase, unsigned long ulGen,\r
+ unsigned long ulIntTrig)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == PWM_BASE);\r
+ ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) ||\r
+ (ulGen == PWM_GEN_2));\r
+\r
+ //\r
+ // Enable the specified interrupts/triggers.\r
+ //\r
+ HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_INTEN) |= ulIntTrig;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Disables interrupts for the specified PWM generator block.\r
+//!\r
+//! \param ulBase is the base address of the PWM module.\r
+//! \param ulGen is the PWM generator to have interrupts and triggers disabled.\r
+//! Must be one of \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2.\r
+//! \param ulIntTrig specifies the interrupts and triggers to be disabled.\r
+//!\r
+//! Masks the specified interrupt(s) and trigger(s) by clearing the\r
+//! specified bits of the interrupt/trigger enable register for the specified\r
+//! PWM generator. The defined values for the bits are as follows:\r
+//!\r
+//! - PWM_INT_CNT_ZERO\r
+//! - PWM_INT_CNT_LOAD\r
+//! - PWM_INT_CMP_AU\r
+//! - PWM_INT_CMP_AD\r
+//! - PWM_INT_CMP_BU\r
+//! - PWM_INT_CMP_BD\r
+//! - PWM_TR_CNT_ZERO\r
+//! - PWM_TR_CNT_LOAD\r
+//! - PWM_TR_CMP_AU\r
+//! - PWM_TR_CMP_AD\r
+//! - PWM_TR_CMP_BU\r
+//! - PWM_TR_CMP_BD\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_geninttrigdisable) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+PWMGenIntTrigDisable(unsigned long ulBase, unsigned long ulGen,\r
+ unsigned long ulIntTrig)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == PWM_BASE);\r
+ ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) ||\r
+ (ulGen == PWM_GEN_2));\r
+\r
+ //\r
+ // Disable the specified interrupts/triggers.\r
+ //\r
+ HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_INTEN) &= ~(ulIntTrig);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Gets interrupt status for the specified PWM generator block.\r
+//!\r
+//! \param ulBase is the base address of the PWM module.\r
+//! \param ulGen is the PWM generator to query. Must be one of \b PWM_GEN_0,\r
+//! \b PWM_GEN_1, or \b PWM_GEN_2.\r
+//! \param bMasked specifies whether masked or raw interrupt status is\r
+//! returned.\r
+//!\r
+//! If \e bMasked is set as \b true, then the masked interrupt status is\r
+//! returned; otherwise, the raw interrupt status will be returned.\r
+//!\r
+//! \return Returns the contents of the interrupt status register, or the\r
+//! contents of the raw interrupt status register, for the specified\r
+//! PWM generator.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_genintstatus) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+unsigned long\r
+PWMGenIntStatus(unsigned long ulBase, unsigned long ulGen, tBoolean bMasked)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == PWM_BASE);\r
+ ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) ||\r
+ (ulGen == PWM_GEN_2));\r
+\r
+ //\r
+ // Compute the generator's base address.\r
+ //\r
+ ulGen = PWM_GEN_BADDR(ulBase, ulGen);\r
+\r
+ //\r
+ // Read and return the specified generator's raw or enabled interrupt\r
+ // status.\r
+ //\r
+ if(bMasked == true)\r
+ {\r
+ return(HWREG(ulGen + PWM_O_X_ISC));\r
+ }\r
+ else\r
+ {\r
+ return(HWREG(ulGen + PWM_O_X_RIS));\r
+ }\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Clears the specified interrupt(s) for the specified PWM generator block.\r
+//!\r
+//! \param ulBase is the base address of the PWM module.\r
+//! \param ulGen is the PWM generator to query. Must be one of \b PWM_GEN_0,\r
+//! \b PWM_GEN_1, or \b PWM_GEN_2.\r
+//! \param ulInts specifies the interrupts to be cleared.\r
+//!\r
+//! Clears the specified interrupt(s) by writing a 1 to the specified bits\r
+//! of the interrupt status register for the specified PWM generator. The\r
+//! defined values for the bits are as follows:\r
+//!\r
+//! - PWM_INT_CNT_ZERO\r
+//! - PWM_INT_CNT_LOAD\r
+//! - PWM_INT_CMP_AU\r
+//! - PWM_INT_CMP_AD\r
+//! - PWM_INT_CMP_BU\r
+//! - PWM_INT_CMP_BD\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_genintclear) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+PWMGenIntClear(unsigned long ulBase, unsigned long ulGen, unsigned long ulInts)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == PWM_BASE);\r
+ ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) ||\r
+ (ulGen == PWM_GEN_2));\r
+\r
+ //\r
+ // Clear the requested interrupts by writing ones to the specified bit\r
+ // of the module's interrupt enable register.\r
+ //\r
+ HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_ISC) = ulInts;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Enables generator and fault interrupts for a PWM module.\r
+//!\r
+//! \param ulBase is the base address of the PWM module.\r
+//! \param ulGenFault contains the interrupts to be enabled. Must be a logical\r
+//! OR of any of \b PWM_INT_GEN_0, \b PWM_INT_GEN_1, \b PWM_INT_GEN_2, or\r
+//! \b PWM_INT_FAULT.\r
+//!\r
+//! Unmasks the specified interrupt(s) by setting the specified bits of\r
+//! the interrupt enable register for the selected PWM module.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+PWMIntEnable(unsigned long ulBase, unsigned long ulGenFault)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == PWM_BASE);\r
+\r
+ //\r
+ // Read the module's interrupt enable register, and enable interrupts\r
+ // for the specified PWM generators.\r
+ //\r
+ HWREG(ulBase + PWM_O_INTEN) |= ulGenFault;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Disables generator and fault interrupts for a PWM module.\r
+//!\r
+//! \param ulBase is the base address of the PWM module.\r
+//! \param ulGenFault contains the interrupts to be disabled. Must be a\r
+//! logical OR of any of \b PWM_INT_GEN_0, \b PWM_INT_GEN_1, \b PWM_INT_GEN_2,\r
+//! or \b PWM_INT_FAULT.\r
+//!\r
+//! Masks the specified interrupt(s) by clearing the specified bits of\r
+//! the interrupt enable register for the selected PWM module.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+PWMIntDisable(unsigned long ulBase, unsigned long ulGenFault)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == PWM_BASE);\r
+\r
+ //\r
+ // Read the module's interrupt enable register, and disable interrupts\r
+ // for the specified PWM generators.\r
+ //\r
+ HWREG(ulBase + PWM_O_INTEN) &= ~(ulGenFault);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Clears the fault interrupt for a PWM module.\r
+//!\r
+//! \param ulBase is the base address of the PWM module.\r
+//!\r
+//! Clears the fault interrupt by writing to the appropriate bit of the\r
+//! interrupt status register for the selected PWM module.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_faultintclear) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+PWMFaultIntClear(unsigned long ulBase)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == PWM_BASE);\r
+\r
+ //\r
+ // Write the only writeable bit in the module's interrupt register.\r
+ //\r
+ HWREG(ulBase + PWM_O_ISC) = PWM_INT_INTFAULT;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Gets the interrupt status for a PWM module.\r
+//!\r
+//! \param ulBase is the base address of the PWM module.\r
+//! \param bMasked specifies whether masked or raw interrupt status is\r
+//! returned.\r
+//!\r
+//! If \e bMasked is set as \b true, then the masked interrupt status is\r
+//! returned; otherwise, the raw interrupt status will be returned.\r
+//!\r
+//! \return The current interrupt status, enumerated as a bit field of\r
+//! \b PWM_INT_GEN_0, \b PWM_INT_GEN_1, \b PWM_INT_GEN_2, and \b PWM_INT_FAULT.\r
+//!\r
+//*****************************************************************************\r
+#if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+unsigned long\r
+PWMIntStatus(unsigned long ulBase, tBoolean bMasked)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == PWM_BASE);\r
+\r
+ //\r
+ // Read and return either the module's raw or enabled interrupt status.\r
+ //\r
+ if(bMasked == true)\r
+ {\r
+ return(HWREG(ulBase + PWM_O_ISC));\r
+ }\r
+ else\r
+ {\r
+ return(HWREG(ulBase + PWM_O_RIS));\r
+ }\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Close the Doxygen group.\r
+//! @}\r
+//\r
+//*****************************************************************************\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// pwm.h - API function protoypes for Pulse Width Modulation (PWM) ports\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 991 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __PWM_H__\r
+#define __PWM_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// The following defines are passed to PWMGenConfigure() as the ulConfig\r
+// parameter and specify the configuration of the PWM generator.\r
+//\r
+//*****************************************************************************\r
+#define PWM_GEN_MODE_DOWN 0x00000000 // Down count mode\r
+#define PWM_GEN_MODE_UP_DOWN 0x00000002 // Up/Down count mode\r
+#define PWM_GEN_MODE_SYNC 0x00000038 // Synchronous updates\r
+#define PWM_GEN_MODE_NO_SYNC 0x00000000 // Immediate updates\r
+#define PWM_GEN_MODE_DBG_RUN 0x00000004 // Continue running in debug mode\r
+#define PWM_GEN_MODE_DBG_STOP 0x00000000 // Stop running in debug mode\r
+\r
+//*****************************************************************************\r
+//\r
+// Defines for enabling, disabling, and clearing PWM generator interrupts and\r
+// triggers.\r
+//\r
+//*****************************************************************************\r
+#define PWM_INT_CNT_ZERO 0x00000001 // Int if COUNT = 0\r
+#define PWM_INT_CNT_LOAD 0x00000002 // Int if COUNT = LOAD\r
+#define PWM_INT_CNT_AU 0x00000004 // Int if COUNT = CMPA U\r
+#define PWM_INT_CNT_AD 0x00000008 // Int if COUNT = CMPA D\r
+#define PWM_INT_CNT_BU 0x00000010 // Int if COUNT = CMPA U\r
+#define PWM_INT_CNT_BD 0x00000020 // Int if COUNT = CMPA D\r
+#define PWM_TR_CNT_ZERO 0x00000100 // Trig if COUNT = 0\r
+#define PWM_TR_CNT_LOAD 0x00000200 // Trig if COUNT = LOAD\r
+#define PWM_TR_CNT_AU 0x00000400 // Trig if COUNT = CMPA U\r
+#define PWM_TR_CNT_AD 0x00000800 // Trig if COUNT = CMPA D\r
+#define PWM_TR_CNT_BU 0x00001000 // Trig if COUNT = CMPA U\r
+#define PWM_TR_CNT_BD 0x00002000 // Trig if COUNT = CMPA D\r
+\r
+//*****************************************************************************\r
+//\r
+// Defines for enabling, disabling, and clearing PWM interrupts.\r
+//\r
+//*****************************************************************************\r
+#define PWM_INT_GEN_0 0x00000001 // Generator 0 interrupt\r
+#define PWM_INT_GEN_1 0x00000002 // Generator 1 interrupt\r
+#define PWM_INT_GEN_2 0x00000004 // Generator 2 interrupt\r
+#define PWM_INT_FAULT 0x00010000 // Fault interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// Defines to identify the generators within a module.\r
+//\r
+//*****************************************************************************\r
+#define PWM_GEN_0 0x00000040 // Offset address of Gen0\r
+#define PWM_GEN_1 0x00000080 // Offset address of Gen1\r
+#define PWM_GEN_2 0x000000C0 // Offset address of Gen2\r
+\r
+#define PWM_GEN_0_BIT 0x00000001 // Bit-wise ID for Gen0\r
+#define PWM_GEN_1_BIT 0x00000002 // Bit-wise ID for Gen1\r
+#define PWM_GEN_2_BIT 0x00000004 // Bit-wise ID for Gen2\r
+\r
+//*****************************************************************************\r
+//\r
+// Defines to identify the outputs within a module.\r
+//\r
+//*****************************************************************************\r
+#define PWM_OUT_0 0x00000040 // Encoded offset address of PWM0\r
+#define PWM_OUT_1 0x00000041 // Encoded offset address of PWM1\r
+#define PWM_OUT_2 0x00000082 // Encoded offset address of PWM2\r
+#define PWM_OUT_3 0x00000083 // Encoded offset address of PWM3\r
+#define PWM_OUT_4 0x000000C4 // Encoded offset address of PWM4\r
+#define PWM_OUT_5 0x000000C5 // Encoded offset address of PWM5\r
+\r
+#define PWM_OUT_0_BIT 0x00000001 // Bit-wise ID for PWM0\r
+#define PWM_OUT_1_BIT 0x00000002 // Bit-wise ID for PWM1\r
+#define PWM_OUT_2_BIT 0x00000004 // Bit-wise ID for PWM2\r
+#define PWM_OUT_3_BIT 0x00000008 // Bit-wise ID for PWM3\r
+#define PWM_OUT_4_BIT 0x00000010 // Bit-wise ID for PWM4\r
+#define PWM_OUT_5_BIT 0x00000020 // Bit-wise ID for PWM5\r
+\r
+//*****************************************************************************\r
+//\r
+// API Function prototypes\r
+//\r
+//*****************************************************************************\r
+extern void PWMGenConfigure(unsigned long ulBase, unsigned long ulGen,\r
+ unsigned long ulConfig);\r
+extern void PWMGenPeriodSet(unsigned long ulBase, unsigned long ulGen,\r
+ unsigned long ulPeriod);\r
+extern unsigned long PWMGenPeriodGet(unsigned long ulBase,\r
+ unsigned long ulGen);\r
+extern void PWMGenEnable(unsigned long ulBase, unsigned long ulGen);\r
+extern void PWMGenDisable(unsigned long ulBase, unsigned long ulGen);\r
+extern void PWMPulseWidthSet(unsigned long ulBase, unsigned long ulPWMOut,\r
+ unsigned long ulWidth);\r
+extern unsigned long PWMPulseWidthGet(unsigned long ulBase,\r
+ unsigned long ulPWMOut);\r
+extern void PWMDeadBandEnable(unsigned long ulBase, unsigned long ulGen,\r
+ unsigned short usRise, unsigned short usFall);\r
+extern void PWMDeadBandDisable(unsigned long ulBase, unsigned long ulGen);\r
+extern void PWMSyncUpdate(unsigned long ulBase, unsigned long ulGenBits);\r
+extern void PWMSyncTimeBase(unsigned long ulBase, unsigned long ulGenBits);\r
+extern void PWMOutputState(unsigned long ulBase, unsigned long ulPWMOutBits,\r
+ tBoolean bEnable);\r
+extern void PWMOutputInvert(unsigned long ulBase, unsigned long ulPWMOutBits,\r
+ tBoolean bInvert);\r
+extern void PWMOutputFault(unsigned long ulBase, unsigned long ulPWMOutBits,\r
+ tBoolean bFaultKill);\r
+extern void PWMGenIntRegister(unsigned long ulBase, unsigned long ulGen,\r
+ void (*pfnIntHandler)(void));\r
+extern void PWMGenIntUnregister(unsigned long ulBase, unsigned long ulGen);\r
+extern void PWMFaultIntRegister(unsigned long ulBase,\r
+ void (*pfnIntHandler)(void));\r
+extern void PWMFaultIntUnregister(unsigned long ulBase);\r
+extern void PWMGenIntTrigEnable(unsigned long ulBase, unsigned long ulGen,\r
+ unsigned long ulIntTrig);\r
+extern void PWMGenIntTrigDisable(unsigned long ulBase, unsigned long ulGen,\r
+ unsigned long ulIntTrig);\r
+extern unsigned long PWMGenIntStatus(unsigned long ulBase, unsigned long ulGen,\r
+ tBoolean bMasked);\r
+extern void PWMGenIntClear(unsigned long ulBase, unsigned long ulGen,\r
+ unsigned long ulInts);\r
+extern void PWMIntEnable(unsigned long ulBase, unsigned long ulGenFault);\r
+extern void PWMIntDisable(unsigned long ulBase, unsigned long ulGenFault);\r
+extern void PWMFaultIntClear(unsigned long ulBase);\r
+extern unsigned long PWMIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __PWM_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// qei.c - Driver for the Quadrature Encoder with Index.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 991 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \addtogroup qei_api\r
+//! @{\r
+//\r
+//*****************************************************************************\r
+\r
+#include "../hw_ints.h"\r
+#include "../hw_memmap.h"\r
+#include "../hw_qei.h"\r
+#include "../hw_types.h"\r
+#include "debug.h"\r
+#include "interrupt.h"\r
+#include "qei.h"\r
+\r
+//*****************************************************************************\r
+//\r
+//! Enables the quadrature encoder.\r
+//!\r
+//! \param ulBase is the base address of the quadrature encoder module.\r
+//!\r
+//! This will enable operation of the quadrature encoder module. It must be\r
+//! configured before it is enabled.\r
+//!\r
+//! \sa QEIConfigure()\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_enable) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+QEIEnable(unsigned long ulBase)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == QEI_BASE);\r
+\r
+ //\r
+ // Enable the QEI module.\r
+ //\r
+ HWREG(ulBase + QEI_O_CTL) |= QEI_CTL_ENABLE;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Disables the quadrature encoder.\r
+//!\r
+//! \param ulBase is the base address of the quadrature encoder module.\r
+//!\r
+//! This will disable operation of the quadrature encoder module.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_disable) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+QEIDisable(unsigned long ulBase)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == QEI_BASE);\r
+\r
+ //\r
+ // Disable the QEI module.\r
+ //\r
+ HWREG(ulBase + QEI_O_CTL) &= ~(QEI_CTL_ENABLE);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Configures the quadrature encoder.\r
+//!\r
+//! \param ulBase is the base address of the quadrature encoder module.\r
+//! \param ulConfig is the configuration for the quadrature encoder. See below\r
+//! for a description of this parameter.\r
+//! \param ulMaxPosition specifies the maximum position value.\r
+//!\r
+//! This will configure the operation of the quadrature encoder. The\r
+//! \e ulConfig parameter provides the configuration of the encoder and is the\r
+//! logical OR of several values:\r
+//!\r
+//! - \b QEI_CONFIG_CAPTURE_A or \b QEI_CONFIG_CAPTURE_A_B to specify if edges\r
+//! on channel A or on both channels A and B should be counted by the\r
+//! position integrator and velocity accumulator.\r
+//! - \b QEI_CONFIG_NO_RESET or \b QEI_CONFIG_RESET_IDX to specify if the\r
+//! position integrator should be reset when the index pulse is detected.\r
+//! - \b QEI_CONFIG_QUADRATURE or \b QEI_CONFIG_CLOCK_DIR to specify if\r
+//! quadrature signals are being provided on ChA and ChB, or if a direction\r
+//! signal and a clock are being provided instead.\r
+//! - \b QEI_CONFIG_NO_SWAP or \b QEI_CONFIG_SWAP to specify if the signals\r
+//! provided on ChA and ChB should be swapped before being processed.\r
+//!\r
+//! \e ulMaxPosition is the maximum value of the position integrator, and is\r
+//! the value used to reset the position capture when in index reset mode and\r
+//! moving in the reverse (negative) direction.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_configure) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+QEIConfigure(unsigned long ulBase, unsigned long ulConfig,\r
+ unsigned long ulMaxPosition)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == QEI_BASE);\r
+\r
+ //\r
+ // Write the new configuration to the hardware.\r
+ //\r
+ HWREG(ulBase + QEI_O_CTL) = ((HWREG(ulBase + QEI_O_CTL) &\r
+ ~(QEI_CTL_CAPMODE | QEI_CTL_RESMODE |\r
+ QEI_CTL_SIGMODE | QEI_CTL_SWAP)) |\r
+ ulConfig);\r
+\r
+ //\r
+ // Set the maximum position.\r
+ //\r
+ HWREG(ulBase + QEI_O_MAXPOS) = ulMaxPosition;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Gets the current encoder position.\r
+//!\r
+//! \param ulBase is the base address of the quadrature encoder module.\r
+//!\r
+//! This returns the current position of the encoder. Depending upon the\r
+//! configuration of the encoder, and the incident of an index pulse, this\r
+//! value may or may not contain the expected data (i.e. if in reset on index\r
+//! mode, if an index pulse has not been encountered, the position counter will\r
+//! not be aligned with the index pulse yet).\r
+//!\r
+//! \return The current position of the encoder.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_positionget) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+unsigned long\r
+QEIPositionGet(unsigned long ulBase)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == QEI_BASE);\r
+\r
+ //\r
+ // Return the current position counter.\r
+ //\r
+ return(HWREG(ulBase + QEI_O_POS));\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Sets the current encoder position.\r
+//!\r
+//! \param ulBase is the base address of the quadrature encoder module.\r
+//! \param ulPosition is the new position for the encoder.\r
+//!\r
+//! This sets the current position of the encoder; the encoder position will\r
+//! then be measured relative to this value.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_positionset) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+QEIPositionSet(unsigned long ulBase, unsigned long ulPosition)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == QEI_BASE);\r
+\r
+ //\r
+ // Set the position counter.\r
+ //\r
+ HWREG(ulBase + QEI_O_POS) = ulPosition;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Gets the current direction of rotation.\r
+//!\r
+//! \param ulBase is the base address of the quadrature encoder module.\r
+//!\r
+//! This returns the current direction of rotation. In this case, current\r
+//! means the most recently detected direction of the encoder; it may not be\r
+//! presently moving but this is the direction it last moved before it stopped.\r
+//!\r
+//! \return 1 if moving in the forward direction or -1 if moving in the reverse\r
+//! direction.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_directionget) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+long\r
+QEIDirectionGet(unsigned long ulBase)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == QEI_BASE);\r
+\r
+ //\r
+ // Return the direction of rotation.\r
+ //\r
+ return((HWREG(ulBase + QEI_O_STAT) & QEI_STAT_DIRECTION) ? -1 : 1);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Gets the encoder error indicator.\r
+//!\r
+//! \param ulBase is the base address of the quadrature encoder module.\r
+//!\r
+//! This returns the error indicator for the quadrature encoder. It is an\r
+//! error for both of the signals of the quadrature input to change at the same\r
+//! time.\r
+//!\r
+//! \return true if an error has occurred and false otherwise.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_errorget) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+tBoolean\r
+QEIErrorGet(unsigned long ulBase)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == QEI_BASE);\r
+\r
+ //\r
+ // Return the error indicator.\r
+ //\r
+ return((HWREG(ulBase + QEI_O_STAT) & QEI_STAT_ERROR) ? true : false);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Enables the velocity capture.\r
+//!\r
+//! \param ulBase is the base address of the quadrature encoder module.\r
+//!\r
+//! This will enable operation of the velocity capture in the quadrature\r
+//! encoder module. It must be configured before it is enabled. Velocity\r
+//! capture will not occur if the quadrature encoder is not enabled.\r
+//!\r
+//! \sa QEIVelocityConfigure() and QEIEnable()\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_velocityenable) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+QEIVelocityEnable(unsigned long ulBase)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == QEI_BASE);\r
+\r
+ //\r
+ // Enable the velocity capture.\r
+ //\r
+ HWREG(ulBase + QEI_O_CTL) |= QEI_CTL_VELEN;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Disables the velocity capture.\r
+//!\r
+//! \param ulBase is the base address of the quadrature encoder module.\r
+//!\r
+//! This will disable operation of the velocity capture in the quadrature\r
+//! encoder module.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_velocitydisable) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+QEIVelocityDisable(unsigned long ulBase)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == QEI_BASE);\r
+\r
+ //\r
+ // Disable the velocity capture.\r
+ //\r
+ HWREG(ulBase + QEI_O_CTL) &= ~(QEI_CTL_VELEN);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Configures the velocity capture.\r
+//!\r
+//! \param ulBase is the base address of the quadrature encoder module.\r
+//! \param ulPreDiv specifies the predivider applied to the input quadrature\r
+//! signal before it is counted; can be one of QEI_VELDIV_1, QEI_VELDIV_2,\r
+//! QEI_VELDIV_4, QEI_VELDIV_8, QEI_VELDIV_16, QEI_VELDIV_32, QEI_VELDIV_64, or\r
+//! QEI_VELDIV_128.\r
+//! \param ulPeriod specifies the number of clock ticks over which to measure\r
+//! the velocity; must be non-zero.\r
+//!\r
+//! This will configure the operation of the velocity capture portion of the\r
+//! quadrature encoder. The position increment signal is predivided as\r
+//! specified by \e ulPreDiv before being accumulated by the velocity capture.\r
+//! The divided signal is accumulated over \e ulPeriod system clock before\r
+//! being saved and resetting the accumulator.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_velocityconfigure) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+QEIVelocityConfigure(unsigned long ulBase, unsigned long ulPreDiv,\r
+ unsigned long ulPeriod)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == QEI_BASE);\r
+ ASSERT(!(ulPreDiv & ~(QEI_CTL_VELDIV_M)));\r
+ ASSERT(ulPeriod != 0);\r
+\r
+ //\r
+ // Set the velocity predivider.\r
+ //\r
+ HWREG(ulBase + QEI_O_CTL) = ((HWREG(ulBase + QEI_O_CTL) &\r
+ ~(QEI_CTL_VELDIV_M)) | ulPreDiv);\r
+\r
+ //\r
+ // Set the timer period.\r
+ //\r
+ HWREG(ulBase + QEI_O_LOAD) = ulPeriod - 1;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Gets the current encoder speed.\r
+//!\r
+//! \param ulBase is the base address of the quadrature encoder module.\r
+//!\r
+//! This returns the current speed of the encoder. The value returned is the\r
+//! number of pulses detected in the specified time period; this number can be\r
+//! multiplied by the number of time periods per second and divided by the\r
+//! number of pulses per revolution to obtain the number of revolutions per\r
+//! second.\r
+//!\r
+//! \return The number of pulses captured in the given time period.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_velocityget) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+unsigned long\r
+QEIVelocityGet(unsigned long ulBase)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == QEI_BASE);\r
+\r
+ //\r
+ // Return the speed capture value.\r
+ //\r
+ return(HWREG(ulBase + QEI_O_SPEED));\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Registers an interrupt handler for the quadrature encoder interrupt.\r
+//!\r
+//! \param ulBase is the base address of the quadrature encoder module.\r
+//! \param pfnHandler is a pointer to the function to be called when the\r
+//! quadrature encoder interrupt occurs.\r
+//!\r
+//! This sets the handler to be called when a quadrature encoder interrupt\r
+//! occurs. This will enable the global interrupt in the interrupt controller;\r
+//! specific quadrature encoder interrupts must be enabled via QEIIntEnable().\r
+//! It is the interrupt handler's responsibility to clear the interrupt source\r
+//! via QEIIntClear().\r
+//!\r
+//! \sa IntRegister() for important information about registering interrupt\r
+//! handlers.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+QEIIntRegister(unsigned long ulBase, void (*pfnHandler)(void))\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == QEI_BASE);\r
+\r
+ //\r
+ // Register the interrupt handler, returning an error if an error occurs.\r
+ //\r
+ IntRegister(INT_QEI, pfnHandler);\r
+\r
+ //\r
+ // Enable the quadrature encoder interrupt.\r
+ //\r
+ IntEnable(INT_QEI);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Unregisters an interrupt handler for the quadrature encoder interrupt.\r
+//!\r
+//! \param ulBase is the base address of the quadrature encoder module.\r
+//!\r
+//! This function will clear the handler to be called when a quadrature encoder\r
+//! interrupt occurs. This will also mask off the interrupt in the interrupt\r
+//! controller so that the interrupt handler no longer is called.\r
+//!\r
+//! \sa IntRegister() for important information about registering interrupt\r
+//! handlers.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+QEIIntUnregister(unsigned long ulBase)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == QEI_BASE);\r
+\r
+ //\r
+ // Disable the interrupt.\r
+ //\r
+ IntDisable(INT_QEI);\r
+\r
+ //\r
+ // Unregister the interrupt handler.\r
+ //\r
+ IntUnregister(INT_QEI);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Enables individual quadrature encoder interrupt sources.\r
+//!\r
+//! \param ulBase is the base address of the quadrature encoder module.\r
+//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled.\r
+//! Can be any of the QEI_INTERROR, QEI_INTDIR, QEI_INTTIMER, or QEI_INTINDEX\r
+//! values.\r
+//!\r
+//! Enables the indicated quadrature encoder interrupt sources. Only the\r
+//! sources that are enabled can be reflected to the processor interrupt;\r
+//! disabled sources have no effect on the processor.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+QEIIntEnable(unsigned long ulBase, unsigned long ulIntFlags)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == QEI_BASE);\r
+\r
+ //\r
+ // Enable the specified interrupts.\r
+ //\r
+ HWREG(ulBase + QEI_O_INTEN) |= ulIntFlags;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Disables individual quadrature encoder interrupt sources.\r
+//!\r
+//! \param ulBase is the base address of the quadrature encoder module.\r
+//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled.\r
+//! Can be any of the QEI_INTERROR, QEI_INTDIR, QEI_INTTIMER, or QEI_INTINDEX\r
+//! values.\r
+//!\r
+//! Disables the indicated quadrature encoder interrupt sources. Only the\r
+//! sources that are enabled can be reflected to the processor interrupt;\r
+//! disabled sources have no effect on the processor.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+QEIIntDisable(unsigned long ulBase, unsigned long ulIntFlags)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == QEI_BASE);\r
+\r
+ //\r
+ // Disable the specified interrupts.\r
+ //\r
+ HWREG(ulBase + QEI_O_INTEN) &= ~(ulIntFlags);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Gets the current interrupt status.\r
+//!\r
+//! \param ulBase is the base address of the quadrature encoder module.\r
+//! \param bMasked is false if the raw interrupt status is required and true if\r
+//! the masked interrupt status is required.\r
+//!\r
+//! This returns the interrupt status for the quadrature encoder module.\r
+//! Either the raw interrupt status or the status of interrupts that are\r
+//! allowed to reflect to the processor can be returned.\r
+//!\r
+//! \return The current interrupt status, enumerated as a bit field of\r
+//! QEI_INTERROR, QEI_INTDIR, QEI_INTTIMER, and QEI_INTINDEX.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+unsigned long\r
+QEIIntStatus(unsigned long ulBase, tBoolean bMasked)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == QEI_BASE);\r
+\r
+ //\r
+ // Return either the interrupt status or the raw interrupt status as\r
+ // requested.\r
+ //\r
+ if(bMasked)\r
+ {\r
+ return(HWREG(ulBase + QEI_O_ISC));\r
+ }\r
+ else\r
+ {\r
+ return(HWREG(ulBase + QEI_O_RIS));\r
+ }\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Clears quadrature encoder interrupt sources.\r
+//!\r
+//! \param ulBase is the base address of the quadrature encoder module.\r
+//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.\r
+//! Can be any of the QEI_INTERROR, QEI_INTDIR, QEI_INTTIMER, or QEI_INTINDEX\r
+//! values.\r
+//!\r
+//! The specified quadrature encoder interrupt sources are cleared, so that\r
+//! they no longer assert. This must be done in the interrupt handler to keep\r
+//! it from being called again immediately upon exit.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+QEIIntClear(unsigned long ulBase, unsigned long ulIntFlags)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == QEI_BASE);\r
+\r
+ //\r
+ // Clear the requested interrupt sources.\r
+ //\r
+ HWREG(ulBase + QEI_O_ISC) = ulIntFlags;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Close the Doxygen group.\r
+//! @}\r
+//\r
+//*****************************************************************************\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// qei.h - Prototypes for the Quadrature Encoder Driver.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 991 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __QEI_H__\r
+#define __QEI_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to QEIConfigure as the ulConfig paramater.\r
+//\r
+//*****************************************************************************\r
+#define QEI_CONFIG_CAPTURE_A 0x00000000 // Count on ChA edges only\r
+#define QEI_CONFIG_CAPTURE_A_B 0x00000008 // Count on ChA and ChB edges\r
+#define QEI_CONFIG_NO_RESET 0x00000000 // Do not reset on index pulse\r
+#define QEI_CONFIG_RESET_IDX 0x00000010 // Reset position on index pulse\r
+#define QEI_CONFIG_QUADRATURE 0x00000000 // ChA and ChB are quadrature\r
+#define QEI_CONFIG_CLOCK_DIR 0x00000004 // ChA and ChB are clock and dir\r
+#define QEI_CONFIG_NO_SWAP 0x00000000 // Do not swap ChA and ChB\r
+#define QEI_CONFIG_SWAP 0x00000002 // Swap ChA and ChB\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to QEIVelocityConfigure as the ulPreDiv parameter.\r
+//\r
+//*****************************************************************************\r
+#define QEI_VELDIV_1 0x00000000 // Predivide by 1\r
+#define QEI_VELDIV_2 0x00000040 // Predivide by 2\r
+#define QEI_VELDIV_4 0x00000080 // Predivide by 4\r
+#define QEI_VELDIV_8 0x000000C0 // Predivide by 8\r
+#define QEI_VELDIV_16 0x00000100 // Predivide by 16\r
+#define QEI_VELDIV_32 0x00000140 // Predivide by 32\r
+#define QEI_VELDIV_64 0x00000180 // Predivide by 64\r
+#define QEI_VELDIV_128 0x000001C0 // Predivide by 128\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to QEIEnableInts, QEIDisableInts, and QEIClearInts\r
+// as the ulIntFlags parameter, and returned by QEIGetIntStatus.\r
+//\r
+//*****************************************************************************\r
+#define QEI_INTERROR 0x00000008 // Phase error detected\r
+#define QEI_INTDIR 0x00000004 // Direction change\r
+#define QEI_INTTIMER 0x00000002 // Velocity timer expired\r
+#define QEI_INTINDEX 0x00000001 // Index pulse detected\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void QEIEnable(unsigned long ulBase);\r
+extern void QEIDisable(unsigned long ulBase);\r
+extern void QEIConfigure(unsigned long ulBase, unsigned long ulConfig,\r
+ unsigned long ulMaxPosition);\r
+extern unsigned long QEIPositionGet(unsigned long ulBase);\r
+extern void QEIPositionSet(unsigned long ulBase, unsigned long ulPosition);\r
+extern long QEIDirectionGet(unsigned long ulBase);\r
+extern tBoolean QEIErrorGet(unsigned long ulBase);\r
+extern void QEIVelocityEnable(unsigned long ulBase);\r
+extern void QEIVelocityDisable(unsigned long ulBase);\r
+extern void QEIVelocityConfigure(unsigned long ulBase, unsigned long ulPreDiv,\r
+ unsigned long ulPeriod);\r
+extern unsigned long QEIVelocityGet(unsigned long ulBase);\r
+extern void QEIIntRegister(unsigned long ulBase, void (*pfnHandler)(void));\r
+extern void QEIIntUnregister(unsigned long ulBase);\r
+extern void QEIIntEnable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void QEIIntDisable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern unsigned long QEIIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern void QEIIntClear(unsigned long ulBase, unsigned long ulIntFlags);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __QEI_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// ssi.c - Driver for Synchronous Serial Interface.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 991 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \addtogroup ssi_api\r
+//! @{\r
+//\r
+//*****************************************************************************\r
+\r
+#include "../hw_ints.h"\r
+#include "../hw_memmap.h"\r
+#include "../hw_ssi.h"\r
+#include "../hw_types.h"\r
+#include "debug.h"\r
+#include "interrupt.h"\r
+#include "ssi.h"\r
+#include "sysctl.h"\r
+\r
+//*****************************************************************************\r
+//\r
+//! Configures the synchronous serial interface.\r
+//!\r
+//! \param ulBase specifies the SSI module base address.\r
+//! \param ulProtocol specifies the data transfer protocol.\r
+//! \param ulMode specifies the mode of operation.\r
+//! \param ulBitRate specifies the clock rate.\r
+//! \param ulDataWidth specifies number of bits transfered per frame.\r
+//!\r
+//! This function configures the synchronous serial interface. It sets\r
+//! the SSI protocol, mode of operation, bit rate, and data width.\r
+//!\r
+//! The parameter \e ulProtocol defines the data frame format. The parameter\r
+//! \e ulProtocol can be one of the following values: SSI_FRF_MOTO_MODE_0,\r
+//! SSI_FRF_MOTO_MODE_1, SSI_FRF_MOTO_MODE_2, SSI_FRF_MOTO_MODE_3,\r
+//! SSI_FRF_TI, or SSI_FRF_NMW. The Motorola frame formats imply the\r
+//! following polarity and phase configurations:\r
+//! <pre>\r
+//! Polarity Phase Mode\r
+//! 0 0 SSI_FRF_MOTO_MODE_0\r
+//! 0 1 SSI_FRF_MOTO_MODE_1\r
+//! 1 0 SSI_FRF_MOTO_MODE_2\r
+//! 1 1 SSI_FRF_MOTO_MODE_3\r
+//! </pre>\r
+//!\r
+//! The parameter \e ulMode defines the operating mode of the SSI module. The\r
+//! SSI module can operate as a master or slave; if a slave, the SSI can be\r
+//! configured to disable output on its serial output line. The parameter\r
+//! \e ulMode can be one of the following values: SSI_MODE_MASTER,\r
+//! SSI_MODE_SLAVE, or SSI_MODE_SLAVE_OD.\r
+//!\r
+//! The parameter \e ulBitRate defines the bit rate for the SSI. This bit rate\r
+//! must satisfy the following clock ratio criteria:\r
+//! - FSSI >= 2 * bit rate (master mode)\r
+//! - FSSI >= 12 * bit rate (slave modes)\r
+//!\r
+//! where FSSI is the frequency of the clock supplied to the SSI module.\r
+//!\r
+//! The parameter \e ulDataWidth defines the width of the data transfers.\r
+//! The parameter \e ulDataWidth can be a value between 4 and 16, inclusive.\r
+//!\r
+//! The SSI clocking is dependent upon the system clock rate returned by\r
+//! SysCtlClockGet(); if it does not return the correct system clock rate then\r
+//! the SSI clock rate will be incorrect.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_config) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+SSIConfig(unsigned long ulBase, unsigned long ulProtocol, unsigned long ulMode,\r
+ unsigned long ulBitRate, unsigned long ulDataWidth)\r
+{\r
+ unsigned long ulMaxBitRate;\r
+ unsigned long ulRegVal;\r
+ unsigned long ulPreDiv;\r
+ unsigned long ulSCR;\r
+ unsigned long ulSPH_SPO;\r
+ unsigned long ulClock;\r
+\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == SSI_BASE);\r
+ ASSERT((ulProtocol == SSI_FRF_MOTO_MODE_0) ||\r
+ (ulProtocol == SSI_FRF_MOTO_MODE_1) ||\r
+ (ulProtocol == SSI_FRF_MOTO_MODE_2) ||\r
+ (ulProtocol == SSI_FRF_MOTO_MODE_3) ||\r
+ (ulProtocol == SSI_FRF_TI) ||\r
+ (ulProtocol == SSI_FRF_NMW));\r
+ ASSERT((ulMode == SSI_MODE_MASTER) ||\r
+ (ulMode == SSI_MODE_SLAVE) ||\r
+ (ulMode == SSI_MODE_SLAVE_OD));\r
+ ASSERT((ulDataWidth >= 4) && (ulDataWidth <= 16));\r
+\r
+ //\r
+ // Get the processor clock rate.\r
+ //\r
+ ulClock = SysCtlClockGet();\r
+\r
+ //\r
+ // Validate the clock speed.\r
+ //\r
+ ASSERT(((ulMode == SSI_MODE_MASTER) && (ulBitRate <= (ulClock / 2))) ||\r
+ ((ulMode != SSI_MODE_MASTER) && (ulBitRate <= (ulClock / 12))));\r
+ ASSERT((ulClock / ulBitRate) <= (254 * 256));\r
+\r
+ //\r
+ // Set the mode.\r
+ //\r
+ ulRegVal = (ulMode == SSI_MODE_SLAVE_OD) ? SSI_CR1_SOD : 0;\r
+ ulRegVal |= (ulMode == SSI_MODE_MASTER) ? 0 : SSI_CR1_MS;\r
+ HWREG(ulBase + SSI_O_CR1) = ulRegVal;\r
+\r
+ //\r
+ // Set the clock predivider.\r
+ //\r
+ ulMaxBitRate = ulClock / ulBitRate;\r
+ ulPreDiv = 0;\r
+ do\r
+ {\r
+ ulPreDiv += 2;\r
+ ulSCR = (ulMaxBitRate / ulPreDiv) - 1;\r
+ }\r
+ while(ulSCR > 255);\r
+ HWREG(ulBase + SSI_O_CPSR) = ulPreDiv;\r
+\r
+ //\r
+ // Set protocol and clock rate.\r
+ //\r
+ ulSPH_SPO = ulProtocol << 6;\r
+ ulProtocol &= SSI_CR0_FRF_MASK;\r
+ ulRegVal = (ulSCR << 8) | ulSPH_SPO | ulProtocol | (ulDataWidth - 1);\r
+ HWREG(ulBase + SSI_O_CR0) = ulRegVal;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Enables the synchronous serial interface.\r
+//!\r
+//! \param ulBase specifies the SSI module base address.\r
+//!\r
+//! This will enable operation of the synchronous serial interface. It must be\r
+//! configured before it is enabled.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_enable) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+SSIEnable(unsigned long ulBase)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == SSI_BASE);\r
+\r
+ //\r
+ // Read-modify-write the enable bit.\r
+ //\r
+ HWREG(ulBase + SSI_O_CR1) |= SSI_CR1_SSE;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Disables the synchronous serial interface.\r
+//!\r
+//! \param ulBase specifies the SSI module base address.\r
+//!\r
+//! This will disable operation of the synchronous serial interface.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_disable) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+SSIDisable(unsigned long ulBase)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == SSI_BASE);\r
+\r
+ //\r
+ // Read-modify-write the enable bit.\r
+ //\r
+ HWREG(ulBase + SSI_O_CR1) &= ~(SSI_CR1_SSE);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Registers an interrupt handler for the synchronous serial interface.\r
+//!\r
+//! \param ulBase specifies the SSI module base address.\r
+//! \param pfnHandler is a pointer to the function to be called when the\r
+//! synchronous serial interface interrupt occurs.\r
+//!\r
+//! This sets the handler to be called when an SSI interrupt\r
+//! occurs. This will enable the global interrupt in the interrupt controller;\r
+//! specific SSI interrupts must be enabled via SSIIntEnable(). If necessary,\r
+//! it is the interrupt handler's responsibility to clear the interrupt source\r
+//! via SSIIntClear().\r
+//!\r
+//! \sa IntRegister() for important information about registering interrupt\r
+//! handlers.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+SSIIntRegister(unsigned long ulBase, void (*pfnHandler)(void))\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == SSI_BASE);\r
+\r
+ //\r
+ // Register the interrupt handler, returning an error if an error occurs.\r
+ //\r
+ IntRegister(INT_SSI, pfnHandler);\r
+\r
+ //\r
+ // Enable the synchronous serial interface interrupt.\r
+ //\r
+ IntEnable(INT_SSI);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Unregisters an interrupt handler for the synchronous serial interface.\r
+//!\r
+//! \param ulBase specifies the SSI module base address.\r
+//!\r
+//! This function will clear the handler to be called when a SSI\r
+//! interrupt occurs. This will also mask off the interrupt in the interrupt\r
+//! controller so that the interrupt handler no longer is called.\r
+//!\r
+//! \sa IntRegister() for important information about registering interrupt\r
+//! handlers.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+SSIIntUnregister(unsigned long ulBase)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == SSI_BASE);\r
+\r
+ //\r
+ // Disable the interrupt.\r
+ //\r
+ IntDisable(INT_SSI);\r
+\r
+ //\r
+ // Unregister the interrupt handler.\r
+ //\r
+ IntUnregister(INT_SSI);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Enables individual SSI interrupt sources.\r
+//!\r
+//! \param ulBase specifies the SSI module base address.\r
+//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled.\r
+//!\r
+//! Enables the indicated SSI interrupt sources. Only the sources that are\r
+//! enabled can be reflected to the processor interrupt; disabled sources\r
+//! have no effect on the processor. The parameter \e ulIntFlags Can be\r
+//! any of the SSI_TXFF, SSI_RXFF, SSI_RXTO, or SSI_RXOR values.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == SSI_BASE);\r
+\r
+ //\r
+ // Enable the specified interrupts.\r
+ //\r
+ HWREG(ulBase + SSI_O_IM) |= ulIntFlags;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Disables individual SSI interrupt sources.\r
+//!\r
+//! \param ulBase specifies the SSI module base address.\r
+//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled.\r
+//!\r
+//! Disables the indicated SSI interrupt sources. The parameter\r
+//! \e ulIntFlags Can be any of the SSI_TXFF, SSI_RXFF, SSI_RXTO,\r
+//! or SSI_RXOR values.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == SSI_BASE);\r
+\r
+ //\r
+ // Disable the specified interrupts.\r
+ //\r
+ HWREG(ulBase + SSI_O_IM) &= ~(ulIntFlags);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Gets the current interrupt status.\r
+//!\r
+//! \param ulBase specifies the SSI module base address.\r
+//! \param bMasked is false if the raw interrupt status is required and\r
+//! true if the masked interrupt status is required.\r
+//!\r
+//! This returns the interrupt status for the SSI module.\r
+//! Either the raw interrupt status or the status of interrupts that are\r
+//! allowed to reflect to the processor can be returned.\r
+//!\r
+//! \return The current interrupt status, enumerated as a bit field of\r
+//! SSI_TXFF, SSI_RXFF, SSI_RXTO, and SSI_RXOR.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+unsigned long\r
+SSIIntStatus(unsigned long ulBase, tBoolean bMasked)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == SSI_BASE);\r
+\r
+ //\r
+ // Return either the interrupt status or the raw interrupt status as\r
+ // requested.\r
+ //\r
+ if(bMasked)\r
+ {\r
+ return(HWREG(ulBase + SSI_O_MIS));\r
+ }\r
+ else\r
+ {\r
+ return(HWREG(ulBase + SSI_O_RIS));\r
+ }\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Clears SSI interrupt sources.\r
+//!\r
+//! \param ulBase specifies the SSI module base address.\r
+//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.\r
+//!\r
+//! The specified SSI interrupt sources are cleared, so that\r
+//! they no longer assert. This must be done in the interrupt handler to\r
+//! keep it from being called again immediately upon exit.\r
+//! The parameter \e ulIntFlags can consist of either or both the SSI_RXTO\r
+//! and SSI_RXOR values.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == SSI_BASE);\r
+\r
+ //\r
+ // Clear the requested interrupt sources.\r
+ //\r
+ HWREG(ulBase + SSI_O_ICR) = ulIntFlags;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Puts a data element into the SSI transmit FIFO.\r
+//!\r
+//! \param ulBase specifies the SSI module base address.\r
+//! \param ulData data to be transmitted over the SSI interface.\r
+//!\r
+//! This function will place the supplied data into the transmit FIFO of\r
+//! the specified SSI module.\r
+//!\r
+//! \note The upper 32 - N bits of the \e ulData will be discarded by the\r
+//! hardware, where N is the data width as configured by SSIConfig(). For\r
+//! example, if the interface is configured for 8 bit data width, the upper 24\r
+//! bits of \e ulData will be discarded.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_dataput) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+SSIDataPut(unsigned long ulBase, unsigned long ulData)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == SSI_BASE);\r
+ ASSERT((ulData & (0xfffffffe << (HWREG(ulBase + SSI_O_CR0) &\r
+ SSI_CR0_DSS))) == 0);\r
+\r
+ //\r
+ // Wait until there is space.\r
+ //\r
+ while(!(HWREG(ulBase + SSI_O_SR) & SSI_SR_TNF))\r
+ {\r
+ }\r
+\r
+ //\r
+ // Write the data to the SSI.\r
+ //\r
+ HWREG(ulBase + SSI_O_DR) = ulData;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Puts a data element into the SSI transmit FIFO.\r
+//!\r
+//! \param ulBase specifies the SSI module base address.\r
+//! \param ulData data to be transmitted over the SSI interface.\r
+//!\r
+//! This function will place the supplied data into the transmit FIFO of\r
+//! the specified SSI module. If there is no space in the FIFO, then this\r
+//! function will return a zero.\r
+//!\r
+//! \note The upper 32 - N bits of the \e ulData will be discarded by the\r
+//! hardware, where N is the data width as configured by SSIConfig(). For\r
+//! example, if the interface is configured for 8 bit data width, the upper 24\r
+//! bits of \e ulData will be discarded.\r
+//!\r
+//! \return Returns the number of elements written to the SSI transmit FIFO.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_datanonblockingput) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+long\r
+SSIDataNonBlockingPut(unsigned long ulBase, unsigned long ulData)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == SSI_BASE);\r
+ ASSERT((ulData & (0xfffffffe << (HWREG(ulBase + SSI_O_CR0) &\r
+ SSI_CR0_DSS))) == 0);\r
+\r
+ //\r
+ // Check for space to write.\r
+ //\r
+ if(HWREG(ulBase + SSI_O_SR) & SSI_SR_TNF)\r
+ {\r
+ HWREG(ulBase + SSI_O_DR) = ulData;\r
+ return(1);\r
+ }\r
+ else\r
+ {\r
+ return(0);\r
+ }\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Gets a data element from the SSI receive FIFO.\r
+//!\r
+//! \param ulBase specifies the SSI module base address.\r
+//! \param pulData pointer to a storage location for data that was received\r
+//! over the SSI interface.\r
+//!\r
+//! This function will get received data from the receive FIFO of the specified\r
+//! SSI module, and place that data into the location specified by the\r
+//! \e pulData parameter.\r
+//!\r
+//! \note Only the lower N bits of the value written to \e pulData will contain\r
+//! valid data, where N is the data width as configured by SSIConfig(). For\r
+//! example, if the interface is configured for 8 bit data width, only the\r
+//! lower 8 bits of the value written to \e pulData will contain valid data.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_dataget) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+SSIDataGet(unsigned long ulBase, unsigned long *pulData)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == SSI_BASE);\r
+\r
+ //\r
+ // Wait until there is data to be read.\r
+ //\r
+ while(!(HWREG(ulBase + SSI_O_SR) & SSI_SR_RNE))\r
+ {\r
+ }\r
+\r
+ //\r
+ // Read data from SSI.\r
+ //\r
+ *pulData = HWREG(ulBase + SSI_O_DR);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Gets a data element from the SSI receive FIFO.\r
+//!\r
+//! \param ulBase specifies the SSI module base address.\r
+//! \param pulData pointer to a storage location for data that was received\r
+//! over the SSI interface.\r
+//!\r
+//! This function will get received data from the receive FIFO of\r
+//! the specified SSI module, and place that data into the location specified\r
+//! by the \e ulData parameter. If there is no data in the FIFO, then this\r
+//! function will return a zero.\r
+//!\r
+//! \note Only the lower N bits of the value written to \e pulData will contain\r
+//! valid data, where N is the data width as configured by SSIConfig(). For\r
+//! example, if the interface is configured for 8 bit data width, only the\r
+//! lower 8 bits of the value written to \e pulData will contain valid data.\r
+//!\r
+//! \return Returns the number of elements read from the SSI receive FIFO.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_datanonblockingget) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+long\r
+SSIDataNonBlockingGet(unsigned long ulBase, unsigned long *pulData)\r
+{ \r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == SSI_BASE);\r
+\r
+ //\r
+ // Check for data to read.\r
+ //\r
+ if(HWREG(ulBase + SSI_O_SR) & SSI_SR_RNE)\r
+ {\r
+ *pulData = HWREG(ulBase + SSI_O_DR);\r
+ return(1);\r
+ }\r
+ else\r
+ {\r
+ return(0);\r
+ }\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Close the Doxygen group.\r
+//! @}\r
+//\r
+//*****************************************************************************\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// ssi.h - Prototypes for the Synchronous Serial Interface Driver.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 991 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __SSI_H__\r
+#define __SSI_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear\r
+// as the ulIntFlags parameter, and returned by SSIIntStatus.\r
+//\r
+//*****************************************************************************\r
+#define SSI_TXFF 0x00000008 // TX FIFO half empty or less\r
+#define SSI_RXFF 0x00000004 // RX FIFO half full or less\r
+#define SSI_RXTO 0x00000002 // RX timeout\r
+#define SSI_RXOR 0x00000001 // RX overrun\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to SSIConfig.\r
+//\r
+//*****************************************************************************\r
+#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0\r
+#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1\r
+#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0\r
+#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1\r
+#define SSI_FRF_TI 0x00000010 // TI frame format\r
+#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format\r
+\r
+#define SSI_MODE_MASTER 0x00000000 // SSI master\r
+#define SSI_MODE_SLAVE 0x00000001 // SSI slave\r
+#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void SSIConfig(unsigned long ulBase, unsigned long ulProtocol,\r
+ unsigned long ulMode, unsigned long ulBitRate,\r
+ unsigned long ulDataWidth);\r
+extern void SSIDataGet(unsigned long ulBase, unsigned long *pulData);\r
+extern long SSIDataNonBlockingGet(unsigned long ulBase,\r
+ unsigned long *pulData);\r
+extern void SSIDataPut(unsigned long ulBase, unsigned long ulData);\r
+extern long SSIDataNonBlockingPut(unsigned long ulBase, unsigned long ulData);\r
+extern void SSIDisable(unsigned long ulBase);\r
+extern void SSIEnable(unsigned long ulBase);\r
+extern void SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void SSIIntRegister(unsigned long ulBase, void(*pfnHandler)(void));\r
+extern unsigned long SSIIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern void SSIIntUnregister(unsigned long ulBase);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __SSI_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// sysctl.c - Driver for the system controller.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. ALl rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 991 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \addtogroup sysctl_api\r
+//! @{\r
+//\r
+//*****************************************************************************\r
+\r
+#include "../hw_ints.h"\r
+#include "../hw_memmap.h"\r
+#include "../hw_nvic.h"\r
+#include "../hw_sysctl.h"\r
+#include "../hw_types.h"\r
+#include "cpu.h"\r
+#include "debug.h"\r
+#include "interrupt.h"\r
+#include "sysctl.h"\r
+\r
+//*****************************************************************************\r
+//\r
+// An array that maps the "peripheral set" number (which is stored in the upper\r
+// nibble of the SYSCTL_PERIPH_* defines) to the SYSCTL DC? register that\r
+// contains the peripheral present bit for that peripheral.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_puldcregs) || defined(BUILD_ALL)\r
+const unsigned long g_pulDCRegs[] =\r
+{\r
+ SYSCTL_DC1,\r
+ SYSCTL_DC2,\r
+ SYSCTL_DC4,\r
+ SYSCTL_DC1\r
+};\r
+#else\r
+extern const unsigned long g_pulDCRegs[];\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// An array that maps the "peripheral set" number (which is stored in the upper\r
+// nibble of the SYSCTL_PERIPH_* defines) to the SYSCTL_SRCR? register that\r
+// controls the software reset for that peripheral.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_pulsrcrregs) || defined(BUILD_ALL)\r
+const unsigned long g_pulSRCRRegs[] =\r
+{\r
+ SYSCTL_SRCR0,\r
+ SYSCTL_SRCR1,\r
+ SYSCTL_SRCR2\r
+};\r
+#else\r
+extern const unsigned long g_pulSRCRRegs[];\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// An array that maps the "peripheral set" number (which is stored in the upper\r
+// nibble of the SYSCTL_PERIPH_* defines) to the SYSCTL_RCGC? register that\r
+// controls the run-mode enable for that peripheral.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_pulrcgcregs) || defined(BUILD_ALL)\r
+const unsigned long g_pulRCGCRegs[] =\r
+{\r
+ SYSCTL_RCGC0,\r
+ SYSCTL_RCGC1,\r
+ SYSCTL_RCGC2\r
+};\r
+#else\r
+extern const unsigned long g_pulRCGCRegs[];\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// An array that maps the "peripheral set" number (which is stored in the upper\r
+// nibble of the SYSCTL_PERIPH_* defines) to the SYSCTL_SCGC? register that\r
+// controls the sleep-mode enable for that peripheral.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_pulscgcregs) || defined(BUILD_ALL)\r
+const unsigned long g_pulSCGCRegs[] =\r
+{\r
+ SYSCTL_SCGC0,\r
+ SYSCTL_SCGC1,\r
+ SYSCTL_SCGC2\r
+};\r
+#else\r
+extern const unsigned long g_pulSCGCRegs[];\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// An array that maps the "peripheral set" number (which is stored in the upper\r
+// nibble of the SYSCTL_PERIPH_* defines) to the SYSCTL_DCGC? register that\r
+// controls the deep-sleep-mode enable for that peripheral.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_pulDCGCregs) || defined(BUILD_ALL)\r
+const unsigned long g_pulDCGCRegs[] =\r
+{\r
+ SYSCTL_DCGC0,\r
+ SYSCTL_DCGC1,\r
+ SYSCTL_DCGC2\r
+};\r
+#else\r
+extern const unsigned long g_pulDCGCRegs[];\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// An array that maps the crystal number in RCC to a frequency.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_pulxtals) || defined(BUILD_ALL)\r
+const unsigned long g_pulXtals[] =\r
+{\r
+ 3579545,\r
+ 3686400,\r
+ 4000000,\r
+ 4096000,\r
+ 4915200,\r
+ 5000000,\r
+ 5120000,\r
+ 6000000,\r
+ 6144000,\r
+ 7372800,\r
+ 8000000,\r
+ 8192000\r
+};\r
+#else\r
+extern const unsigned long g_pulXtals[];\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Gets the size of the SRAM.\r
+//!\r
+//! This function determines the size of the SRAM on the Stellaris device.\r
+//!\r
+//! \return The total number of bytes of SRAM.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_sramsizeget) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+unsigned long\r
+SysCtlSRAMSizeGet(void)\r
+{\r
+ //\r
+ // Compute the size of the SRAM.\r
+ //\r
+ return(((HWREG(SYSCTL_DC0) & SYSCTL_DC0_SRAMSZ_MASK) >> 8) + 0x100);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Gets the size of the flash.\r
+//!\r
+//! This function determines the size of the flash on the Stellaris device.\r
+//!\r
+//! \return The total number of bytes of flash.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_flashsizeget) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+unsigned long\r
+SysCtlFlashSizeGet(void)\r
+{\r
+ //\r
+ // Compute the size of the flash.\r
+ //\r
+ return(((HWREG(SYSCTL_DC0) & SYSCTL_DC0_FLASHSZ_MASK) << 11) + 0x800);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Determines if a pin is present.\r
+//!\r
+//! \param ulPin is the pin in question.\r
+//!\r
+//! Determines if a particular pin is present in the device. The PWM, analog\r
+//! comparators, ADC, and timers have a varying number of pins across members\r
+//! of the Stellaris family; this will determine which are present on this\r
+//! device.\r
+//!\r
+//! The \b ulPin argument must be only one of the following values:\r
+//! \b SYSCTL_PIN_PWM0, \b SYSCTL_PIN_PWM1, \b SYSCTL_PIN_PWM2,\r
+//! \b SYSCTL_PIN_PWM3, \b SYSCTL_PIN_PWM4, \b SYSCTL_PIN_PWM5,\r
+//! \b SYSCTL_PIN_C0MINUS, \b SYSCTL_PIN_C0PLUS, \b SYSCTL_PIN_C0O,\r
+//! \b SYSCTL_PIN_C1MINUS, \b SYSCTL_PIN_C1PLUS, \b SYSCTL_PIN_C1O,\r
+//! \b SYSCTL_PIN_C2MINUS, \b SYSCTL_PIN_C2PLUS, \b SYSCTL_PIN_C2O,\r
+//! \b SYSCTL_PIN_ADC0, \b SYSCTL_PIN_ADC1, \b SYSCTL_PIN_ADC2,\r
+//! \b SYSCTL_PIN_ADC3, \b SYSCTL_PIN_ADC4, \b SYSCTL_PIN_ADC5,\r
+//! \b SYSCTL_PIN_ADC6, \b SYSCTL_PIN_ADC7, \b SYSCTL_PIN_CCP0,\r
+//! \b SYSCTL_PIN_CCP1, \b SYSCTL_PIN_CCP2, \b SYSCTL_PIN_CCP3,\r
+//! \b SYSCTL_PIN_CCP4, \b SYSCTL_PIN_CCP5, or \b SYSCTL_PIN_32KHZ.\r
+//!\r
+//! \return Returns \b true if the specified pin is present and \b false if it\r
+//! is not.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_pinpresent) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+tBoolean\r
+SysCtlPinPresent(unsigned long ulPin)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulPin == SYSCTL_PIN_PWM0) ||\r
+ (ulPin == SYSCTL_PIN_PWM1) ||\r
+ (ulPin == SYSCTL_PIN_PWM2) ||\r
+ (ulPin == SYSCTL_PIN_PWM3) ||\r
+ (ulPin == SYSCTL_PIN_PWM4) ||\r
+ (ulPin == SYSCTL_PIN_PWM5) ||\r
+ (ulPin == SYSCTL_PIN_C0MINUS) ||\r
+ (ulPin == SYSCTL_PIN_C0PLUS) ||\r
+ (ulPin == SYSCTL_PIN_C0O) ||\r
+ (ulPin == SYSCTL_PIN_C1MINUS) ||\r
+ (ulPin == SYSCTL_PIN_C1PLUS) ||\r
+ (ulPin == SYSCTL_PIN_C1O) ||\r
+ (ulPin == SYSCTL_PIN_C2MINUS) ||\r
+ (ulPin == SYSCTL_PIN_C2PLUS) ||\r
+ (ulPin == SYSCTL_PIN_C2O) ||\r
+ (ulPin == SYSCTL_PIN_ADC0) ||\r
+ (ulPin == SYSCTL_PIN_ADC1) ||\r
+ (ulPin == SYSCTL_PIN_ADC2) ||\r
+ (ulPin == SYSCTL_PIN_ADC3) ||\r
+ (ulPin == SYSCTL_PIN_ADC4) ||\r
+ (ulPin == SYSCTL_PIN_ADC5) ||\r
+ (ulPin == SYSCTL_PIN_ADC6) ||\r
+ (ulPin == SYSCTL_PIN_ADC7) ||\r
+ (ulPin == SYSCTL_PIN_CCP0) ||\r
+ (ulPin == SYSCTL_PIN_CCP1) ||\r
+ (ulPin == SYSCTL_PIN_CCP2) ||\r
+ (ulPin == SYSCTL_PIN_CCP3) ||\r
+ (ulPin == SYSCTL_PIN_CCP4) ||\r
+ (ulPin == SYSCTL_PIN_CCP5) ||\r
+ (ulPin == SYSCTL_PIN_32KHZ))\r
+\r
+ //\r
+ // Determine if this pin is present.\r
+ //\r
+ if(HWREG(SYSCTL_DC3) & ulPin)\r
+ {\r
+ return(true);\r
+ }\r
+ else\r
+ {\r
+ return(false);\r
+ }\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Determines if a peripheral is present.\r
+//!\r
+//! \param ulPeripheral is the peripheral in question.\r
+//!\r
+//! Determines if a particular peripheral is present in the device. Each\r
+//! member of the Stellaris family has a different peripheral set; this will\r
+//! determine which are present on this device.\r
+//!\r
+//! The \b ulPeripheral argument must be only one of the following values:\r
+//! \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_WDOG,\r
+//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_SSI,\r
+//! \b SYSCTL_PERIPH_QEI, \b SYSCTL_PERIPH_I2C, \b SYSCTL_PERIPH_TIMER0,\r
+//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_COMP0,\r
+//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_GPIOA,\r
+//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD,\r
+//! \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_MPU, \b SYSCTL_PERIPH_TEMP, or\r
+//! \b SYSCTL_PERIPH_PLL.\r
+//!\r
+//! \return Returns \b true if the specified peripheral is present and \b false\r
+//! if it is not.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_peripheralpresent) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+tBoolean\r
+SysCtlPeripheralPresent(unsigned long ulPeripheral)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulPeripheral == SYSCTL_PERIPH_PWM) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_ADC) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_WDOG) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_UART0) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_UART1) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_SSI) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_QEI) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_I2C) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_TIMER0) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_TIMER1) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_TIMER2) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_COMP0) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_COMP1) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_COMP2) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_GPIOA) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_GPIOB) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_GPIOC) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_GPIOD) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_GPIOE) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_MPU) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_TEMP) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_PLL));\r
+\r
+ //\r
+ // Read the correct DC register and determine if this peripheral exists.\r
+ //\r
+ if(HWREG(g_pulDCRegs[ulPeripheral >> 28]) & ulPeripheral & 0x0fffffff)\r
+ {\r
+ return(true);\r
+ }\r
+ else\r
+ {\r
+ return(false);\r
+ }\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Performs a software reset of a peripheral.\r
+//!\r
+//! \param ulPeripheral is the peripheral to reset.\r
+//!\r
+//! This function performs a software reset of the specified peripheral. An\r
+//! individual peripheral reset signal is asserted for a brief period and then\r
+//! deasserted, leaving the peripheral in a operating state but in its reset\r
+//! condition.\r
+//!\r
+//! The \b ulPeripheral argument must be only one of the following values:\r
+//! \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_WDOG,\r
+//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_SSI,\r
+//! \b SYSCTL_PERIPH_QEI, \b SYSCTL_PERIPH_I2C, \b SYSCTL_PERIPH_TIMER0,\r
+//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_COMP0,\r
+//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_GPIOA,\r
+//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, or\r
+//! \b SYSCTL_PERIPH_GPIOE.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_peripheralreset) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+SysCtlPeripheralReset(unsigned long ulPeripheral)\r
+{\r
+ volatile unsigned long ulDelay;\r
+\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulPeripheral == SYSCTL_PERIPH_PWM) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_ADC) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_WDOG) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_UART0) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_UART1) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_SSI) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_QEI) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_I2C) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_TIMER0) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_TIMER1) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_TIMER2) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_COMP0) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_COMP1) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_COMP2) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_GPIOA) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_GPIOB) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_GPIOC) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_GPIOD) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_GPIOE));\r
+\r
+ //\r
+ // Put the peripheral into the reset state.\r
+ //\r
+ HWREG(g_pulSRCRRegs[ulPeripheral >> 28]) |= ulPeripheral & 0x0fffffff;\r
+ \r
+ //\r
+ // Delay for a little bit.\r
+ //\r
+ for(ulDelay = 0; ulDelay < 16; ulDelay++)\r
+ {\r
+ }\r
+\r
+ //\r
+ // Take the peripheral out of the reset state.\r
+ //\r
+ HWREG(g_pulSRCRRegs[ulPeripheral >> 28]) &= ~(ulPeripheral);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Enables a peripheral.\r
+//!\r
+//! \param ulPeripheral is the peripheral to enable.\r
+//!\r
+//! Peripherals are enabled with this function. At power-up, all peripherals\r
+//! are disabled; they must be enabled in order to operate or respond to\r
+//! register reads/writes.\r
+//!\r
+//! The \b ulPeripheral argument must be only one of the following values:\r
+//! \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_WDOG,\r
+//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_SSI,\r
+//! \b SYSCTL_PERIPH_QEI, \b SYSCTL_PERIPH_I2C, \b SYSCTL_PERIPH_TIMER0,\r
+//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_COMP0,\r
+//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_GPIOA,\r
+//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, or\r
+//! \b SYSCTL_PERIPH_GPIOE.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_peripheralenable) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+SysCtlPeripheralEnable(unsigned long ulPeripheral)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulPeripheral == SYSCTL_PERIPH_PWM) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_ADC) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_WDOG) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_UART0) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_UART1) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_SSI) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_QEI) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_I2C) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_TIMER0) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_TIMER1) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_TIMER2) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_COMP0) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_COMP1) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_COMP2) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_GPIOA) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_GPIOB) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_GPIOC) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_GPIOD) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_GPIOE));\r
+\r
+ //\r
+ // Enable this peripheral.\r
+ //\r
+ HWREG(g_pulRCGCRegs[ulPeripheral >> 28]) |= ulPeripheral & 0x0fffffff;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Disables a peripheral.\r
+//!\r
+//! \param ulPeripheral is the peripheral to disable.\r
+//!\r
+//! Peripherals are disabled with this function. Once disabled, they will not\r
+//! operate or respond to register reads/writes.\r
+//!\r
+//! The \b ulPeripheral argument must be only one of the following values:\r
+//! \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_WDOG,\r
+//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_SSI,\r
+//! \b SYSCTL_PERIPH_QEI, \b SYSCTL_PERIPH_I2C, \b SYSCTL_PERIPH_TIMER0,\r
+//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_COMP0,\r
+//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_GPIOA,\r
+//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, or\r
+//! \b SYSCTL_PERIPH_GPIOE.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_peripheraldisable) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+SysCtlPeripheralDisable(unsigned long ulPeripheral)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulPeripheral == SYSCTL_PERIPH_PWM) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_ADC) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_WDOG) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_UART0) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_UART1) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_SSI) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_QEI) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_I2C) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_TIMER0) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_TIMER1) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_TIMER2) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_COMP0) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_COMP1) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_COMP2) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_GPIOA) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_GPIOB) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_GPIOC) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_GPIOD) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_GPIOE));\r
+\r
+ //\r
+ // Disable this peripheral.\r
+ //\r
+ HWREG(g_pulRCGCRegs[ulPeripheral >> 28]) &= ~(ulPeripheral & 0x0fffffff);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Enables a peripheral in sleep mode.\r
+//!\r
+//! \param ulPeripheral is the peripheral to enable in sleep mode.\r
+//!\r
+//! This function allows a peripheral to continue operating when the processor\r
+//! goes into sleep mode. Since the clocking configuration of the device does\r
+//! not change, any peripheral can safely continue operating while the\r
+//! processor is in sleep mode, and can therefore wake the processor from sleep\r
+//! mode.\r
+//!\r
+//! Sleep mode clocking of peripherals must be enabled via\r
+//! SysCtlPeripheralClockGating(); if disabled, the peripheral sleep mode\r
+//! configuration is maintained but has no effect when sleep mode is entered.\r
+//!\r
+//! The \b ulPeripheral argument must be only one of the following values:\r
+//! \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_WDOG,\r
+//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_SSI,\r
+//! \b SYSCTL_PERIPH_QEI, \b SYSCTL_PERIPH_I2C, \b SYSCTL_PERIPH_TIMER0,\r
+//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_COMP0,\r
+//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_GPIOA,\r
+//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, or\r
+//! \b SYSCTL_PERIPH_GPIOE.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_peripheralsleepenable) || defined(BUILD_ALL) || \\r
+ defined(DOXYGEN)\r
+void\r
+SysCtlPeripheralSleepEnable(unsigned long ulPeripheral)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulPeripheral == SYSCTL_PERIPH_PWM) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_ADC) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_WDOG) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_UART0) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_UART1) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_SSI) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_QEI) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_I2C) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_TIMER0) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_TIMER1) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_TIMER2) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_COMP0) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_COMP1) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_COMP2) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_GPIOA) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_GPIOB) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_GPIOC) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_GPIOD) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_GPIOE));\r
+\r
+ //\r
+ // Enable this peripheral in sleep mode.\r
+ //\r
+ HWREG(g_pulSCGCRegs[ulPeripheral >> 28]) |= ulPeripheral & 0x0fffffff;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Disables a peripheral in sleep mode.\r
+//!\r
+//! \param ulPeripheral is the peripheral to disable in sleep mode.\r
+//!\r
+//! This function causes a peripheral to stop operating when the processor goes\r
+//! into sleep mode. Disabling peripherals while in sleep mode helps to lower\r
+//! the current draw of the device. If enabled (via SysCtlPeripheralEnable()),\r
+//! the peripheral will automatically resume operation when the processor\r
+//! leaves sleep mode, maintaining its entire state from before sleep mode was\r
+//! entered.\r
+//!\r
+//! Sleep mode clocking of peripherals must be enabled via\r
+//! SysCtlPeripheralClockGating(); if disabled, the peripheral sleep mode\r
+//! configuration is maintained but has no effect when sleep mode is entered.\r
+//!\r
+//! The \b ulPeripheral argument must be only one of the following values:\r
+//! \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_WDOG,\r
+//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_SSI,\r
+//! \b SYSCTL_PERIPH_QEI, \b SYSCTL_PERIPH_I2C, \b SYSCTL_PERIPH_TIMER0,\r
+//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_COMP0,\r
+//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_GPIOA,\r
+//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, or\r
+//! \b SYSCTL_PERIPH_GPIOE.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_peripheralsleepdisable) || defined(BUILD_ALL) || \\r
+ defined(DOXYGEN)\r
+void\r
+SysCtlPeripheralSleepDisable(unsigned long ulPeripheral)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulPeripheral == SYSCTL_PERIPH_PWM) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_ADC) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_WDOG) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_UART0) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_UART1) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_SSI) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_QEI) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_I2C) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_TIMER0) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_TIMER1) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_TIMER2) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_COMP0) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_COMP1) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_COMP2) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_GPIOA) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_GPIOB) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_GPIOC) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_GPIOD) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_GPIOE));\r
+\r
+ //\r
+ // Disable this peripheral in sleep mode.\r
+ //\r
+ HWREG(g_pulSCGCRegs[ulPeripheral >> 28]) &= ~(ulPeripheral & 0x0fffffff);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Enables a peripheral in deep-sleep mode.\r
+//!\r
+//! \param ulPeripheral is the peripheral to enable in deep-sleep mode.\r
+//!\r
+//! This function allows a peripheral to continue operating when the processor\r
+//! goes into deep-sleep mode. Since the clocking configuration of the device\r
+//! may change, not all peripherals can safely continue operating while the\r
+//! processor is in sleep mode. Those that must run at a particular frequency\r
+//! (such as a UART) will not work as expected if the clock changes. It is the\r
+//! responsibility of the caller to make sensible choices.\r
+//!\r
+//! Deep-sleep mode clocking of peripherals must be enabled via\r
+//! SysCtlPeripheralClockGating(); if disabled, the peripheral deep-sleep mode\r
+//! configuration is maintained but has no effect when deep-sleep mode is\r
+//! entered.\r
+//!\r
+//! The \b ulPeripheral argument must be one of the following values:\r
+//! \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_WDOG,\r
+//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_SSI,\r
+//! \b SYSCTL_PERIPH_QEI, \b SYSCTL_PERIPH_I2C, \b SYSCTL_PERIPH_TIMER0,\r
+//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_COMP0,\r
+//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_GPIOA,\r
+//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, or\r
+//! \b SYSCTL_PERIPH_GPIOE.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_peripheraldeepsleepenable) || defined(BUILD_ALL) || \\r
+ defined(DOXYGEN)\r
+void\r
+SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulPeripheral == SYSCTL_PERIPH_PWM) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_ADC) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_WDOG) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_UART0) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_UART1) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_SSI) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_QEI) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_I2C) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_TIMER0) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_TIMER1) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_TIMER2) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_COMP0) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_COMP1) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_COMP2) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_GPIOA) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_GPIOB) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_GPIOC) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_GPIOD) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_GPIOE));\r
+\r
+ //\r
+ // Enable this peripheral in deep-sleep mode.\r
+ //\r
+ HWREG(g_pulDCGCRegs[ulPeripheral >> 28]) |= ulPeripheral & 0x0fffffff;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Disables a peripheral in deep-sleep mode.\r
+//!\r
+//! \param ulPeripheral is the peripheral to disable in deep-sleep mode.\r
+//!\r
+//! This function causes a peripheral to stop operating when the processor goes\r
+//! into deep-sleep mode. Disabling peripherals while in deep-sleep mode helps\r
+//! to lower the current draw of the device, and can keep peripherals that\r
+//! require a particular clock frequency from operating when the clock changes\r
+//! as a result of entering deep-sleep mode. If enabled (via\r
+//! SysCtlPeripheralEnable()), the peripheral will automatically resume\r
+//! operation when the processor leaves deep-sleep mode, maintaining its entire\r
+//! state from before deep-sleep mode was entered.\r
+//!\r
+//! Deep-sleep mode clocking of peripherals must be enabled via\r
+//! SysCtlPeripheralClockGating(); if disabled, the peripheral deep-sleep mode\r
+//! configuration is maintained but has no effect when deep-sleep mode is\r
+//! entered.\r
+//!\r
+//! The \b ulPeripheral argument must be one of the following values:\r
+//! \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_WDOG,\r
+//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_SSI,\r
+//! \b SYSCTL_PERIPH_QEI, \b SYSCTL_PERIPH_I2C, \b SYSCTL_PERIPH_TIMER0,\r
+//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_COMP0,\r
+//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_GPIOA,\r
+//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, or\r
+//! \b SYSCTL_PERIPH_GPIOE.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_peripheraldeepsleepdisable) || defined(BUILD_ALL) || \\r
+ defined(DOXYGEN)\r
+void\r
+SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulPeripheral == SYSCTL_PERIPH_PWM) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_ADC) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_WDOG) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_UART0) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_UART1) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_SSI) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_QEI) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_I2C) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_TIMER0) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_TIMER1) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_TIMER2) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_COMP0) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_COMP1) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_COMP2) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_GPIOA) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_GPIOB) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_GPIOC) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_GPIOD) ||\r
+ (ulPeripheral == SYSCTL_PERIPH_GPIOE));\r
+\r
+ //\r
+ // Disable this peripheral in deep-sleep mode.\r
+ //\r
+ HWREG(g_pulDCGCRegs[ulPeripheral >> 28]) &= ~(ulPeripheral & 0x0fffffff);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Controls peripheral clock gating in sleep and deep-sleep mode.\r
+//!\r
+//! \param bEnable is a boolean that is \b true if the sleep and deep-sleep\r
+//! peripheral configuration should be used and \b false if not.\r
+//!\r
+//! This function controls how peripherals are clocked when the processor goes\r
+//! into sleep or deep-sleep mode. By default, the peripherals are clocked the\r
+//! same as in run mode; if peripheral clock gating is enabled they are clocked\r
+//! according to the configuration set by SysCtlPeripheralSleepEnable(),\r
+//! SysCtlPeripheralSleepDisable(), SysCtlPeripheralDeepSleepEnable(), and\r
+//! SysCtlPeripheralDeepSleepDisable().\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_peripheralclockgating) || defined(BUILD_ALL) || \\r
+ defined(DOXYGEN)\r
+void\r
+SysCtlPeripheralClockGating(tBoolean bEnable)\r
+{\r
+ //\r
+ // Enable peripheral clock gating as requested.\r
+ //\r
+ if(bEnable)\r
+ {\r
+ HWREG(SYSCTL_RCC) |= SYSCTL_RCC_ACG;\r
+ }\r
+ else\r
+ {\r
+ HWREG(SYSCTL_RCC) &= ~(SYSCTL_RCC_ACG);\r
+ }\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Registers an interrupt handler for the system control interrupt.\r
+//!\r
+//! \param pfnHandler is a pointer to the function to be called when the system\r
+//! control interrupt occurs.\r
+//!\r
+//! This sets the handler to be called when a system control interrupt occurs.\r
+//! This will enable the global interrupt in the interrupt controller; specific\r
+//! system control interrupts must be enabled via SysCtlIntEnable(). It is the\r
+//! interrupt handler's responsibility to clear the interrupt source via\r
+//! SysCtlIntClear().\r
+//!\r
+//! System control can generate interrupts when the PLL achieves lock, if the\r
+//! internal LDO current limit is exceeded, if the internal oscillator fails,\r
+//! if the main oscillator fails, if the internal LDO output voltage droops too\r
+//! much, if the external voltage droops too much, or if the PLL fails.\r
+//!\r
+//! \sa IntRegister() for important information about registering interrupt\r
+//! handlers.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+SysCtlIntRegister(void (*pfnHandler)(void))\r
+{\r
+ //\r
+ // Register the interrupt handler, returning an error if an error occurs.\r
+ //\r
+ IntRegister(INT_SYSCTL, pfnHandler);\r
+\r
+ //\r
+ // Enable the system control interrupt.\r
+ //\r
+ IntEnable(INT_SYSCTL);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Unregisters the interrupt handler for the system control interrupt.\r
+//!\r
+//! This function will clear the handler to be called when a system control\r
+//! interrupt occurs. This will also mask off the interrupt in the interrupt\r
+//! controller so that the interrupt handler no longer is called.\r
+//!\r
+//! \sa IntRegister() for important information about registering interrupt\r
+//! handlers.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+SysCtlIntUnregister(void)\r
+{\r
+ //\r
+ // Disable the interrupt.\r
+ //\r
+ IntDisable(INT_SYSCTL);\r
+\r
+ //\r
+ // Unregister the interrupt handler.\r
+ //\r
+ IntUnregister(INT_SYSCTL);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Enables individual system control interrupt sources.\r
+//!\r
+//! \param ulInts is a bit mask of the interrupt sources to be enabled. Must\r
+//! be a logical OR of \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_CUR_LIMIT,\r
+//! \b SYSCTL_INT_IOSC_FAIL, \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_POR,\r
+//! \b SYSCTL_INT_BOR, and/or \b SYSCTL_INT_PLL_FAIL.\r
+//!\r
+//! Enables the indicated system control interrupt sources. Only the sources\r
+//! that are enabled can be reflected to the processor interrupt; disabled\r
+//! sources have no effect on the processor.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+SysCtlIntEnable(unsigned long ulInts)\r
+{\r
+ //\r
+ // Enable the specified interrupts.\r
+ //\r
+ HWREG(SYSCTL_IMC) |= ulInts;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Disables individual system control interrupt sources.\r
+//!\r
+//! \param ulInts is a bit mask of the interrupt sources to be disabled. Must\r
+//! be a logical OR of \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_CUR_LIMIT,\r
+//! \b SYSCTL_INT_IOSC_FAIL, \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_POR,\r
+//! \b SYSCTL_INT_BOR, and/or \b SYSCTL_INT_PLL_FAIL.\r
+//!\r
+//! Disables the indicated system control interrupt sources. Only the sources\r
+//! that are enabled can be reflected to the processor interrupt; disabled\r
+//! sources have no effect on the processor.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+SysCtlIntDisable(unsigned long ulInts)\r
+{\r
+ //\r
+ // Disable the specified interrupts.\r
+ //\r
+ HWREG(SYSCTL_IMC) &= ~(ulInts);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Clears system control interrupt sources.\r
+//!\r
+//! \param ulInts is a bit mask of the interrupt sources to be cleared. Must\r
+//! be a logical OR of \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_CUR_LIMIT,\r
+//! \b SYSCTL_INT_IOSC_FAIL, \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_POR,\r
+//! \b SYSCTL_INT_BOR, and/or \b SYSCTL_INT_PLL_FAIL.\r
+//!\r
+//! The specified system control interrupt sources are cleared, so that they no\r
+//! longer assert. This must be done in the interrupt handler to keep it from\r
+//! being called again immediately upon exit.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+SysCtlIntClear(unsigned long ulInts)\r
+{\r
+ //\r
+ // Clear the requested interrupt sources.\r
+ //\r
+ HWREG(SYSCTL_MISC) = ulInts;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Gets the current interrupt status.\r
+//!\r
+//! \param bMasked is false if the raw interrupt status is required and true if\r
+//! the masked interrupt status is required.\r
+//!\r
+//! This returns the interrupt status for the system controller. Either the\r
+//! raw interrupt status or the status of interrupts that are allowed to\r
+//! reflect to the processor can be returned.\r
+//!\r
+//! \return The current interrupt status, enumerated as a bit field of\r
+//! \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_CUR_LIMIT, \b SYSCTL_INT_IOSC_FAIL,\r
+//! \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_POR, \b SYSCTL_INT_BOR, and\r
+//! \b SYSCTL_INT_PLL_FAIL.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+unsigned long\r
+SysCtlIntStatus(tBoolean bMasked)\r
+{\r
+ //\r
+ // Return either the interrupt status or the raw interrupt status as\r
+ // requested.\r
+ //\r
+ if(bMasked)\r
+ {\r
+ return(HWREG(SYSCTL_MISC));\r
+ }\r
+ else\r
+ {\r
+ return(HWREG(SYSCTL_RIS));\r
+ }\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Sets the output voltage of the LDO.\r
+//!\r
+//! \param ulVoltage is the required output voltage from the LDO. Must be one\r
+//! of \b SYSCTL_LDO_2_25V, \b SYSCTL_LDO_2_30V, \b SYSCTL_LDO_2_35V,\r
+//! \b SYSCTL_LDO_2_40V, \b SYSCTL_LDO_2_45V, \b SYSCTL_LDO_2_50V,\r
+//! \b SYSCTL_LDO_2_55V, \b SYSCTL_LDO_2_60V, \b SYSCTL_LDO_2_65V,\r
+//! \b SYSCTL_LDO_2_70V, or \b SYSCTL_LDO_2_75V.\r
+//!\r
+//! This function sets the output voltage of the LDO. The default voltage is\r
+//! 2.5 V; it can be adjusted +/- 10%.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_ldoset) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+SysCtlLDOSet(unsigned long ulVoltage)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulVoltage == SYSCTL_LDO_2_25V) ||\r
+ (ulVoltage == SYSCTL_LDO_2_30V) ||\r
+ (ulVoltage == SYSCTL_LDO_2_35V) ||\r
+ (ulVoltage == SYSCTL_LDO_2_40V) ||\r
+ (ulVoltage == SYSCTL_LDO_2_45V) ||\r
+ (ulVoltage == SYSCTL_LDO_2_50V) ||\r
+ (ulVoltage == SYSCTL_LDO_2_55V) ||\r
+ (ulVoltage == SYSCTL_LDO_2_60V) ||\r
+ (ulVoltage == SYSCTL_LDO_2_65V) ||\r
+ (ulVoltage == SYSCTL_LDO_2_70V) ||\r
+ (ulVoltage == SYSCTL_LDO_2_75V));\r
+\r
+ //\r
+ // Set the LDO voltage to the requested value.\r
+ //\r
+ HWREG(SYSCTL_LDOPCTL) = ulVoltage;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Gets the output voltage of the LDO.\r
+//!\r
+//! This function determines the output voltage of the LDO, as specified by the\r
+//! control register.\r
+//!\r
+//! \return Returns the current voltage of the LDO; will be one of\r
+//! \b SYSCTL_LDO_2_25V, \b SYSCTL_LDO_2_30V, \b SYSCTL_LDO_2_35V,\r
+//! \b SYSCTL_LDO_2_40V, \b SYSCTL_LDO_2_45V, \b SYSCTL_LDO_2_50V,\r
+//! \b SYSCTL_LDO_2_55V, \b SYSCTL_LDO_2_60V, \b SYSCTL_LDO_2_65V,\r
+//! \b SYSCTL_LDO_2_70V, or \b SYSCTL_LDO_2_75V.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_ldoget) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+unsigned long\r
+SysCtlLDOGet(void)\r
+{\r
+ //\r
+ // Return the LDO voltage setting.\r
+ //\r
+ return(HWREG(SYSCTL_LDOPCTL));\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Configures the LDO failure control.\r
+//!\r
+//! \param ulConfig is the required LDO failure control setting; can be either\r
+//! \b SYSCTL_LDOCFG_ARST or \b SYSCTL_LDOCFG_NORST.\r
+//!\r
+//! This function allows the LDO to be configured to cause a processor reset\r
+//! when the output voltage becomes unregulated.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_ldoconfigset) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+SysCtlLDOConfigSet(unsigned long ulConfig)\r
+{\r
+ //\r
+ // Check hte arguments.\r
+ //\r
+ ASSERT((ulConfig == SYSCTL_LDOCFG_ARST) ||\r
+ (ulConfig == SYSCTL_LDOCFG_NORST));\r
+\r
+ //\r
+ // Set the reset control as requested.\r
+ //\r
+ HWREG(SYSCTL_LDOARST) = ulConfig;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Resets the device.\r
+//!\r
+//! This function will perform a software reset of the entire device. The\r
+//! processor and all peripherals will be reset and all device registers will\r
+//! return to their default values (with the exception of the reset cause\r
+//! register, which will maintain its current value but have the software reset\r
+//! bit set as well).\r
+//!\r
+//! \return This function does not return.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_reset) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+SysCtlReset(void)\r
+{\r
+ //\r
+ // Perform a software reset request. This will cause the device to reset,\r
+ // no further code will be executed.\r
+ //\r
+ HWREG(NVIC_APINT) = NVIC_APINT_VECTKEY | NVIC_APINT_SYSRESETREQ;\r
+\r
+ //\r
+ // The device should have reset, so this should never be reached. Just in\r
+ // case, loop forever.\r
+ //\r
+ while(1)\r
+ {\r
+ }\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Puts the processor into sleep mode.\r
+//!\r
+//! This function places the processor into sleep mode; it will not return\r
+//! until the processor returns to run mode. The peripherals that are enabled\r
+//! via SysCtlPeripheralSleepEnable() continue to operate and can wake up the\r
+//! processor (if automatic clock gating is enabled with\r
+//! SysCtlPeripheralClockGating(), otherwise all peripherals continue to\r
+//! operate).\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_sleep) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+SysCtlSleep(void)\r
+{\r
+ //\r
+ // Wait for an interrupt.\r
+ //\r
+ CPUwfi();\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Puts the processor into deep-sleep mode.\r
+//!\r
+//! This function places the processor into deep-sleep mode; it will not return\r
+//! until the processor returns to run mode. The peripherals that are enabled\r
+//! via SysCtlPeripheralDeepSleepEnable() continue to operate and can wake up\r
+//! the processor (if automatic clock gating is enabled with\r
+//! SysCtlPeripheralClockGating(), otherwise all peripherals continue to\r
+//! operate).\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_deepsleep) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+SysCtlDeepSleep(void)\r
+{\r
+ //\r
+ // Enable deep-sleep.\r
+ //\r
+ HWREG(NVIC_SYS_CTRL) |= NVIC_SYS_CTRL_SLEEPDEEP;\r
+\r
+ //\r
+ // Wait for an interrupt.\r
+ //\r
+ CPUwfi();\r
+\r
+ //\r
+ // Disable deep-sleep so that a future sleep will work correctly.\r
+ //\r
+ HWREG(NVIC_SYS_CTRL) &= ~(NVIC_SYS_CTRL_SLEEPDEEP);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Gets the reason for a reset.\r
+//!\r
+//! This function will return the reason(s) for a reset. Since the reset\r
+//! reasons are sticky until either cleared by software or an external reset,\r
+//! multiple reset reasons may be returned if multiple resets have occurred.\r
+//! The reset reason will be a logical OR of \b SYSCTL_CAUSE_LDO,\r
+//! \b SYSCTL_CAUSE_SW, \b SYSCTL_CAUSE_WDOG, \b SYSCTL_CAUSE_BOR,\r
+//! \b SYSCTL_CAUSE_POR, and/or \b SYSCTL_CAUSE_EXT.\r
+//!\r
+//! \return The reason(s) for a reset.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_resetcauseget) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+unsigned long\r
+SysCtlResetCauseGet(void)\r
+{\r
+ //\r
+ // Return the reset reasons.\r
+ //\r
+ return(HWREG(SYSCTL_RESC));\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Clears reset reasons.\r
+//!\r
+//! \param ulCauses are the reset causes to be cleared; must be a logical OR of\r
+//! \b SYSCTL_CAUSE_LDO, \b SYSCTL_CAUSE_SW, \b SYSCTL_CAUSE_WDOG,\r
+//! \b SYSCTL_CAUSE_BOR, \b SYSCTL_CAUSE_POR, and/or \b SYSCTL_CAUSE_EXT.\r
+//!\r
+//! This function clears the specified sticky reset reasons. Once cleared,\r
+//! another reset for the same reason can be detected, and a reset for a\r
+//! different reason can be distinguished (instead of having two reset causes\r
+//! set). If the reset reason is used by an application, all reset causes\r
+//! should be cleared after they are retrieved with SysCtlResetCauseGet().\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_resetcauseclear) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+SysCtlResetCauseClear(unsigned long ulCauses)\r
+{\r
+ //\r
+ // Clear the given reset reasons.\r
+ //\r
+ HWREG(SYSCTL_RESC) &= ~(ulCauses);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Configures the brown-out control.\r
+//!\r
+//! \param ulConfig is the desired configuration of the brown-out control.\r
+//! Must be the logical OR of \b SYSCTL_BOR_RESET and/or\r
+//! \b SYSCTL_BOR_RESAMPLE.\r
+//! \param ulDelay is the number of internal oscillator cycles to wait before\r
+//! resampling an asserted brown-out signal. This value only has meaning when\r
+//! \b SYSCTL_BOR_RESAMPLE is set and must be less than 8192.\r
+//!\r
+//! This function configures how the brown-out control operates. It can detect\r
+//! a brown-out by looking at only the brown-out output, or it can wait for it\r
+//! to be active for two consecutive samples separated by a configurable time.\r
+//! When it detects a brown-out condition, it can either reset the device or\r
+//! generate a processor interrupt.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_brownoutconfigset) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+SysCtlBrownOutConfigSet(unsigned long ulConfig, unsigned long ulDelay)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(!(ulConfig & ~(SYSCTL_BOR_RESET | SYSCTL_BOR_RESAMPLE)));\r
+ ASSERT(ulDelay < 8192);\r
+\r
+ //\r
+ // Configure the brown-out reset control.\r
+ //\r
+ HWREG(SYSCTL_PBORCTL) = (ulDelay << SYSCTL_PBORCTL_BOR_SH) | ulConfig;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Sets the clocking of the device.\r
+//!\r
+//! \param ulConfig is the required configuration of the device clocking.\r
+//!\r
+//! This function configures the clocking of the device. The input crystal\r
+//! frequency, oscillator to be used, use of the PLL, and the system clock\r
+//! divider are all configured with this function.\r
+//!\r
+//! The \b ulConfig parameter is the logical OR of several different values,\r
+//! many of which are grouped into sets where only one can be chosen.\r
+//!\r
+//! The system clock divider is chosen with one of the following values:\r
+//! \b SYSCTL_SYSDIV_1, \b SYSCTL_SYSDIV_2, \b SYSCTL_SYSDIV_3,\r
+//! \b SYSCTL_SYSDIV_4, \b SYSCTL_SYSDIV_5, \b SYSCTL_SYSDIV_6,\r
+//! \b SYSCTL_SYSDIV_7, \b SYSCTL_SYSDIV_8, \b SYSCTL_SYSDIV_9,\r
+//! \b SYSCTL_SYSDIV_10, \b SYSCTL_SYSDIV_11, \b SYSCTL_SYSDIV_12,\r
+//! \b SYSCTL_SYSDIV_13, \b SYSCTL_SYSDIV_14, \b SYSCTL_SYSDIV_15, or\r
+//! \b SYSCTL_SYSDIV_16.\r
+//!\r
+//! The use of the PLL is chosen with either \b SYSCTL_USE_PLL or\r
+//! \b SYSCTL_USE_OSC.\r
+//!\r
+//! The external crystal frequency is chosen with one of the following values:\r
+//! \b SYSCTL_XTAL_3_57MHZ, \b SYSCTL_XTAL_3_68MHZ, \b SYSCTL_XTAL_4MHZ,\r
+//! \b SYSCTL_XTAL_4_09MHZ, \b SYSCTL_XTAL_4_91MHZ, \b SYSCTL_XTAL_5MHZ,\r
+//! \b SYSCTL_XTAL_5_12MHZ, \b SYSCTL_XTAL_6MHZ, \b SYSCTL_XTAL_6_14MHZ,\r
+//! \b SYSCTL_XTAL_7_37MHZ, \b SYSCTL_XTAL_8MHZ, or \b SYSCTL_XTAL_8_19MHZ.\r
+//!\r
+//! The oscillator source is chosen with one of the following values:\r
+//! \b SYSCTL_OSC_MAIN, \b SYSCTL_OSC_INT, or \b SYSCTL_OSC_INT4.\r
+//!\r
+//! The internal and main oscillators are disabled with the\r
+//! \b SYSCTL_INT_OSC_DIS and \b SYSCTL_MAIN_OSC_DIS flags, respectively.\r
+//! The external oscillator must be enabled in order to use an external clock\r
+//! source. Note that attempts to disable the oscillator used to clock the\r
+//! device will be prevented by the hardware.\r
+//!\r
+//! To clock the system from an external source (such as an external crystal\r
+//! oscillator), use \b SYSCTL_USE_OSC \b | \b SYSCTL_OSC_MAIN. To clock the\r
+//! system from the main oscillator, use \b SYSCTL_USE_OSC \b |\r
+//! \b SYSCTL_OSC_MAIN. To clock the system from the PLL, use\r
+//! \b SYSCTL_USE_PLL \b | \b SYSCTL_OSC_MAIN, and select the appropriate\r
+//! crystal with one of the \b SYSCTL_XTAL_xxx values.\r
+//!\r
+//! \note If selecting the PLL as the system clock source (i.e. via\r
+//! \b SYSCTL_USE_PLL), this function will poll the PLL lock interrupt to\r
+//! determine when the PLL has locked. If an interrupt handler for the\r
+//! system control interrupt is in place, and it responds to and clears the\r
+//! PLL lock interrupt, this function will delay until its timeout has occurred\r
+//! instead of completing as soon as PLL lock is achieved.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_clockset) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+SysCtlClockSet(unsigned long ulConfig)\r
+{\r
+ volatile unsigned long ulDelay;\r
+ unsigned long ulRCC;\r
+\r
+ //\r
+ // Get the current value of the RCC register.\r
+ //\r
+ ulRCC = HWREG(SYSCTL_RCC);\r
+\r
+ //\r
+ // Bypass the PLL and system clock dividers for now.\r
+ //\r
+ ulRCC |= SYSCTL_RCC_BYPASS;\r
+ ulRCC &= ~(SYSCTL_RCC_USE_SYSDIV);\r
+\r
+ //\r
+ // Write the new RCC value.\r
+ //\r
+ HWREG(SYSCTL_RCC) = ulRCC;\r
+\r
+ //\r
+ // Make sure that the PLL and system clock dividers are bypassed for now.\r
+ //\r
+ ulRCC |= SYSCTL_RCC_BYPASS;\r
+ ulRCC &= ~(SYSCTL_RCC_USE_SYSDIV);\r
+\r
+ //\r
+ // Make sure that the required oscillators are enabled. For now, the\r
+ // previously enabled oscillators must be enabled along with the newly\r
+ // requested oscillators.\r
+ //\r
+ ulRCC &= (~(SYSCTL_RCC_IOSCDIS | SYSCTL_RCC_MOSCDIS) |\r
+ (ulConfig & (SYSCTL_RCC_IOSCDIS | SYSCTL_RCC_MOSCDIS)));\r
+\r
+ //\r
+ // Set the new crystal value, oscillator source, and PLL configuration.\r
+ //\r
+ ulRCC &= ~(SYSCTL_RCC_XTAL_MASK | SYSCTL_RCC_OSCSRC_MASK |\r
+ SYSCTL_RCC_PWRDN | SYSCTL_RCC_OE);\r
+ ulRCC |= ulConfig & (SYSCTL_RCC_XTAL_MASK | SYSCTL_RCC_OSCSRC_MASK |\r
+ SYSCTL_RCC_PWRDN | SYSCTL_RCC_OE);\r
+\r
+ //\r
+ // Clear the PLL lock interrupt.\r
+ //\r
+ HWREG(SYSCTL_MISC) = SYSCTL_INT_PLL_LOCK;\r
+\r
+ //\r
+ // Write the new RCC value.\r
+ //\r
+ HWREG(SYSCTL_RCC) = ulRCC;\r
+\r
+ //\r
+ // Wait for a bit so that new crystal value and oscillator source can take\r
+ // effect. One of the oscillators may need to be started as well.\r
+ //\r
+ for(ulDelay = 0; ulDelay < 16; ulDelay++)\r
+ {\r
+ }\r
+\r
+ //\r
+ // Disable the appropriate oscillators.\r
+ //\r
+ ulRCC &= ~(SYSCTL_RCC_IOSCDIS | SYSCTL_RCC_MOSCDIS);\r
+ ulRCC |= ulConfig & (SYSCTL_RCC_IOSCDIS | SYSCTL_RCC_MOSCDIS);\r
+\r
+ //\r
+ // Write the new RCC value.\r
+ //\r
+ HWREG(SYSCTL_RCC) = ulRCC;\r
+\r
+ //\r
+ // Set the requested system divider. This will not get written\r
+ // immediately.\r
+ //\r
+ ulRCC &= ~(SYSCTL_RCC_SYSDIV_MASK | SYSCTL_RCC_USE_SYSDIV);\r
+ ulRCC |= ulConfig & (SYSCTL_RCC_SYSDIV_MASK | SYSCTL_RCC_USE_SYSDIV);\r
+\r
+ //\r
+ // See if the PLL output is being used to clock the system.\r
+ //\r
+ if(!(ulConfig & SYSCTL_RCC_BYPASS))\r
+ {\r
+ //\r
+ // Wait until the PLL has locked.\r
+ //\r
+ for(ulDelay = 32768; ulDelay > 0; ulDelay--)\r
+ {\r
+ if(HWREG(SYSCTL_RIS) & SYSCTL_INT_PLL_LOCK)\r
+ {\r
+ break;\r
+ }\r
+ }\r
+\r
+ //\r
+ // Enable use of the PLL.\r
+ //\r
+ ulRCC &= ~(SYSCTL_RCC_BYPASS);\r
+ }\r
+\r
+ //\r
+ // Write the final RCC value.\r
+ //\r
+ HWREG(SYSCTL_RCC) = ulRCC;\r
+\r
+ //\r
+ // Delay for a little bit so that the system divider takes effect.\r
+ //\r
+ for(ulDelay = 0; ulDelay < 16; ulDelay++)\r
+ {\r
+ }\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Gets the processor clock rate.\r
+//!\r
+//! This function determines the clock rate of the processor clock. This is\r
+//! also the clock rate of all the peripheral modules (with the exception of\r
+//! PWM, which has its own clock divider).\r
+//!\r
+//! \note This will not return accurate results if SysCtlClockSet() has not\r
+//! been called to configure the clocking of the device, or if the device is\r
+//! directly clocked from a crystal (or a clock source) that is not one of the\r
+//! supported crystal frequencies. In the later case, this function should be\r
+//! modified to directly return the correct system clock rate.\r
+//!\r
+//! \return The processor clock rate.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_clockget) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+unsigned long\r
+SysCtlClockGet(void)\r
+{\r
+ unsigned long ulRCC, ulPLL, ulClk;\r
+\r
+ //\r
+ // Read RCC.\r
+ //\r
+ ulRCC = HWREG(SYSCTL_RCC);\r
+\r
+ //\r
+ // Get the base clock rate.\r
+ //\r
+ switch(ulRCC & SYSCTL_RCC_OSCSRC_MASK)\r
+ {\r
+ //\r
+ // The main oscillator is the clock source. Determine its rate from\r
+ // the crystal setting field.\r
+ //\r
+ case SYSCTL_RCC_OSCSRC_MAIN:\r
+ {\r
+ ulClk = g_pulXtals[((ulRCC & SYSCTL_RCC_XTAL_MASK) >>\r
+ SYSCTL_RCC_XTAL_SHIFT) -\r
+ (SYSCTL_RCC_XTAL_3_57MHZ >>\r
+ SYSCTL_RCC_XTAL_SHIFT)];\r
+ break;\r
+ }\r
+\r
+ //\r
+ // The internal oscillator is the source clock. This is not an\r
+ // accurate clock (it is +/- 50%); what is used is the nominal.\r
+ //\r
+ case SYSCTL_RCC_OSCSRC_INT:\r
+ {\r
+ ulClk = 15000000;\r
+ break;\r
+ }\r
+\r
+ //\r
+ // The internal oscillator divided by four is the source clock. This\r
+ // is not an accurate clock (it is +/- 50%); what is used is the\r
+ // nominal.\r
+ //\r
+ case SYSCTL_RCC_OSCSRC_INT4:\r
+ {\r
+ ulClk = 15000000 / 4;\r
+ break;\r
+ }\r
+\r
+ //\r
+ // An unknown setting, so return a zero clock (i.e. an unknown clock\r
+ // rate).\r
+ //\r
+ default:\r
+ {\r
+ return(0);\r
+ }\r
+ }\r
+\r
+ //\r
+ // See if the PLL is being used.\r
+ //\r
+ if(!(ulRCC & SYSCTL_RCC_BYPASS))\r
+ {\r
+ //\r
+ // Get the PLL configuration.\r
+ //\r
+ ulPLL = HWREG(SYSCTL_PLLCFG);\r
+\r
+ //\r
+ // Compute the PLL output frequency based on its input frequency.\r
+ //\r
+ ulClk = ((ulClk * (((ulPLL & SYSCTL_PLLCFG_F_MASK) >>\r
+ SYSCTL_PLLCFG_F_SHIFT) + 2)) /\r
+ (((ulPLL & SYSCTL_PLLCFG_R_MASK) >>\r
+ SYSCTL_PLLCFG_R_SHIFT) + 2));\r
+\r
+ //\r
+ // See if the optional output divide by 2 is being used.\r
+ //\r
+ if(ulPLL & SYSCTL_PLLCFG_OD_2)\r
+ {\r
+ ulClk /= 2;\r
+ }\r
+\r
+ //\r
+ // See if the optional output divide by 4 is being used.\r
+ //\r
+ if(ulPLL & SYSCTL_PLLCFG_OD_4)\r
+ {\r
+ ulClk /= 4;\r
+ }\r
+ }\r
+\r
+ //\r
+ // See if the system divider is being used.\r
+ //\r
+ if(ulRCC & SYSCTL_RCC_USE_SYSDIV)\r
+ {\r
+ //\r
+ // Adjust the clock rate by the system clock divider.\r
+ //\r
+ ulClk /= ((ulRCC & SYSCTL_RCC_SYSDIV_MASK) >>\r
+ SYSCTL_RCC_SYSDIV_SHIFT) + 1;\r
+ }\r
+\r
+ //\r
+ // Return the computed clock rate.\r
+ //\r
+ return(ulClk);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Sets the PWM clock configuration.\r
+//!\r
+//! \param ulConfig is the configuration for the PWM clock; it must be one of\r
+//! \b SYSCTL_PWMDIV_1, \b SYSCTL_PWMDIV_2, \b SYSCTL_PWMDIV_4,\r
+//! \b SYSCTL_PWMDIV_8, \b SYSCTL_PWMDIV_16, \b SYSCTL_PWMDIV_32, or\r
+//! \b SYSCTL_PWMDIV_64.\r
+//!\r
+//! This function sets the rate of the clock provided to the PWM module as a\r
+//! ratio of the processor clock. This clock is used by the PWM module to\r
+//! generate PWM signals; its rate forms the basis for all PWM signals.\r
+//!\r
+//! \note The clocking of the PWM is dependent upon the system clock rate as\r
+//! configured by SysCtlClockSet().\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_pwmclockset) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+SysCtlPWMClockSet(unsigned long ulConfig)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulConfig == SYSCTL_PWMDIV_1) ||\r
+ (ulConfig == SYSCTL_PWMDIV_2) ||\r
+ (ulConfig == SYSCTL_PWMDIV_4) ||\r
+ (ulConfig == SYSCTL_PWMDIV_8) ||\r
+ (ulConfig == SYSCTL_PWMDIV_16) ||\r
+ (ulConfig == SYSCTL_PWMDIV_32) ||\r
+ (ulConfig == SYSCTL_PWMDIV_64));\r
+\r
+ //\r
+ // Check that there is a PWM block on this part.\r
+ //\r
+ ASSERT(HWREG(SYSCTL_DC1) & SYSCTL_DC1_PWM);\r
+\r
+ //\r
+ // Set the PWM clock configuration into the run-mode clock configuration\r
+ // register.\r
+ //\r
+ HWREG(SYSCTL_RCC) = ((HWREG(SYSCTL_RCC) &\r
+ ~(SYSCTL_RCC_USE_PWMDIV | SYSCTL_RCC_PWMDIV_MASK)) |\r
+ ulConfig);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Gets the current PWM clock configuration.\r
+//!\r
+//! This function returns the current PWM clock configuration.\r
+//!\r
+//! \return The current PWM clock configuration; will be one of\r
+//! \b SYSCTL_PWMDIV_1, \b SYSCTL_PWMDIV_2, \b SYSCTL_PWMDIV_4,\r
+//! \b SYSCTL_PWMDIV_8, \b SYSCTL_PWMDIV_16, \b SYSCTL_PWMDIV_32, or\r
+//! \b SYSCTL_PWMDIV_64.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_pwmclockget) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+unsigned long\r
+SysCtlPWMClockGet(void)\r
+{\r
+ //\r
+ // Check that there is a PWM block on this part.\r
+ //\r
+ ASSERT(HWREG(SYSCTL_DC1) & SYSCTL_DC1_PWM);\r
+\r
+ //\r
+ // Return the current PWM clock configuration.\r
+ //\r
+ return(HWREG(SYSCTL_RCC) &\r
+ (SYSCTL_RCC_USE_PWMDIV | SYSCTL_RCC_PWMDIV_MASK));\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Sets the sample rate of the ADC.\r
+//!\r
+//! \param ulSpeed is the desired sample rate of the ADC; must be one of\r
+//! \b SYSCTL_ADCSPEED_1MSPS, \b SYSCTL_ADCSPEED_500KSPS,\r
+//! \b SYSCTL_ADCSPEED_250KSPS, or \b SYSCTL_ADCSPEED_125KSPS.\r
+//!\r
+//! This function sets the rate at which the ADC samples are captured by the\r
+//! ADC block. The sampling speed may be limited by the hardware, so the\r
+//! sample rate may end up being slower than requested. SysCtlADCSpeedGet()\r
+//! will return the actual speed in use.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_adcspeedset) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+SysCtlADCSpeedSet(unsigned long ulSpeed)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulSpeed == SYSCTL_ADCSPEED_1MSPS) ||\r
+ (ulSpeed == SYSCTL_ADCSPEED_500KSPS) ||\r
+ (ulSpeed == SYSCTL_ADCSPEED_250KSPS) ||\r
+ (ulSpeed == SYSCTL_ADCSPEED_125KSPS));\r
+\r
+ //\r
+ // Check that there is an ADC block on this part.\r
+ //\r
+ ASSERT(HWREG(SYSCTL_DC1) & SYSCTL_DC1_ADC);\r
+\r
+ //\r
+ // Set the ADC speed in run, sleep, and deep-sleep mode.\r
+ //\r
+ HWREG(SYSCTL_RCGC0) = ((HWREG(SYSCTL_RCGC0) & ~(SYSCTL_SET0_ADCSPD_MASK)) |\r
+ ulSpeed);\r
+ HWREG(SYSCTL_SCGC0) = ((HWREG(SYSCTL_SCGC0) & ~(SYSCTL_SET0_ADCSPD_MASK)) |\r
+ ulSpeed);\r
+ HWREG(SYSCTL_DCGC0) = ((HWREG(SYSCTL_DCGC0) & ~(SYSCTL_SET0_ADCSPD_MASK)) |\r
+ ulSpeed);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Gets the sample rate of the ADC.\r
+//!\r
+//! This function gets the current sample rate of the ADC.\r
+//!\r
+//! \return Returns the current ADC sample rate; will be one of\r
+//! \b SYSCTL_ADCSPEED_1MSPS, \b SYSCTL_ADCSPEED_500KSPS,\r
+//! \b SYSCTL_ADCSPEED_250KSPS, or \b SYSCTL_ADCSPEED_125KSPS.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_adcspeedget) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+unsigned long\r
+SysCtlADCSpeedGet(void)\r
+{\r
+ //\r
+ // Check that there is an ADC block on this part.\r
+ //\r
+ ASSERT(HWREG(SYSCTL_DC1) & SYSCTL_DC1_ADC);\r
+\r
+ //\r
+ // Return the current ADC speed.\r
+ //\r
+ return(HWREG(SYSCTL_RCGC0) & SYSCTL_SET0_ADCSPD_MASK);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Configures the internal oscillator verification timer.\r
+//!\r
+//! \param bEnable is a boolean that is \b true if the internal oscillator\r
+//! verification timer should be enabled.\r
+//!\r
+//! This function allows the internal oscillator verification timer to be\r
+//! enabled or disabled. When enabled, an interrupt will be generated if the\r
+//! internal oscillator ceases to operate.\r
+//!\r
+//! \note Both oscillators (main and internal) must be enabled for this\r
+//! verification timer to operate as the main oscillator will verify the\r
+//! internal oscillator.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_boscverificationset) || defined(BUILD_ALL) || \\r
+ defined(DOXYGEN)\r
+void\r
+SysCtlIOSCVerificationSet(tBoolean bEnable)\r
+{\r
+ //\r
+ // Enable or disable the internal oscillator verification timer as\r
+ // requested.\r
+ //\r
+ if(bEnable)\r
+ {\r
+ HWREG(SYSCTL_RCC) |= SYSCTL_RCC_IOSCVER;\r
+ }\r
+ else\r
+ {\r
+ HWREG(SYSCTL_RCC) &= ~(SYSCTL_RCC_IOSCVER);\r
+ }\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Configures the main oscillator verification timer.\r
+//!\r
+//! \param bEnable is a boolean that is \b true if the main oscillator\r
+//! verification timer should be enabled.\r
+//!\r
+//! This function allows the main oscillator verification timer to be enabled\r
+//! or disabled. When enabled, an interrupt will be generated if the main\r
+//! oscillator ceases to operate.\r
+//!\r
+//! \note Both oscillators (main and internal) must be enabled for this\r
+//! verification timer to operate as the internal oscillator will verify the\r
+//! main oscillator.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_moscverificationset) || defined(BUILD_ALL) || \\r
+ defined(DOXYGEN)\r
+void\r
+SysCtlMOSCVerificationSet(tBoolean bEnable)\r
+{\r
+ //\r
+ // Enable or disable the main oscillator verification timer as requested.\r
+ //\r
+ if(bEnable)\r
+ {\r
+ HWREG(SYSCTL_RCC) |= SYSCTL_RCC_MOSCVER;\r
+ }\r
+ else\r
+ {\r
+ HWREG(SYSCTL_RCC) &= ~(SYSCTL_RCC_MOSCVER);\r
+ }\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Configures the PLL verification timer.\r
+//!\r
+//! \param bEnable is a boolean that is \b true if the PLL verification timer\r
+//! should be enabled.\r
+//!\r
+//! This function allows the PLL verification timer to be enabled or disabled.\r
+//! When enabled, an interrupt will be generated if the PLL ceases to operate.\r
+//!\r
+//! \note The main oscillator must be enabled for this verification timer to\r
+//! operate as it is used to check the PLL. Also, the verification timer\r
+//! should be disabled while the PLL is being reconfigured via\r
+//! SysCtlClockSet().\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_pllverificationset) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+SysCtlPLLVerificationSet(tBoolean bEnable)\r
+{\r
+ //\r
+ // Enable or disable the PLL verification timer as requested.\r
+ //\r
+ if(bEnable)\r
+ {\r
+ HWREG(SYSCTL_RCC) |= SYSCTL_RCC_PLLVER;\r
+ }\r
+ else\r
+ {\r
+ HWREG(SYSCTL_RCC) &= ~(SYSCTL_RCC_PLLVER);\r
+ }\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Clears the clock verification status.\r
+//!\r
+//! This function clears the status of the clock verification timers, allowing\r
+//! them to assert another failure if detected.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_clkverificationclear) || defined(BUILD_ALL) || \\r
+ defined(DOXYGEN)\r
+void\r
+SysCtlClkVerificationClear(void)\r
+{\r
+ //\r
+ // Clear the clock verification.\r
+ //\r
+ HWREG(SYSCTL_CLKVCLR) = SYSCTL_CLKVCLR_CLR;\r
+\r
+ //\r
+ // The bit does not self-reset, so clear it.\r
+ //\r
+ HWREG(SYSCTL_CLKVCLR) = 0;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Close the Doxygen group.\r
+//! @}\r
+//\r
+//*****************************************************************************\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// sysctl.h - Prototypes for the system control driver.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 991 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __SYSCTL_H__\r
+#define __SYSCTL_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the\r
+// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(),\r
+// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the\r
+// ulPeripheral parameter. The peripherals in the fourth group (upper nibble\r
+// is 3) can only be used with the SysCtlPeripheralPresent() API.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_PERIPH_PWM 0x00100000 // PWM\r
+#define SYSCTL_PERIPH_ADC 0x00010000 // ADC\r
+#define SYSCTL_PERIPH_WDOG 0x00000008 // Watchdog\r
+#define SYSCTL_PERIPH_UART0 0x10000001 // UART 0\r
+#define SYSCTL_PERIPH_UART1 0x10000002 // UART 1\r
+#define SYSCTL_PERIPH_SSI 0x10000010 // SSI\r
+#define SYSCTL_PERIPH_QEI 0x10000100 // QEI\r
+#define SYSCTL_PERIPH_I2C 0x10001000 // I2C\r
+#define SYSCTL_PERIPH_TIMER0 0x10010000 // Timer 0\r
+#define SYSCTL_PERIPH_TIMER1 0x10020000 // Timer 1\r
+#define SYSCTL_PERIPH_TIMER2 0x10040000 // Timer 2\r
+#define SYSCTL_PERIPH_COMP0 0x11000000 // Analog comparator 0\r
+#define SYSCTL_PERIPH_COMP1 0x12000000 // Analog comparator 1\r
+#define SYSCTL_PERIPH_COMP2 0x14000000 // Analog comparator 2\r
+#define SYSCTL_PERIPH_GPIOA 0x20000001 // GPIO A\r
+#define SYSCTL_PERIPH_GPIOB 0x20000002 // GPIO B\r
+#define SYSCTL_PERIPH_GPIOC 0x20000004 // GPIO C\r
+#define SYSCTL_PERIPH_GPIOD 0x20000008 // GPIO D\r
+#define SYSCTL_PERIPH_GPIOE 0x20000010 // GPIO E\r
+#define SYSCTL_PERIPH_MPU 0x30000080 // Cortex M3 MPU\r
+#define SYSCTL_PERIPH_TEMP 0x30000020 // Temperature sensor\r
+#define SYSCTL_PERIPH_PLL 0x30000010 // PLL\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlPinPresent() API\r
+// as the ulPin parameter.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_PIN_PWM0 0x00000001 // PWM0 pin\r
+#define SYSCTL_PIN_PWM1 0x00000002 // PWM1 pin\r
+#define SYSCTL_PIN_PWM2 0x00000004 // PWM2 pin\r
+#define SYSCTL_PIN_PWM3 0x00000008 // PWM3 pin\r
+#define SYSCTL_PIN_PWM4 0x00000010 // PWM4 pin\r
+#define SYSCTL_PIN_PWM5 0x00000020 // PWM5 pin\r
+#define SYSCTL_PIN_C0MINUS 0x00000040 // C0- pin\r
+#define SYSCTL_PIN_C0PLUS 0x00000080 // C0+ pin\r
+#define SYSCTL_PIN_C0O 0x00000100 // C0o pin\r
+#define SYSCTL_PIN_C1MINUS 0x00000200 // C1- pin\r
+#define SYSCTL_PIN_C1PLUS 0x00000400 // C1+ pin\r
+#define SYSCTL_PIN_C1O 0x00000800 // C1o pin\r
+#define SYSCTL_PIN_C2MINUS 0x00001000 // C2- pin\r
+#define SYSCTL_PIN_C2PLUS 0x00002000 // C2+ pin\r
+#define SYSCTL_PIN_C2O 0x00004000 // C2o pin\r
+#define SYSCTL_PIN_ADC0 0x00010000 // ADC0 pin\r
+#define SYSCTL_PIN_ADC1 0x00020000 // ADC1 pin\r
+#define SYSCTL_PIN_ADC2 0x00040000 // ADC2 pin\r
+#define SYSCTL_PIN_ADC3 0x00080000 // ADC3 pin\r
+#define SYSCTL_PIN_ADC4 0x00100000 // ADC4 pin\r
+#define SYSCTL_PIN_ADC5 0x00200000 // ADC5 pin\r
+#define SYSCTL_PIN_ADC6 0x00400000 // ADC6 pin\r
+#define SYSCTL_PIN_ADC7 0x00800000 // ADC7 pin\r
+#define SYSCTL_PIN_CCP0 0x01000000 // CCP0 pin\r
+#define SYSCTL_PIN_CCP1 0x02000000 // CCP1 pin\r
+#define SYSCTL_PIN_CCP2 0x04000000 // CCP2 pin\r
+#define SYSCTL_PIN_CCP3 0x08000000 // CCP3 pin\r
+#define SYSCTL_PIN_CCP4 0x10000000 // CCP4 pin\r
+#define SYSCTL_PIN_CCP5 0x20000000 // CCP5 pin\r
+#define SYSCTL_PIN_32KHZ 0x80000000 // 32kHz pin\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlLDOSet() API as\r
+// the ulVoltage value, or returned by the SysCtlLDOGet() API.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_LDO_2_25V 0x00000005 // LDO output of 2.25V\r
+#define SYSCTL_LDO_2_30V 0x00000004 // LDO output of 2.30V\r
+#define SYSCTL_LDO_2_35V 0x00000003 // LDO output of 2.35V\r
+#define SYSCTL_LDO_2_40V 0x00000002 // LDO output of 2.40V\r
+#define SYSCTL_LDO_2_45V 0x00000001 // LDO output of 2.45V\r
+#define SYSCTL_LDO_2_50V 0x00000000 // LDO output of 2.50V\r
+#define SYSCTL_LDO_2_55V 0x0000001f // LDO output of 2.55V\r
+#define SYSCTL_LDO_2_60V 0x0000001e // LDO output of 2.60V\r
+#define SYSCTL_LDO_2_65V 0x0000001d // LDO output of 2.65V\r
+#define SYSCTL_LDO_2_70V 0x0000001c // LDO output of 2.70V\r
+#define SYSCTL_LDO_2_75V 0x0000001b // LDO output of 2.75V\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlLDOConfigSet() API.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_LDOCFG_ARST 0x00000001 // Allow LDO failure to reset\r
+#define SYSCTL_LDOCFG_NORST 0x00000000 // Do not reset on LDO failure\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlIntEnable(),\r
+// SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask\r
+// by the SysCtlIntStatus() API.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt\r
+#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt\r
+#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int\r
+#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int\r
+#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt\r
+#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt\r
+#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlResetCauseClear()\r
+// API or returned by the SysCtlResetCauseGet() API.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_CAUSE_LDO 0x00000020 // LDO power not OK reset\r
+#define SYSCTL_CAUSE_SW 0x00000010 // Software reset\r
+#define SYSCTL_CAUSE_WDOG 0x00000008 // Watchdog reset\r
+#define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset\r
+#define SYSCTL_CAUSE_POR 0x00000002 // Power on reset\r
+#define SYSCTL_CAUSE_EXT 0x00000001 // External reset\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlBrownOutConfigSet()\r
+// API as the ulConfig parameter.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_BOR_RESET 0x00000002 // Reset instead of interrupting\r
+#define SYSCTL_BOR_RESAMPLE 0x00000001 // Resample BOR before asserting\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlPWMClockSet() API\r
+// as the ulConfig parameter, and can be returned by the SysCtlPWMClockGet()\r
+// API.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_PWMDIV_1 0x00000000 // PWM clock is processor clock /1\r
+#define SYSCTL_PWMDIV_2 0x00100000 // PWM clock is processor clock /2\r
+#define SYSCTL_PWMDIV_4 0x00120000 // PWM clock is processor clock /4\r
+#define SYSCTL_PWMDIV_8 0x00140000 // PWM clock is processor clock /8\r
+#define SYSCTL_PWMDIV_16 0x00160000 // PWM clock is processor clock /16\r
+#define SYSCTL_PWMDIV_32 0x00180000 // PWM clock is processor clock /32\r
+#define SYSCTL_PWMDIV_64 0x001A0000 // PWM clock is processor clock /64\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlADCSpeedSet() API\r
+// as the ulSpeed parameter, and can be returned by the SyCtlADCSpeedGet()\r
+// API.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_ADCSPEED_1MSPS 0x00000300 // 1,000,000 samples per second\r
+#define SYSCTL_ADCSPEED_500KSPS 0x00000200 // 500,000 samples per second\r
+#define SYSCTL_ADCSPEED_250KSPS 0x00000100 // 250,000 samples per second\r
+#define SYSCTL_ADCSPEED_125KSPS 0x00000000 // 125,000 samples per second\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlClockSet() API as\r
+// the ulConfig parameter.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_SYSDIV_1 0x07800000 // Processor clock is osc/pll /1\r
+#define SYSCTL_SYSDIV_2 0x00C00000 // Processor clock is osc/pll /2\r
+#define SYSCTL_SYSDIV_3 0x01400000 // Processor clock is osc/pll /3\r
+#define SYSCTL_SYSDIV_4 0x01C00000 // Processor clock is osc/pll /4\r
+#define SYSCTL_SYSDIV_5 0x02400000 // Processor clock is osc/pll /5\r
+#define SYSCTL_SYSDIV_6 0x02C00000 // Processor clock is osc/pll /6\r
+#define SYSCTL_SYSDIV_7 0x03400000 // Processor clock is osc/pll /7\r
+#define SYSCTL_SYSDIV_8 0x03C00000 // Processor clock is osc/pll /8\r
+#define SYSCTL_SYSDIV_9 0x04400000 // Processor clock is osc/pll /9\r
+#define SYSCTL_SYSDIV_10 0x04C00000 // Processor clock is osc/pll /10\r
+#define SYSCTL_SYSDIV_11 0x05400000 // Processor clock is osc/pll /11\r
+#define SYSCTL_SYSDIV_12 0x05C00000 // Processor clock is osc/pll /12\r
+#define SYSCTL_SYSDIV_13 0x06400000 // Processor clock is osc/pll /13\r
+#define SYSCTL_SYSDIV_14 0x06C00000 // Processor clock is osc/pll /14\r
+#define SYSCTL_SYSDIV_15 0x07400000 // Processor clock is osc/pll /15\r
+#define SYSCTL_SYSDIV_16 0x07C00000 // Processor clock is osc/pll /16\r
+#define SYSCTL_USE_PLL 0x00000000 // System clock is the PLL clock\r
+#define SYSCTL_USE_OSC 0x00003800 // System clock is the osc clock\r
+#define SYSCTL_XTAL_3_57MHZ 0x00000100 // External crystal is 3.579545MHz\r
+#define SYSCTL_XTAL_3_68MHZ 0x00000140 // External crystal is 3.6864MHz\r
+#define SYSCTL_XTAL_4MHZ 0x00000180 // External crystal is 4MHz\r
+#define SYSCTL_XTAL_4_09MHZ 0x000001C0 // External crystal is 4.096MHz\r
+#define SYSCTL_XTAL_4_91MHZ 0x00000200 // External crystal is 4.9152MHz\r
+#define SYSCTL_XTAL_5MHZ 0x00000240 // External crystal is 5MHz\r
+#define SYSCTL_XTAL_5_12MHZ 0x00000280 // External crystal is 5.12MHz\r
+#define SYSCTL_XTAL_6MHZ 0x000002C0 // External crystal is 6MHz\r
+#define SYSCTL_XTAL_6_14MHZ 0x00000300 // External crystal is 6.144MHz\r
+#define SYSCTL_XTAL_7_37MHZ 0x00000340 // External crystal is 7.3728MHz\r
+#define SYSCTL_XTAL_8MHZ 0x00000380 // External crystal is 8MHz\r
+#define SYSCTL_XTAL_8_19MHZ 0x000003C0 // External crystal is 8.192MHz\r
+#define SYSCTL_OSC_MAIN 0x00000000 // Oscillator source is main osc\r
+#define SYSCTL_OSC_INT 0x00000010 // Oscillator source is int. osc\r
+#define SYSCTL_OSC_INT4 0x00000020 // Oscillator source is int. osc /4\r
+#define SYSCTL_INT_OSC_DIS 0x00000002 // Disable internal oscillator\r
+#define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern unsigned long SysCtlSRAMSizeGet(void);\r
+extern unsigned long SysCtlFlashSizeGet(void);\r
+extern tBoolean SysCtlPinPresent(unsigned long ulPin);\r
+extern tBoolean SysCtlPeripheralPresent(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralReset(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralEnable(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralDisable(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralSleepEnable(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralSleepDisable(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralClockGating(tBoolean bEnable);\r
+extern void SysCtlIntRegister(void (*pfnHandler)(void));\r
+extern void SysCtlIntUnregister(void);\r
+extern void SysCtlIntEnable(unsigned long ulInts);\r
+extern void SysCtlIntDisable(unsigned long ulInts);\r
+extern void SysCtlIntClear(unsigned long ulInts);\r
+extern unsigned long SysCtlIntStatus(tBoolean bMasked);\r
+extern void SysCtlLDOSet(unsigned long ulVoltage);\r
+extern unsigned long SysCtlLDOGet(void);\r
+extern void SysCtlLDOConfigSet(unsigned long ulConfig);\r
+extern void SysCtlReset(void);\r
+extern void SysCtlSleep(void);\r
+extern void SysCtlDeepSleep(void);\r
+extern unsigned long SysCtlResetCauseGet(void);\r
+extern void SysCtlResetCauseClear(unsigned long ulCauses);\r
+extern void SysCtlBrownOutConfigSet(unsigned long ulConfig,\r
+ unsigned long ulDelay);\r
+extern void SysCtlClockSet(unsigned long ulConfig);\r
+extern unsigned long SysCtlClockGet(void);\r
+extern void SysCtlPWMClockSet(unsigned long ulConfig);\r
+extern unsigned long SysCtlPWMClockGet(void);\r
+extern void SysCtlADCSpeedSet(unsigned long ulSpeed);\r
+extern unsigned long SysCtlADCSpeedGet(void);\r
+extern void SysCtlIOSCVerificationSet(tBoolean bEnable);\r
+extern void SysCtlMOSCVerificationSet(tBoolean bEnable);\r
+extern void SysCtlPLLVerificationSet(tBoolean bEnable);\r
+extern void SysCtlClkVerificationClear(void);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __SYSCTL_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// systick.c - Driver for the SysTick timer in NVIC.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 991 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \addtogroup systick_api\r
+//! @{\r
+//\r
+//*****************************************************************************\r
+\r
+#include "../hw_ints.h"\r
+#include "../hw_nvic.h"\r
+#include "../hw_types.h"\r
+#include "debug.h"\r
+#include "interrupt.h"\r
+#include "systick.h"\r
+\r
+//*****************************************************************************\r
+//\r
+//! Enables the SysTick counter.\r
+//!\r
+//! This will start the SysTick counter. If an interrupt handler has been\r
+//! registered, it will be called when the SysTick counter rolls over.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_enable) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+SysTickEnable(void)\r
+{\r
+ //\r
+ // Enable SysTick.\r
+ //\r
+ HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_CLK_SRC | NVIC_ST_CTRL_ENABLE;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Disables the SysTick counter.\r
+//!\r
+//! This will stop the SysTick counter. If an interrupt handler has been\r
+//! registered, it will no longer be called until SysTick is restarted.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_disable) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+SysTickDisable(void)\r
+{\r
+ //\r
+ // Disable SysTick.\r
+ //\r
+ HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_ENABLE);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Registers an interrupt handler for the SysTick interrupt.\r
+//!\r
+//! \param pfnHandler is a pointer to the function to be called when the\r
+//! SysTick interrupt occurs.\r
+//!\r
+//! This sets the handler to be called when a SysTick interrupt occurs.\r
+//!\r
+//! \sa IntRegister() for important information about registering interrupt\r
+//! handlers.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+SysTickIntRegister(void (*pfnHandler)(void))\r
+{\r
+ //\r
+ // Register the interrupt handler, returning an error if an error occurs.\r
+ //\r
+ IntRegister(FAULT_SYSTICK, pfnHandler);\r
+\r
+ //\r
+ // Enable the SysTick interrupt.\r
+ //\r
+ HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Unregisters the interrupt handler for the SysTick interrupt.\r
+//!\r
+//! This function will clear the handler to be called when a SysTick interrupt\r
+//! occurs.\r
+//!\r
+//! \sa IntRegister() for important information about registering interrupt\r
+//! handlers.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+SysTickIntUnregister(void)\r
+{\r
+ //\r
+ // Disable the SysTick interrupt.\r
+ //\r
+ HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN);\r
+\r
+ //\r
+ // Unregister the interrupt handler.\r
+ //\r
+ IntUnregister(FAULT_SYSTICK);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Enables the SysTick interrupt.\r
+//!\r
+//! This function will enable the SysTick interrupt, allowing it to be\r
+//! reflected to the processor.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+SysTickIntEnable(void)\r
+{\r
+ //\r
+ // Enable the SysTick interrupt.\r
+ //\r
+ HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Disables the SysTick interrupt.\r
+//!\r
+//! This function will disable the SysTick interrupt, preventing it from being\r
+//! reflected to the processor.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+SysTickIntDisable(void)\r
+{\r
+ //\r
+ // Disable the SysTick interrupt.\r
+ //\r
+ HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Sets the period of the SysTick counter.\r
+//!\r
+//! \param ulPeriod is the number of clock ticks in each period of the SysTick\r
+//! counter; must be between 1 and 16,777,216, inclusive.\r
+//!\r
+//! This function sets the rate at which the SysTick counter wraps; this\r
+//! equates to the number of processor clocks between interrupts.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_periodset) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+SysTickPeriodSet(unsigned long ulPeriod)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulPeriod > 0) && (ulPeriod <= 16777216));\r
+\r
+ //\r
+ // Set the period of the SysTick counter.\r
+ //\r
+ HWREG(NVIC_ST_RELOAD) = ulPeriod - 1;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Gets the period of the SysTick counter.\r
+//!\r
+//! This function returns the rate at which the SysTick counter wraps; this\r
+//! equates to the number of processor clocks between interrupts.\r
+//!\r
+//! \return Returns the period of the SysTick counter.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_periodget) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+unsigned long\r
+SysTickPeriodGet(void)\r
+{\r
+ //\r
+ // Return the period of the SysTick counter.\r
+ //\r
+ return(HWREG(NVIC_ST_RELOAD) + 1);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Gets the current value of the SysTick counter.\r
+//!\r
+//! This function returns the current value of the SysTick counter; this will\r
+//! be a value between the period - 1 and zero, inclusive.\r
+//!\r
+//! \return Returns the current value of the SysTick counter.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_valueget) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+unsigned long\r
+SysTickValueGet(void)\r
+{\r
+ //\r
+ // Return the current value of the SysTick counter.\r
+ //\r
+ return(HWREG(NVIC_ST_CURRENT));\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Close the Doxygen group.\r
+//! @}\r
+//\r
+//*****************************************************************************\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// systick.h - Prototypes for the SysTick driver.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 991 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __SYSTICK_H__\r
+#define __SYSTICK_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void SysTickEnable(void);\r
+extern void SysTickDisable(void);\r
+extern void SysTickIntRegister(void (*pfnHandler)(void));\r
+extern void SysTickIntUnregister(void);\r
+extern void SysTickIntEnable(void);\r
+extern void SysTickIntDisable(void);\r
+extern void SysTickPeriodSet(unsigned long ulPeriod);\r
+extern unsigned long SysTickPeriodGet(void);\r
+extern unsigned long SysTickValueGet(void);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __SYSTICK_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// timer.c - Driver for the timer module.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 991 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \addtogroup timer_api\r
+//! @{\r
+//\r
+//*****************************************************************************\r
+\r
+#include "../hw_ints.h"\r
+#include "../hw_memmap.h"\r
+#include "../hw_timer.h"\r
+#include "../hw_types.h"\r
+#include "debug.h"\r
+#include "interrupt.h"\r
+#include "timer.h"\r
+\r
+//*****************************************************************************\r
+//\r
+//! Enables the timer(s).\r
+//!\r
+//! \param ulBase is the base address of the timer module.\r
+//! \param ulTimer specifies the timer(s) to enable; must be one of \b TIMER_A,\r
+//! \b TIMER_B, or \b TIMER_BOTH.\r
+//!\r
+//! This will enable operation of the timer module. The timer must be\r
+//! configured before it is enabled.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_enable) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+TimerEnable(unsigned long ulBase, unsigned long ulTimer)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) ||\r
+ (ulBase == TIMER2_BASE));\r
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||\r
+ (ulTimer == TIMER_BOTH));\r
+\r
+ //\r
+ // Enable the timer(s) module.\r
+ //\r
+ HWREG(ulBase + TIMER_O_CTL) |= ulTimer & (TIMER_CTL_TAEN | TIMER_CTL_TBEN);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Disables the timer(s).\r
+//!\r
+//! \param ulBase is the base address of the timer module.\r
+//! \param ulTimer specifies the timer(s) to disable; must be one of\r
+//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH.\r
+//!\r
+//! This will disable operation of the timer module.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_disable) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+TimerDisable(unsigned long ulBase, unsigned long ulTimer)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) ||\r
+ (ulBase == TIMER2_BASE));\r
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||\r
+ (ulTimer == TIMER_BOTH));\r
+\r
+ //\r
+ // Disable the timer module.\r
+ //\r
+ HWREG(ulBase + TIMER_O_CTL) &= ~(ulTimer &\r
+ (TIMER_CTL_TAEN | TIMER_CTL_TBEN));\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Configures the timer(s).\r
+//!\r
+//! \param ulBase is the base address of the timer module.\r
+//! \param ulConfig is the configuration for the timer.\r
+//!\r
+//! This function configures the operating mode of the timer(s). The timer\r
+//! module is disabled before being configured, and is left in the disabled\r
+//! state. The configuration is specified in \e ulConfig as one of the\r
+//! following values:\r
+//!\r
+//! - \b TIMER_CFG_32_BIT_OS - 32-bit one shot timer\r
+//! - \b TIMER_CFG_32_BIT_PER - 32-bit periodic timer\r
+//! - \b TIMER_CFG_32_RTC - 32-bit real time clock timer\r
+//! - \b TIMER_CFG_16_BIT_PAIR - Two 16-bit timers\r
+//!\r
+//! When configured for a pair of 16-bit timers, each timer is separately\r
+//! configured. The first timer is configured by setting \e ulConfig to\r
+//! the result of a logical OR operation between one of the following values\r
+//! and \e ulConfig:\r
+//!\r
+//! - \b TIMER_CFG_A_ONE_SHOT - 16-bit one shot timer\r
+//! - \b TIMER_CFG_A_PERIODIC - 16-bit periodic timer\r
+//! - \b TIMER_CFG_A_CAP_COUNT - 16-bit edge count capture\r
+//! - \b TIMER_CFG_A_CAP_TIME - 16-bit edge time capture\r
+//! - \b TIMER_CFG_A_PWM - 16-bit PWM output\r
+//!\r
+//! Similarly, the second timer is configured by setting \e ulConfig to\r
+//! the result of a logical OR operation between one of the corresponding\r
+//! \b TIMER_CFG_B_* values and \e ulConfig.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_configure) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+TimerConfigure(unsigned long ulBase, unsigned long ulConfig)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) ||\r
+ (ulBase == TIMER2_BASE));\r
+ ASSERT((ulConfig == TIMER_CFG_32_BIT_OS) ||\r
+ (ulConfig == TIMER_CFG_32_BIT_PER) ||\r
+ (ulConfig == TIMER_CFG_32_RTC) ||\r
+ ((ulConfig & 0xff000000) == TIMER_CFG_16_BIT_PAIR));\r
+ ASSERT(((ulConfig & 0xff000000) != TIMER_CFG_16_BIT_PAIR) ||\r
+ ((((ulConfig & 0x000000ff) == TIMER_CFG_A_ONE_SHOT) ||\r
+ ((ulConfig & 0x000000ff) == TIMER_CFG_A_PERIODIC) ||\r
+ ((ulConfig & 0x000000ff) == TIMER_CFG_A_CAP_COUNT) ||\r
+ ((ulConfig & 0x000000ff) == TIMER_CFG_A_CAP_TIME) ||\r
+ ((ulConfig & 0x000000ff) == TIMER_CFG_A_PWM)) &&\r
+ (((ulConfig & 0x0000ff00) == TIMER_CFG_B_ONE_SHOT) ||\r
+ ((ulConfig & 0x0000ff00) == TIMER_CFG_B_PERIODIC) ||\r
+ ((ulConfig & 0x0000ff00) == TIMER_CFG_B_CAP_COUNT) ||\r
+ ((ulConfig & 0x0000ff00) == TIMER_CFG_B_CAP_TIME) ||\r
+ ((ulConfig & 0x0000ff00) == TIMER_CFG_B_PWM))));\r
+\r
+ //\r
+ // Disable the timers.\r
+ //\r
+ HWREG(ulBase + TIMER_O_CTL) &= ~(TIMER_CTL_TAEN | TIMER_CTL_TBEN);\r
+\r
+ //\r
+ // Set the global timer configuration.\r
+ //\r
+ HWREG(ulBase + TIMER_O_CFG) = ulConfig >> 24;\r
+\r
+ //\r
+ // Set the configuration of the A and B timers. Note that the B timer\r
+ // configuration is ignored by the hardware in 32-bit modes.\r
+ //\r
+ HWREG(ulBase + TIMER_O_TAMR) = ulConfig & 255;\r
+ HWREG(ulBase + TIMER_O_TBMR) = (ulConfig >> 8) & 255;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Controls the output level.\r
+//!\r
+//! \param ulBase is the base address of the timer module.\r
+//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A,\r
+//! \b TIMER_B, or \b TIMER_BOTH.\r
+//! \param bInvert specifies the output level.\r
+//!\r
+//! This function sets the PWM output level for the specified timer. If the\r
+//! parameter \e bInvert is \b true, then the timer's output will be made\r
+//! active low; otherwise, it will be made active high.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_controllevel) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+TimerControlLevel(unsigned long ulBase, unsigned long ulTimer,\r
+ tBoolean bInvert)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) ||\r
+ (ulBase == TIMER2_BASE));\r
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||\r
+ (ulTimer == TIMER_BOTH));\r
+\r
+ //\r
+ // Set the output levels as requested.\r
+ //\r
+ ulTimer &= TIMER_CTL_TAPWML | TIMER_CTL_TBPWML;\r
+ HWREG(ulBase + TIMER_O_CTL) = (bInvert ?\r
+ (HWREG(ulBase + TIMER_O_CTL) | ulTimer) :\r
+ (HWREG(ulBase + TIMER_O_CTL) & ~(ulTimer)));\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Enables or disables the trigger output.\r
+//!\r
+//! \param ulBase is the base address of the timer module.\r
+//! \param ulTimer specifies the timer to adjust; must be one of \b TIMER_A,\r
+//! \b TIMER_B, or \b TIMER_BOTH.\r
+//! \param bEnable specifies the desired trigger state.\r
+//!\r
+//! This function controls the trigger output for the specified timer. If the\r
+//! parameter \e bEnable is \b true, then the timer's output trigger is\r
+//! enabled; otherwise it is disabled.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_controltrigger) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer,\r
+ tBoolean bEnable)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) ||\r
+ (ulBase == TIMER2_BASE));\r
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||\r
+ (ulTimer == TIMER_BOTH));\r
+\r
+ //\r
+ // Set the trigger output as requested.\r
+ //\r
+ ulTimer &= TIMER_CTL_TAOTE | TIMER_CTL_TBOTE;\r
+ HWREG(ulBase + TIMER_O_CTL) = (bEnable ?\r
+ (HWREG(ulBase + TIMER_O_CTL) | ulTimer) :\r
+ (HWREG(ulBase + TIMER_O_CTL) & ~(ulTimer)));\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Controls the event type.\r
+//!\r
+//! \param ulBase is the base address of the timer module.\r
+//! \param ulTimer specifies the timer(s) to be adjusted; must be one of\r
+//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH.\r
+//! \param ulEvent specifies the type of event; must be one of\r
+//! \b TIMER_EVENT_POS_EDGE, \b TIMER_EVENT_NEG_EDGE, or\r
+//! \b TIMER_EVENT_BOTH_EDGES.\r
+//!\r
+//! This function sets the signal edge(s) that will trigger the timer when in\r
+//! capture mode.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_controlevent) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+TimerControlEvent(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulEvent)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) ||\r
+ (ulBase == TIMER2_BASE));\r
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||\r
+ (ulTimer == TIMER_BOTH));\r
+\r
+ //\r
+ // Set the event type.\r
+ //\r
+ ulEvent &= ulTimer & (TIMER_CTL_TAEVENT_MSK | TIMER_CTL_TBEVENT_MSK);\r
+ HWREG(ulBase + TIMER_O_CTL) = ((HWREG(ulBase + TIMER_O_CTL) &\r
+ ~(TIMER_CTL_TAEVENT_MSK |\r
+ TIMER_CTL_TBEVENT_MSK)) | ulEvent);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Controls the stall handling.\r
+//!\r
+//! \param ulBase is the base address of the timer module.\r
+//! \param ulTimer specifies the timer(s) to be adjusted; must be one of\r
+//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH.\r
+//! \param bStall specifies the response to a stall signal.\r
+//!\r
+//! This function controls the stall response for the specified timer. If the\r
+//! parameter \e bStall is \b true, then the timer will stop counting if the\r
+//! processor enters debug mode; otherwise the timer will keep running while in\r
+//! debug mode.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_controlstall) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+TimerControlStall(unsigned long ulBase, unsigned long ulTimer,\r
+ tBoolean bStall)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) ||\r
+ (ulBase == TIMER2_BASE));\r
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||\r
+ (ulTimer == TIMER_BOTH));\r
+\r
+ //\r
+ // Set the stall mode.\r
+ //\r
+ ulTimer &= TIMER_CTL_TASTALL | TIMER_CTL_TBSTALL;\r
+ HWREG(ulBase + TIMER_O_CTL) = (bStall ?\r
+ (HWREG(ulBase + TIMER_O_CTL) | ulTimer) :\r
+ (HWREG(ulBase + TIMER_O_CTL) & ~(ulTimer)));\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Enable RTC counting.\r
+//!\r
+//! \param ulBase is the base address of the timer module.\r
+//!\r
+//! This function causes the timer to start counting when in RTC mode. If not\r
+//! configured for RTC mode, this will do nothing.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_rtcenable) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+TimerRTCEnable(unsigned long ulBase)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) ||\r
+ (ulBase == TIMER2_BASE));\r
+\r
+ //\r
+ // Enable RTC counting.\r
+ //\r
+ HWREG(ulBase + TIMER_O_CTL) |= TIMER_CTL_RTCEN;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Disable RTC counting.\r
+//!\r
+//! \param ulBase is the base address of the timer module.\r
+//!\r
+//! This function causes the timer to stop counting when in RTC mode.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_rtcdisable) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+TimerRTCDisable(unsigned long ulBase)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) ||\r
+ (ulBase == TIMER2_BASE));\r
+\r
+ //\r
+ // Disable RTC counting.\r
+ //\r
+ HWREG(ulBase + TIMER_O_CTL) &= ~(TIMER_CTL_RTCEN);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Set the timer prescale value.\r
+//!\r
+//! \param ulBase is the base address of the timer module.\r
+//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A,\r
+//! \b TIMER_B, or \b TIMER_BOTH.\r
+//! \param ulValue is the timer prescale value; must be between 0 and 255,\r
+//! inclusive.\r
+//!\r
+//! This function sets the value of the input clock prescaler. The prescaler\r
+//! is only operational when in 16-bit mode and is used to extend the range of\r
+//! the 16-bit timer modes.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_prescaleset) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulValue)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) ||\r
+ (ulBase == TIMER2_BASE));\r
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||\r
+ (ulTimer == TIMER_BOTH));\r
+ ASSERT(ulValue < 256);\r
+\r
+ //\r
+ // Set the timer A prescaler if requested.\r
+ //\r
+ if(ulTimer & TIMER_A)\r
+ {\r
+ HWREG(ulBase + TIMER_O_TAPR) = ulValue;\r
+ }\r
+\r
+ //\r
+ // Set the timer B prescaler if requested.\r
+ //\r
+ if(ulTimer & TIMER_B)\r
+ {\r
+ HWREG(ulBase + TIMER_O_TBPR) = ulValue;\r
+ }\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Get the timer prescale value.\r
+//!\r
+//! \param ulBase is the base address of the timer module.\r
+//! \param ulTimer specifies the timer; must be one of \b TIMER_A or\r
+//! \b TIMER_B.\r
+//!\r
+//! This function gets the value of the input clock prescaler. The prescaler\r
+//! is only operational when in 16-bit mode and is used to extend the range of\r
+//! the 16-bit timer modes.\r
+//!\r
+//! \return The value of the timer prescaler.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_prescaleget) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+unsigned long\r
+TimerPrescaleGet(unsigned long ulBase, unsigned long ulTimer)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) ||\r
+ (ulBase == TIMER2_BASE));\r
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||\r
+ (ulTimer == TIMER_BOTH));\r
+\r
+ //\r
+ // Return the appropriate prescale value.\r
+ //\r
+ return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAPR) :\r
+ HWREG(ulBase + TIMER_O_TBPR));\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Set the timer prescale match value.\r
+//!\r
+//! \param ulBase is the base address of the timer module.\r
+//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A,\r
+//! \b TIMER_B, or \b TIMER_BOTH.\r
+//! \param ulValue is the timer prescale match value; must be between 0 and\r
+//! 255, inclusive.\r
+//!\r
+//! This function sets the value of the input clock prescaler match value.\r
+//! When in a 16-bit mode that uses the counter match (edge count or PWM), the\r
+//! prescale match effectively extends the range of the counter to 24-bits.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_prescalematchset) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulValue)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) ||\r
+ (ulBase == TIMER2_BASE));\r
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||\r
+ (ulTimer == TIMER_BOTH));\r
+ ASSERT(ulValue < 256);\r
+\r
+ //\r
+ // Set the timer A prescale match if requested.\r
+ //\r
+ if(ulTimer & TIMER_A)\r
+ {\r
+ HWREG(ulBase + TIMER_O_TAPMR) = ulValue;\r
+ }\r
+\r
+ //\r
+ // Set the timer B prescale match if requested.\r
+ //\r
+ if(ulTimer & TIMER_B)\r
+ {\r
+ HWREG(ulBase + TIMER_O_TBPMR) = ulValue;\r
+ }\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Get the timer prescale match value.\r
+//!\r
+//! \param ulBase is the base address of the timer module.\r
+//! \param ulTimer specifies the timer; must be one of \b TIMER_A or\r
+//! \b TIMER_B.\r
+//!\r
+//! This function gets the value of the input clock prescaler match value.\r
+//! When in a 16-bit mode that uses the counter match (edge count or PWM), the\r
+//! prescale match effectively extends the range of the counter to 24-bits.\r
+//!\r
+//! \return The value of the timer prescale match.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_prescalematchget) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+unsigned long\r
+TimerPrescaleMatchGet(unsigned long ulBase, unsigned long ulTimer)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) ||\r
+ (ulBase == TIMER2_BASE));\r
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||\r
+ (ulTimer == TIMER_BOTH));\r
+\r
+ //\r
+ // Return the appropriate prescale match value.\r
+ //\r
+ return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAPMR) :\r
+ HWREG(ulBase + TIMER_O_TBPMR));\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Sets the timer load value.\r
+//!\r
+//! \param ulBase is the base address of the timer module.\r
+//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A,\r
+//! \b TIMER_B, or \b TIMER_BOTH. Only \b TIMER_A should be used when the\r
+//! timer is configured for 32-bit operation.\r
+//! \param ulValue is the load value.\r
+//!\r
+//! This function sets the timer load value; if the timer is running then the\r
+//! value will be immediately loaded into the timer.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_loadset) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+TimerLoadSet(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulValue)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) ||\r
+ (ulBase == TIMER2_BASE));\r
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||\r
+ (ulTimer == TIMER_BOTH));\r
+\r
+ //\r
+ // Set the timer A load value if requested.\r
+ //\r
+ if(ulTimer & TIMER_A)\r
+ {\r
+ HWREG(ulBase + TIMER_O_TAILR) = ulValue;\r
+ }\r
+\r
+ //\r
+ // Set the timer B load value if requested.\r
+ //\r
+ if(ulTimer & TIMER_B)\r
+ {\r
+ HWREG(ulBase + TIMER_O_TBILR) = ulValue;\r
+ }\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Gets the timer load value.\r
+//!\r
+//! \param ulBase is the base address of the timer module.\r
+//! \param ulTimer specifies the timer; must be one of \b TIMER_A or\r
+//! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured\r
+//! for 32-bit operation.\r
+//!\r
+//! This function gets the currently programmed interval load value for the\r
+//! specified timer.\r
+//!\r
+//! \return Returns the load value for the timer.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_loadget) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+unsigned long\r
+TimerLoadGet(unsigned long ulBase, unsigned long ulTimer)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) ||\r
+ (ulBase == TIMER2_BASE));\r
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B));\r
+\r
+ //\r
+ // Return the appropriate load value.\r
+ //\r
+ return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAILR) :\r
+ HWREG(ulBase + TIMER_O_TBILR));\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Gets the current timer value.\r
+//!\r
+//! \param ulBase is the base address of the timer module.\r
+//! \param ulTimer specifies the timer; must be one of \b TIMER_A or\r
+//! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured\r
+//! for 32-bit operation.\r
+//!\r
+//! This function reads the current value of the specified timer.\r
+//!\r
+//! \return Returns the current value of the timer.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_valueget) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+unsigned long\r
+TimerValueGet(unsigned long ulBase, unsigned long ulTimer)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) ||\r
+ (ulBase == TIMER2_BASE));\r
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B));\r
+\r
+ //\r
+ // Return the appropriate timer value.\r
+ //\r
+ return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAR) :\r
+ HWREG(ulBase + TIMER_O_TBR));\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Sets the timer match value.\r
+//!\r
+//! \param ulBase is the base address of the timer module.\r
+//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A,\r
+//! \b TIMER_B, or \b TIMER_BOTH. Only \b TIMER_A should be used when the\r
+//! timer is configured for 32-bit operation.\r
+//! \param ulValue is the match value.\r
+//!\r
+//! This function sets the match value for a timer. This is used in capture\r
+//! count mode to determine when to interrupt the processor and in PWM mode to\r
+//! determine the duty cycle of the output signal.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_matchset) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+TimerMatchSet(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulValue)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) ||\r
+ (ulBase == TIMER2_BASE));\r
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||\r
+ (ulTimer == TIMER_BOTH));\r
+\r
+ //\r
+ // Set the timer A match value if requested.\r
+ //\r
+ if(ulTimer & TIMER_A)\r
+ {\r
+ HWREG(ulBase + TIMER_O_TAMATCHR) = ulValue;\r
+ }\r
+\r
+ //\r
+ // Set the timer B match value if requested.\r
+ //\r
+ if(ulTimer & TIMER_B)\r
+ {\r
+ HWREG(ulBase + TIMER_O_TBMATCHR) = ulValue;\r
+ }\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Gets the timer match value.\r
+//!\r
+//! \param ulBase is the base address of the timer module.\r
+//! \param ulTimer specifies the timer; must be one of \b TIMER_A or\r
+//! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured\r
+//! for 32-bit operation.\r
+//!\r
+//! This function gets the match value for the specified timer.\r
+//!\r
+//! \return Returns the match value for the timer.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_matchget) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+unsigned long\r
+TimerMatchGet(unsigned long ulBase, unsigned long ulTimer)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) ||\r
+ (ulBase == TIMER2_BASE));\r
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B));\r
+\r
+ //\r
+ // Return the appropriate match value.\r
+ //\r
+ return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAMATCHR) :\r
+ HWREG(ulBase + TIMER_O_TBMATCHR));\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Registers an interrupt handler for the timer interrupt.\r
+//!\r
+//! \param ulBase is the base address of the timer module.\r
+//! \param ulTimer specifies the timer(s); must be one of \b TIMER_A,\r
+//! \b TIMER_B, or \b TIMER_BOTH.\r
+//! \param pfnHandler is a pointer to the function to be called when the timer\r
+//! interrupt occurs.\r
+//!\r
+//! This sets the handler to be called when a timer interrupt occurs. This\r
+//! will enable the global interrupt in the interrupt controller; specific\r
+//! timer interrupts must be enabled via TimerIntEnable(). It is the interrupt\r
+//! handler's responsibility to clear the interrupt source via TimerIntClear().\r
+//!\r
+//! \sa IntRegister() for important information about registering interrupt\r
+//! handlers.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+TimerIntRegister(unsigned long ulBase, unsigned long ulTimer,\r
+ void (*pfnHandler)(void))\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) ||\r
+ (ulBase == TIMER2_BASE));\r
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||\r
+ (ulTimer == TIMER_BOTH));\r
+\r
+ //\r
+ // Get the interrupt number for this timer module.\r
+ //\r
+ ulBase = ((ulBase == TIMER0_BASE) ? INT_TIMER0A :\r
+ ((ulBase == TIMER1_BASE) ? INT_TIMER1A : INT_TIMER2A));\r
+\r
+ //\r
+ // Register an interrupt handler for timer A if requested.\r
+ //\r
+ if(ulTimer & TIMER_A)\r
+ {\r
+ //\r
+ // Register the interrupt handler.\r
+ //\r
+ IntRegister(ulBase, pfnHandler);\r
+\r
+ //\r
+ // Enable the interrupt.\r
+ //\r
+ IntEnable(ulBase);\r
+ }\r
+\r
+ //\r
+ // Register an interrupt handler for timer B if requested.\r
+ //\r
+ if(ulTimer & TIMER_B)\r
+ {\r
+ //\r
+ // Register the interrupt handler.\r
+ //\r
+ IntRegister(ulBase + 1, pfnHandler);\r
+\r
+ //\r
+ // Enable the interrupt.\r
+ //\r
+ IntEnable(ulBase + 1);\r
+ }\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Unregisters an interrupt handler for the timer interrupt.\r
+//!\r
+//! \param ulBase is the base address of the timer module.\r
+//! \param ulTimer specifies the timer(s); must be one of \b TIMER_A,\r
+//! \b TIMER_B, or \b TIMER_BOTH.\r
+//!\r
+//! This function will clear the handler to be called when a timer interrupt\r
+//! occurs. This will also mask off the interrupt in the interrupt controller\r
+//! so that the interrupt handler no longer is called.\r
+//!\r
+//! \sa IntRegister() for important information about registering interrupt\r
+//! handlers.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) ||\r
+ (ulBase == TIMER2_BASE));\r
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||\r
+ (ulTimer == TIMER_BOTH));\r
+\r
+ //\r
+ // Get the interrupt number for this timer module.\r
+ //\r
+ ulBase = ((ulBase == TIMER0_BASE) ? INT_TIMER0A :\r
+ ((ulBase == TIMER1_BASE) ? INT_TIMER1A : INT_TIMER2A));\r
+\r
+ //\r
+ // Unregister the interrupt handler for timer A if requested.\r
+ //\r
+ if(ulTimer & TIMER_A)\r
+ {\r
+ //\r
+ // Disable the interrupt.\r
+ //\r
+ IntDisable(ulBase);\r
+\r
+ //\r
+ // Unregister the interrupt handler.\r
+ //\r
+ IntUnregister(ulBase);\r
+ }\r
+\r
+ //\r
+ // Unregister the interrupt handler for timer B if requested.\r
+ //\r
+ if(ulTimer & TIMER_B)\r
+ {\r
+ //\r
+ // Disable the interrupt.\r
+ //\r
+ IntDisable(ulBase + 1);\r
+\r
+ //\r
+ // Unregister the interrupt handler.\r
+ //\r
+ IntUnregister(ulBase + 1);\r
+ }\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Enables individual timer interrupt sources.\r
+//!\r
+//! \param ulBase is the base address of the timer module.\r
+//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled.\r
+//!\r
+//! Enables the indicated timer interrupt sources. Only the sources that are\r
+//! enabled can be reflected to the processor interrupt; disabled sources have\r
+//! no effect on the processor.\r
+//!\r
+//! The parameter \e ulIntFlags must be the logical OR of any combination of\r
+//! the following:\r
+//!\r
+//! - TIMER_CAPB_EVENT - Capture B event interrupt\r
+//! - TIMER_CAPB_MATCH - Capture B match interrupt\r
+//! - TIMER_TIMB_TIMEOUT - Timer B timeout interrupt\r
+//! - TIMER_RTC_MATCH - RTC interrupt mask\r
+//! - TIMER_CAPA_EVENT - Capture A event interrupt\r
+//! - TIMER_CAPA_MATCH - Capture A match interrupt\r
+//! - TIMER_TIMA_TIMEOUT - Timer A timeout interrupt\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) ||\r
+ (ulBase == TIMER2_BASE));\r
+\r
+ //\r
+ // Enable the specified interrupts.\r
+ //\r
+ HWREG(ulBase + TIMER_O_IMR) |= ulIntFlags;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Disables individual timer interrupt sources.\r
+//!\r
+//! \param ulBase is the base address of the timer module.\r
+//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled.\r
+//!\r
+//! Disables the indicated timer interrupt sources. Only the sources that are\r
+//! enabled can be reflected to the processor interrupt; disabled sources have\r
+//! no effect on the processor.\r
+//!\r
+//! The parameter \e ulIntFlags has the same definition as the \e ulIntFlags\r
+//! parameter to TimerIntEnable().\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) ||\r
+ (ulBase == TIMER2_BASE));\r
+\r
+ //\r
+ // Disable the specified interrupts.\r
+ //\r
+ HWREG(ulBase + TIMER_O_IMR) &= ~(ulIntFlags);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Gets the current interrupt status.\r
+//!\r
+//! \param ulBase is the base address of the timer module.\r
+//! \param bMasked is false if the raw interrupt status is required and true if\r
+//! the masked interrupt status is required.\r
+//!\r
+//! This returns the interrupt status for the timer module. Either the raw\r
+//! interrupt status or the status of interrupts that are allowed to reflect to\r
+//! the processor can be returned.\r
+//!\r
+//! \return The current interrupt status, enumerated as a bit field of\r
+//! values described in TimerIntEnable().\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+unsigned long\r
+TimerIntStatus(unsigned long ulBase, tBoolean bMasked)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) ||\r
+ (ulBase == TIMER2_BASE));\r
+\r
+ //\r
+ // Return either the interrupt status or the raw interrupt status as\r
+ // requested.\r
+ //\r
+ return(bMasked ? HWREG(ulBase + TIMER_O_MIS) :\r
+ HWREG(ulBase + TIMER_O_RIS));\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Clears timer interrupt sources.\r
+//!\r
+//! \param ulBase is the base address of the timer module.\r
+//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.\r
+//!\r
+//! The specified timer interrupt sources are cleared, so that they no longer\r
+//! assert. This must be done in the interrupt handler to keep it from being\r
+//! called again immediately upon exit.\r
+//!\r
+//! The parameter \e ulIntFlags has the same definition as the \e ulIntFlags\r
+//! parameter to TimerIntEnable().\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) ||\r
+ (ulBase == TIMER2_BASE));\r
+\r
+ //\r
+ // Clear the requested interrupt sources.\r
+ //\r
+ HWREG(ulBase + TIMER_O_ICR) = ulIntFlags;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Puts the timer into its reset state.\r
+//!\r
+//! \param ulBase is the base address of the timer module.\r
+//!\r
+//! The specified timer is disabled, and all its interrupts are disabled,\r
+//! cleared, and unregistered. Then the timer registers are set to their reset\r
+//! value.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_quiesce) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+TimerQuiesce(unsigned long ulBase)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) ||\r
+ (ulBase == TIMER2_BASE));\r
+\r
+ //\r
+ // Disable the timer.\r
+ //\r
+ HWREG(ulBase + TIMER_O_CTL) = TIMER_RV_CTL;\r
+\r
+ //\r
+ // Disable all the timer interrupts.\r
+ //\r
+ HWREG(ulBase + TIMER_O_IMR) = TIMER_RV_IMR;\r
+\r
+ //\r
+ // Clear all the timer interrupts.\r
+ //\r
+ HWREG(ulBase + TIMER_O_ICR) = 0xFFFFFFFF;\r
+\r
+ //\r
+ // Unregister the interrupt handler. This also disables interrupts to the\r
+ // core.\r
+ //\r
+ TimerIntUnregister(ulBase, TIMER_BOTH);\r
+\r
+ //\r
+ // Set all the registers to their reset value.\r
+ //\r
+ HWREG(ulBase + TIMER_O_CFG) = TIMER_RV_CFG;\r
+ HWREG(ulBase + TIMER_O_TAMR) = TIMER_RV_TAMR;\r
+ HWREG(ulBase + TIMER_O_TBMR) = TIMER_RV_TBMR;\r
+ HWREG(ulBase + TIMER_O_RIS) = TIMER_RV_RIS;\r
+ HWREG(ulBase + TIMER_O_MIS) = TIMER_RV_MIS;\r
+ HWREG(ulBase + TIMER_O_TAILR) = TIMER_RV_TAILR;\r
+ HWREG(ulBase + TIMER_O_TBILR) = TIMER_RV_TBILR;\r
+ HWREG(ulBase + TIMER_O_TAMATCHR) = TIMER_RV_TAMATCHR;\r
+ HWREG(ulBase + TIMER_O_TBMATCHR) = TIMER_RV_TBMATCHR;\r
+ HWREG(ulBase + TIMER_O_TAPR) = TIMER_RV_TAPR;\r
+ HWREG(ulBase + TIMER_O_TBPR) = TIMER_RV_TBPR;\r
+ HWREG(ulBase + TIMER_O_TAPMR) = TIMER_RV_TAPMR;\r
+ HWREG(ulBase + TIMER_O_TBPMR) = TIMER_RV_TBPMR;\r
+ HWREG(ulBase + TIMER_O_TAR) = TIMER_RV_TAR;\r
+ HWREG(ulBase + TIMER_O_TBR) = TIMER_RV_TBR;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Close the Doxygen group.\r
+//! @}\r
+//\r
+//*****************************************************************************\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// timer.h - Prototypes for the timer module\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 991 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __TIMER_H__\r
+#define __TIMER_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to TimerConfigure as the ulConfig parameter.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_CFG_32_BIT_OS 0x00000001 // 32-bit one-shot timer\r
+#define TIMER_CFG_32_BIT_PER 0x00000002 // 32-bit periodic timer\r
+#define TIMER_CFG_32_RTC 0x01000000 // 32-bit RTC timer\r
+#define TIMER_CFG_16_BIT_PAIR 0x04000000 // Two 16-bit timers\r
+#define TIMER_CFG_A_ONE_SHOT 0x00000001 // Timer A one-shot timer\r
+#define TIMER_CFG_A_PERIODIC 0x00000002 // Timer A periodic timer\r
+#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter\r
+#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer\r
+#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output\r
+#define TIMER_CFG_B_ONE_SHOT 0x00000100 // Timer B one-shot timer\r
+#define TIMER_CFG_B_PERIODIC 0x00000200 // Timer B periodic timer\r
+#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter\r
+#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer\r
+#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to TimerIntEnable, TimerIntDisable, and\r
+// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt\r
+#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt\r
+#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt\r
+#define TIMER_RTC_MATCH 0x00000008 // RTC interrupt mask\r
+#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt\r
+#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt\r
+#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to TimerControlEvent as the ulEvent parameter.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges\r
+#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges\r
+#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to most of the timer APIs as the ulTimer\r
+// parameter.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_A 0x000000ff // Timer A\r
+#define TIMER_B 0x0000ff00 // Timer B\r
+#define TIMER_BOTH 0x0000ffff // Timer Both\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer);\r
+extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer);\r
+extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig);\r
+extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer,\r
+ tBoolean bInvert);\r
+extern void TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer,\r
+ tBoolean bEnable);\r
+extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulEvent);\r
+extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer,\r
+ tBoolean bStall);\r
+extern void TimerRTCEnable(unsigned long ulBase);\r
+extern void TimerRTCDisable(unsigned long ulBase);\r
+extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulValue);\r
+extern unsigned long TimerPrescaleGet(unsigned long ulBase,\r
+ unsigned long ulTimer);\r
+extern void TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulValue);\r
+extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase,\r
+ unsigned long ulTimer);\r
+extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulValue);\r
+extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer);\r
+extern unsigned long TimerValueGet(unsigned long ulBase,\r
+ unsigned long ulTimer);\r
+extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulValue);\r
+extern unsigned long TimerMatchGet(unsigned long ulBase,\r
+ unsigned long ulTimer);\r
+extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer,\r
+ void (*pfnHandler)(void));\r
+extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer);\r
+extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void TimerQuiesce(unsigned long ulBase);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __TIMER_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// uart.c - Driver for the UART.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 991 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \addtogroup uart_api\r
+//! @{\r
+//\r
+//*****************************************************************************\r
+\r
+#include "../hw_ints.h"\r
+#include "../hw_memmap.h"\r
+#include "../hw_types.h"\r
+#include "../hw_uart.h"\r
+#include "debug.h"\r
+#include "interrupt.h"\r
+#include "sysctl.h"\r
+#include "uart.h"\r
+\r
+//*****************************************************************************\r
+//\r
+//! Sets the type of parity.\r
+//!\r
+//! \param ulBase is the base address of the UART port.\r
+//! \param ulParity specifies the type of parity to use.\r
+//!\r
+//! Sets the type of parity to use for transmitting and expect when receiving.\r
+//! The \e ulParity parameter must be one of \b UART_CONFIG_PAR_NONE,\r
+//! \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD, \b UART_CONFIG_PAR_ONE,\r
+//! or \b UART_CONFIG_PAR_ZERO. The last two allow direct control of the\r
+//! parity bit; it will always be either be one or zero based on the mode.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_paritymodeset) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+UARTParityModeSet(unsigned long ulBase, unsigned long ulParity)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));\r
+ ASSERT((ulParity == UART_CONFIG_PAR_NONE) ||\r
+ (ulParity == UART_CONFIG_PAR_EVEN) ||\r
+ (ulParity == UART_CONFIG_PAR_ODD) ||\r
+ (ulParity == UART_CONFIG_PAR_ONE) ||\r
+ (ulParity == UART_CONFIG_PAR_ZERO));\r
+\r
+ //\r
+ // Set the parity mode.\r
+ //\r
+ HWREG(ulBase + UART_O_LCR_H) = ((HWREG(ulBase + UART_O_LCR_H) &\r
+ ~(UART_LCR_H_SPS | UART_LCR_H_EPS |\r
+ UART_LCR_H_PEN)) | ulParity);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Gets the type of parity currently being used.\r
+//!\r
+//! \param ulBase is the base address of the UART port.\r
+//!\r
+//! \return The current parity settings, specified as one of\r
+//! \b UART_CONFIG_PAR_NONE, \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD,\r
+//! \b UART_CONFIG_PAR_ONE, or \b UART_CONFIG_PAR_ZERO.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_paritymodeget) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+unsigned long\r
+UARTParityModeGet(unsigned long ulBase)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));\r
+\r
+ //\r
+ // Return the current parity setting.\r
+ //\r
+ return(HWREG(ulBase + UART_O_LCR_H) &\r
+ (UART_LCR_H_SPS | UART_LCR_H_EPS | UART_LCR_H_PEN));\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Sets the configuration of a UART.\r
+//!\r
+//! \param ulBase is the base address of the UART port.\r
+//! \param ulBaud is the desired baud rate.\r
+//! \param ulConfig is the data format for the port (number of data bits,\r
+//! number of stop bits, and parity).\r
+//!\r
+//! This function will configure the UART for operation in the specified data\r
+//! format. The baud rate is provided in the \e ulBaud parameter and the\r
+//! data format in the \e ulConfig parameter.\r
+//!\r
+//! The \e ulConfig parameter is the logical OR of three values: the number of\r
+//! data bits, the number of stop bits, and the parity. \b UART_CONFIG_WLEN_8,\r
+//! \b UART_CONFIG_WLEN_7, \b UART_CONFIG_WLEN_6, and \b UART_CONFIG_WLEN_5\r
+//! select from eight to five data bits per byte (respectively).\r
+//! \b UART_CONFIG_STOP_ONE and \b UART_CONFIG_STOP_TWO select one or two stop\r
+//! bits (respectively). \b UART_CONFIG_PAR_NONE, \b UART_CONFIG_PAR_EVEN,\r
+//! \b UART_CONFIG_PAR_ODD, \b UART_CONFIG_PAR_ONE, and \b UART_CONFIG_PAR_ZERO\r
+//! select the parity mode (no parity bit, even parity bit, odd parity bit,\r
+//! parity bit always one, and parity bit always zero, respectively).\r
+//!\r
+//! The baud rate is dependent upon the system clock rate returned by\r
+//! SysCtlClockGet(); if it does not return the correct system clock rate then\r
+//! the baud rate will be incorrect.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_configset) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+UARTConfigSet(unsigned long ulBase, unsigned long ulBaud,\r
+ unsigned long ulConfig)\r
+{\r
+ unsigned long ulUARTClk, ulInt, ulFrac;\r
+\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));\r
+\r
+ //\r
+ // Stop the UART.\r
+ //\r
+ UARTDisable(ulBase);\r
+\r
+ //\r
+ // Determine the UART clock rate.\r
+ //\r
+ ulUARTClk = SysCtlClockGet();\r
+\r
+ //\r
+ // Compute the fractional baud rate divider.\r
+ //\r
+ ulInt = ulUARTClk / (16 * ulBaud);\r
+ ulFrac = ulUARTClk % (16 * ulBaud);\r
+ ulFrac = ((((2 * ulFrac * 4) / ulBaud) + 1) / 2);\r
+\r
+ //\r
+ // Set the baud rate.\r
+ //\r
+ HWREG(ulBase + UART_O_IBRD) = ulInt;\r
+ HWREG(ulBase + UART_O_FBRD) = ulFrac;\r
+\r
+ //\r
+ // Set parity, data length, and number of stop bits.\r
+ //\r
+ HWREG(ulBase + UART_O_LCR_H) = ulConfig;\r
+\r
+ //\r
+ // Clear the flags register.\r
+ //\r
+ HWREG(ulBase + UART_O_FR) = 0;\r
+\r
+ //\r
+ // Start the UART.\r
+ //\r
+ UARTEnable(ulBase);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Gets the current configuration of a UART.\r
+//!\r
+//! \param ulBase is the base address of the UART port.\r
+//! \param pulBaud is a pointer to storage for the baud rate.\r
+//! \param pulConfig is a pointer to storage for the data format.\r
+//!\r
+//! The baud rate and data format for the UART is determined. The returned\r
+//! baud rate is the actual baud rate; it may not be the exact baud rate\r
+//! requested or an ``official'' baud rate. The data format returned in\r
+//! \e pulConfig is enumerated the same as the \e ulConfig parameter of\r
+//! UARTConfigSet().\r
+//!\r
+//! The baud rate is dependent upon the system clock rate returned by\r
+//! SysCtlClockGet(); if it does not return the correct system clock rate then\r
+//! the baud rate will be computed incorrectly.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_configget) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+UARTConfigGet(unsigned long ulBase, unsigned long *pulBaud,\r
+ unsigned long *pulConfig)\r
+\r
+{\r
+ unsigned long ulInt, ulFrac;\r
+\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));\r
+\r
+ //\r
+ // Compute the baud rate.\r
+ //\r
+ ulInt = HWREG(ulBase + UART_O_IBRD);\r
+ ulFrac = HWREG(ulBase + UART_O_FBRD);\r
+ *pulBaud = (SysCtlClockGet() * 4) / ((64 * ulInt) + ulFrac);\r
+\r
+ //\r
+ // Get the parity, data length, and number of stop bits.\r
+ //\r
+ *pulConfig = (HWREG(ulBase + UART_O_LCR_H) &\r
+ (UART_LCR_H_SPS | UART_LCR_H_WLEN | UART_LCR_H_STP2 |\r
+ UART_LCR_H_EPS | UART_LCR_H_PEN));\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Enables transmitting and receiving.\r
+//!\r
+//! \param ulBase is the base address of the UART port.\r
+//!\r
+//! Sets the UARTEN, TXE, and RXE bits, and enables the transmit and receive\r
+//! FIFOs.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_enable) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+UARTEnable(unsigned long ulBase)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));\r
+\r
+ //\r
+ // Enable the FIFO.\r
+ //\r
+ HWREG(ulBase + UART_O_LCR_H) |= UART_LCR_H_FEN;\r
+\r
+ //\r
+ // Enable RX, TX, and the UART.\r
+ //\r
+ HWREG(ulBase + UART_O_CTL) |= (UART_CTL_UARTEN | UART_CTL_TXE |\r
+ UART_CTL_RXE);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Disables transmitting and receiving.\r
+//!\r
+//! \param ulBase is the base address of the UART port.\r
+//!\r
+//! Clears the UARTEN, TXE, and RXE bits, then waits for the end of\r
+//! transmission of the current character, and flushes the transmit FIFO.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_disable) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+UARTDisable(unsigned long ulBase)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));\r
+\r
+ //\r
+ // Wait for end of TX.\r
+ //\r
+ while(HWREG(ulBase + UART_O_FR) & UART_FR_BUSY)\r
+ {\r
+ }\r
+\r
+ //\r
+ // Disable the FIFO.\r
+ //\r
+ HWREG(ulBase + UART_O_LCR_H) &= ~(UART_LCR_H_FEN);\r
+\r
+ //\r
+ // Disable the UART.\r
+ //\r
+ HWREG(ulBase + UART_O_CTL) &= ~(UART_CTL_UARTEN | UART_CTL_TXE |\r
+ UART_CTL_RXE);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Determines if there are any characters in the receive FIFO.\r
+//!\r
+//! \param ulBase is the base address of the UART port.\r
+//!\r
+//! This function returns a flag indicating whether or not there is data\r
+//! available in the receive FIFO.\r
+//!\r
+//! \return Returns \b true if there is data in the receive FIFO, and \b false\r
+//! if there is no data in the receive FIFO.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_charsavail) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+tBoolean\r
+UARTCharsAvail(unsigned long ulBase)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));\r
+\r
+ //\r
+ // Return the availability of characters.\r
+ //\r
+ return((HWREG(ulBase + UART_O_FR) & UART_FR_RXFE) ? false : true);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Determines if there is any space in the transmit FIFO.\r
+//!\r
+//! \param ulBase is the base address of the UART port.\r
+//!\r
+//! This function returns a flag indicating whether or not there is space\r
+//! available in the transmit FIFO.\r
+//!\r
+//! \return Returns \b true if there is space available in the transmit FIFO,\r
+//! and \b false if there is no space available in the transmit FIFO.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_spaceavail) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+tBoolean\r
+UARTSpaceAvail(unsigned long ulBase)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));\r
+\r
+ //\r
+ // Return the availability of space.\r
+ //\r
+ return((HWREG(ulBase + UART_O_FR) & UART_FR_TXFF) ? false : true);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Receives a character from the specified port.\r
+//!\r
+//! \param ulBase is the base address of the UART port.\r
+//!\r
+//! Gets a character from the receive FIFO for the specified port.\r
+//!\r
+//! \return Returns the character read from the specified port, cast as a\r
+//! \e long. A \b -1 will be returned if there are no characters present in\r
+//! the receive FIFO. The UARTCharsAvail() function should be called before\r
+//! attempting to call this function.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_charnonblockingget) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+long\r
+UARTCharNonBlockingGet(unsigned long ulBase)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));\r
+\r
+ //\r
+ // See if there are any characters in the receive FIFO.\r
+ //\r
+ if(!(HWREG(ulBase + UART_O_FR) & UART_FR_RXFE))\r
+ {\r
+ //\r
+ // Read and return the next character.\r
+ //\r
+ return(HWREG(ulBase + UART_O_DR));\r
+ }\r
+ else\r
+ {\r
+ //\r
+ // There are no characters, so return a failure.\r
+ //\r
+ return(-1);\r
+ }\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Waits for a character from the specified port.\r
+//!\r
+//! \param ulBase is the base address of the UART port.\r
+//!\r
+//! Gets a character from the receive FIFO for the specified port. If there\r
+//! are no characters available, this function will wait until a character is\r
+//! received before returning.\r
+//!\r
+//! \return Returns the character read from the specified port, cast as an\r
+//! \e int.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_charget) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+long\r
+UARTCharGet(unsigned long ulBase)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));\r
+\r
+ //\r
+ // Wait until a char is available.\r
+ //\r
+ while(HWREG(ulBase + UART_O_FR) & UART_FR_RXFE)\r
+ {\r
+ }\r
+\r
+ //\r
+ // Now get the char.\r
+ //\r
+ return(HWREG(ulBase + UART_O_DR));\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Sends a character to the specified port.\r
+//!\r
+//! \param ulBase is the base address of the UART port.\r
+//! \param ucData is the character to be transmitted.\r
+//!\r
+//! Writes the character \e ucData to the transmit FIFO for the specified port.\r
+//! This function does not block, so if there is no space available, then a\r
+//! \b false is returned, and the application will have to retry the function\r
+//! later.\r
+//!\r
+//! \return Returns \b true if the character was successfully placed in the\r
+//! transmit FIFO, and \b false if there was no space available in the transmit\r
+//! FIFO.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_charnonblockingput) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+tBoolean\r
+UARTCharNonBlockingPut(unsigned long ulBase, unsigned char ucData)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));\r
+\r
+ //\r
+ // See if there is space in the transmit FIFO.\r
+ //\r
+ if(!(HWREG(ulBase + UART_O_FR) & UART_FR_TXFF))\r
+ {\r
+ //\r
+ // Write this character to the transmit FIFO.\r
+ //\r
+ HWREG(ulBase + UART_O_DR) = ucData;\r
+\r
+ //\r
+ // Success.\r
+ //\r
+ return(true);\r
+ }\r
+ else\r
+ {\r
+ //\r
+ // There is no space in the transmit FIFO, so return a failure.\r
+ //\r
+ return(false);\r
+ }\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Waits to send a character from the specified port.\r
+//!\r
+//! \param ulBase is the base address of the UART port.\r
+//! \param ucData is the character to be transmitted.\r
+//!\r
+//! Sends the character \e ucData to the transmit FIFO for the specified port.\r
+//! If there is no space available in the transmit FIFO, this function will\r
+//! wait until there is space available before returning.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_charput) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+UARTCharPut(unsigned long ulBase, unsigned char ucData)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));\r
+\r
+ //\r
+ // Wait until space is available.\r
+ //\r
+ while(HWREG(ulBase + UART_O_FR) & UART_FR_TXFF)\r
+ {\r
+ }\r
+\r
+ //\r
+ // Send the char.\r
+ //\r
+ HWREG(ulBase + UART_O_DR) = ucData;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Causes a BREAK to be sent.\r
+//!\r
+//! \param ulBase is the base address of the UART port.\r
+//! \param bBreakState controls the output level.\r
+//!\r
+//! Calling this function with \e bBreakState set to \b true will assert a\r
+//! break condition on the UART. Calling this function with \e bBreakState set\r
+//! to \b false will remove the break condition. For proper transmission of a\r
+//! break command, the break must be asserted for at least two complete frames.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_breakctl) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));\r
+\r
+ //\r
+ // Set the break condition as requested.\r
+ //\r
+ HWREG(ulBase + UART_O_LCR_H) =\r
+ (bBreakState ?\r
+ (HWREG(ulBase + UART_O_LCR_H) | UART_LCR_H_BRK) :\r
+ (HWREG(ulBase + UART_O_LCR_H) & ~(UART_LCR_H_BRK)));\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Registers an interrupt handler for a UART interrupt.\r
+//!\r
+//! \param ulBase is the base address of the UART port.\r
+//! \param pfnHandler is a pointer to the function to be called when the\r
+//! UART interrupt occurs.\r
+//!\r
+//! This function does the actual registering of the interrupt handler. This\r
+//! will enable the global interrupt in the interrupt controller; specific UART\r
+//! interrupts must be enabled via UARTIntEnable(). It is the interrupt\r
+//! handler's responsibility to clear the interrupt source.\r
+//!\r
+//! \sa IntRegister() for important information about registering interrupt\r
+//! handlers.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+UARTIntRegister(unsigned long ulBase, void (*pfnHandler)(void))\r
+{\r
+ unsigned long ulInt;\r
+\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));\r
+\r
+ //\r
+ // Determine the interrupt number based on the UART port.\r
+ //\r
+ ulInt = (ulBase == UART0_BASE) ? INT_UART0 : INT_UART1;\r
+\r
+ //\r
+ // Register the interrupt handler.\r
+ //\r
+ IntRegister(ulInt, pfnHandler);\r
+\r
+ //\r
+ // Enable the UART interrupt.\r
+ //\r
+ IntEnable(ulInt);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Unregisters an interrupt handler for a UART interrupt.\r
+//!\r
+//! \param ulBase is the base address of the UART port.\r
+//!\r
+//! This function does the actual unregistering of the interrupt handler. It\r
+//! will clear the handler to be called when a UART interrupt occurs. This\r
+//! will also mask off the interrupt in the interrupt controller so that the\r
+//! interrupt handler no longer is called.\r
+//!\r
+//! \sa IntRegister() for important information about registering interrupt\r
+//! handlers.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+UARTIntUnregister(unsigned long ulBase)\r
+{\r
+ unsigned long ulInt;\r
+\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));\r
+\r
+ //\r
+ // Determine the interrupt number based on the UART port.\r
+ //\r
+ ulInt = (ulBase == UART0_BASE) ? INT_UART0 : INT_UART1;\r
+\r
+ //\r
+ // Disable the interrupt.\r
+ //\r
+ IntDisable(ulInt);\r
+\r
+ //\r
+ // Unregister the interrupt handler.\r
+ //\r
+ IntUnregister(ulInt);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Enables individual UART interrupt sources.\r
+//!\r
+//! \param ulBase is the base address of the UART port.\r
+//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled.\r
+//!\r
+//! Enables the indicated UART interrupt sources. Only the sources that are\r
+//! enabled can be reflected to the processor interrupt; disabled sources have\r
+//! no effect on the processor.\r
+//!\r
+//! The parameter \e ulIntFlags is the logical OR of any of the following:\r
+//!\r
+//! - UART_INT_OE - Overrun Error interrupt\r
+//! - UART_INT_BE - Break Error interrupt\r
+//! - UART_INT_PE - Parity Error interrupt\r
+//! - UART_INT_FE - Framing Error interrupt\r
+//! - UART_INT_RT - Receive Timeout interrupt\r
+//! - UART_INT_TX - Transmit interrupt\r
+//! - UART_INT_RX - Receive interrupt\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));\r
+\r
+ //\r
+ // Enable the specified interrupts.\r
+ //\r
+ HWREG(ulBase + UART_O_IM) |= ulIntFlags;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Disables individual UART interrupt sources.\r
+//!\r
+//! \param ulBase is the base address of the UART port.\r
+//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled.\r
+//!\r
+//! Disables the indicated UART interrupt sources. Only the sources that are\r
+//! enabled can be reflected to the processor interrupt; disabled sources have\r
+//! no effect on the processor.\r
+//!\r
+//! The parameter \e ulIntFlags has the same definition as the same parameter\r
+//! to UARTIntEnable().\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));\r
+\r
+ //\r
+ // Disable the specified interrupts.\r
+ //\r
+ HWREG(ulBase + UART_O_IM) &= ~(ulIntFlags);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Gets the current interrupt status.\r
+//!\r
+//! \param ulBase is the base address of the UART port.\r
+//! \param bMasked is false if the raw interrupt status is required and true\r
+//! if the masked interrupt status is required.\r
+//!\r
+//! This returns the interrupt status for the specified UART. Either the raw\r
+//! interrupt status or the status of interrupts that are allowed to reflect to\r
+//! the processor can be returned.\r
+//!\r
+//! \return The current interrupt status, enumerated as a bit field of\r
+//! values described in UARTIntEnable().\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+unsigned long\r
+UARTIntStatus(unsigned long ulBase, tBoolean bMasked)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));\r
+\r
+ //\r
+ // Return either the interrupt status or the raw interrupt status as\r
+ // requested.\r
+ //\r
+ if(bMasked)\r
+ {\r
+ return(HWREG(ulBase + UART_O_MIS));\r
+ }\r
+ else\r
+ {\r
+ return(HWREG(ulBase + UART_O_RIS));\r
+ }\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Clears UART interrupt sources.\r
+//!\r
+//! \param ulBase is the base address of the UART port.\r
+//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.\r
+//!\r
+//! The specified UART interrupt sources are cleared, so that they no longer\r
+//! assert. This must be done in the interrupt handler to keep it from being\r
+//! called again immediately upon exit.\r
+//!\r
+//! The parameter \e ulIntFlags has the same definition as the same parameter\r
+//! to UARTIntEnable().\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));\r
+\r
+ //\r
+ // Clear the requested interrupt sources.\r
+ //\r
+ HWREG(ulBase + UART_O_ICR) = ulIntFlags;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Close the Doxygen group.\r
+//! @}\r
+//\r
+//*****************************************************************************\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// uart.h - Defines and Macros for the UART.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 991 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __UART_H__\r
+#define __UART_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear\r
+// as the ulIntFlags parameter, and returned from UARTIntStatus.\r
+//\r
+//*****************************************************************************\r
+#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask\r
+#define UART_INT_BE 0x200 // Break Error Interrupt Mask\r
+#define UART_INT_PE 0x100 // Parity Error Interrupt Mask\r
+#define UART_INT_FE 0x080 // Framing Error Interrupt Mask\r
+#define UART_INT_RT 0x040 // Receive Timeout Interrupt Mask\r
+#define UART_INT_TX 0x020 // Transmit Interrupt Mask\r
+#define UART_INT_RX 0x010 // Receive Interrupt Mask\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to UARTConfigSet as the ulConfig parameter and\r
+// returned by UARTConfigGet in the pulConfig parameter. Additionally, the\r
+// UART_CONFIG_PAR_* subset can be passed to UARTParityModeSet as the ulParity\r
+// parameter, and are returned by UARTParityModeGet.\r
+//\r
+//*****************************************************************************\r
+#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data\r
+#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data\r
+#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data\r
+#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data\r
+#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit\r
+#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits\r
+#define UART_CONFIG_PAR_NONE 0x00000000 // No parity\r
+#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity\r
+#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity\r
+#define UART_CONFIG_PAR_ONE 0x00000086 // Parity bit is one\r
+#define UART_CONFIG_PAR_ZERO 0x00000082 // Parity bit is zero\r
+\r
+//*****************************************************************************\r
+//\r
+// API Function prototypes\r
+//\r
+//*****************************************************************************\r
+extern void UARTParityModeSet(unsigned long ulBase, unsigned long ulParity);\r
+extern unsigned long UARTParityModeGet(unsigned long ulBase);\r
+extern void UARTConfigSet(unsigned long ulBase, unsigned long ulBaud,\r
+ unsigned long ulConfig);\r
+extern void UARTConfigGet(unsigned long ulBase, unsigned long *pulBaud,\r
+ unsigned long *pulConfig);\r
+extern void UARTEnable(unsigned long ulBase);\r
+extern void UARTDisable(unsigned long ulBase);\r
+extern tBoolean UARTCharsAvail(unsigned long ulBase);\r
+extern tBoolean UARTSpaceAvail(unsigned long ulBase);\r
+extern long UARTCharNonBlockingGet(unsigned long ulBase);\r
+extern long UARTCharGet(unsigned long ulBase);\r
+extern tBoolean UARTCharNonBlockingPut(unsigned long ulBase,\r
+ unsigned char ucData);\r
+extern void UARTCharPut(unsigned long ulBase, unsigned char ucData);\r
+extern void UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState);\r
+extern void UARTIntRegister(unsigned long ulBase, void(*pfnHandler)(void));\r
+extern void UARTIntUnregister(unsigned long ulBase);\r
+extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __UART_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// watchdog.c - Driver for the Watchdog Timer Module.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 991 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \addtogroup watchdog_api\r
+//! @{\r
+//\r
+//*****************************************************************************\r
+\r
+#include "../hw_ints.h"\r
+#include "../hw_memmap.h"\r
+#include "../hw_types.h"\r
+#include "../hw_watchdog.h"\r
+#include "debug.h"\r
+#include "interrupt.h"\r
+#include "watchdog.h"\r
+\r
+//*****************************************************************************\r
+//\r
+//! Determines if the watchdog timer is enabled.\r
+//!\r
+//! \param ulBase is the base address of the watchdog timer module.\r
+//!\r
+//! This will check to see if the watchdog timer is enabled.\r
+//!\r
+//! \return Returns \b true if the watchdog timer is enabled, and \b false\r
+//! if it is not.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_running) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+tBoolean\r
+WatchdogRunning(unsigned long ulBase)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == WATCHDOG_BASE);\r
+\r
+ //\r
+ // See if the watchdog timer module is enabled, and return.\r
+ //\r
+ return(HWREG(ulBase + WDT_O_CTL) & WDT_CTL_INTEN);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Enables the watchdog timer.\r
+//!\r
+//! \param ulBase is the base address of the watchdog timer module.\r
+//!\r
+//! This will enable the watchdog timer counter and interrupt.\r
+//!\r
+//! \note This function will have no effect if the watchdog timer has\r
+//! been locked.\r
+//!\r
+//! \sa WatchdogLock(), WatchdogUnlock()\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_enable) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+WatchdogEnable(unsigned long ulBase)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == WATCHDOG_BASE);\r
+\r
+ //\r
+ // Enable the watchdog timer module.\r
+ //\r
+ HWREG(ulBase + WDT_O_CTL) |= WDT_CTL_INTEN;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Enables the watchdog timer reset.\r
+//!\r
+//! \param ulBase is the base address of the watchdog timer module.\r
+//!\r
+//! Enables the capability of the watchdog timer to issue a reset to the\r
+//! processor upon a second timeout condition.\r
+//!\r
+//! \note This function will have no effect if the watchdog timer has\r
+//! been locked.\r
+//!\r
+//! \sa WatchdogLock(), WatchdogUnlock()\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_resetenable) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+WatchdogResetEnable(unsigned long ulBase)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == WATCHDOG_BASE);\r
+\r
+ //\r
+ // Enable the watchdog reset.\r
+ //\r
+ HWREG(ulBase + WDT_O_CTL) |= WDT_CTL_RESEN;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Disables the watchdog timer reset.\r
+//!\r
+//! \param ulBase is the base address of the watchdog timer module.\r
+//!\r
+//! Disables the capability of the watchdog timer to issue a reset to the\r
+//! processor upon a second timeout condition.\r
+//!\r
+//! \note This function will have no effect if the watchdog timer has\r
+//! been locked.\r
+//!\r
+//! \sa WatchdogLock(), WatchdogUnlock()\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_resetdisable) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+WatchdogResetDisable(unsigned long ulBase)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == WATCHDOG_BASE);\r
+\r
+ //\r
+ // Disable the watchdog reset.\r
+ //\r
+ HWREG(ulBase + WDT_O_CTL) &= ~(WDT_CTL_RESEN);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Enables the watchdog timer lock mechanism.\r
+//!\r
+//! \param ulBase is the base address of the watchdog timer module.\r
+//!\r
+//! Locks out write access to the watchdog timer configuration registers.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_lock) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+WatchdogLock(unsigned long ulBase)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == WATCHDOG_BASE);\r
+\r
+ //\r
+ // Lock out watchdog register writes. Writing anything to the WDT_O_LOCK\r
+ // register causes the lock to go into effect.\r
+ //\r
+ HWREG(ulBase + WDT_O_LOCK) = WDT_LOCK_LOCKED;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Disables the watchdog timer lock mechanism.\r
+//!\r
+//! \param ulBase is the base address of the watchdog timer module.\r
+//!\r
+//! Enables write access to the watchdog timer configuration registers.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_unlock) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+WatchdogUnlock(unsigned long ulBase)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == WATCHDOG_BASE);\r
+\r
+ //\r
+ // Unlock watchdog register writes.\r
+ //\r
+ HWREG(ulBase + WDT_O_LOCK) = WDT_LOCK_UNLOCK;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Gets the state of the watchdog timer lock mechanism.\r
+//!\r
+//! \param ulBase is the base address of the watchdog timer module.\r
+//!\r
+//! Returns the lock state of the watchdog timer registers.\r
+//!\r
+//! \return Returns \b true if the watchdog timer registers are locked, and\r
+//! \b false if they are not locked.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_lockstate) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+tBoolean\r
+WatchdogLockState(unsigned long ulBase)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == WATCHDOG_BASE);\r
+\r
+ //\r
+ // Get the lock state.\r
+ //\r
+ return((HWREG(ulBase + WDT_O_LOCK) == WDT_LOCK_LOCKED) ? true : false);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Sets the watchdog timer reload value.\r
+//!\r
+//! \param ulBase is the base address of the watchdog timer module.\r
+//! \param ulLoadVal is the load value for the watchdog timer.\r
+//!\r
+//! This function sets the value to load into the watchdog timer when the count\r
+//! reaches zero for the first time; if the watchdog timer is running when this\r
+//! function is called, then the value will be immediately loaded into the\r
+//! watchdog timer counter. If the parameter \e ulLoadVal is 0, then an\r
+//! interrupt is immediately generated.\r
+//!\r
+//! \note This function will have no effect if the watchdog timer has\r
+//! been locked.\r
+//!\r
+//! \sa WatchdogLock(), WatchdogUnlock(), WatchdogReloadGet()\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_reloadset) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == WATCHDOG_BASE);\r
+\r
+ //\r
+ // Set the load register.\r
+ //\r
+ HWREG(ulBase + WDT_O_LOAD) = ulLoadVal;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Gets the watchdog timer reload value.\r
+//!\r
+//! \param ulBase is the base address of the watchdog timer module.\r
+//!\r
+//! This function gets the value that is loaded into the watchdog timer when\r
+//! the count reaches zero for the first time.\r
+//!\r
+//! \sa WatchdogReloadSet()\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_reloadget) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+unsigned long\r
+WatchdogReloadGet(unsigned long ulBase)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == WATCHDOG_BASE);\r
+\r
+ //\r
+ // Get the load register.\r
+ //\r
+ return(HWREG(ulBase + WDT_O_LOAD));\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Gets the current watchdog timer value.\r
+//!\r
+//! \param ulBase is the base address of the watchdog timer module.\r
+//!\r
+//! This function reads the current value of the watchdog timer.\r
+//!\r
+//! \return Returns the current value of the watchdog timer.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_valueget) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+unsigned long\r
+WatchdogValueGet(unsigned long ulBase)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == WATCHDOG_BASE);\r
+\r
+ //\r
+ // Get the current watchdog timer register value.\r
+ //\r
+ return(HWREG(ulBase + WDT_O_VALUE));\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Registers an interrupt handler for watchdog timer interrupt.\r
+//!\r
+//! \param ulBase is the base address of the watchdog timer module.\r
+//! \param pfnHandler is a pointer to the function to be called when the\r
+//! watchdog timer interrupt occurs.\r
+//!\r
+//! This function does the actual registering of the interrupt handler. This\r
+//! will enable the global interrupt in the interrupt controller; the watchdog\r
+//! timer interrupt must be enabled via WatchdogEnable(). It is the interrupt\r
+//! handler's responsibility to clear the interrupt source via\r
+//! WatchdogIntClear().\r
+//!\r
+//! \sa IntRegister() for important information about registering interrupt\r
+//! handlers.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+WatchdogIntRegister(unsigned long ulBase, void (*pfnHandler)(void))\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == WATCHDOG_BASE);\r
+\r
+ //\r
+ // Register the interrupt handler.\r
+ //\r
+ IntRegister(INT_WATCHDOG, pfnHandler);\r
+\r
+ //\r
+ // Enable the watchdog timer interrupt.\r
+ //\r
+ IntEnable(INT_WATCHDOG);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Unregisters an interrupt handler for the watchdog timer interrupt.\r
+//!\r
+//! \param ulBase is the base address of the watchdog timer module.\r
+//!\r
+//! This function does the actual unregistering of the interrupt handler. This\r
+//! function will clear the handler to be called when a watchdog timer\r
+//! interrupt occurs. This will also mask off the interrupt in the interrupt\r
+//! controller so that the interrupt handler no longer is called.\r
+//!\r
+//! \sa IntRegister() for important information about registering interrupt\r
+//! handlers.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+WatchdogIntUnregister(unsigned long ulBase)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == WATCHDOG_BASE);\r
+\r
+ //\r
+ // Disable the interrupt.\r
+ //\r
+ IntDisable(INT_WATCHDOG);\r
+\r
+ //\r
+ // Unregister the interrupt handler.\r
+ //\r
+ IntUnregister(INT_WATCHDOG);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Enables the watchdog timer interrupt.\r
+//!\r
+//! \param ulBase is the base address of the watchdog timer module.\r
+//!\r
+//! Enables the watchdog timer interrupt.\r
+//!\r
+//! \note This function will have no effect if the watchdog timer has\r
+//! been locked.\r
+//!\r
+//! \sa WatchdogLock(), WatchdogUnlock(), WatchdogEnable()\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+WatchdogIntEnable(unsigned long ulBase)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == WATCHDOG_BASE);\r
+\r
+ //\r
+ // Enable the watchdog interrupt.\r
+ //\r
+ HWREG(ulBase + WDT_O_CTL) |= WDT_CTL_INTEN;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Gets the current watchdog timer interrupt status.\r
+//!\r
+//! \param ulBase is the base address of the watchdog timer module.\r
+//! \param bMasked is \b false if the raw interrupt status is required and\r
+//! \b true if the masked interrupt status is required.\r
+//!\r
+//! This returns the interrupt status for the watchdog timer module. Either\r
+//! the raw interrupt status or the status of interrupt that is allowed to\r
+//! reflect to the processor can be returned.\r
+//!\r
+//! \return The current interrupt status, where a 1 indicates that the watchdog\r
+//! interrupt is active, and a 0 indicates that it is not active.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+unsigned long\r
+WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == WATCHDOG_BASE);\r
+\r
+ //\r
+ // Return either the interrupt status or the raw interrupt status as\r
+ // requested.\r
+ //\r
+ if(bMasked)\r
+ {\r
+ return(HWREG(ulBase + WDT_O_MIS));\r
+ }\r
+ else\r
+ {\r
+ return(HWREG(ulBase + WDT_O_RIS));\r
+ }\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Clears the watchdog timer interrupt.\r
+//!\r
+//! \param ulBase is the base address of the watchdog timer module.\r
+//!\r
+//! The watchdog timer interrupt source is cleared, so that it no longer\r
+//! asserts.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+WatchdogIntClear(unsigned long ulBase)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == WATCHDOG_BASE);\r
+\r
+ //\r
+ // Clear the interrupt source.\r
+ //\r
+ HWREG(ulBase + WDT_O_ICR) = WDT_INT_TIMEOUT;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Enables stalling of the watchdog timer during debug events.\r
+//!\r
+//! \param ulBase is the base address of the watchdog timer module.\r
+//!\r
+//! This function allows the watchdog timer to stop counting when the processor\r
+//! is stopped by the debugger. By doing so, the watchdog is prevented from\r
+//! expiring (typically almost immediately from a human time perspective) and\r
+//! resetting the system (if reset is enabled). The watchdog will instead\r
+//! expired after the appropriate number of processor cycles have been executed\r
+//! while debugging (or at the appropriate time after the processor has been\r
+//! restarted).\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_stallenable) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+WatchdogStallEnable(unsigned long ulBase)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == WATCHDOG_BASE);\r
+\r
+ //\r
+ // Enable timer stalling.\r
+ //\r
+ HWREG(ulBase + WDT_O_TEST) |= WDT_TEST_STALL;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! Disables stalling of the watchdog timer during debug events.\r
+//!\r
+//! \param ulBase is the base address of the watchdog timer module.\r
+//!\r
+//! This function disables the debug mode stall of the watchdog timer. By\r
+//! doing so, the watchdog timer continues to count regardless of the processor\r
+//! debug state.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(GROUP_stalldisable) || defined(BUILD_ALL) || defined(DOXYGEN)\r
+void\r
+WatchdogStallDisable(unsigned long ulBase)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulBase == WATCHDOG_BASE);\r
+\r
+ //\r
+ // Disable timer stalling.\r
+ //\r
+ HWREG(ulBase + WDT_O_TEST) &= ~(WDT_TEST_STALL);\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Close the Doxygen group.\r
+//! @}\r
+//\r
+//*****************************************************************************\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// watchdog.h - Prototypes for the Watchdog Timer API\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 991 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __WATCHDOG_H__\r
+#define __WATCHDOG_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern tBoolean WatchdogRunning(unsigned long ulBase);\r
+extern void WatchdogEnable(unsigned long ulBase);\r
+extern void WatchdogResetEnable(unsigned long ulBase);\r
+extern void WatchdogResetDisable(unsigned long ulBase);\r
+extern void WatchdogLock(unsigned long ulBase);\r
+extern void WatchdogUnlock(unsigned long ulBase);\r
+extern tBoolean WatchdogLockState(unsigned long ulBase);\r
+extern void WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal);\r
+extern unsigned long WatchdogReloadGet(unsigned long ulBase);\r
+extern unsigned long WatchdogValueGet(unsigned long ulBase);\r
+extern void WatchdogIntRegister(unsigned long ulBase, void(*pfnHandler)(void));\r
+extern void WatchdogIntUnregister(unsigned long ulBase);\r
+extern void WatchdogIntEnable(unsigned long ulBase);\r
+extern unsigned long WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern void WatchdogIntClear(unsigned long ulBase);\r
+extern void WatchdogStallDisable(unsigned long ulBase);\r
+extern void WatchdogStallDisable(unsigned long ulBase);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __WATCHDOG_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// startup.c - Boot code for Stellaris.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 1049 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+// Forward declaration of the default fault handlers.\r
+//\r
+//*****************************************************************************\r
+void ResetISR(void);\r
+static void NmiSR(void);\r
+static void FaultISR(void);\r
+static void IntDefaultHandler(void);\r
+extern void xPortPendSVHandler(void);\r
+extern void xPortSysTickHandler(void);\r
+extern void vUART_ISR( void );\r
+extern void vGPIO_ISR( void );\r
+\r
+//*****************************************************************************\r
+//\r
+// The entry point for the application.\r
+//\r
+//*****************************************************************************\r
+extern int main(void);\r
+\r
+//*****************************************************************************\r
+//\r
+// Reserve space for the system stack.\r
+//\r
+//*****************************************************************************\r
+#ifndef STACK_SIZE\r
+#define STACK_SIZE 64\r
+#endif\r
+static unsigned long pulStack[STACK_SIZE];\r
+\r
+//*****************************************************************************\r
+//\r
+// The minimal vector table for a Cortex M3. Note that the proper constructs\r
+// must be placed on this to ensure that it ends up at physical address\r
+// 0x0000.0000.\r
+//\r
+//*****************************************************************************\r
+__attribute__ ((section(".isr_vector")))\r
+void (* const g_pfnVectors[])(void) =\r
+{\r
+ (void (*)(void))((unsigned long)pulStack + sizeof(pulStack)),\r
+ // The initial stack pointer\r
+ ResetISR, // The reset handler\r
+ NmiSR, // The NMI handler\r
+ FaultISR, // The hard fault handler\r
+ IntDefaultHandler, // The MPU fault handler\r
+ IntDefaultHandler, // The bus fault handler\r
+ IntDefaultHandler, // The usage fault handler\r
+ 0, // Reserved\r
+ 0, // Reserved\r
+ 0, // Reserved\r
+ 0, // Reserved\r
+ IntDefaultHandler, // SVCall handler\r
+ IntDefaultHandler, // Debug monitor handler\r
+ 0, // Reserved\r
+ xPortPendSVHandler, // The PendSV handler\r
+ xPortSysTickHandler, // The SysTick handler\r
+ IntDefaultHandler, // GPIO Port A\r
+ IntDefaultHandler, // GPIO Port B\r
+ vGPIO_ISR, // GPIO Port C\r
+ IntDefaultHandler, // GPIO Port D\r
+ IntDefaultHandler, // GPIO Port E\r
+ vUART_ISR, // UART0 Rx and Tx\r
+ IntDefaultHandler, // UART1 Rx and Tx\r
+ IntDefaultHandler, // SSI Rx and Tx\r
+ IntDefaultHandler, // I2C Master and Slave\r
+ IntDefaultHandler, // PWM Fault\r
+ IntDefaultHandler, // PWM Generator 0\r
+ IntDefaultHandler, // PWM Generator 1\r
+ IntDefaultHandler, // PWM Generator 2\r
+ IntDefaultHandler, // Quadrature Encoder\r
+ IntDefaultHandler, // ADC Sequence 0\r
+ IntDefaultHandler, // ADC Sequence 1\r
+ IntDefaultHandler, // ADC Sequence 2\r
+ IntDefaultHandler, // ADC Sequence 3\r
+ IntDefaultHandler, // Watchdog timer\r
+ IntDefaultHandler, // Timer 0 subtimer A\r
+ IntDefaultHandler, // Timer 0 subtimer B\r
+ IntDefaultHandler, // Timer 1 subtimer A\r
+ IntDefaultHandler, // Timer 1 subtimer B\r
+ IntDefaultHandler, // Timer 2 subtimer A\r
+ IntDefaultHandler, // Timer 2 subtimer B\r
+ IntDefaultHandler, // Analog Comparator 0\r
+ IntDefaultHandler, // Analog Comparator 1\r
+ IntDefaultHandler, // Analog Comparator 2\r
+ IntDefaultHandler, // System Control (PLL, OSC, BO)\r
+ IntDefaultHandler // FLASH Control\r
+};\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are constructs created by the linker, indicating where the\r
+// the "data" and "bss" segments reside in memory. The initializers for the\r
+// for the "data" segment resides immediately following the "text" segment.\r
+//\r
+//*****************************************************************************\r
+extern unsigned long _etext;\r
+extern unsigned long _data;\r
+extern unsigned long _edata;\r
+extern unsigned long _bss;\r
+extern unsigned long _ebss;\r
+\r
+//*****************************************************************************\r
+//\r
+// This is the code that gets called when the processor first starts execution\r
+// following a reset event. Only the absolutely necessary set is performed,\r
+// after which the application supplied main() routine is called. Any fancy\r
+// actions (such as making decisions based on the reset cause register, and\r
+// resetting the bits in that register) are left solely in the hands of the\r
+// application.\r
+//\r
+//*****************************************************************************\r
+void\r
+ResetISR(void)\r
+{\r
+ unsigned long *pulSrc, *pulDest;\r
+\r
+ //\r
+ // Copy the data segment initializers from flash to SRAM.\r
+ //\r
+ pulSrc = &_etext;\r
+ for(pulDest = &_data; pulDest < &_edata; )\r
+ {\r
+ *pulDest++ = *pulSrc++;\r
+ }\r
+\r
+ //\r
+ // Zero fill the bss segment.\r
+ //\r
+ for(pulDest = &_bss; pulDest < &_ebss; )\r
+ {\r
+ *pulDest++ = 0;\r
+ }\r
+\r
+ //\r
+ // Call the application's entry point.\r
+ //\r
+ main();\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+// This is the code that gets called when the processor receives a NMI. This\r
+// simply enters an infinite loop, preserving the system state for examination\r
+// by a debugger.\r
+//\r
+//*****************************************************************************\r
+static void\r
+NmiSR(void)\r
+{\r
+ //\r
+ // Enter an infinite loop.\r
+ //\r
+ while(1)\r
+ {\r
+ }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+// This is the code that gets called when the processor receives a fault\r
+// interrupt. This simply enters an infinite loop, preserving the system state\r
+// for examination by a debugger.\r
+//\r
+//*****************************************************************************\r
+static void\r
+FaultISR(void)\r
+{\r
+ //\r
+ // Enter an infinite loop.\r
+ //\r
+ while(1)\r
+ {\r
+ }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+// This is the code that gets called when the processor receives an unexpected\r
+// interrupt. This simply enters an infinite loop, preserving the system state\r
+// for examination by a debugger.\r
+//\r
+//*****************************************************************************\r
+static void\r
+IntDefaultHandler(void)\r
+{\r
+ //\r
+ // Go into an infinite loop.\r
+ //\r
+ while(1)\r
+ {\r
+ }\r
+}\r
--- /dev/null
+/*\r
+ FreeRTOS.org V4.1.3 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+\r
+/*\r
+ * This project contains an application demonstrating the use of the\r
+ * FreeRTOS.org mini real time scheduler on the Luminary Micro LM3S811 Eval\r
+ * board. See http://www.FreeRTOS.org for more information.\r
+ *\r
+ * main() simply sets up the hardware, creates all the demo application tasks,\r
+ * then starts the scheduler. http://www.freertos.org/a00102.html provides\r
+ * more information on the standard demo tasks.\r
+ *\r
+ * In addition to a subset of the standard demo application tasks, main.c also\r
+ * defines the following tasks:\r
+ *\r
+ * + A 'Print' task. The print task is the only task permitted to access the\r
+ * LCD - thus ensuring mutual exclusion and consistent access to the resource.\r
+ * Other tasks do not access the LCD directly, but instead send the text they\r
+ * wish to display to the print task. The print task spends most of its time\r
+ * blocked - only waking when a message is queued for display.\r
+ *\r
+ * + A 'Button handler' task. The eval board contains a user push button that\r
+ * is configured to generate interrupts. The interrupt handler uses a\r
+ * semaphore to wake the button handler task - demonstrating how the priority\r
+ * mechanism can be used to defer interrupt processing to the task level. The\r
+ * button handler task sends a message both to the LCD (via the print task) and\r
+ * the UART where it can be viewed using a dumb terminal (via the UART to USB\r
+ * converter on the eval board). NOTES: The dumb terminal must be closed in\r
+ * order to reflash the microcontroller. A very basic interrupt driven UART\r
+ * driver is used that does not use the FIFO. 19200 baud is used.\r
+ *\r
+ * + A 'check' task. The check task only executes every five seconds but has a\r
+ * high priority so is guaranteed to get processor time. Its function is to\r
+ * check that all the other tasks are still operational and that no errors have\r
+ * been detected at any time. If no errors have every been detected 'PASS' is\r
+ * written to the display (via the print task) - if an error has ever been\r
+ * detected the message is changed to 'FAIL'. The position of the message is\r
+ * changed for each write.\r
+ */\r
+\r
+\r
+\r
+/* Environment includes. */\r
+#include "DriverLib.h"\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "queue.h"\r
+#include "semphr.h"\r
+\r
+/* Demo app includes. */\r
+#include "integer.h"\r
+#include "PollQ.h"\r
+#include "semtest.h"\r
+#include "BlockQ.h"\r
+\r
+/* Delay between cycles of the 'check' task. */\r
+#define mainCHECK_DELAY ( ( portTickType ) 5000 / portTICK_RATE_MS )\r
+\r
+/* UART configuration - note this does not use the FIFO so is not very\r
+efficient. */\r
+#define mainBAUD_RATE ( 19200 )\r
+#define mainFIFO_SET ( 0x10 )\r
+\r
+/* Demo task priorities. */\r
+#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )\r
+#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+\r
+/* Demo board specifics. */\r
+#define mainPUSH_BUTTON GPIO_PIN_4\r
+\r
+/* Misc. */\r
+#define mainQUEUE_SIZE ( 3 )\r
+#define mainDEBOUNCE_DELAY ( ( portTickType ) 150 / portTICK_RATE_MS )\r
+#define mainNO_DELAY ( ( portTickType ) 0 )\r
+/*\r
+ * Configure the processor and peripherals for this demo.\r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+/*\r
+ * The 'check' task, as described at the top of this file.\r
+ */\r
+static void vCheckTask( void *pvParameters );\r
+\r
+/*\r
+ * The task that is woken by the ISR that processes GPIO interrupts originating\r
+ * from the push button.\r
+ */\r
+static void vButtonHandlerTask( void *pvParameters );\r
+\r
+/*\r
+ * The task that controls access to the LCD.\r
+ */\r
+static void vPrintTask( void *pvParameter );\r
+\r
+/* String that is transmitted on the UART. */\r
+static portCHAR *cMessage = "Task woken by button interrupt! --- ";\r
+static volatile portCHAR *pcNextChar;\r
+\r
+/* The semaphore used to wake the button handler task from within the GPIO\r
+interrupt handler. */\r
+xSemaphoreHandle xButtonSemaphore;\r
+\r
+/* The queue used to send strings to the print task for display on the LCD. */\r
+xQueueHandle xPrintQueue;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+int main( void )\r
+{\r
+ /* Configure the clocks, UART and GPIO. */\r
+ prvSetupHardware();\r
+\r
+ /* Create the semaphore used to wake the button handler task from the GPIO\r
+ ISR. */\r
+ vSemaphoreCreateBinary( xButtonSemaphore );\r
+ xSemaphoreTake( xButtonSemaphore, 0 );\r
+\r
+ /* Create the queue used to pass message to vPrintTask. */\r
+ xPrintQueue = xQueueCreate( mainQUEUE_SIZE, sizeof( portCHAR * ) );\r
+\r
+ /* Start the standard demo tasks. */\r
+ vStartIntegerMathTasks( tskIDLE_PRIORITY );\r
+ vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );\r
+ vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );\r
+ vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
+\r
+ /* Start the tasks defined within the file. */\r
+ xTaskCreate( vCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );\r
+ xTaskCreate( vButtonHandlerTask, "Status", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY + 1, NULL );\r
+ xTaskCreate( vPrintTask, "Print", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY - 1, NULL );\r
+\r
+ /* Start the scheduler. */\r
+ vTaskStartScheduler();\r
+\r
+ /* Will only get here if there was insufficient heap to start the\r
+ scheduler. */\r
+\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vCheckTask( void *pvParameters )\r
+{\r
+portBASE_TYPE xErrorOccurred = pdFALSE;\r
+portTickType xLastExecutionTime;\r
+const portCHAR *pcPassMessage = "PASS";\r
+const portCHAR *pcFailMessage = "FAIL";\r
+\r
+ /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil()\r
+ works correctly. */\r
+ xLastExecutionTime = xTaskGetTickCount();\r
+\r
+ for( ;; )\r
+ {\r
+ /* Perform this check every mainCHECK_DELAY milliseconds. */\r
+ vTaskDelayUntil( &xLastExecutionTime, mainCHECK_DELAY );\r
+\r
+ /* Has an error been found in any task? */\r
+\r
+ if( xAreIntegerMathsTaskStillRunning() != pdTRUE )\r
+ {\r
+ xErrorOccurred = pdTRUE;\r
+ }\r
+ \r
+ if( xArePollingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ xErrorOccurred = pdTRUE;\r
+ }\r
+ \r
+ if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
+ {\r
+ xErrorOccurred = pdTRUE;\r
+ }\r
+\r
+ if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ xErrorOccurred = pdTRUE;\r
+ }\r
+\r
+ /* Send either a pass or fail message. If an error is found it is\r
+ never cleared again. We do not write directly to the LCD, but instead\r
+ queue a message for display by the print task. */\r
+ if( xErrorOccurred == pdTRUE )\r
+ {\r
+ xQueueSend( xPrintQueue, &pcFailMessage, portMAX_DELAY );\r
+ }\r
+ else\r
+ {\r
+ xQueueSend( xPrintQueue, &pcPassMessage, portMAX_DELAY );\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupHardware( void )\r
+{\r
+ /* Setup the PLL. */\r
+ SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ );\r
+\r
+ /* Setup the push button. */\r
+ SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC);\r
+ GPIODirModeSet(GPIO_PORTC_BASE, mainPUSH_BUTTON, GPIO_DIR_MODE_IN);\r
+ GPIOIntTypeSet( GPIO_PORTC_BASE, mainPUSH_BUTTON,GPIO_FALLING_EDGE );\r
+ GPIOPinIntEnable( GPIO_PORTC_BASE, mainPUSH_BUTTON );\r
+ IntEnable( INT_GPIOC );\r
+\r
+\r
+\r
+ /* Enable the UART. */\r
+ SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0);\r
+ SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);\r
+\r
+ /* Set GPIO A0 and A1 as peripheral function. They are used to output the\r
+ UART signals. */\r
+ GPIODirModeSet( GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1, GPIO_DIR_MODE_HW );\r
+\r
+ /* Configure the UART for 8-N-1 operation. */\r
+ UARTConfigSet( UART0_BASE, mainBAUD_RATE, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE );\r
+\r
+ /* We don't want to use the fifo. This is for test purposes to generate\r
+ as many interrupts as possible. */\r
+ HWREG( UART0_BASE + UART_O_LCR_H ) &= ~mainFIFO_SET;\r
+\r
+ /* Enable Tx interrupts. */\r
+ HWREG( UART0_BASE + UART_O_IM ) |= UART_INT_TX;\r
+ IntEnable( INT_UART0 );\r
+\r
+\r
+ /* Initialise the LCD> */\r
+ OSRAMInit( false );\r
+ OSRAMStringDraw("www.FreeRTOS.org", 0, 0);\r
+ OSRAMStringDraw("LM3S811 demo", 16, 1);\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vButtonHandlerTask( void *pvParameters )\r
+{\r
+const portCHAR *pcInterruptMessage = "Int";\r
+\r
+ for( ;; )\r
+ {\r
+ /* Wait for a GPIO interrupt to wake this task. */\r
+ while( xSemaphoreTake( xButtonSemaphore, portMAX_DELAY ) != pdPASS );\r
+\r
+ /* Start the Tx of the message on the UART. */\r
+ UARTIntDisable( UART0_BASE, UART_INT_TX );\r
+ {\r
+ pcNextChar = cMessage;\r
+\r
+ /* Send the first character. */\r
+ if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) )\r
+ {\r
+ HWREG( UART0_BASE + UART_O_DR ) = *pcNextChar;\r
+ }\r
+\r
+ pcNextChar++;\r
+ }\r
+ UARTIntEnable(UART0_BASE, UART_INT_TX);\r
+\r
+ /* Queue a message for the print task to display on the LCD. */\r
+ xQueueSend( xPrintQueue, &pcInterruptMessage, portMAX_DELAY );\r
+\r
+ /* Make sure we don't process bounces. */\r
+ vTaskDelay( mainDEBOUNCE_DELAY );\r
+ xSemaphoreTake( xButtonSemaphore, mainNO_DELAY );\r
+ }\r
+}\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vUART_ISR(void)\r
+{\r
+unsigned portLONG ulStatus;\r
+\r
+ /* What caused the interrupt. */\r
+ ulStatus = UARTIntStatus( UART0_BASE, pdTRUE );\r
+\r
+ /* Clear the interrupt. */\r
+ UARTIntClear( UART0_BASE, ulStatus );\r
+\r
+ /* Was a Tx interrupt pending? */\r
+ if( ulStatus & UART_INT_TX )\r
+ {\r
+ /* Send the next character in the string. We are not using the FIFO. */\r
+ if( *pcNextChar != 0 )\r
+ {\r
+ if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) )\r
+ {\r
+ HWREG( UART0_BASE + UART_O_DR ) = *pcNextChar;\r
+ }\r
+ pcNextChar++;\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vGPIO_ISR( void )\r
+{\r
+ /* Clear the interrupt. */\r
+ GPIOPinIntClear(GPIO_PORTC_BASE, mainPUSH_BUTTON);\r
+\r
+ /* Wake the button handler task. */\r
+ if( xSemaphoreGiveFromISR( xButtonSemaphore, pdFALSE ) )\r
+ {\r
+ portEND_SWITCHING_ISR( pdTRUE );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vPrintTask( void *pvParameters )\r
+{\r
+portCHAR *pcMessage;\r
+unsigned portBASE_TYPE uxLine = 0, uxRow = 0;\r
+\r
+ for( ;; )\r
+ {\r
+ /* Wait for a message to arrive. */\r
+ xQueueReceive( xPrintQueue, &pcMessage, portMAX_DELAY );\r
+\r
+ /* Write the message to the LCD. */\r
+ uxRow++;\r
+ uxLine++;\r
+ OSRAMClear();\r
+ OSRAMStringDraw( pcMessage, uxLine & 0x3f, uxRow & 0x01);\r
+ }\r
+}\r
+\r
--- /dev/null
+#******************************************************************************
+#
+# makedefs - Definitions common to all makefiles.
+#
+# Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
+#
+# Software License Agreement
+#
+# Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+# exclusively on LMI's Stellaris Family of microcontroller products.
+#
+# The software is owned by LMI and/or its suppliers, and is protected under
+# applicable copyright laws. All rights are reserved. Any use in violation
+# of the foregoing restrictions may subject the user to criminal sanctions
+# under applicable laws, as well as to civil liability for the breach of the
+# terms and conditions of this license.
+#
+# THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+# OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+# LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+# CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+#
+#******************************************************************************
+
+#******************************************************************************
+#
+# Get the operating system name. If this is Cygwin, the .d files will be
+# munged to convert c: into /cygdrive/c so that "make" will be happy with the
+# auto-generated dependencies.
+#
+#******************************************************************************
+os:=${shell uname -s}
+
+#******************************************************************************
+#
+# The compiler to be used.
+#
+#******************************************************************************
+ifndef COMPILER
+COMPILER=gcc
+endif
+
+#******************************************************************************
+#
+# The debugger to be used.
+#
+#******************************************************************************
+ifndef DEBUGGER
+DEBUGGER=gdb
+endif
+
+#******************************************************************************
+#
+# Definitions for using GCC.
+#
+#******************************************************************************
+ifeq (${COMPILER}, gcc)
+
+#
+# The command for calling the compiler.
+#
+CC=arm-stellaris-eabi-gcc
+
+#
+# The flags passed to the assembler.
+#
+AFLAGS=-mthumb \
+ -mcpu=cortex-m3 \
+ -MD
+
+#
+# The flags passed to the compiler.
+#
+CFLAGS=-mthumb \
+ -mcpu=cortex-m3 \
+ -O2 \
+ -MD
+
+#
+# The command for calling the library archiver.
+#
+AR=arm-stellaris-eabi-ar
+
+#
+# The command for calling the linker.
+#
+LD=arm-stellaris-eabi-ld
+
+#
+# The flags passed to the linker.
+#
+LDFLAGS= -Map gcc/out.map
+
+#
+# Get the location of libgcc.a from the GCC front-end.
+#
+LIBGCC=${shell ${CC} -mthumb -march=armv6t2 -print-libgcc-file-name}
+
+#
+# Get the location of libc.a from the GCC front-end.
+#
+LIBC=${shell ${CC} -mthumb -march=armv6t2 -print-file-name=libc.a}
+
+#
+# The command for extracting images from the linked executables.
+#
+OBJCOPY=arm-stellaris-eabi-objcopy
+
+endif
+
+#******************************************************************************
+#
+# Tell the compiler to include debugging information if the DEBUG environment
+# variable is set.
+#
+#******************************************************************************
+ifdef DEBUG
+CFLAGS += -g
+endif
+
+#******************************************************************************
+#
+# The rule for building the object file from each C source file.
+#
+#******************************************************************************
+${COMPILER}/%.o: %.c
+ @if [ 'x${VERBOSE}' = x ]; \
+ then \
+ echo " CC ${<}"; \
+ else \
+ echo ${CC} ${CFLAGS} -D${COMPILER} -o ${@} -c ${<}; \
+ fi
+ @${CC} ${CFLAGS} -D${COMPILER} -o ${@} -c ${<}
+ifeq (${COMPILER}, rvds)
+ @mv -f ${notdir ${@:.o=.d}} ${COMPILER}
+endif
+ifneq ($(findstring CYGWIN, ${os}), )
+ @perl -i.bak -p -e 's/[Cc]:/\/cygdrive\/c/g' ${@:.o=.d}
+endif
+
+#******************************************************************************
+#
+# The rule for building the object file from each assembly source file.
+#
+#******************************************************************************
+${COMPILER}/%.o: %.S
+ @if [ 'x${VERBOSE}' = x ]; \
+ then \
+ echo " CC ${<}"; \
+ else \
+ echo ${CC} ${AFLAGS} -D${COMPILER} -o ${@} -c ${<}; \
+ fi
+ifeq (${COMPILER}, rvds)
+ @${CC} ${AFLAGS} -D${COMPILER} -E ${<} > ${@:.o=_.S}
+ @${CC} ${AFLAGS} -o ${@} -c ${@:.o=_.S}
+ @rm ${@:.o=_.S}
+ @${CC} ${AFLAGS} -D${COMPILER} --md -E ${<}
+ @sed 's,<stdout>,${@},g' ${notdir ${<:.S=.d}} > ${@:.o=.d}
+ @rm ${notdir ${<:.S=.d}}
+endif
+ifeq (${COMPILER}, gcc)
+ @${CC} ${AFLAGS} -D${COMPILER} -o ${@} -c ${<}
+endif
+ifneq ($(findstring CYGWIN, ${os}), )
+ @perl -i.bak -p -e 's/[Cc]:/\/cygdrive\/c/g' ${@:.o=.d}
+endif
+
+#******************************************************************************
+#
+# The rule for creating an object library.
+#
+#******************************************************************************
+${COMPILER}/%.a:
+ @if [ 'x${VERBOSE}' = x ]; \
+ then \
+ echo " AR ${@}"; \
+ else \
+ echo ${AR} -cr ${@} ${^}; \
+ fi
+ @${AR} -cr ${@} ${^}
+
+#******************************************************************************
+#
+# The rule for linking the application.
+#
+#******************************************************************************
+${COMPILER}/%.axf:
+ @if [ 'x${VERBOSE}' = x ]; \
+ then \
+ echo " LD ${@}"; \
+ fi
+ifeq (${COMPILER}, gcc)
+ @if [ 'x${VERBOSE}' != x ]; \
+ then \
+ echo ${LD} -T ${SCATTER_${notdir ${@:.axf=}}} \
+ --entry ${ENTRY_${notdir ${@:.axf=}}} \
+ ${LDFLAGSgcc_${notdir ${@:.axf=}}} \
+ ${LDFLAGS} -o ${@} ${^} \
+ '${LIBC}' '${LIBGCC}'; \
+ fi
+ @${LD} -T ${SCATTER_${notdir ${@:.axf=}}} \
+ --entry ${ENTRY_${notdir ${@:.axf=}}} \
+ ${LDFLAGSgcc_${notdir ${@:.axf=}}} \
+ ${LDFLAGS} -o ${@} ${^} \
+ '${LIBC}' '${LIBGCC}'
+ @${OBJCOPY} -O binary ${@} ${@:.axf=.bin}
+endif
--- /dev/null
+/******************************************************************************\r
+ *\r
+ * standalone.ld - Linker script for applications using startup.c and\r
+ * DriverLib.\r
+ *\r
+ * Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+ *\r
+ * Software License Agreement\r
+ *\r
+ * Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+ * exclusively on LMI's microcontroller products.\r
+ *\r
+ * The software is owned by LMI and/or its suppliers, and is protected under\r
+ * applicable copyright laws. All rights are reserved. Any use in violation\r
+ * of the foregoing restrictions may subject the user to criminal sanctions\r
+ * under applicable laws, as well as to civil liability for the breach of the\r
+ * terms and conditions of this license.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ * This is part of revision 1049 of the Stellaris Driver Library.\r
+ *\r
+ *****************************************************************************/\r
+\r
+MEMORY\r
+{\r
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K\r
+ SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 8K\r
+}\r
+\r
+SECTIONS\r
+{\r
+ .text :\r
+ {\r
+ KEEP(*(.isr_vector))\r
+ *(.text)\r
+ *(.rodata*)\r
+ _etext = .;\r
+ } > FLASH\r
+\r
+ .data : AT (ADDR(.text) + SIZEOF(.text))\r
+ {\r
+ _data = .;\r
+ *(vtable)\r
+ *(.data)\r
+ _edata = .;\r
+ } > SRAM\r
+\r
+ .bss :\r
+ {\r
+ _bss = .;\r
+ *(.bss)\r
+ *(COMMON)\r
+ _ebss = .;\r
+ } > SRAM\r
+}\r
projects / freertos / commitdiff