/*\r
- FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
-//*****************************************************************************
-//
-// startup.c - Boot code for Stellaris.
-//
-// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
-//
-// Software License Agreement
-//
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's Stellaris Family of microcontroller products.
-//
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws. All rights are reserved. Any use in violation
-// of the foregoing restrictions may subject the user to criminal sanctions
-// under applicable laws, as well as to civil liability for the breach of the
-// terms and conditions of this license.
-//
-// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-//
-//*****************************************************************************
-
-//*****************************************************************************
-//
-// Forward declaration of the default fault handlers.
-//
-//*****************************************************************************
-void ResetISR(void);
-static void NmiSR(void);
-void FaultISR(void);
-extern void xPortPendSVHandler(void);
-extern void xPortSysTickHandler(void);
-extern void vUART_ISR( void );
-
-//*****************************************************************************
-//
-// The entry point for the application.
-//
-//*****************************************************************************
-extern void entry(void);
-
-//*****************************************************************************
-//
-// Reserve space for the system stack.
-//
-//*****************************************************************************
-#ifndef STACK_SIZE
-#define STACK_SIZE 51
-#endif
-static unsigned long pulMainStack[STACK_SIZE];
-
-//*****************************************************************************
-//
-// The minimal vector table for a Cortex M3. Note that the proper constructs
-// must be placed on this to ensure that it ends up at physical address
-// 0x0000.0000.
-//
-//*****************************************************************************
-__attribute__ ((section("vectors")))
-void (* const g_pfnVectors[])(void) =
-{
- (void (*)(void))((unsigned long)pulMainStack + sizeof(pulMainStack)),
- ResetISR,
- NmiSR,
- FaultISR, //FAULT
- 0, // The MPU fault handler
- 0, // The bus fault handler
- 0, // The usage fault handler
- 0, // Reserved
- 0, // Reserved
- 0, // Reserved
- 0, // Reserved
- 0, // SVCall handler
- 0, // Debug monitor handler
- 0, // Reserved
- xPortPendSVHandler, // The PendSV handler
- xPortSysTickHandler, // The SysTick handler
- 0, // GPIO Port A
- 0, // GPIO Port B
- 0, // GPIO Port C
- 0, // GPIO Port D
- 0, // GPIO Port E
- vUART_ISR // UART0 Rx and Tx
-};
-
-//*****************************************************************************
-//
-// The following are constructs created by the linker, indicating where the
-// the "data" and "bss" segments reside in memory. The initializers for the
-// for the "data" segment resides immediately following the "text" segment.
-//
-//*****************************************************************************
-extern unsigned long _etext;
-extern unsigned long _data;
-extern unsigned long _edata;
-extern unsigned long _bss;
-extern unsigned long _ebss;
-
-//*****************************************************************************
-//
-// This is the code that gets called when the processor first starts execution
-// following a reset event. Only the absolutely necessary set is performed,
-// after which the application supplied entry() routine is called. Any fancy
-// actions (such as making decisions based on the reset cause register, and
-// resetting the bits in that register) are left solely in the hands of the
-// application.
-//
-//*****************************************************************************
-void
-ResetISR(void)
-{
- unsigned long *pulSrc, *pulDest;
-
- //
- // Copy the data segment initializers from flash to SRAM.
- //
- pulSrc = &_etext;
- for(pulDest = &_data; pulDest < &_edata; )
- {
- *pulDest++ = *pulSrc++;
- }
-
- //
- // Zero fill the bss segment.
- //
- for(pulDest = &_bss; pulDest < &_ebss; )
- {
- *pulDest++ = 0;
- }
-
- //
- // Call the application's entry point.
- //
- Main();
-}
-
-//*****************************************************************************
-//
-// This is the code that gets called when the processor receives a NMI. This
-// simply enters an infinite loop, preserving the system state for examination
-// by a debugger.
-//
-//*****************************************************************************
-static void
-NmiSR(void)
-{
- //
- // Enter an infinite loop.
- //
- while(1)
- {
- }
-}
-
-//*****************************************************************************
-//
-// This is the code that gets called when the processor receives a fault
-// interrupt. This simply enters an infinite loop, preserving the system state
-// for examination by a debugger.
-//
-//*****************************************************************************
-void
-FaultISR(void)
-{
- //
- // Enter an infinite loop.
- //
- while(1)
- {
- }
-}
+//*****************************************************************************\r
+//\r
+// startup.c - Boot code for Stellaris.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+// Forward declaration of the default fault handlers.\r
+//\r
+//*****************************************************************************\r
+void ResetISR(void);\r
+static void NmiSR(void);\r
+void FaultISR(void);\r
+extern void xPortPendSVHandler(void);\r
+extern void xPortSysTickHandler(void);\r
+extern void vUART_ISR( void );\r
+\r
+//*****************************************************************************\r
+//\r
+// The entry point for the application.\r
+//\r
+//*****************************************************************************\r
+extern void entry(void);\r
+\r
+//*****************************************************************************\r
+//\r
+// Reserve space for the system stack.\r
+//\r
+//*****************************************************************************\r
+#ifndef STACK_SIZE\r
+#define STACK_SIZE 51\r
+#endif\r
+static unsigned long pulMainStack[STACK_SIZE];\r
+\r
+//*****************************************************************************\r
+//\r
+// The minimal vector table for a Cortex M3. Note that the proper constructs\r
+// must be placed on this to ensure that it ends up at physical address\r
+// 0x0000.0000.\r
+//\r
+//*****************************************************************************\r
+__attribute__ ((section("vectors")))\r
+void (* const g_pfnVectors[])(void) =\r
+{\r
+ (void (*)(void))((unsigned long)pulMainStack + sizeof(pulMainStack)),\r
+ ResetISR,\r
+ NmiSR,\r
+ FaultISR, //FAULT\r
+ 0, // The MPU fault handler\r
+ 0, // The bus fault handler\r
+ 0, // The usage fault handler\r
+ 0, // Reserved\r
+ 0, // Reserved\r
+ 0, // Reserved\r
+ 0, // Reserved\r
+ 0, // SVCall handler\r
+ 0, // Debug monitor handler\r
+ 0, // Reserved\r
+ xPortPendSVHandler, // The PendSV handler\r
+ xPortSysTickHandler, // The SysTick handler\r
+ 0, // GPIO Port A\r
+ 0, // GPIO Port B\r
+ 0, // GPIO Port C\r
+ 0, // GPIO Port D\r
+ 0, // GPIO Port E\r
+ vUART_ISR // UART0 Rx and Tx\r
+};\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are constructs created by the linker, indicating where the\r
+// the "data" and "bss" segments reside in memory. The initializers for the\r
+// for the "data" segment resides immediately following the "text" segment.\r
+//\r
+//*****************************************************************************\r
+extern unsigned long _etext;\r
+extern unsigned long _data;\r
+extern unsigned long _edata;\r
+extern unsigned long _bss;\r
+extern unsigned long _ebss;\r
+\r
+//*****************************************************************************\r
+//\r
+// This is the code that gets called when the processor first starts execution\r
+// following a reset event. Only the absolutely necessary set is performed,\r
+// after which the application supplied entry() routine is called. Any fancy\r
+// actions (such as making decisions based on the reset cause register, and\r
+// resetting the bits in that register) are left solely in the hands of the\r
+// application.\r
+//\r
+//*****************************************************************************\r
+void\r
+ResetISR(void)\r
+{\r
+ unsigned long *pulSrc, *pulDest;\r
+\r
+ //\r
+ // Copy the data segment initializers from flash to SRAM.\r
+ //\r
+ pulSrc = &_etext;\r
+ for(pulDest = &_data; pulDest < &_edata; )\r
+ {\r
+ *pulDest++ = *pulSrc++;\r
+ }\r
+\r
+ //\r
+ // Zero fill the bss segment.\r
+ //\r
+ for(pulDest = &_bss; pulDest < &_ebss; )\r
+ {\r
+ *pulDest++ = 0;\r
+ }\r
+\r
+ //\r
+ // Call the application's entry point.\r
+ //\r
+ Main();\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+// This is the code that gets called when the processor receives a NMI. This\r
+// simply enters an infinite loop, preserving the system state for examination\r
+// by a debugger.\r
+//\r
+//*****************************************************************************\r
+static void\r
+NmiSR(void)\r
+{\r
+ //\r
+ // Enter an infinite loop.\r
+ //\r
+ while(1)\r
+ {\r
+ }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+// This is the code that gets called when the processor receives a fault\r
+// interrupt. This simply enters an infinite loop, preserving the system state\r
+// for examination by a debugger.\r
+//\r
+//*****************************************************************************\r
+void\r
+FaultISR(void)\r
+{\r
+ //\r
+ // Enter an infinite loop.\r
+ //\r
+ while(1)\r
+ {\r
+ }\r
+}\r
/*\r
- FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
-//*****************************************************************************
-//
-// pdc.c - Driver for the Peripheral Device Controller (PDC) on the Stellaris
-// development board.
-//
-// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
-//
-// Software License Agreement
-//
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's Stellaris Family of microcontroller products.
-//
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws. All rights are reserved. Any use in violation
-// of the foregoing restrictions may subject the user to criminal sanctions
-// under applicable laws, as well as to civil liability for the breach of the
-// terms and conditions of this license.
-//
-// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-//
-//*****************************************************************************
-
-#include "LM3Sxxx.h"
-#include "pdc.h"
-
-//*****************************************************************************
-//
-//! Initializes the connection to the PDC.
-//!
-//! This function will enable clocking to the SSI and GPIO A modules, configure
-//! the GPIO pins to be used for an SSI interface, and it will configure the
-//! SSI as a 1Mb master device, operating in MOTO mode. It will also enable
-//! the SSI module, and will enable the chip select for the PDC on the
-//! Stellaris development board.
-//!
-//! This function is contained in <tt>utils/pdc.c</tt>, with
-//! <tt>utils/pdc.h</tt> containing the API definition for use by applications.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-PDCInit(void)
-{
- //
- // Enable the peripherals used to drive the PDC.
- //
- SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI);
- SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
-
- //
- // Configure the appropriate pins to be SSI instead of GPIO.
- //
- GPIODirModeSet(GPIO_PORTA_BASE, SSI_CLK | SSI_TX | SSI_RX,
- GPIO_DIR_MODE_HW);
- GPIODirModeSet(GPIO_PORTA_BASE, SSI_CS, GPIO_DIR_MODE_OUT);
- GPIOPadConfigSet(GPIO_PORTA_BASE, SSI_CLK, GPIO_STRENGTH_4MA,
- GPIO_PIN_TYPE_STD_WPU);
-
- //
- // Configure the SSI port.
- //
- SSIConfig(SSI_BASE, SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, 1000000, 8);
- SSIEnable(SSI_BASE);
-
- //
- // Reset the PDC SSI state machine. The chip select needs to be held low
- // for 100ns; the procedure call overhead more than accounts for this time.
- //
- GPIOPinWrite(GPIO_PORTA_BASE, PDC_CS, 0);
- GPIOPinWrite(GPIO_PORTA_BASE, PDC_CS, PDC_CS);
-}
-
-//*****************************************************************************
-//
-//! Write a PDC register.
-//!
-//! \param ucAddr specifies the PDC register to write.
-//! \param ucData specifies the data to write.
-//!
-//! This function will perform the SSI transfers required to write a register
-//! in the PDC on the Stellaris development board.
-//!
-//! This function is contained in <tt>utils/pdc.c</tt>, with
-//! <tt>utils/pdc.h</tt> containing the API definition for use by applications.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-PDCWrite(unsigned char ucAddr, unsigned char ucData)
-{
- unsigned long ulTemp;
-
- //
- // Send address and write command.
- //
- SSIDataPut(SSI_BASE, (ucAddr & 0x0F) | PDC_WR);
-
- //
- // Write the data.
- //
- SSIDataPut(SSI_BASE, ucData);
-
- //
- // Flush data read during address write.
- //
- SSIDataGet(SSI_BASE, &ulTemp);
-
- //
- // Flush data read during data write.
- //
- SSIDataGet(SSI_BASE, &ulTemp);
+//*****************************************************************************\r
+//\r
+// pdc.c - Driver for the Peripheral Device Controller (PDC) on the Stellaris\r
+// development board.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+//*****************************************************************************\r
+\r
+#include "LM3Sxxx.h"\r
+#include "pdc.h"\r
+\r
+//*****************************************************************************\r
+//\r
+//! Initializes the connection to the PDC.\r
+//!\r
+//! This function will enable clocking to the SSI and GPIO A modules, configure\r
+//! the GPIO pins to be used for an SSI interface, and it will configure the\r
+//! SSI as a 1Mb master device, operating in MOTO mode. It will also enable\r
+//! the SSI module, and will enable the chip select for the PDC on the\r
+//! Stellaris development board.\r
+//!\r
+//! This function is contained in <tt>utils/pdc.c</tt>, with\r
+//! <tt>utils/pdc.h</tt> containing the API definition for use by applications.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+PDCInit(void)\r
+{\r
+ //\r
+ // Enable the peripherals used to drive the PDC.\r
+ //\r
+ SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI);\r
+ SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);\r
+\r
+ //\r
+ // Configure the appropriate pins to be SSI instead of GPIO.\r
+ //\r
+ GPIODirModeSet(GPIO_PORTA_BASE, SSI_CLK | SSI_TX | SSI_RX,\r
+ GPIO_DIR_MODE_HW);\r
+ GPIODirModeSet(GPIO_PORTA_BASE, SSI_CS, GPIO_DIR_MODE_OUT);\r
+ GPIOPadConfigSet(GPIO_PORTA_BASE, SSI_CLK, GPIO_STRENGTH_4MA,\r
+ GPIO_PIN_TYPE_STD_WPU);\r
+\r
+ //\r
+ // Configure the SSI port.\r
+ //\r
+ SSIConfig(SSI_BASE, SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, 1000000, 8);\r
+ SSIEnable(SSI_BASE);\r
+\r
+ //\r
+ // Reset the PDC SSI state machine. The chip select needs to be held low\r
+ // for 100ns; the procedure call overhead more than accounts for this time.\r
+ //\r
+ GPIOPinWrite(GPIO_PORTA_BASE, PDC_CS, 0);\r
+ GPIOPinWrite(GPIO_PORTA_BASE, PDC_CS, PDC_CS);\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Write a PDC register.\r
+//!\r
+//! \param ucAddr specifies the PDC register to write.\r
+//! \param ucData specifies the data to write.\r
+//!\r
+//! This function will perform the SSI transfers required to write a register\r
+//! in the PDC on the Stellaris development board.\r
+//!\r
+//! This function is contained in <tt>utils/pdc.c</tt>, with\r
+//! <tt>utils/pdc.h</tt> containing the API definition for use by applications.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+PDCWrite(unsigned char ucAddr, unsigned char ucData)\r
+{\r
+ unsigned long ulTemp;\r
+\r
+ //\r
+ // Send address and write command.\r
+ //\r
+ SSIDataPut(SSI_BASE, (ucAddr & 0x0F) | PDC_WR);\r
+\r
+ //\r
+ // Write the data.\r
+ //\r
+ SSIDataPut(SSI_BASE, ucData);\r
+\r
+ //\r
+ // Flush data read during address write.\r
+ //\r
+ SSIDataGet(SSI_BASE, &ulTemp);\r
+\r
+ //\r
+ // Flush data read during data write.\r
+ //\r
+ SSIDataGet(SSI_BASE, &ulTemp);\r
}\r
-//*****************************************************************************
-//
-// pdc.h - Stellaris development board Peripheral Device Controller definitions
-// and prototypes.
-//
-// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
-//
-// Software License Agreement
-//
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's Stellaris Family of microcontroller products.
-//
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws. All rights are reserved. Any use in violation
-// of the foregoing restrictions may subject the user to criminal sanctions
-// under applicable laws, as well as to civil liability for the breach of the
-// terms and conditions of this license.
-//
-// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-//
-//*****************************************************************************
-
-#ifndef __PDC_H__
-#define __PDC_H__
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-//*****************************************************************************
-//
-// The registers within the peripheral device controller.
-//
-//*****************************************************************************
-#define PDC_VER 0x0 // Version register
-#define PDC_CSR 0x1 // Command/Status register
-#define PDC_DSW 0x4 // DIP Switch register
-#define PDC_LED 0x5 // LED register
-#define PDC_LCD_CSR 0x6 // LCD Command/Status register
-#define PDC_LCD_RAM 0x7 // LCD RAM register
-#define PDC_GPXDAT 0x8 // GPIO X Data register
-#define PDC_GPXDIR 0x9 // GPIO X Direction register
-#define PDC_GPYDAT 0xA // GPIO Y Data register
-#define PDC_GPYDIR 0xB // GPIO Y Direction register
-#define PDC_GPZDAT 0xC // GPIO Z Data register
-#define PDC_GPZDIR 0xD // GPIO Z Direction register
-
-//*****************************************************************************
-//
-// Flags indicating a read or write to the peripheral device controller.
-//
-//*****************************************************************************
-#define PDC_RD 0x80 // PDC read command
-#define PDC_WR 0x00 // PDC write command
-
-//*****************************************************************************
-//
-// LCD panel (Crystalfontz CFAH1602B) commands, RS = 0
-//
-//*****************************************************************************
-#define LCD_CLEAR 0x01 // Clear display (0 fill DDRAM).
-#define LCD_HOME 0x02 // Cursor home.
-#define LCD_MODE 0x04 // Set entry mode (cursor dir)
-#define LCD_ON 0x08 // Set display, cursor, blinking
- // on/off
-#define LCD_CUR 0x10 // Cursor, display shift
-#define LCD_IF 0x20 // Set interface data length,
- // lines, font
-#define LCD_CGADDR 0x40 // Set CGRAM AC address
-#define LCD_DDADDR 0x80 // Set DDRAM AC address
-
-//*****************************************************************************
-//
-// LCD Status bit
-//
-//*****************************************************************************
-#define LCD_B_BUSY 0x80 // Busy flag.
-
-//*****************************************************************************
-//
-// The GPIO port A pin numbers for the various SSI signals.
-//
-//*****************************************************************************
-#define SSI_CS GPIO_PIN_3
-#define PDC_CS GPIO_PIN_3
-#define SSI_CLK GPIO_PIN_2
-#define SSI_TX GPIO_PIN_5
-#define SSI_RX GPIO_PIN_4
-
-//*****************************************************************************
-//
-// Function Prototypes
-//
-//*****************************************************************************
-extern void PDCInit(void);
-extern unsigned char PDCRead(unsigned char ucAddr);
-extern void PDCWrite(unsigned char ucAddr, unsigned char ucData);
-extern unsigned char PDCDIPRead(void);
-extern void PDCLEDWrite(unsigned char ucLED);
-extern unsigned char PDCLEDRead(void);
-extern void PDCLCDInit(void);
-extern void PDCLCDBacklightOn(void);
-extern void PDCLCDBacklightOff(void);
-extern void PDCLCDClear(void);
-extern void PDCLCDCreateChar(unsigned char ucChar, unsigned char *pucData);
-extern void PDCLCDSetPos(unsigned char ucX, unsigned char ucY);
-extern void PDCLCDWrite(const char *pcStr, unsigned long ulCount);
-extern unsigned char PDCGPIODirRead(unsigned char ucIdx);
-extern void PDCGPIODirWrite(unsigned char ucIdx, unsigned char ucValue);
-extern unsigned char PDCGPIORead(unsigned char ucIdx);
-extern void PDCGPIOWrite(unsigned char ucIdx, unsigned char ucValue);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif // __PDC_H__
+//*****************************************************************************\r
+//\r
+// pdc.h - Stellaris development board Peripheral Device Controller definitions\r
+// and prototypes.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __PDC_H__\r
+#define __PDC_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// The registers within the peripheral device controller.\r
+//\r
+//*****************************************************************************\r
+#define PDC_VER 0x0 // Version register\r
+#define PDC_CSR 0x1 // Command/Status register\r
+#define PDC_DSW 0x4 // DIP Switch register\r
+#define PDC_LED 0x5 // LED register\r
+#define PDC_LCD_CSR 0x6 // LCD Command/Status register\r
+#define PDC_LCD_RAM 0x7 // LCD RAM register\r
+#define PDC_GPXDAT 0x8 // GPIO X Data register\r
+#define PDC_GPXDIR 0x9 // GPIO X Direction register\r
+#define PDC_GPYDAT 0xA // GPIO Y Data register\r
+#define PDC_GPYDIR 0xB // GPIO Y Direction register\r
+#define PDC_GPZDAT 0xC // GPIO Z Data register\r
+#define PDC_GPZDIR 0xD // GPIO Z Direction register\r
+\r
+//*****************************************************************************\r
+//\r
+// Flags indicating a read or write to the peripheral device controller.\r
+//\r
+//*****************************************************************************\r
+#define PDC_RD 0x80 // PDC read command\r
+#define PDC_WR 0x00 // PDC write command\r
+\r
+//*****************************************************************************\r
+//\r
+// LCD panel (Crystalfontz CFAH1602B) commands, RS = 0\r
+//\r
+//*****************************************************************************\r
+#define LCD_CLEAR 0x01 // Clear display (0 fill DDRAM).\r
+#define LCD_HOME 0x02 // Cursor home.\r
+#define LCD_MODE 0x04 // Set entry mode (cursor dir)\r
+#define LCD_ON 0x08 // Set display, cursor, blinking\r
+ // on/off\r
+#define LCD_CUR 0x10 // Cursor, display shift\r
+#define LCD_IF 0x20 // Set interface data length,\r
+ // lines, font\r
+#define LCD_CGADDR 0x40 // Set CGRAM AC address\r
+#define LCD_DDADDR 0x80 // Set DDRAM AC address\r
+\r
+//*****************************************************************************\r
+//\r
+// LCD Status bit\r
+//\r
+//*****************************************************************************\r
+#define LCD_B_BUSY 0x80 // Busy flag.\r
+\r
+//*****************************************************************************\r
+//\r
+// The GPIO port A pin numbers for the various SSI signals.\r
+//\r
+//*****************************************************************************\r
+#define SSI_CS GPIO_PIN_3\r
+#define PDC_CS GPIO_PIN_3\r
+#define SSI_CLK GPIO_PIN_2\r
+#define SSI_TX GPIO_PIN_5\r
+#define SSI_RX GPIO_PIN_4\r
+\r
+//*****************************************************************************\r
+//\r
+// Function Prototypes\r
+//\r
+//*****************************************************************************\r
+extern void PDCInit(void);\r
+extern unsigned char PDCRead(unsigned char ucAddr);\r
+extern void PDCWrite(unsigned char ucAddr, unsigned char ucData);\r
+extern unsigned char PDCDIPRead(void);\r
+extern void PDCLEDWrite(unsigned char ucLED);\r
+extern unsigned char PDCLEDRead(void);\r
+extern void PDCLCDInit(void);\r
+extern void PDCLCDBacklightOn(void);\r
+extern void PDCLCDBacklightOff(void);\r
+extern void PDCLCDClear(void);\r
+extern void PDCLCDCreateChar(unsigned char ucChar, unsigned char *pucData);\r
+extern void PDCLCDSetPos(unsigned char ucX, unsigned char ucY);\r
+extern void PDCLCDWrite(const char *pcStr, unsigned long ulCount);\r
+extern unsigned char PDCGPIODirRead(unsigned char ucIdx);\r
+extern void PDCGPIODirWrite(unsigned char ucIdx, unsigned char ucValue);\r
+extern unsigned char PDCGPIORead(unsigned char ucIdx);\r
+extern void PDCGPIOWrite(unsigned char ucIdx, unsigned char ucValue);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __PDC_H__\r
/*\r
- FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
projects / freertos / commitdiff