*/\r
void OLED_clear_display( oled_no_of_line LINES )\r
{\r
- uint8_t i, j,start_line,end_line;\r
+ uint8_t i, j,start_line = 0,end_line = 0;\r
uint8_t clear_8_columns[] =\r
{\r
OLED_DATA_CODE, 0x00,\r
+++ /dev/null
-/*******************************************************************************\r
- * (c) Copyright 2009 Actel Corporation. All rights reserved.\r
- * \r
- * SVN $Revision: 2840 $\r
- * SVN $Date: 2010-07-20 17:00:32 +0100 (Tue, 20 Jul 2010) $\r
- */\r
-#include "mss_ace.h"\r
-#include "mss_ace_configurator.h"\r
-#include "../../CMSIS/a2fxxxm3.h"\r
-#include "../../CMSIS/mss_assert.h"\r
-#include "../../drivers_config/mss_ace/ace_handles.h"\r
-#include "../../drivers_config/mss_ace/ace_config.h"\r
-#include <string.h>\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif \r
-\r
-#define MAX_FULL_FLAG_NAME_LENGTH (MAX_CHANNEL_NAME_LENGTH + MAX_FLAG_NAME_LENGTH + 1)\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- * Number of flag types supported.\r
- * the supported flag types are:\r
- * - BASIC_THRESHOLD_OVER\r
- * - BASIC_THRESHOLD_UNDER\r
- * - STATE_FILTERED_OVER\r
- * - STATE_FILTERED_UNDER\r
- * - DUAL_HYSTERESIS_OVER\r
- * - DUAL_HYSTERESIS_UNDER\r
- * - IPMI_HYSTERESIS_OVER\r
- * - IPMI_HYSTERESIS_UNDER\r
- */\r
-#define NB_OF_FLAG_TYPES 8\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- *\r
- */\r
-#define THRESHOLD_FLAG0 0u\r
-#define THRESHOLD_FLAG1 1u\r
-#define THRESHOLD_FLAG2 2u\r
-#define THRESHOLD_FLAG3 3u\r
-#define THRESHOLD_FLAG4 4u\r
-#define THRESHOLD_FLAG5 5u\r
-#define THRESHOLD_FLAG6 6u\r
-#define THRESHOLD_FLAG7 7u\r
-#define THRESHOLD_FLAG8 8u\r
-#define THRESHOLD_FLAG9 9u\r
-#define THRESHOLD_FLAG10 10u\r
-#define THRESHOLD_FLAG11 11u\r
-#define THRESHOLD_FLAG12 12u\r
-#define THRESHOLD_FLAG13 13u\r
-#define THRESHOLD_FLAG14 14u\r
-#define THRESHOLD_FLAG15 15u\r
-#define THRESHOLD_FLAG16 16u\r
-#define THRESHOLD_FLAG17 17u\r
-#define THRESHOLD_FLAG18 18u\r
-#define THRESHOLD_FLAG19 19u\r
-#define THRESHOLD_FLAG20 20u\r
-#define THRESHOLD_FLAG21 21u\r
-#define THRESHOLD_FLAG22 22u\r
-#define THRESHOLD_FLAG23 23u\r
-#define THRESHOLD_FLAG24 24u\r
-#define THRESHOLD_FLAG25 25u\r
-#define THRESHOLD_FLAG26 26u\r
-#define THRESHOLD_FLAG27 27u\r
-#define THRESHOLD_FLAG28 28u\r
-#define THRESHOLD_FLAG29 29u\r
-#define THRESHOLD_FLAG30 30u\r
-#define THRESHOLD_FLAG31 31u\r
-#define NB_OF_THRESHOLD_IRQ 32u\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- *\r
- */\r
-void ace_init_flags( void );\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- * Flag interrupots routines function prototypes\r
- */\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void ACE_PPE_Flag0_IRQHandler( void );\r
-#else\r
-void ACE_PPE_Flag0_IRQHandler( void );\r
-#endif\r
-\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void ACE_PPE_Flag1_IRQHandler( void );\r
-#else\r
-void ACE_PPE_Flag1_IRQHandler( void );\r
-#endif\r
-\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void ACE_PPE_Flag2_IRQHandler( void );\r
-#else\r
-void ACE_PPE_Flag2_IRQHandler( void );\r
-#endif\r
-\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void ACE_PPE_Flag3_IRQHandler( void );\r
-#else\r
-void ACE_PPE_Flag3_IRQHandler( void );\r
-#endif\r
-\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void ACE_PPE_Flag4_IRQHandler( void );\r
-#else\r
-void ACE_PPE_Flag4_IRQHandler( void );\r
-#endif\r
-\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void ACE_PPE_Flag5_IRQHandler( void );\r
-#else\r
-void ACE_PPE_Flag5_IRQHandler( void );\r
-#endif\r
-\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void ACE_PPE_Flag6_IRQHandler( void );\r
-#else\r
-void ACE_PPE_Flag6_IRQHandler( void );\r
-#endif\r
-\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void ACE_PPE_Flag7_IRQHandler( void );\r
-#else\r
-void ACE_PPE_Flag7_IRQHandler( void );\r
-#endif\r
-\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void ACE_PPE_Flag8_IRQHandler( void );\r
-#else\r
-void ACE_PPE_Flag8_IRQHandler( void );\r
-#endif\r
-\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void ACE_PPE_Flag9_IRQHandler( void );\r
-#else\r
-void ACE_PPE_Flag9_IRQHandler( void );\r
-#endif\r
-\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void ACE_PPE_Flag10_IRQHandler( void );\r
-#else\r
-void ACE_PPE_Flag10_IRQHandler( void );\r
-#endif\r
-\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void ACE_PPE_Flag11_IRQHandler( void );\r
-#else\r
-void ACE_PPE_Flag11_IRQHandler( void );\r
-#endif\r
-\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void ACE_PPE_Flag12_IRQHandler( void );\r
-#else\r
-void ACE_PPE_Flag12_IRQHandler( void );\r
-#endif\r
-\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void ACE_PPE_Flag13_IRQHandler( void );\r
-#else\r
-void ACE_PPE_Flag13_IRQHandler( void );\r
-#endif\r
-\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void ACE_PPE_Flag14_IRQHandler( void );\r
-#else\r
-void ACE_PPE_Flag14_IRQHandler( void );\r
-#endif\r
-\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void ACE_PPE_Flag15_IRQHandler( void );\r
-#else\r
-void ACE_PPE_Flag15_IRQHandler( void );\r
-#endif\r
-\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void ACE_PPE_Flag16_IRQHandler( void );\r
-#else\r
-void ACE_PPE_Flag16_IRQHandler( void );\r
-#endif\r
-\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void ACE_PPE_Flag17_IRQHandler( void );\r
-#else\r
-void ACE_PPE_Flag17_IRQHandler( void );\r
-#endif\r
-\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void ACE_PPE_Flag18_IRQHandler( void );\r
-#else\r
-void ACE_PPE_Flag18_IRQHandler( void );\r
-#endif\r
-\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void ACE_PPE_Flag19_IRQHandler( void );\r
-#else\r
-void ACE_PPE_Flag19_IRQHandler( void );\r
-#endif\r
-\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void ACE_PPE_Flag20_IRQHandler( void );\r
-#else\r
-void ACE_PPE_Flag20_IRQHandler( void );\r
-#endif\r
-\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void ACE_PPE_Flag21_IRQHandler( void );\r
-#else\r
-void ACE_PPE_Flag21_IRQHandler( void );\r
-#endif\r
-\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void ACE_PPE_Flag22_IRQHandler( void );\r
-#else\r
-void ACE_PPE_Flag22_IRQHandler( void );\r
-#endif\r
-\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void ACE_PPE_Flag23_IRQHandler( void );\r
-#else\r
-void ACE_PPE_Flag23_IRQHandler( void );\r
-#endif\r
-\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void ACE_PPE_Flag24_IRQHandler( void );\r
-#else\r
-void ACE_PPE_Flag24_IRQHandler( void );\r
-#endif\r
-\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void ACE_PPE_Flag25_IRQHandler( void );\r
-#else\r
-void ACE_PPE_Flag25_IRQHandler( void );\r
-#endif\r
-\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void ACE_PPE_Flag26_IRQHandler( void );\r
-#else\r
-void ACE_PPE_Flag26_IRQHandler( void );\r
-#endif\r
-\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void ACE_PPE_Flag27_IRQHandler( void );\r
-#else\r
-void ACE_PPE_Flag27_IRQHandler( void );\r
-#endif\r
-\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void ACE_PPE_Flag28_IRQHandler( void );\r
-#else\r
-void ACE_PPE_Flag28_IRQHandler( void );\r
-#endif\r
-\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void ACE_PPE_Flag29_IRQHandler( void );\r
-#else\r
-void ACE_PPE_Flag29_IRQHandler( void );\r
-#endif\r
-\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void ACE_PPE_Flag30_IRQHandler( void );\r
-#else\r
-void ACE_PPE_Flag30_IRQHandler( void );\r
-#endif\r
-\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void ACE_PPE_Flag31_IRQHandler( void );\r
-#else\r
-void ACE_PPE_Flag31_IRQHandler( void );\r
-#endif\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- *\r
- */\r
-#if (ACE_NB_OF_PPE_FLAGS > 0)\r
-extern ppe_flag_desc_t g_ppe_flags_desc_table[ACE_NB_OF_PPE_FLAGS];\r
-#endif\r
-\r
-extern ace_channel_desc_t g_ace_channel_desc_table[ACE_NB_OF_INPUT_CHANNELS];\r
-\r
-extern ace_adc_config_t g_ace_adc_config[ACE_NB_OF_ADC];\r
-\r
-#if (ACE_NB_OF_PPE_FLAGS > 0)\r
-/*-------------------------------------------------------------------------*//**\r
- Lookup table indexed on flag_id_t of the index of the flag's descriptor index\r
- in the flag descriptors table g_ppe_flags_desc_table[]\r
- */\r
-static ace_flag_handle_t g_ppe_flag_handles_lut[NB_OF_PPE_FLAGS];\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- *\r
- */\r
-static flag_isr_t g_ppe_flags_isr_lut[NB_OF_PPE_FLAGS];\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- *\r
- */\r
-static global_flag_isr_t g_ppe_global_flags_isr;\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- *\r
- */\r
-static channel_flag_isr_t g_ppe_channel_flags_isr_lut[ACE_NB_OF_INPUT_CHANNELS];\r
-#endif\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- Intialise the ACE driver's internal data structures used by flag control\r
- functions.\r
- */\r
-void ace_init_flags( void )\r
-{\r
- /* Ensure the generated ACE configuration files are consistent. */\r
- ASSERT(NB_OF_ACE_FLAG_HANDLES == ACE_NB_OF_PPE_FLAGS);\r
- \r
-#if (ACE_NB_OF_PPE_FLAGS > 0) \r
- {\r
- uint8_t flag_idx;\r
- uint8_t channel_idx;\r
- \r
- for ( flag_idx = 0u; flag_idx < (uint8_t)NB_OF_PPE_FLAGS; ++flag_idx )\r
- {\r
- g_ppe_flags_isr_lut[flag_idx] = 0;\r
- g_ppe_flag_handles_lut[flag_idx] = INVALID_FLAG_HANDLE;\r
- }\r
- \r
- for ( flag_idx = 0u; flag_idx < (uint8_t)ACE_NB_OF_PPE_FLAGS; ++flag_idx )\r
- {\r
- ASSERT( g_ppe_flags_desc_table[flag_idx].flag_id < NB_OF_PPE_FLAGS );\r
- g_ppe_flag_handles_lut[g_ppe_flags_desc_table[flag_idx].flag_id] = (ace_flag_handle_t)flag_idx;\r
- }\r
- \r
- for ( channel_idx = 0u; channel_idx < (uint8_t)ACE_NB_OF_INPUT_CHANNELS; ++channel_idx )\r
- {\r
- g_ppe_channel_flags_isr_lut[channel_idx] = 0;\r
- }\r
- \r
- g_ppe_global_flags_isr = 0u;\r
- }\r
-#endif\r
-}\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- *\r
- */\r
-uint32_t ACE_is_hysteresis_flag( ace_flag_handle_t flag_handle )\r
-{\r
- uint32_t hysteresis = 0u;\r
- \r
-#if (ACE_NB_OF_PPE_FLAGS > 0)\r
- ASSERT( flag_handle < NB_OF_ACE_FLAG_HANDLES );\r
- \r
- if ( g_ppe_flags_desc_table[flag_handle].flag_type >= DUAL_HYSTERESIS_OVER )\r
- {\r
- hysteresis = 1u;\r
- }\r
-#endif\r
- return hysteresis;\r
-}\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- *\r
- */\r
-uint32_t ACE_is_under_flag\r
-(\r
- ace_flag_handle_t flag_handle\r
-)\r
-{\r
- uint32_t is_under = 0;\r
- \r
-#if (ACE_NB_OF_PPE_FLAGS > 0)\r
- const uint32_t flag_type_lut[NB_OF_FLAG_TYPES] =\r
- {\r
- 0, /* BASIC_THRESHOLD_OVER */\r
- 1, /* BASIC_THRESHOLD_UNDER */\r
- 0, /* STATE_FILTERED_OVER */\r
- 1, /* STATE_FILTERED_UNDER */\r
- 0, /* DUAL_HYSTERESIS_OVER */\r
- 1, /* DUAL_HYSTERESIS_UNDER */\r
- 0, /* IPMI_HYSTERESIS_OVER */\r
- 1, /* IPMI_HYSTERESIS_UNDER */\r
- };\r
- \r
- ASSERT(flag_handle < ACE_NB_OF_PPE_FLAGS);\r
- if (flag_handle < ACE_NB_OF_PPE_FLAGS)\r
- {\r
- uint8_t flag_type;\r
- flag_type = g_ppe_flags_desc_table[flag_handle].flag_type;\r
- ASSERT(flag_type < NB_OF_FLAG_TYPES);\r
- if (flag_type < NB_OF_FLAG_TYPES)\r
- {\r
- is_under = flag_type_lut[flag_type];\r
- }\r
- }\r
-#endif\r
- return is_under;\r
-}\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- Mask of the threshold value bits within a PPE RAM meory location holding the\r
- threshold value for a flag.\r
- */\r
-#define PPE_RAM_THRESHOLD_MASK 0x0000FFFFuL\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- * TODO: handle IPMI hysteresis flags\r
- */\r
-void ACE_set_flag_threshold\r
-(\r
- ace_flag_handle_t flag_handle,\r
- uint16_t new_threshold\r
-)\r
-{\r
-#if (ACE_NB_OF_PPE_FLAGS > 0)\r
- uint16_t ppe_offset;\r
- \r
- ASSERT( flag_handle < NB_OF_ACE_FLAG_HANDLES );\r
- \r
- if ( flag_handle < NB_OF_ACE_FLAG_HANDLES )\r
- {\r
- \r
- ppe_offset = g_ppe_flags_desc_table[flag_handle].threshold_ppe_offset;\r
- \r
- if ( ACE_is_hysteresis_flag( flag_handle ) == 0u )\r
- {\r
- ACE->PPE_RAM_DATA[ppe_offset] = (ACE->PPE_RAM_DATA[ppe_offset] & (uint32_t)~PPE_RAM_THRESHOLD_MASK) + new_threshold;\r
- }\r
- else\r
- {\r
- uint16_t high_threshold;\r
- uint16_t low_threshold;\r
- ace_channel_handle_t channel_handle;\r
- uint16_t hysteresis;\r
- uint32_t adc_id;\r
- uint16_t adc_resolution;\r
- \r
- high_threshold = (uint16_t)(ACE->PPE_RAM_DATA[ppe_offset] & PPE_RAM_THRESHOLD_MASK);\r
- low_threshold = (uint16_t)(ACE->PPE_RAM_DATA[ppe_offset + 1u] & PPE_RAM_THRESHOLD_MASK);\r
- ASSERT(high_threshold > low_threshold);\r
- hysteresis = (uint16_t)(high_threshold - low_threshold) / 2u;\r
- \r
- channel_handle = g_ppe_flags_desc_table[flag_handle].channel_handle;\r
- adc_id = (uint32_t)(g_ace_channel_desc_table[channel_handle].signal_id) >> 4u;\r
- ASSERT( adc_id < (uint32_t)ACE_NB_OF_ADC );\r
- \r
- if ( adc_id < (uint32_t)ACE_NB_OF_ADC )\r
- {\r
- adc_resolution = g_ace_adc_config[adc_id].adc_resolution - 1u;\r
- \r
- high_threshold = new_threshold + hysteresis;\r
- if ( high_threshold > adc_resolution )\r
- {\r
- high_threshold = adc_resolution;\r
- }\r
- \r
- if ( hysteresis > new_threshold )\r
- {\r
- low_threshold = 1u;\r
- }\r
- else\r
- {\r
- low_threshold = new_threshold - hysteresis;\r
- }\r
- \r
- ACE->PPE_RAM_DATA[ppe_offset] = (ACE->PPE_RAM_DATA[ppe_offset] & ~PPE_RAM_THRESHOLD_MASK) + high_threshold;\r
- ACE->PPE_RAM_DATA[ppe_offset + 1u] = (ACE->PPE_RAM_DATA[ppe_offset + 1u] & (uint32_t)~PPE_RAM_THRESHOLD_MASK) + low_threshold;\r
- }\r
- }\r
- }\r
-#endif\r
-}\r
-\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- *\r
- */\r
-#define FLAG_OVER_UNDER_MASK 0x01u\r
-#define FLAG_OVER 0x00u\r
-#define FLAF_UNDER 0x01\r
-\r
-void ACE_set_flag_assertion\r
-(\r
- ace_flag_handle_t flag_handle,\r
- uint16_t assertion_value\r
-)\r
-{\r
-#if (ACE_NB_OF_PPE_FLAGS > 0)\r
- uint16_t ppe_offset;\r
- \r
- ASSERT( flag_handle < NB_OF_ACE_FLAG_HANDLES );\r
- \r
- if ( flag_handle < NB_OF_ACE_FLAG_HANDLES )\r
- {\r
- if (ACE_is_hysteresis_flag(flag_handle))\r
- {\r
- uint8_t flag_direction;\r
- flag_direction = g_ppe_flags_desc_table[flag_handle].flag_type & FLAG_OVER_UNDER_MASK;\r
- \r
- if ( FLAG_OVER == flag_direction )\r
- {\r
- ppe_offset = g_ppe_flags_desc_table[flag_handle].threshold_ppe_offset;\r
- }\r
- else\r
- {\r
- ppe_offset = g_ppe_flags_desc_table[flag_handle].threshold_ppe_offset + 1u;\r
- }\r
- }\r
- else\r
- {\r
- ppe_offset = g_ppe_flags_desc_table[flag_handle].threshold_ppe_offset;\r
- }\r
- ACE->PPE_RAM_DATA[ppe_offset] = (ACE->PPE_RAM_DATA[ppe_offset] & ~PPE_RAM_THRESHOLD_MASK) + assertion_value;\r
- }\r
-#endif\r
-}\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- *\r
- */\r
-void ACE_set_flag_deassertion\r
-(\r
- ace_flag_handle_t flag_handle,\r
- uint16_t assertion_value\r
-)\r
-{\r
-#if (ACE_NB_OF_PPE_FLAGS > 0)\r
- uint16_t ppe_offset;\r
- \r
- ASSERT( flag_handle < NB_OF_ACE_FLAG_HANDLES );\r
- ASSERT(ACE_is_hysteresis_flag(flag_handle));\r
- \r
- if ((flag_handle < NB_OF_ACE_FLAG_HANDLES) && (ACE_is_hysteresis_flag(flag_handle)))\r
- {\r
- uint8_t flag_direction;\r
- flag_direction = g_ppe_flags_desc_table[flag_handle].flag_type & FLAG_OVER_UNDER_MASK;\r
- \r
- if ( FLAG_OVER == flag_direction )\r
- {\r
- ppe_offset = g_ppe_flags_desc_table[flag_handle].threshold_ppe_offset + 1u;\r
- }\r
- else\r
- {\r
- ppe_offset = g_ppe_flags_desc_table[flag_handle].threshold_ppe_offset;\r
- }\r
- \r
- ACE->PPE_RAM_DATA[ppe_offset] = (ACE->PPE_RAM_DATA[ppe_offset] & ~PPE_RAM_THRESHOLD_MASK) + assertion_value;\r
- }\r
-#endif\r
-}\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- *\r
- */\r
-void\r
-ACE_set_flag_hysteresis\r
-(\r
- ace_flag_handle_t flag_handle,\r
- uint16_t adc_hysteresis\r
-)\r
-{\r
-#if (ACE_NB_OF_PPE_FLAGS > 0)\r
- uint16_t ppe_offset;\r
- uint32_t high_threshold;\r
- uint32_t low_threshold;\r
- uint32_t nominal_threshold;\r
- uint16_t adc_resolution;\r
- uint32_t adc_id;\r
- \r
- ASSERT( flag_handle < NB_OF_ACE_FLAG_HANDLES );\r
- ASSERT(ACE_is_hysteresis_flag(flag_handle));\r
- \r
- if ( ( flag_handle < NB_OF_ACE_FLAG_HANDLES ) && ( ACE_is_hysteresis_flag( flag_handle ) ) )\r
- {\r
- ace_channel_handle_t channel_handle;\r
- \r
- ppe_offset = g_ppe_flags_desc_table[flag_handle].threshold_ppe_offset;\r
- \r
- high_threshold = ACE->PPE_RAM_DATA[ppe_offset] & PPE_RAM_THRESHOLD_MASK;\r
- low_threshold = ACE->PPE_RAM_DATA[ppe_offset + 1u] & PPE_RAM_THRESHOLD_MASK;\r
- ASSERT(high_threshold > low_threshold);\r
- nominal_threshold = (low_threshold + ((high_threshold - low_threshold) / 2u));\r
- \r
- channel_handle = g_ppe_flags_desc_table[flag_handle].channel_handle;\r
- adc_id = (uint32_t)((uint32_t)g_ace_channel_desc_table[channel_handle].signal_id >> 4u);\r
- ASSERT( adc_id < (uint32_t)ACE_NB_OF_ADC );\r
- \r
- if ( adc_id < (uint32_t)ACE_NB_OF_ADC )\r
- {\r
- adc_resolution = g_ace_adc_config[adc_id].adc_resolution;\r
- \r
- high_threshold = nominal_threshold + adc_hysteresis;\r
- if ( high_threshold > adc_resolution )\r
- {\r
- high_threshold = (uint32_t)adc_resolution - 1u;\r
- }\r
- \r
- if ( adc_hysteresis > nominal_threshold )\r
- {\r
- low_threshold = 1u;\r
- }\r
- else\r
- {\r
- low_threshold = nominal_threshold - adc_hysteresis;\r
- }\r
- \r
- ACE->PPE_RAM_DATA[ppe_offset] = (ACE->PPE_RAM_DATA[ppe_offset] & ~PPE_RAM_THRESHOLD_MASK) + high_threshold;\r
- ACE->PPE_RAM_DATA[ppe_offset + 1u] = (ACE->PPE_RAM_DATA[ppe_offset + 1u] & ~PPE_RAM_THRESHOLD_MASK) + low_threshold;\r
- }\r
- }\r
-#endif\r
-}\r
-\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- *\r
- */\r
-void\r
-ACE_set_channel_hysteresis\r
-(\r
- ace_channel_handle_t channel_handle,\r
- uint16_t adc_hysteresis\r
-)\r
-{\r
-#if (ACE_NB_OF_PPE_FLAGS > 0)\r
- ace_flag_handle_t flag_handle;\r
- \r
- ASSERT( channel_handle < NB_OF_ACE_CHANNEL_HANDLES );\r
- \r
- if ( channel_handle < NB_OF_ACE_CHANNEL_HANDLES )\r
- {\r
- uint16_t i;\r
- \r
- for( i = 0u; i < g_ace_channel_desc_table[channel_handle].nb_of_flags; ++i )\r
- {\r
- flag_handle = (ace_flag_handle_t)g_ace_channel_desc_table[channel_handle].p_flags_array[i];\r
- ACE_set_flag_hysteresis( flag_handle, adc_hysteresis );\r
- }\r
- }\r
-#endif\r
-}\r
-\r
-/*==============================================================================\r
- *\r
- */\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- Masking a flag_id with FLAG_BIT_OFFSET_MASK results in the offset of the \r
- flag bit within a PPE__FLAGSn register.\r
- */\r
-#define FLAG_BIT_OFFSET_MASK 0x0000001FuL\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- Shifting right a flag_id by FLAG_PPE_REG_SHIFT results in identifying the\r
- PPE_FLAGSn or PPE_SFFLAGS the flags belongs to.\r
- */\r
-#define FLAG_PPE_REG_SHIFT 5u\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- There is a set of 5 PPE flag registers to control and report status of the PPE\r
- flags resulting in the PPE flags being grouped into 5 separate flag groups at\r
- the register level. Each register provides status or control for 32 flags.\r
- */\r
-#define NB_OF_FLAG_GROUPS 5u\r
-#define NB_OF_FLAGS_PER_GROUP 32u\r
-\r
-#if (ACE_NB_OF_PPE_FLAGS > 0)\r
-/*-------------------------------------------------------------------------*//**\r
- Lookup table of the address PPE_FLAGSn registers for fast reading of PPE\r
- status.\r
- */\r
-static volatile uint32_t * const g_ppe_flags_regs_lut[NB_OF_FLAG_GROUPS] =\r
-{\r
- &ACE->PPE_FLAGS0,\r
- &ACE->PPE_FLAGS1,\r
- &ACE->PPE_FLAGS2,\r
- &ACE->PPE_FLAGS3,\r
- &ACE->PPE_SFFLAGS\r
-};\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- Lookup table of the address of the PPE flags interrupt enable registers.\r
- */\r
-static uint32_t volatile * const flags_irq_enable_regs_lut[NB_OF_FLAG_GROUPS] =\r
-{\r
- &ACE->PPE_FLAGS0_IRQ_EN,\r
- &ACE->PPE_FLAGS1_IRQ_EN,\r
- &ACE->PPE_FLAGS2_IRQ_EN,\r
- &ACE->PPE_FLAGS3_IRQ_EN,\r
- &ACE->PPE_SFFLAGS_IRQ_EN\r
-};\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- Lookup table of the address of the PPE flags interrupt status registers.\r
- */\r
-static uint32_t volatile const * const flags_irq_status_regs_lut[NB_OF_FLAG_GROUPS] =\r
-{\r
- &ACE->PPE_FLAGS0_IRQ,\r
- &ACE->PPE_FLAGS1_IRQ,\r
- &ACE->PPE_FLAGS2_IRQ,\r
- &ACE->PPE_FLAGS3_IRQ,\r
- &ACE->PPE_SFFLAGS_IRQ\r
-};\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- Lookup table of the address of the PPE flags interrupt clearing registers.\r
- */\r
-static uint32_t volatile * const flags_irq_clear_regs_lut[NB_OF_FLAG_GROUPS] =\r
-{\r
- &ACE->PPE_FLAGS0_IRQ_CLR,\r
- &ACE->PPE_FLAGS1_IRQ_CLR,\r
- &ACE->PPE_FLAGS2_IRQ_CLR,\r
- &ACE->PPE_FLAGS3_IRQ_CLR,\r
- &ACE->PPE_SFFLAGS_IRQ_CLR\r
-};\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- *\r
- */\r
-static const IRQn_Type threshold_irqn_lut[NB_OF_THRESHOLD_IRQ] =\r
-{\r
- ACE_PPE_Flag0_IRQn,\r
- ACE_PPE_Flag1_IRQn,\r
- ACE_PPE_Flag2_IRQn,\r
- ACE_PPE_Flag3_IRQn,\r
- ACE_PPE_Flag4_IRQn,\r
- ACE_PPE_Flag5_IRQn,\r
- ACE_PPE_Flag6_IRQn,\r
- ACE_PPE_Flag7_IRQn,\r
- ACE_PPE_Flag8_IRQn,\r
- ACE_PPE_Flag9_IRQn,\r
- ACE_PPE_Flag10_IRQn,\r
- ACE_PPE_Flag11_IRQn,\r
- ACE_PPE_Flag12_IRQn,\r
- ACE_PPE_Flag13_IRQn,\r
- ACE_PPE_Flag14_IRQn,\r
- ACE_PPE_Flag15_IRQn,\r
- ACE_PPE_Flag16_IRQn,\r
- ACE_PPE_Flag17_IRQn,\r
- ACE_PPE_Flag18_IRQn,\r
- ACE_PPE_Flag19_IRQn,\r
- ACE_PPE_Flag20_IRQn,\r
- ACE_PPE_Flag21_IRQn,\r
- ACE_PPE_Flag22_IRQn,\r
- ACE_PPE_Flag23_IRQn,\r
- ACE_PPE_Flag24_IRQn,\r
- ACE_PPE_Flag25_IRQn,\r
- ACE_PPE_Flag26_IRQn,\r
- ACE_PPE_Flag27_IRQn,\r
- ACE_PPE_Flag28_IRQn,\r
- ACE_PPE_Flag29_IRQn,\r
- ACE_PPE_Flag30_IRQn,\r
- ACE_PPE_Flag31_IRQn\r
-};\r
-#endif\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- */\r
-ace_flag_handle_t\r
-ACE_get_flag_handle\r
-(\r
- const uint8_t * p_sz_full_flag_name\r
-)\r
-{\r
- ace_flag_handle_t flag_handle = INVALID_FLAG_HANDLE;\r
-#if (ACE_NB_OF_PPE_FLAGS > 0)\r
- ace_flag_handle_t flag_idx;\r
- \r
- for ( flag_idx = (ace_flag_handle_t)0; flag_idx < NB_OF_ACE_FLAG_HANDLES; ++flag_idx )\r
- {\r
- if ( g_ppe_flags_desc_table[flag_idx].p_sz_flag_name != 0 )\r
- {\r
- int32_t diff;\r
- diff = strncmp( (const char *)p_sz_full_flag_name, (const char *)g_ppe_flags_desc_table[flag_idx].p_sz_flag_name, (size_t)MAX_FULL_FLAG_NAME_LENGTH );\r
- if ( 0 == diff )\r
- {\r
- /* flag name found. */\r
- flag_handle = (ace_flag_handle_t)flag_idx;\r
- break;\r
- }\r
- }\r
- }\r
-#endif\r
- return flag_handle;\r
-}\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- */\r
-int32_t\r
-ACE_get_flag_status\r
-(\r
- ace_flag_handle_t flag_handle\r
-)\r
-{\r
- int32_t flag_state = UNKNOWN_FLAG;\r
-#if (ACE_NB_OF_PPE_FLAGS > 0) \r
- ppe_flag_id_t flag_id;\r
- \r
- ASSERT( flag_handle < NB_OF_ACE_FLAG_HANDLES );\r
- \r
- if ( flag_handle < NB_OF_ACE_FLAG_HANDLES )\r
- {\r
- uint32_t flag_bit_offset;\r
- uint32_t ppe_flag_group;\r
- uint32_t flag_id_mask;\r
- uint32_t flag_status;\r
-\r
- flag_id = g_ppe_flags_desc_table[flag_handle].flag_id;\r
- \r
- if ( flag_id < NB_OF_PPE_FLAGS )\r
- {\r
- flag_bit_offset = ((uint32_t)flag_id & FLAG_BIT_OFFSET_MASK);\r
- ppe_flag_group = ((uint32_t)flag_id >> FLAG_PPE_REG_SHIFT);\r
- flag_id_mask = 1uL << flag_bit_offset;\r
- flag_status = *(g_ppe_flags_regs_lut[ppe_flag_group]) & flag_id_mask;\r
- if ( flag_status > 0u )\r
- {\r
- flag_state = FLAG_ASSERTED;\r
- }\r
- else\r
- {\r
- flag_state = FLAG_NOT_ASSERTED;\r
- }\r
- }\r
-\r
- }\r
-#endif\r
- return flag_state;\r
-}\r
-\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- */\r
-const uint8_t *\r
-ACE_get_flag_name\r
-(\r
- ace_flag_handle_t flag_handle\r
-)\r
-{\r
- const uint8_t * psz_flag_name = 0;\r
-#if (ACE_NB_OF_PPE_FLAGS > 0) \r
- ASSERT( flag_handle < NB_OF_ACE_FLAG_HANDLES );\r
- \r
- if ( flag_handle < NB_OF_ACE_FLAG_HANDLES )\r
- {\r
- psz_flag_name = g_ppe_flags_desc_table[flag_handle].p_sz_flag_name;\r
- }\r
-#endif\r
- return psz_flag_name;\r
-}\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- */\r
-ace_channel_handle_t\r
-ACE_get_flag_channel\r
-(\r
- ace_flag_handle_t flag_handle\r
-)\r
-{\r
- ace_channel_handle_t channel_handle = INVALID_CHANNEL_HANDLE;\r
-#if (ACE_NB_OF_PPE_FLAGS > 0)\r
- ASSERT( flag_handle < NB_OF_ACE_FLAG_HANDLES );\r
- \r
- if ( flag_handle < NB_OF_ACE_FLAG_HANDLES )\r
- {\r
- channel_handle = g_ppe_flags_desc_table[flag_handle].channel_handle;\r
- }\r
-#endif\r
- return channel_handle;\r
-}\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- */\r
-uint32_t\r
-ACE_get_channel_flag_count\r
-(\r
- ace_channel_handle_t channel_handle\r
-)\r
-{\r
- uint32_t flag_count = 0;\r
-#if (ACE_NB_OF_PPE_FLAGS > 0)\r
- ASSERT( channel_handle < ACE_NB_OF_INPUT_CHANNELS );\r
- if (channel_handle < ACE_NB_OF_INPUT_CHANNELS)\r
- {\r
- flag_count = g_ace_channel_desc_table[channel_handle].nb_of_flags;\r
- }\r
-#endif\r
- return flag_count;\r
-}\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- \r
- */\r
-ace_flag_handle_t\r
-ACE_get_channel_first_flag\r
-(\r
- ace_channel_handle_t channel_handle,\r
- uint16_t * iterator\r
-)\r
-{\r
- ace_flag_handle_t flag_handle = INVALID_FLAG_HANDLE;\r
-#if (ACE_NB_OF_PPE_FLAGS > 0)\r
- ASSERT( channel_handle < NB_OF_ACE_CHANNEL_HANDLES);\r
- \r
- *iterator = 0u;\r
- \r
- if ( channel_handle < NB_OF_ACE_CHANNEL_HANDLES)\r
- {\r
- if ( g_ace_channel_desc_table[channel_handle].nb_of_flags > 0u )\r
- {\r
- flag_handle = (ace_flag_handle_t)g_ace_channel_desc_table[channel_handle].p_flags_array[*iterator];\r
- }\r
- }\r
-#endif \r
- return flag_handle;\r
-}\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- \r
- */\r
-ace_flag_handle_t\r
-ACE_get_channel_next_flag\r
-(\r
- ace_channel_handle_t channel_handle,\r
- uint16_t * iterator\r
-)\r
-{\r
- ace_flag_handle_t flag_handle = INVALID_FLAG_HANDLE;\r
-#if (ACE_NB_OF_PPE_FLAGS > 0) \r
- ASSERT( channel_handle < NB_OF_ACE_CHANNEL_HANDLES);\r
-\r
- if ( channel_handle < NB_OF_ACE_CHANNEL_HANDLES)\r
- {\r
- ++(*iterator);\r
- \r
- if ( *iterator >= g_ace_channel_desc_table[channel_handle].nb_of_flags )\r
- {\r
- *iterator = 0u;\r
- }\r
- \r
- if ( g_ace_channel_desc_table[channel_handle].nb_of_flags > 0u )\r
- {\r
- flag_handle = (ace_flag_handle_t)g_ace_channel_desc_table[channel_handle].p_flags_array[*iterator];\r
- }\r
- }\r
-#endif\r
- return flag_handle;\r
-}\r
-\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- *\r
- */\r
-void ACE_enable_channel_flags_irq\r
-(\r
- ace_channel_handle_t channel_handle\r
-)\r
-{\r
-#if (ACE_NB_OF_PPE_FLAGS > 0)\r
- uint32_t flag_idx;\r
- ace_flag_handle_t flag_handle;\r
- \r
- ASSERT( channel_handle < NB_OF_ACE_CHANNEL_HANDLES );\r
- \r
- if ( channel_handle < NB_OF_ACE_CHANNEL_HANDLES )\r
- {\r
- for ( flag_idx = 0u; flag_idx < g_ace_channel_desc_table[channel_handle].nb_of_flags; ++flag_idx )\r
- {\r
- flag_handle = (ace_flag_handle_t)g_ace_channel_desc_table[channel_handle].p_flags_array[flag_idx];\r
- ACE_enable_flag_irq( flag_handle );\r
- }\r
- }\r
-#endif\r
-}\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- *\r
- */\r
-void ACE_disable_channel_flags_irq\r
-(\r
- ace_channel_handle_t channel_handle\r
-)\r
-{\r
-#if (ACE_NB_OF_PPE_FLAGS > 0)\r
- uint32_t flag_idx;\r
- ace_flag_handle_t flag_handle;\r
- \r
- ASSERT( channel_handle < NB_OF_ACE_CHANNEL_HANDLES );\r
- \r
- if ( channel_handle < NB_OF_ACE_CHANNEL_HANDLES )\r
- {\r
- for ( flag_idx = 0u; flag_idx < g_ace_channel_desc_table[channel_handle].nb_of_flags; ++flag_idx )\r
- {\r
- flag_handle = (ace_flag_handle_t)g_ace_channel_desc_table[channel_handle].p_flags_array[flag_idx];\r
- ACE_disable_flag_irq( flag_handle );\r
- }\r
- }\r
-#endif\r
-}\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- *\r
- */\r
-void ACE_clear_channel_flags_irq\r
-(\r
- ace_channel_handle_t channel_handle\r
-)\r
-{\r
-#if (ACE_NB_OF_PPE_FLAGS > 0)\r
- uint32_t flag_idx;\r
- ace_flag_handle_t flag_handle;\r
- \r
- ASSERT( channel_handle < NB_OF_ACE_CHANNEL_HANDLES );\r
- \r
- if ( channel_handle < NB_OF_ACE_CHANNEL_HANDLES )\r
- {\r
- for ( flag_idx = 0u; flag_idx < g_ace_channel_desc_table[channel_handle].nb_of_flags; ++flag_idx )\r
- {\r
- flag_handle = (ace_flag_handle_t)g_ace_channel_desc_table[channel_handle].p_flags_array[flag_idx];\r
- ACE_clear_flag_irq( flag_handle );\r
- }\r
- }\r
-#endif\r
-}\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- *\r
- */\r
-void ACE_enable_flag_irq\r
-(\r
- ace_flag_handle_t flag_handle\r
-)\r
-{\r
-#if (ACE_NB_OF_PPE_FLAGS > 0)\r
- ASSERT( flag_handle < NB_OF_ACE_FLAG_HANDLES );\r
- \r
- if ( flag_handle < NB_OF_ACE_FLAG_HANDLES )\r
- {\r
- ppe_flag_id_t flag_id;\r
- uint32_t flag_bit_offset;\r
- uint32_t ppe_flag_group;\r
- uint32_t flag_id_mask;\r
- \r
- flag_id = g_ppe_flags_desc_table[flag_handle].flag_id;\r
- \r
- ASSERT( flag_id < NB_OF_PPE_FLAGS );\r
- \r
- flag_bit_offset = ((uint32_t)flag_id & FLAG_BIT_OFFSET_MASK);\r
- ppe_flag_group = ((uint32_t)flag_id >> FLAG_PPE_REG_SHIFT);\r
- flag_id_mask = 1uL << flag_bit_offset;\r
- \r
- ASSERT( ppe_flag_group < NB_OF_FLAG_GROUPS );\r
- \r
- if ( ppe_flag_group < NB_OF_FLAG_GROUPS )\r
- {\r
- *(flags_irq_enable_regs_lut[ppe_flag_group]) |= flag_id_mask;\r
- }\r
- \r
- NVIC_EnableIRQ( threshold_irqn_lut[flag_bit_offset] );\r
- }\r
-#endif\r
-}\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- *\r
- */\r
-void ACE_disable_flag_irq\r
-(\r
- ace_flag_handle_t flag_handle\r
-)\r
-{\r
-#if (ACE_NB_OF_PPE_FLAGS > 0)\r
- ASSERT( flag_handle < NB_OF_ACE_FLAG_HANDLES );\r
- \r
- if ( flag_handle < NB_OF_ACE_FLAG_HANDLES )\r
- {\r
- ppe_flag_id_t flag_id;\r
- uint32_t flag_bit_offset;\r
- uint32_t ppe_flag_group;\r
- uint32_t flag_id_mask;\r
- \r
- flag_id = g_ppe_flags_desc_table[flag_handle].flag_id;\r
- \r
- ASSERT( flag_id < NB_OF_PPE_FLAGS );\r
- \r
- flag_bit_offset = ((uint32_t)flag_id & FLAG_BIT_OFFSET_MASK);\r
- ppe_flag_group = ((uint32_t)flag_id >> FLAG_PPE_REG_SHIFT);\r
- flag_id_mask = 1uL << flag_bit_offset;\r
- \r
- ASSERT( ppe_flag_group < NB_OF_FLAG_GROUPS );\r
- \r
- if ( ppe_flag_group < NB_OF_FLAG_GROUPS )\r
- {\r
- *(flags_irq_enable_regs_lut[ppe_flag_group]) &= (uint32_t)~flag_id_mask;\r
- }\r
- }\r
-#endif\r
-}\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- *\r
- */\r
-void ACE_clear_flag_irq\r
-(\r
- ace_flag_handle_t flag_handle\r
-)\r
-{\r
-#if (ACE_NB_OF_PPE_FLAGS > 0)\r
- ASSERT( flag_handle < NB_OF_ACE_FLAG_HANDLES );\r
- \r
- if ( flag_handle < NB_OF_ACE_FLAG_HANDLES )\r
- {\r
- ppe_flag_id_t flag_id;\r
- uint32_t flag_bit_offset;\r
- uint32_t ppe_flag_group;\r
- uint32_t flag_id_mask;\r
- \r
- flag_id = g_ppe_flags_desc_table[flag_handle].flag_id;\r
- \r
- ASSERT( flag_id < NB_OF_PPE_FLAGS );\r
- \r
- flag_bit_offset = ((uint32_t)flag_id & FLAG_BIT_OFFSET_MASK);\r
- ppe_flag_group = ((uint32_t)flag_id >> FLAG_PPE_REG_SHIFT);\r
- flag_id_mask = 1uL << flag_bit_offset;\r
- \r
- ASSERT( ppe_flag_group < NB_OF_FLAG_GROUPS );\r
- \r
- if ( ppe_flag_group < NB_OF_FLAG_GROUPS )\r
- {\r
- *(flags_irq_clear_regs_lut[ppe_flag_group]) |= flag_id_mask;\r
- }\r
- }\r
-#endif\r
-}\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- *\r
- */\r
-void ACE_register_flag_isr\r
-(\r
- ace_flag_handle_t flag_handle,\r
- flag_isr_t flag_isr\r
-)\r
-{\r
-#if (ACE_NB_OF_PPE_FLAGS > 0)\r
- ppe_flag_id_t flag_id;\r
- \r
- ASSERT( flag_handle < NB_OF_ACE_FLAG_HANDLES );\r
- \r
- if ( flag_handle < NB_OF_ACE_FLAG_HANDLES )\r
- {\r
- flag_id = g_ppe_flags_desc_table[flag_handle].flag_id;\r
- \r
- ASSERT( flag_id < NB_OF_PPE_FLAGS );\r
- \r
- if ( flag_id < NB_OF_PPE_FLAGS )\r
- {\r
- g_ppe_flags_isr_lut[flag_id] = flag_isr;\r
- }\r
- }\r
-#endif\r
-}\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- *\r
- */\r
-void ACE_register_channel_flags_isr\r
-(\r
- ace_channel_handle_t channel_handle,\r
- channel_flag_isr_t channel_flag_isr\r
-)\r
-{\r
-#if (ACE_NB_OF_PPE_FLAGS > 0)\r
- ASSERT( channel_handle < NB_OF_ACE_CHANNEL_HANDLES );\r
- \r
- if ( channel_handle < NB_OF_ACE_CHANNEL_HANDLES )\r
- {\r
- g_ppe_channel_flags_isr_lut[channel_handle] = channel_flag_isr;\r
- }\r
-#endif\r
-}\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- *\r
- */\r
-void ACE_register_global_flags_isr\r
-(\r
- global_flag_isr_t global_flag_isr\r
-)\r
-{\r
-#if (ACE_NB_OF_PPE_FLAGS > 0)\r
- g_ppe_global_flags_isr = global_flag_isr;\r
-#endif\r
-}\r
-\r
-\r
-/*==============================================================================\r
- *\r
- */\r
- \r
-/*-------------------------------------------------------------------------*//**\r
- * Actual PPE flag interrupt service routines:\r
- */\r
-\r
-static void process_flag_irq( uint8_t threshold_flag_id )\r
-{\r
-#if (ACE_NB_OF_PPE_FLAGS > 0)\r
- uint8_t flag_group;\r
- uint32_t threshold_flag_mask;\r
- ppe_flag_id_t flag_id;\r
- uint32_t irq_enable_reg;\r
- uint32_t irq_status_reg;\r
- uint32_t irq_active;\r
- \r
- threshold_flag_mask = 1uL << threshold_flag_id;\r
- \r
- \r
- for ( flag_group = 0u; flag_group < NB_OF_FLAG_GROUPS; ++flag_group )\r
- {\r
- irq_enable_reg = *flags_irq_enable_regs_lut[flag_group];\r
- irq_status_reg = *flags_irq_status_regs_lut[flag_group];\r
- irq_active = threshold_flag_mask & irq_enable_reg & irq_status_reg;\r
- \r
- if ( irq_active )\r
- {\r
- ace_flag_handle_t flag_handle;\r
- ace_channel_handle_t channel_handle;\r
- \r
- flag_id = (ppe_flag_id_t)((flag_group * NB_OF_FLAGS_PER_GROUP) + threshold_flag_id);\r
- flag_handle = g_ppe_flag_handles_lut[flag_id];\r
- \r
- /* Call individual flag handler */\r
- if ( g_ppe_flags_isr_lut[flag_id] != 0 ) \r
- {\r
- g_ppe_flags_isr_lut[flag_id]( flag_handle );\r
- }\r
- \r
- /* Call the channel flag handler. */\r
- channel_handle = g_ppe_flags_desc_table[flag_handle].channel_handle;\r
- if ( channel_handle < NB_OF_ACE_CHANNEL_HANDLES )\r
- {\r
- if ( g_ppe_channel_flags_isr_lut[channel_handle] != 0 )\r
- {\r
- g_ppe_channel_flags_isr_lut[channel_handle]( flag_handle );\r
- }\r
- }\r
- \r
- /* Call the global flag handler. */\r
- if ( g_ppe_global_flags_isr != 0 )\r
- {\r
- g_ppe_global_flags_isr( flag_handle, channel_handle );\r
- }\r
- \r
- /* Clear the flag interrupt */\r
- *flags_irq_clear_regs_lut[flag_group] |= threshold_flag_mask;\r
- }\r
- }\r
-#endif\r
-}\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- *\r
- */\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void ACE_PPE_Flag0_IRQHandler( void )\r
-#else\r
-void ACE_PPE_Flag0_IRQHandler( void )\r
-#endif\r
-{\r
- process_flag_irq( THRESHOLD_FLAG0 );\r
- NVIC_ClearPendingIRQ( ACE_PPE_Flag0_IRQn );\r
-}\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- *\r
- */\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void ACE_PPE_Flag1_IRQHandler( void )\r
-#else\r
-void ACE_PPE_Flag1_IRQHandler( void )\r
-#endif\r
-{\r
- process_flag_irq( THRESHOLD_FLAG1 );\r
- NVIC_ClearPendingIRQ( ACE_PPE_Flag1_IRQn );\r
-}\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- *\r
- */\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void ACE_PPE_Flag2_IRQHandler( void )\r
-#else\r
-void ACE_PPE_Flag2_IRQHandler( void )\r
-#endif\r
-{\r
- process_flag_irq( THRESHOLD_FLAG2 );\r
- NVIC_ClearPendingIRQ( ACE_PPE_Flag2_IRQn );\r
-}\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- *\r
- */\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void ACE_PPE_Flag3_IRQHandler( void )\r
-#else\r
-void ACE_PPE_Flag3_IRQHandler( void )\r
-#endif\r
-{\r
- process_flag_irq( THRESHOLD_FLAG3 );\r
- NVIC_ClearPendingIRQ( ACE_PPE_Flag3_IRQn );\r
-}\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- *\r
- */\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void ACE_PPE_Flag4_IRQHandler( void )\r
-#else\r
-void ACE_PPE_Flag4_IRQHandler( void )\r
-#endif\r
-{\r
- process_flag_irq( THRESHOLD_FLAG4 );\r
- NVIC_ClearPendingIRQ( ACE_PPE_Flag4_IRQn );\r
-}\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- *\r
- */\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void ACE_PPE_Flag5_IRQHandler( void )\r
-#else\r
-void ACE_PPE_Flag5_IRQHandler( void )\r
-#endif\r
-{\r
- process_flag_irq( THRESHOLD_FLAG5 );\r
- NVIC_ClearPendingIRQ( ACE_PPE_Flag5_IRQn );\r
-}\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- *\r
- */\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void ACE_PPE_Flag6_IRQHandler( void )\r
-#else\r
-void ACE_PPE_Flag6_IRQHandler( void )\r
-#endif\r
-{\r
- process_flag_irq( THRESHOLD_FLAG6 );\r
- NVIC_ClearPendingIRQ( ACE_PPE_Flag6_IRQn );\r
-}\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- *\r
- */\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void ACE_PPE_Flag7_IRQHandler( void )\r
-#else\r
-void ACE_PPE_Flag7_IRQHandler( void )\r
-#endif\r
-{\r
- process_flag_irq( THRESHOLD_FLAG7 );\r
- NVIC_ClearPendingIRQ( ACE_PPE_Flag7_IRQn );\r
-}\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- *\r
- */\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void ACE_PPE_Flag8_IRQHandler( void )\r
-#else\r
-void ACE_PPE_Flag8_IRQHandler( void )\r
-#endif\r
-{\r
- process_flag_irq( THRESHOLD_FLAG8 );\r
- NVIC_ClearPendingIRQ( ACE_PPE_Flag8_IRQn );\r
-}\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- *\r
- */\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void ACE_PPE_Flag9_IRQHandler( void )\r
-#else\r
-void ACE_PPE_Flag9_IRQHandler( void )\r
-#endif\r
-{\r
- process_flag_irq( THRESHOLD_FLAG9 );\r
- NVIC_ClearPendingIRQ( ACE_PPE_Flag9_IRQn );\r
-}\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- *\r
- */\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void ACE_PPE_Flag10_IRQHandler( void )\r
-#else\r
-void ACE_PPE_Flag10_IRQHandler( void )\r
-#endif\r
-{\r
- process_flag_irq( THRESHOLD_FLAG10 );\r
- NVIC_ClearPendingIRQ( ACE_PPE_Flag10_IRQn );\r
-}\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- *\r
- */\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void ACE_PPE_Flag11_IRQHandler( void )\r
-#else\r
-void ACE_PPE_Flag11_IRQHandler( void )\r
-#endif\r
-{\r
- process_flag_irq( THRESHOLD_FLAG11 );\r
- NVIC_ClearPendingIRQ( ACE_PPE_Flag11_IRQn );\r
-}\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- *\r
- */\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void ACE_PPE_Flag12_IRQHandler( void )\r
-#else\r
-void ACE_PPE_Flag12_IRQHandler( void )\r
-#endif\r
-{\r
- process_flag_irq( THRESHOLD_FLAG12 );\r
- NVIC_ClearPendingIRQ( ACE_PPE_Flag12_IRQn );\r
-}\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- *\r
- */\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void ACE_PPE_Flag13_IRQHandler( void )\r
-#else\r
-void ACE_PPE_Flag13_IRQHandler( void )\r
-#endif\r
-{\r
- process_flag_irq( THRESHOLD_FLAG13 );\r
- NVIC_ClearPendingIRQ( ACE_PPE_Flag13_IRQn );\r
-}\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- *\r
- */\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void ACE_PPE_Flag14_IRQHandler( void )\r
-#else\r
-void ACE_PPE_Flag14_IRQHandler( void )\r
-#endif\r
-{\r
- process_flag_irq( THRESHOLD_FLAG14 );\r
- NVIC_ClearPendingIRQ( ACE_PPE_Flag14_IRQn );\r
-}\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- *\r
- */\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void ACE_PPE_Flag15_IRQHandler( void )\r
-#else\r
-void ACE_PPE_Flag15_IRQHandler( void )\r
-#endif\r
-{\r
- process_flag_irq( THRESHOLD_FLAG15 );\r
- NVIC_ClearPendingIRQ( ACE_PPE_Flag15_IRQn );\r
-}\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- *\r
- */\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void ACE_PPE_Flag16_IRQHandler( void )\r
-#else\r
-void ACE_PPE_Flag16_IRQHandler( void )\r
-#endif\r
-{\r
- process_flag_irq( THRESHOLD_FLAG16 );\r
- NVIC_ClearPendingIRQ( ACE_PPE_Flag16_IRQn );\r
-}\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- *\r
- */\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void ACE_PPE_Flag17_IRQHandler( void )\r
-#else\r
-void ACE_PPE_Flag17_IRQHandler( void )\r
-#endif\r
-{\r
- process_flag_irq( THRESHOLD_FLAG17 );\r
- NVIC_ClearPendingIRQ( ACE_PPE_Flag17_IRQn );\r
-}\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- *\r
- */\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void ACE_PPE_Flag18_IRQHandler( void )\r
-#else\r
-void ACE_PPE_Flag18_IRQHandler( void )\r
-#endif\r
-{\r
- process_flag_irq( THRESHOLD_FLAG18 );\r
- NVIC_ClearPendingIRQ( ACE_PPE_Flag18_IRQn );\r
-}\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- *\r
- */\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void ACE_PPE_Flag19_IRQHandler( void )\r
-#else\r
-void ACE_PPE_Flag19_IRQHandler( void )\r
-#endif\r
-{\r
- process_flag_irq( THRESHOLD_FLAG19 );\r
- NVIC_ClearPendingIRQ( ACE_PPE_Flag19_IRQn );\r
-}\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- *\r
- */\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void ACE_PPE_Flag20_IRQHandler( void )\r
-#else\r
-void ACE_PPE_Flag20_IRQHandler( void )\r
-#endif\r
-{\r
- process_flag_irq( THRESHOLD_FLAG20 );\r
- NVIC_ClearPendingIRQ( ACE_PPE_Flag20_IRQn );\r
-}\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- *\r
- */\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void ACE_PPE_Flag21_IRQHandler( void )\r
-#else\r
-void ACE_PPE_Flag21_IRQHandler( void )\r
-#endif\r
-{\r
- process_flag_irq( THRESHOLD_FLAG21 );\r
- NVIC_ClearPendingIRQ( ACE_PPE_Flag21_IRQn );\r
-}\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- *\r
- */\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void ACE_PPE_Flag22_IRQHandler( void )\r
-#else\r
-void ACE_PPE_Flag22_IRQHandler( void )\r
-#endif\r
-{\r
- process_flag_irq( THRESHOLD_FLAG22 );\r
- NVIC_ClearPendingIRQ( ACE_PPE_Flag22_IRQn );\r
-}\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- *\r
- */\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void ACE_PPE_Flag23_IRQHandler( void )\r
-#else\r
-void ACE_PPE_Flag23_IRQHandler( void )\r
-#endif\r
-{\r
- process_flag_irq( THRESHOLD_FLAG23 );\r
- NVIC_ClearPendingIRQ( ACE_PPE_Flag23_IRQn );\r
-}\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- *\r
- */\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void ACE_PPE_Flag24_IRQHandler( void )\r
-#else\r
-void ACE_PPE_Flag24_IRQHandler( void )\r
-#endif\r
-{\r
- process_flag_irq( THRESHOLD_FLAG24 );\r
- NVIC_ClearPendingIRQ( ACE_PPE_Flag24_IRQn );\r
-}\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- *\r
- */\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void ACE_PPE_Flag25_IRQHandler( void )\r
-#else\r
-void ACE_PPE_Flag25_IRQHandler( void )\r
-#endif\r
-{\r
- process_flag_irq( THRESHOLD_FLAG25 );\r
- NVIC_ClearPendingIRQ( ACE_PPE_Flag25_IRQn );\r
-}\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- *\r
- */\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void ACE_PPE_Flag26_IRQHandler( void )\r
-#else\r
-void ACE_PPE_Flag26_IRQHandler( void )\r
-#endif\r
-{\r
- process_flag_irq( THRESHOLD_FLAG26 );\r
- NVIC_ClearPendingIRQ( ACE_PPE_Flag26_IRQn );\r
-}\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- *\r
- */\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void ACE_PPE_Flag27_IRQHandler( void )\r
-#else\r
-void ACE_PPE_Flag27_IRQHandler( void )\r
-#endif\r
-{\r
- process_flag_irq( THRESHOLD_FLAG27 );\r
- NVIC_ClearPendingIRQ( ACE_PPE_Flag27_IRQn );\r
-}\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- *\r
- */\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void ACE_PPE_Flag28_IRQHandler( void )\r
-#else\r
-void ACE_PPE_Flag28_IRQHandler( void )\r
-#endif\r
-{\r
- process_flag_irq( THRESHOLD_FLAG28 );\r
- NVIC_ClearPendingIRQ( ACE_PPE_Flag28_IRQn );\r
-}\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- *\r
- */\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void ACE_PPE_Flag29_IRQHandler( void )\r
-#else\r
-void ACE_PPE_Flag29_IRQHandler( void )\r
-#endif\r
-{\r
- process_flag_irq( THRESHOLD_FLAG29 );\r
- NVIC_ClearPendingIRQ( ACE_PPE_Flag29_IRQn );\r
-}\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- *\r
- */\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void ACE_PPE_Flag30_IRQHandler( void )\r
-#else\r
-void ACE_PPE_Flag30_IRQHandler( void )\r
-#endif\r
-{\r
- process_flag_irq( THRESHOLD_FLAG30 );\r
- NVIC_ClearPendingIRQ( ACE_PPE_Flag30_IRQn );\r
-}\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- *\r
- */\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void ACE_PPE_Flag31_IRQHandler( void )\r
-#else\r
-void ACE_PPE_Flag31_IRQHandler( void )\r
-#endif\r
-{\r
- process_flag_irq( THRESHOLD_FLAG31 );\r
- NVIC_ClearPendingIRQ( ACE_PPE_Flag31_IRQn );\r
-}\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
+++ /dev/null
-/*******************************************************************************\r
- * (c) Copyright 2009 Actel Corporation. All rights reserved.\r
- * \r
- * SVN $Revision: 2905 $\r
- * SVN $Date: 2010-08-20 14:03:28 +0100 (Fri, 20 Aug 2010) $\r
- */\r
-#include "mss_ace.h"\r
-#include "mss_ace_configurator.h"\r
-#include "../../drivers_config/mss_ace/ace_handles.h"\r
-#include "../../drivers_config/mss_ace/ace_config.h"\r
-\r
-#include "../../CMSIS/a2fxxxm3.h"\r
-#include "../../CMSIS/mss_assert.h"\r
-#include <string.h>\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif \r
-\r
-#define SSE_START 1uL\r
-#define SSE_STOP 0uL\r
-\r
-#define NB_OF_ANALOG_BLOCKS 3u\r
-#define SEE_RAM_WORD_SIZE 512\r
-\r
-#define TS_ENABLE_MASK 0x01u\r
-#define PPE_ENABLE_MASK 0x01u\r
-#define ADC_RESET_MASK 0x10u\r
-#define ADC_FIFO_CLR_MASK 0x04u\r
-#define PDMA_DATAOUT_CLR_MASK 0x04u\r
-\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- *\r
- */\r
-extern ace_procedure_desc_t g_sse_sequences_desc_table[ACE_NB_OF_SSE_PROCEDURES];\r
- \r
-/*-------------------------------------------------------------------------*//**\r
- *\r
- */\r
-sse_sequence_handle_t\r
-ACE_get_sse_seq_handle\r
-(\r
- const uint8_t * p_sz_sequence_name\r
-)\r
-{\r
- uint16_t seq_idx;\r
- sse_sequence_handle_t handle = INVALID_SSE_SEQ_HANDLE;\r
- \r
- for ( seq_idx = 0u; seq_idx < (uint32_t)ACE_NB_OF_SSE_PROCEDURES; ++seq_idx )\r
- {\r
- if ( g_sse_sequences_desc_table[seq_idx].p_sz_proc_name != 0 )\r
- {\r
- int32_t diff;\r
- diff = strncmp( (const char *)p_sz_sequence_name, (const char *)g_sse_sequences_desc_table[seq_idx].p_sz_proc_name, MAX_PROCEDURE_NAME_LENGTH );\r
- if ( 0 == diff )\r
- {\r
- /* channel name found. */\r
- handle = seq_idx;\r
- break;\r
- }\r
- }\r
- }\r
- return handle;\r
-}\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- *\r
- */\r
-static uint32_t volatile * const sse_pc_ctrl_lut[NB_OF_ANALOG_BLOCKS] =\r
-{\r
- &ACE->PC0_CTRL,\r
- &ACE->PC1_CTRL,\r
- &ACE->PC2_CTRL\r
-};\r
-\r
-static uint32_t volatile * const sse_pc_lo_lut[NB_OF_ANALOG_BLOCKS] =\r
-{\r
- &ACE->PC0_LO,\r
- &ACE->PC1_LO,\r
- &ACE->PC2_LO\r
-};\r
-\r
-static uint32_t volatile * const sse_pc_hi_lut[NB_OF_ANALOG_BLOCKS] =\r
-{\r
- &ACE->PC0_HI,\r
- &ACE->PC1_HI,\r
- &ACE->PC2_HI\r
-};\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- *\r
- */\r
-void ACE_load_sse\r
-(\r
- sse_sequence_handle_t sequence\r
-)\r
-{\r
- ASSERT( sequence < (sse_sequence_handle_t)ACE_NB_OF_SSE_PROCEDURES );\r
- \r
- if ( sequence < (sse_sequence_handle_t)ACE_NB_OF_SSE_PROCEDURES )\r
- {\r
- uint16_t i;\r
- uint16_t offset;\r
- const uint16_t * p_ucode;\r
- \r
- ASSERT( g_sse_sequences_desc_table[sequence].sse_pc_id < NB_OF_ANALOG_BLOCKS );\r
- \r
- if ( g_sse_sequences_desc_table[sequence].sse_pc_id < NB_OF_ANALOG_BLOCKS )\r
- {\r
- /* Stop relevant program counter. */\r
- *sse_pc_ctrl_lut[g_sse_sequences_desc_table[sequence].sse_pc_id] = SSE_STOP;\r
- \r
- /* Load microcode into SEE RAM.*/\r
- p_ucode = g_sse_sequences_desc_table[sequence].sse_ucode;\r
- offset = g_sse_sequences_desc_table[sequence].sse_load_offset;\r
- \r
- for ( i = 0u; i < g_sse_sequences_desc_table[sequence].sse_ucode_length; ++i )\r
- {\r
- ACE->SSE_RAM_DATA[offset + i] = (uint32_t)*p_ucode;\r
- ++p_ucode;\r
- }\r
- }\r
- }\r
-}\r
-\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- *\r
- */\r
-void ACE_start_sse\r
-(\r
- sse_sequence_handle_t sequence\r
-)\r
-{\r
- ASSERT( sequence < (sse_sequence_handle_t)ACE_NB_OF_SSE_PROCEDURES );\r
- \r
- if ( sequence < (sse_sequence_handle_t)ACE_NB_OF_SSE_PROCEDURES )\r
- {\r
- uint16_t pc;\r
- \r
- ASSERT( g_sse_sequences_desc_table[sequence].sse_pc_id < NB_OF_ANALOG_BLOCKS );\r
- ASSERT( g_sse_sequences_desc_table[sequence].sse_load_offset < SEE_RAM_WORD_SIZE );\r
- \r
- pc = g_sse_sequences_desc_table[sequence].sse_load_offset;\r
- \r
- if ( pc < 256u )\r
- {\r
- *sse_pc_lo_lut[g_sse_sequences_desc_table[sequence].sse_pc_id] = pc;\r
- }\r
- else\r
- {\r
- *sse_pc_hi_lut[g_sse_sequences_desc_table[sequence].sse_pc_id] = pc - 256;\r
- }\r
- \r
- *sse_pc_ctrl_lut[g_sse_sequences_desc_table[sequence].sse_pc_id] = SSE_START;\r
- \r
- /* Enable Sample Sequencing Engine in case it was not done as part of\r
- * system boot. */\r
- ACE->SSE_TS_CTRL |= TS_ENABLE_MASK;\r
- }\r
-}\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- *\r
- */\r
-void ACE_restart_sse\r
-(\r
- sse_sequence_handle_t sequence\r
-)\r
-{\r
- ASSERT( sequence < ACE_NB_OF_SSE_PROCEDURES );\r
- ASSERT( g_sse_sequences_desc_table[sequence].sse_pc_id < NB_OF_ANALOG_BLOCKS );\r
- ASSERT( g_sse_sequences_desc_table[sequence].sse_load_offset < SEE_RAM_WORD_SIZE );\r
- \r
- if ( sequence < (sse_sequence_handle_t)ACE_NB_OF_SSE_PROCEDURES )\r
- {\r
- uint16_t pc;\r
- \r
- pc = g_sse_sequences_desc_table[sequence].sse_loop_pc;\r
- \r
- if ( pc < 256u )\r
- {\r
- *sse_pc_lo_lut[g_sse_sequences_desc_table[sequence].sse_pc_id] = pc;\r
- }\r
- else\r
- {\r
- *sse_pc_hi_lut[g_sse_sequences_desc_table[sequence].sse_pc_id] = pc - 256;\r
- }\r
- \r
- *sse_pc_ctrl_lut[g_sse_sequences_desc_table[sequence].sse_pc_id] = SSE_START;\r
- }\r
-}\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- *\r
- */\r
-void ACE_stop_sse\r
-(\r
- sse_sequence_handle_t sequence\r
-)\r
-{\r
- ASSERT( sequence < ACE_NB_OF_SSE_PROCEDURES );\r
- \r
- if ( sequence < (sse_sequence_handle_t)ACE_NB_OF_SSE_PROCEDURES )\r
- {\r
- /* Stop relevant program counter. */\r
- *sse_pc_ctrl_lut[g_sse_sequences_desc_table[sequence].sse_pc_id] = SSE_STOP;\r
- }\r
-}\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- *\r
- */\r
-void ACE_resume_sse\r
-(\r
- sse_sequence_handle_t sequence\r
-)\r
-{\r
- ASSERT( sequence < ACE_NB_OF_SSE_PROCEDURES );\r
- \r
- if ( sequence < (sse_sequence_handle_t)ACE_NB_OF_SSE_PROCEDURES )\r
- {\r
- *sse_pc_ctrl_lut[g_sse_sequences_desc_table[sequence].sse_pc_id] = SSE_START;\r
- }\r
-}\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- *\r
- */\r
-void ACE_enable_sse_irq\r
-(\r
- sse_irq_id_t sse_irq_id\r
-)\r
-{\r
- ASSERT( sse_irq_id < NB_OF_SSE_FLAG_IRQS );\r
- \r
- ACE->SSE_IRQ_EN |= 1uL << (uint32_t)sse_irq_id;\r
-}\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- *\r
- */\r
-void ACE_disable_sse_irq\r
-(\r
- sse_irq_id_t sse_irq_id\r
-)\r
-{\r
- ASSERT( sse_irq_id < NB_OF_SSE_FLAG_IRQS );\r
- \r
- ACE->SSE_IRQ_EN &= (uint32_t)~(1uL << (uint32_t)sse_irq_id);\r
-}\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- *\r
- */\r
-void ACE_clear_sse_irq\r
-(\r
- sse_irq_id_t sse_irq_id\r
-)\r
-{\r
- ASSERT( sse_irq_id < NB_OF_SSE_FLAG_IRQS );\r
- \r
- ACE->SSE_IRQ_CLR |= 1uL << (uint32_t)sse_irq_id;\r
-}\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- *\r
- */\r
-void ACE_clear_sample_pipeline(void)\r
-{\r
- uint32_t saved_sse_ctrl;\r
- uint32_t saved_ppe_ctrl;\r
- \r
- /* Pause the Sample Sequencing Engine. */\r
- saved_sse_ctrl = ACE->SSE_TS_CTRL;\r
- ACE->SSE_TS_CTRL = ACE->SSE_TS_CTRL & ~((uint32_t)TS_ENABLE_MASK);\r
- \r
- /* Pause the Post Processing Engine. */\r
- saved_ppe_ctrl = ACE->PPE_CTRL;\r
- ACE->PPE_CTRL = ACE->PPE_CTRL & ~((uint32_t)PPE_ENABLE_MASK);\r
- \r
- /* Reset the ADCs */\r
- ACE->ADC0_MISC_CTRL |= ADC_RESET_MASK;\r
- ACE->ADC1_MISC_CTRL |= ADC_RESET_MASK;\r
- ACE->ADC2_MISC_CTRL |= ADC_RESET_MASK;\r
- \r
- /* Clear ADC FIFOs */\r
- ACE->ADC0_FIFO_CTRL |= ADC_FIFO_CLR_MASK;\r
- ACE->ADC1_FIFO_CTRL |= ADC_FIFO_CLR_MASK;\r
- ACE->ADC2_FIFO_CTRL |= ADC_FIFO_CLR_MASK;\r
- \r
- /* clear DMA FIFOs */\r
- ACE->PPE_PDMA_CTRL |= PDMA_DATAOUT_CLR_MASK;\r
- \r
- /* Unpause the Post Processing Engine. */\r
- ACE->PPE_CTRL = saved_ppe_ctrl;\r
- \r
- /* Unpause the Sample Sequencing Engine. */\r
- ACE->SSE_TS_CTRL = saved_sse_ctrl;\r
-}\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
+++ /dev/null
-/*******************************************************************************\r
- * (c) Copyright 2010 Actel Corporation. All rights reserved.\r
- *\r
- * This file contains the implementation of the functions used to dynamically\r
- * control the linear transforms applied by the ACE post processing engine to\r
- * the samples read from the SSE.\r
- *\r
- * SVN $Revision: 2908 $\r
- * SVN $Date: 2010-08-20 16:01:28 +0100 (Fri, 20 Aug 2010) $\r
- */\r
-\r
-#include "mss_ace.h"\r
-#include "mss_ace_configurator.h"\r
-#include "mtd_data.h"\r
-#include "envm_layout.h"\r
-#include "../../CMSIS/a2fxxxm3.h"\r
-#include "../../CMSIS/mss_assert.h"\r
-#include "../../drivers_config/mss_ace/ace_config.h"\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif \r
-\r
-/*\r
- * The ACE_set_linear_transform() is only available when using ACE configuration\r
- * files generated by Libero 9.1 or later.\r
- */\r
-#ifdef ACE_CFG_DATA_FORMAT_VERSION\r
-\r
-/*------------------------------------------------------------------------------\r
- * Masks ans shift values used to derive the ABPS ranges from the analog block\r
- * configuration.\r
- */\r
-#define ABPS1_CFG_BITS_MASK (uint32_t)0x06\r
-#define ABPS1_CFG_BITS_SHIFT (uint32_t)1\r
-\r
-#define ABPS2_CFG_BITS_MASK (uint32_t)0x60\r
-#define ABPS2_CFG_BITS_SHIFT (uint32_t)5\r
-\r
-/*------------------------------------------------------------------------------\r
- * One Bit DAC definitions.\r
- */\r
-#define OBD_CURRENT (uint32_t)1\r
-#define OBD_VOLTAGE (uint32_t)0\r
-\r
-#define OBD_MODE_MASK (uint32_t)0x01\r
-#define OBD_CHOPPING_MASK (uint32_t)0x02\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- Neutral factor and offset for m*x + c trnasform.\r
- */\r
-#define NEUTRAL_M_FACTOR 0x4000\r
-#define NEUTRAL_C_OFFSET 0x0000\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- Enumearation of the various input channel types. This is used to differentiate\r
- between channel types in order to extract the relevant factory calibration\r
- data(m1 and c1).\r
- */\r
-typedef enum channel_type\r
-{\r
- ABPS1_CHAN = 0,\r
- ABPS2_CHAN,\r
- CMB_CHAN,\r
- TMB_CHAN,\r
- DIRECT_ADC_INPUT_CHAN,\r
- OBDOUT_CHAN,\r
- FLOATING_CHAN\r
-} cal_channel_type_t;\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- This data structure is used to store factory calibration data for a specific\r
- analog input.\r
- */\r
-typedef struct __channel_calibration_t\r
-{\r
- uint16_t mext;\r
- uint16_t m1;\r
- uint16_t c1;\r
-} channel_calibration_t;\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- Local functions\r
- */\r
-int32_t extend_sign\r
-(\r
- uint16_t x\r
-);\r
-\r
-uint32_t adjust_to_24bit_ace_format\r
-(\r
- int64_t signed48\r
-);\r
-\r
-uint32_t adjust_to_16bit_ace_format\r
-(\r
- int64_t signed48\r
-);\r
-\r
-void get_calibration\r
-(\r
- adc_channel_id_t channel_id,\r
- channel_calibration_t * p_calibration\r
-);\r
-\r
-void write_transform_coefficients\r
-(\r
- ace_channel_handle_t channel_handle,\r
- uint32_t m,\r
- uint32_t c\r
-);\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- \r
- */\r
-extern const uint8_t g_ace_external_varef_used[ACE_NB_OF_ADC];\r
-\r
-extern ace_channel_desc_t g_ace_channel_desc_table[ACE_NB_OF_INPUT_CHANNELS];\r
-\r
-extern const ppe_transforms_desc_t g_ace_ppe_transforms_desc_table[ACE_NB_OF_INPUT_CHANNELS];\r
-\r
-/*------------------------------------------------------------------------------\r
- * Pointer to the manufacturing test data containing trimming information\r
- * generated during manufacturing.\r
- */\r
-static const mtd_data_t * const p_mtd_data = (mtd_data_t *)MTD_ADDRESS;\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- See "mss_ace.h" for details of how to use this function.\r
- */\r
-int16_t ACE_get_default_m_factor\r
-(\r
- ace_channel_handle_t channel_handle\r
-)\r
-{\r
- ASSERT( channel_handle < NB_OF_ACE_CHANNEL_HANDLES );\r
- \r
- return g_ace_ppe_transforms_desc_table[channel_handle].m_ppe_offset;\r
-}\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- See "mss_ace.h" for details of how to use this function.\r
- */\r
-int16_t ACE_get_default_c_offset\r
-(\r
- ace_channel_handle_t channel_handle\r
-)\r
-{\r
- ASSERT( channel_handle < NB_OF_ACE_CHANNEL_HANDLES );\r
- \r
- return g_ace_ppe_transforms_desc_table[channel_handle].c_ppe_offset;\r
-}\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- See "mss_ace.h" for details of how to use this function.\r
- \r
- m = m2 * m1 * mext\r
- c = (m2 * c1 * mext) + (c2 * mext)\r
- */\r
-void ACE_set_linear_transform\r
-(\r
- ace_channel_handle_t channel_handle,\r
- int16_t m2,\r
- int16_t c2\r
-)\r
-{\r
- adc_channel_id_t channel_id;\r
- uint32_t m;\r
- uint32_t c;\r
- int32_t m32;\r
- int64_t m64;\r
- int32_t c32;\r
- int64_t c64_1;\r
- int64_t c64_2;\r
- uint16_t m1;\r
- uint16_t c1;\r
- uint16_t mext;\r
- \r
- channel_calibration_t calibration;\r
- \r
- ASSERT( channel_handle < NB_OF_ACE_CHANNEL_HANDLES );\r
- \r
- if(channel_handle < NB_OF_ACE_CHANNEL_HANDLES)\r
- {\r
- channel_id = g_ace_channel_desc_table[channel_handle].signal_id;\r
- \r
- get_calibration(channel_id, &calibration);\r
- \r
- m1 = calibration.m1;\r
- c1 = calibration.c1;\r
- \r
- mext = calibration.mext;\r
-\r
- /* \r
- * m = m2 * m1 * mext\r
- */\r
- m32 = extend_sign(m2) * extend_sign(m1);\r
- m64 = (int64_t)m32 * extend_sign(mext);\r
- \r
- /* Convert 48-bit result to 32-bit ACE format result. */\r
- m = adjust_to_16bit_ace_format(m64);\r
-\r
- /*\r
- * c = (m2 * c1 * mext) + (c2 * mext)\r
- */\r
- c32 = extend_sign(m2) * extend_sign(c1);\r
- c64_1 = (int64_t)c32 * extend_sign(mext);\r
-\r
- c64_2 = ((int64_t)(extend_sign(c2) * extend_sign(mext))) << 14;\r
- \r
- c = adjust_to_24bit_ace_format(c64_1 + c64_2);\r
- \r
- write_transform_coefficients(channel_handle, m, c);\r
- }\r
-}\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- Extend 16-bit signed number to 32-bit signed number.\r
- */\r
-int32_t extend_sign\r
-(\r
- uint16_t x\r
-)\r
-{\r
- int32_t y;\r
- const uint32_t sign_bit_mask = 0x00008000u;\r
- \r
- y = (x ^ sign_bit_mask) - sign_bit_mask;\r
- \r
- return y;\r
-}\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- Take a 48-bit signed number, adjust it for saturation in the range -8 to\r
- +7.999, translate into 24-bit ACE format.\r
- */\r
-uint32_t adjust_to_24bit_ace_format\r
-(\r
- int64_t signed48\r
-)\r
-{\r
- int32_t ace24_format;\r
- const int64_t MAX_POSITIVE = 0x00001FFFFFFFFFFFuLL; /* +7.9999 */\r
- const int64_t MIN_NEGATIVE = 0xFFFF200000000000uLL; /* -8 */\r
- \r
- /* Check saturation. */\r
- if(signed48 > MAX_POSITIVE)\r
- {\r
- signed48 = MAX_POSITIVE;\r
- }\r
- else if(signed48 < MIN_NEGATIVE)\r
- {\r
- signed48 = MIN_NEGATIVE;\r
- }\r
- \r
- /* Adjust to 24-bit ACE format. */\r
- ace24_format = (uint32_t)(signed48 >> 14);\r
- \r
- return ace24_format;\r
-}\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- Take a 48-bit signed number, adjust it for saturation in the range -8 to\r
- +7.999, translate into 16-bit ACE format.\r
- */\r
-uint32_t adjust_to_16bit_ace_format\r
-(\r
- int64_t signed48\r
-)\r
-{\r
- int32_t ace24_format;\r
- const int64_t MAX_POSITIVE = 0x00001FFFFFFFFFFFuLL; /* +7.9999 */\r
- const int64_t MIN_NEGATIVE = 0xFFFF200000000000uLL; /* -8 */\r
- \r
- /* Check saturation. */\r
- if(signed48 > MAX_POSITIVE)\r
- {\r
- signed48 = MAX_POSITIVE;\r
- }\r
- else if(signed48 < MIN_NEGATIVE)\r
- {\r
- signed48 = MIN_NEGATIVE;\r
- }\r
- \r
- /* Adjust to 24-bit ACE format. */\r
- ace24_format = (uint32_t)(signed48 >> 20);\r
- \r
- return ace24_format;\r
-}\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- \r
- */\r
-void get_calibration\r
-(\r
- adc_channel_id_t channel_id,\r
- channel_calibration_t * p_calibration\r
-)\r
-{\r
- const uint32_t channel_mask = 0x0000000F;\r
- const uint32_t CMB_MUX_SEL_MASK = 0x01;\r
- const uint32_t TMB_MUX_SEL_MASK = 0x01;\r
- \r
- const cal_channel_type_t channel_type_lut[16] =\r
- {\r
- FLOATING_CHAN,\r
- ABPS1_CHAN,\r
- ABPS2_CHAN,\r
- CMB_CHAN,\r
- TMB_CHAN,\r
- ABPS1_CHAN,\r
- ABPS2_CHAN,\r
- CMB_CHAN,\r
- TMB_CHAN,\r
- DIRECT_ADC_INPUT_CHAN,\r
- DIRECT_ADC_INPUT_CHAN,\r
- DIRECT_ADC_INPUT_CHAN,\r
- DIRECT_ADC_INPUT_CHAN,\r
- FLOATING_CHAN,\r
- FLOATING_CHAN,\r
- OBDOUT_CHAN\r
- };\r
- \r
- cal_channel_type_t channel_type;\r
- uint32_t channel_nb;\r
- uint32_t adc_nb;\r
- uint32_t range;\r
- uint32_t quad_id;\r
- mtd_calibration_mc_t const * p_mc_coeff = 0;\r
- \r
- channel_nb = channel_id & channel_mask;\r
- channel_type = channel_type_lut[channel_nb];\r
- adc_nb = ((uint32_t)channel_id & 0x30u) >> 4u;\r
- \r
- quad_id = adc_nb * 2;\r
- \r
- if ( (channel_nb > 4) && (channel_nb < 9) ) { ++quad_id; }\r
- \r
- switch ( channel_type )\r
- {\r
- case ABPS1_CHAN:\r
- range = (ACE->ACB_DATA[quad_id].b8 & ABPS1_CFG_BITS_MASK) >> ABPS1_CFG_BITS_SHIFT;\r
- p_mc_coeff = &p_mtd_data->abps_calibration[quad_id][0][range];\r
- break;\r
- \r
- case ABPS2_CHAN:\r
- range = (ACE->ACB_DATA[quad_id].b8 & ABPS2_CFG_BITS_MASK) >> ABPS2_CFG_BITS_SHIFT;\r
- p_mc_coeff = &p_mtd_data->abps_calibration[quad_id][1][range];\r
- break;\r
- \r
- case CMB_CHAN:\r
- {\r
- uint32_t cmb_mux_sel = (uint32_t)ACE->ACB_DATA[quad_id].b9 & CMB_MUX_SEL_MASK;\r
- if ( cmb_mux_sel == 0 )\r
- { /* current monitor */\r
- p_mc_coeff = &p_mtd_data->cm_calibration[quad_id];\r
- }\r
- else\r
- { /* direct input */\r
- p_mc_coeff = &p_mtd_data->quads_direct_input_cal[quad_id][0];\r
- }\r
- }\r
- break;\r
- \r
- case TMB_CHAN:\r
- {\r
- uint32_t tmb_mux_sel = (uint32_t)ACE->ACB_DATA[quad_id].b10 & TMB_MUX_SEL_MASK;\r
- if ( tmb_mux_sel == 0 )\r
- { /* temperature monitor */\r
- p_mc_coeff = &p_mtd_data->tm_calibration[quad_id];\r
- }\r
- else\r
- { /* direct input */\r
- p_mc_coeff = &p_mtd_data->quads_direct_input_cal[quad_id][1];\r
- }\r
- }\r
- break;\r
- \r
- case DIRECT_ADC_INPUT_CHAN:\r
- {\r
- const uint32_t channel_to_direct_in_lut[16]\r
- = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 0, 0, 0};\r
- uint32_t direct_in_id;\r
- \r
- direct_in_id = channel_to_direct_in_lut[channel_id & channel_mask];\r
- p_mc_coeff = &p_mtd_data->adc_direct_input_cal[adc_nb][direct_in_id];\r
- }\r
- break;\r
- \r
- case OBDOUT_CHAN:\r
- {\r
- uint32_t obd_mode = (uint32_t)ACE->ACB_DATA[quad_id].b6 & OBD_MODE_MASK;\r
- uint32_t chopping_option = (uint32_t)ACE->ACB_DATA[quad_id].b6 & OBD_CHOPPING_MASK;\r
- if (obd_mode > 0)\r
- {\r
- obd_mode = 1;\r
- }\r
- if (chopping_option > 0)\r
- {\r
- chopping_option = 1;\r
- }\r
- p_mc_coeff = &p_mtd_data->obd_calibration[adc_nb][obd_mode][chopping_option];\r
- }\r
- break;\r
- \r
- case FLOATING_CHAN:\r
- default:\r
- /* Give neutral values is invalid channel. */\r
- p_calibration->m1 = NEUTRAL_M_FACTOR;\r
- p_calibration->c1 = NEUTRAL_C_OFFSET;\r
- break;\r
- }\r
- \r
- if (p_mc_coeff != 0)\r
- {\r
- p_calibration->m1 = p_mc_coeff->m;\r
- p_calibration->c1 = p_mc_coeff->c;\r
- \r
- }\r
- \r
- /*--------------------------------------------------------------------------\r
- Retrieve the value of the mext factor. This depends if external VAREF is\r
- used by the ADC sampling the analog input channel.\r
- */\r
- if (g_ace_external_varef_used[adc_nb])\r
- {\r
- p_calibration->mext = p_mtd_data->global_settings.varef_m;\r
- }\r
- else\r
- {\r
- p_calibration->mext = NEUTRAL_M_FACTOR;\r
- }\r
-}\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- Write new m and c transform factors into the PPE RAM. The m and c factors\r
- should be in 32-bit ACE number format. The factors will be merged with\r
- relevant PE opcode into PPE RAM. The 32-bit factors are shifted right by one\r
- byte giving a 24-bit ACE number which is then merged with an 8-bit PPE opcode\r
- located in the most significant byte of the PPE RAM location.\r
- */\r
-void write_transform_coefficients\r
-(\r
- ace_channel_handle_t channel_handle,\r
- uint32_t m,\r
- uint32_t c\r
-)\r
-{\r
- uint16_t m_ppe_offset;\r
- uint16_t c_ppe_offset;\r
- const uint32_t PPE_OPCODE_MASK = 0xFF000000u;\r
- \r
- m_ppe_offset = g_ace_ppe_transforms_desc_table[channel_handle].m_ppe_offset;\r
- c_ppe_offset = g_ace_ppe_transforms_desc_table[channel_handle].c_ppe_offset;\r
- \r
- ACE->PPE_RAM_DATA[m_ppe_offset]\r
- = (ACE->PPE_RAM_DATA[m_ppe_offset] & PPE_OPCODE_MASK) | (m >> 8u);\r
- \r
- ACE->PPE_RAM_DATA[c_ppe_offset]\r
- = (ACE->PPE_RAM_DATA[c_ppe_offset] & PPE_OPCODE_MASK) | (c >> 8u);\r
-}\r
-\r
-#endif /* ACE_CFG_DATA_FORMAT_VERSION */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
/*******************************************************************************\r
* (c) Copyright 2009 Actel Corporation. All rights reserved.\r
- * \r
+ *\r
* SVN $Revision: 2905 $\r
* SVN $Date: 2010-08-20 14:03:28 +0100 (Fri, 20 Aug 2010) $\r
*/\r
\r
#ifdef __cplusplus\r
extern "C" {\r
-#endif \r
+#endif\r
\r
#define START_ADC_CONVERSION 0x80uL\r
\r
void ACE_init( void )\r
{\r
/* Initialize driver's internal data. */\r
- ace_init_flags();\r
- \r
+ #if (ACE_NB_OF_PPE_FLAGS > 0)\r
+ ace_init_flags();\r
+ #endif\r
+\r
/* Initialize the data structures used by conversion functions. */\r
ace_init_convert();\r
}\r
uint32_t data_valid;\r
\r
ASSERT( adc_id < NB_OF_ANALOG_MODULES );\r
- \r
+\r
if ( adc_id < (uint8_t)NB_OF_ANALOG_MODULES )\r
{\r
do {\r
data_valid = *adc_status_reg_lut[adc_id] & ADC_DATAVALID_MASK;\r
} while ( !data_valid );\r
- \r
+\r
result = (uint16_t)(*adc_status_reg_lut[adc_id] & ADC_RESULT_MASK);\r
}\r
return result;\r
\r
#define SDD_ENABLE_MASK 0x20uL\r
#define SDD_REG_SEL_MASK 0x40uL\r
- \r
+\r
#define DAC0_SYNC_EN_MASK 0x10uL\r
#define DAC1_SYNC_EN_MASK 0x20uL\r
#define DAC2_SYNC_EN_MASK 0x40uL\r
)\r
{\r
ASSERT( sdd_id < NB_OF_SDD );\r
- \r
+\r
if ( sdd_id < NB_OF_SDD )\r
{\r
const uint8_t sdd_2_quad_lut[NB_OF_SDD] = {0u, 2u, 4u};\r
uint8_t obd_mode_idx = 1u;\r
uint8_t chopping_mode_idx = 0u;\r
uint32_t saved_pc2_ctrl;\r
- \r
+\r
quad_id = sdd_2_quad_lut[sdd_id];\r
- \r
+\r
/* Pause the SSE PC2 while accesses to ACB from APB3 are taking place. */\r
saved_pc2_ctrl = ACE->PC2_CTRL;\r
ACE->PC2_CTRL = 0u;\r
- \r
+\r
/* Select between voltage/current and RTZ modes.*/\r
ACE->ACB_DATA[quad_id].b6 = mode;\r
- \r
+\r
/* Load manufacturing generated trim value. */\r
if ( (mode & OBD_MODE_MASK) > 0u )\r
{\r
}\r
ACE->ACB_DATA[quad_id].b4\r
= p_mtd_data->odb_trimming[sdd_id][obd_mode_idx][chopping_mode_idx];\r
- \r
+\r
/* Restore SSE PC2 operations since no ACB accesses should take place\r
* beyond this point. */\r
ACE->PC2_CTRL = saved_pc2_ctrl;\r
- \r
+\r
/* Set SDD resolution. */\r
*dac_ctrl_reg_lut[sdd_id] = (uint32_t)resolution;\r
- \r
+\r
/* Update SDD value through SSE_DACn_BYTES01. */\r
*dac_ctrl_reg_lut[sdd_id] |= SDD_REG_SEL_MASK;\r
- \r
+\r
/* Synchronous or individual SDD update. */\r
if ( INDIVIDUAL_UPDATE == sync_update )\r
{\r
)\r
{\r
ASSERT( sdd_id < NB_OF_SDD );\r
- \r
+\r
if ( sdd_id < NB_OF_SDD )\r
{\r
*dac_ctrl_reg_lut[sdd_id] |= SDD_ENABLE_MASK;\r
)\r
{\r
ASSERT( sdd_id < NB_OF_SDD );\r
- \r
+\r
if ( sdd_id < NB_OF_SDD )\r
{\r
*dac_ctrl_reg_lut[sdd_id] &= ~SDD_ENABLE_MASK;\r
)\r
{\r
ASSERT( sdd_id < NB_OF_SDD );\r
- \r
+\r
if ( sdd_id < NB_OF_SDD )\r
{\r
*dac_byte2_reg_lut[sdd_id] = sdd_value >> 16;\r
)\r
{\r
uint32_t dac_sync_ctrl;\r
- \r
+\r
dac_sync_ctrl = ACE->DAC_SYNC_CTRL;\r
- \r
+\r
if ( SDD_NO_UPDATE != sdd0_value )\r
{\r
ACE->DAC0_BYTE2 = sdd0_value >> 16;\r
ACE->SSE_DAC2_BYTES01 = sdd2_value;\r
dac_sync_ctrl |= DAC2_SYNC_UPDATE;\r
}\r
- \r
+\r
ACE->DAC_SYNC_CTRL = dac_sync_ctrl;\r
}\r
\r
{\r
uint8_t scb_id;\r
uint32_t odd;\r
- \r
+\r
odd = (uint32_t)comp_id & 0x01uL;\r
- \r
+\r
ASSERT( comp_id < NB_OF_COMPARATORS );\r
ASSERT( reference < NB_OF_COMP_REF );\r
ASSERT( odd ); /* Only Temperature block comparators have configurable reference input. */\r
- \r
+\r
if ( (comp_id < NB_OF_COMPARATORS) && (reference < NB_OF_COMP_REF) && (odd) )\r
{\r
uint32_t saved_pc2_ctrl;\r
- \r
+\r
scb_id = comp_id_2_scb_lut[comp_id];\r
- \r
+\r
/* Pause the SSE PC2 while accesses to ACB from APB3 are taking place. */\r
saved_pc2_ctrl = ACE->PC2_CTRL;\r
ACE->PC2_CTRL = 0u;\r
- \r
+\r
if ( ADC_IN_COMP_REF == reference )\r
{\r
ACE->ACB_DATA[scb_id].b10 &= (uint8_t)~B10_COMP_VREF_SW_MASK;\r
ACE->ACB_DATA[scb_id].b10 &= (uint8_t)~B10_COMP_VREF_SW_MASK;\r
ACE->ACB_DATA[scb_id].b11 = (ACE->ACB_DATA[scb_id].b11 & (uint8_t)~B11_DAC_MUXSEL_MASK) + (uint8_t)reference;\r
}\r
- \r
+\r
/* Restore SSE PC2 operations since no ACB accesses should take place\r
* beyond this point. */\r
ACE->PC2_CTRL = saved_pc2_ctrl;\r
)\r
{\r
uint8_t scb_id;\r
- \r
+\r
ASSERT( comp_id < NB_OF_COMPARATORS );\r
ASSERT( hysteresis < NB_OF_HYSTERESIS );\r
- \r
+\r
if ( (comp_id < NB_OF_COMPARATORS) && (hysteresis < NB_OF_HYSTERESIS) )\r
{\r
uint32_t odd;\r
uint32_t saved_pc2_ctrl;\r
- \r
+\r
scb_id = comp_id_2_scb_lut[comp_id];\r
odd = (uint32_t)comp_id & 0x01uL;\r
- \r
+\r
/* Pause the SSE PC2 while accesses to ACB from APB3 are taking place. */\r
saved_pc2_ctrl = ACE->PC2_CTRL;\r
ACE->PC2_CTRL = 0u;\r
- \r
+\r
if ( odd )\r
{\r
/* Temperature monitor block comparator. */\r
/* Current monitor block comparator. */\r
ACE->ACB_DATA[scb_id].b9 = (ACE->ACB_DATA[scb_id].b9 & HYSTERESIS_MASK) | (uint8_t)((uint8_t)hysteresis << HYSTERESIS_SHIFT);\r
}\r
- \r
+\r
/* Restore SSE PC2 operations since no ACB accesses should take place\r
* beyond this point. */\r
ACE->PC2_CTRL = saved_pc2_ctrl;\r
}\r
\r
/*-------------------------------------------------------------------------*//**\r
- \r
+\r
*/\r
void ACE_enable_comp\r
(\r
)\r
{\r
uint8_t scb_id;\r
- \r
+\r
ASSERT( comp_id < NB_OF_COMPARATORS );\r
- \r
+\r
if ( comp_id < NB_OF_COMPARATORS )\r
{\r
uint32_t odd;\r
uint32_t saved_pc2_ctrl;\r
- \r
+\r
scb_id = comp_id_2_scb_lut[comp_id];\r
odd = (uint32_t)comp_id & 0x01uL;\r
- \r
+\r
/* Pause the SSE PC2 while accesses to ACB from APB3 are taking place. */\r
saved_pc2_ctrl = ACE->PC2_CTRL;\r
ACE->PC2_CTRL = 0u;\r
- \r
+\r
if ( odd )\r
{\r
/* Temperature monitor block comparator. */\r
/* Current monitor block comparator. */\r
ACE->ACB_DATA[scb_id].b9 |= COMPARATOR_ENABLE_MASK;\r
}\r
- \r
+\r
/* Restore SSE PC2 operations since no ACB accesses should take place\r
* beyond this point. */\r
ACE->PC2_CTRL = saved_pc2_ctrl;\r
)\r
{\r
uint8_t scb_id;\r
- \r
+\r
ASSERT( comp_id < NB_OF_COMPARATORS );\r
- \r
+\r
if ( comp_id < NB_OF_COMPARATORS )\r
{\r
uint32_t odd;\r
uint32_t saved_pc2_ctrl;\r
- \r
+\r
scb_id = comp_id_2_scb_lut[comp_id];\r
odd = (uint32_t)comp_id & 0x01uL;\r
- \r
+\r
/* Pause the SSE PC2 while accesses to ACB from APB3 are taking place. */\r
saved_pc2_ctrl = ACE->PC2_CTRL;\r
ACE->PC2_CTRL = 0u;\r
- \r
+\r
if ( odd )\r
{\r
/* Temperature monitor block comparator. */\r
/* Current monitor block comparator. */\r
ACE->ACB_DATA[scb_id].b9 &= (uint8_t)~COMPARATOR_ENABLE_MASK;\r
}\r
- \r
+\r
/* Restore SSE PC2 operations since no ACB accesses should take place\r
* beyond this point. */\r
ACE->PC2_CTRL = saved_pc2_ctrl;\r
)\r
{\r
ASSERT( comp_id < NB_OF_COMPARATORS );\r
- \r
+\r
ACE->COMP_IRQ_EN |= (FIRST_RISE_IRQ_MASK << (uint32_t)comp_id);\r
}\r
\r
)\r
{\r
ASSERT( comp_id < NB_OF_COMPARATORS );\r
- \r
+\r
ACE->COMP_IRQ_EN &= ~(FIRST_RISE_IRQ_MASK << (uint32_t)comp_id);\r
}\r
\r
)\r
{\r
ASSERT( comp_id < NB_OF_COMPARATORS );\r
- \r
+\r
ACE->COMP_IRQ_CLR |= (FIRST_RISE_IRQ_MASK << (uint32_t)comp_id);\r
}\r
\r
)\r
{\r
ASSERT( comp_id < NB_OF_COMPARATORS );\r
- \r
+\r
ACE->COMP_IRQ_EN |= (FIRST_FALL_IRQ_MASK << (uint32_t)comp_id);\r
}\r
\r
)\r
{\r
ASSERT( comp_id < NB_OF_COMPARATORS );\r
- \r
+\r
ACE->COMP_IRQ_EN &= ~(FIRST_FALL_IRQ_MASK << (uint32_t)comp_id);\r
}\r
\r
)\r
{\r
ASSERT( comp_id < NB_OF_COMPARATORS );\r
- \r
+\r
ACE->COMP_IRQ_CLR |= (FIRST_FALL_IRQ_MASK << (uint32_t)comp_id);\r
}\r
\r
)\r
{\r
ace_channel_handle_t channel_handle;\r
- \r
+\r
channel_handle = (ace_channel_handle_t)0;\r
- \r
+\r
return channel_handle;\r
}\r
\r
)\r
{\r
++channel_handle;\r
- \r
+\r
if ( channel_handle >= NB_OF_ACE_CHANNEL_HANDLES )\r
{\r
channel_handle = (ace_channel_handle_t)0;\r
}\r
- \r
+\r
return channel_handle;\r
}\r
\r
{\r
uint16_t channel_idx;\r
ace_channel_handle_t channel_handle = INVALID_CHANNEL_HANDLE;\r
- \r
+\r
for ( channel_idx = 0u; channel_idx < (uint16_t)ACE_NB_OF_INPUT_CHANNELS; ++channel_idx )\r
{\r
if ( g_ace_channel_desc_table[channel_idx].p_sz_channel_name != 0 )\r
{\r
uint16_t channel_idx;\r
ace_channel_handle_t channel_handle = INVALID_CHANNEL_HANDLE;\r
- \r
+\r
for ( channel_idx = 0u; channel_idx < (uint16_t)ACE_NB_OF_INPUT_CHANNELS; ++channel_idx )\r
{\r
if ( g_ace_channel_desc_table[channel_idx].signal_id == channel_id )\r
{\r
uint16_t sample;\r
uint16_t ppe_offset;\r
- \r
+\r
ppe_offset = g_ace_channel_desc_table[channel_handle].signal_ppe_offset;\r
sample = (uint16_t)(ACE->PPE_RAM_DATA[ppe_offset] >> 16u);\r
- \r
+\r
return sample;\r
}\r
\r
/*******************************************************************************\r
* (c) Copyright 2009 Actel Corporation. All rights reserved.\r
- * \r
+ *\r
* SmartFusion ACE driver public API.\r
*\r
* SVN $Revision: 2884 $\r
\95 Sigma Delta Digital to Analog Converters (SDD) control\r
\95 Direct analog block configuration and usage\r
\r
- \r
+\r
Initialization\r
The ACE driver is initialized through a call to the ACE_init() function. The\r
ACE_init() function must be called before any other ACE driver functions can\r
be called. It initializes the ACE\92s internal data.\r
\r
- \r
+\r
Reading analog input channels values and properties\r
The ACE driver allows retrieving the most recent post processed sample value\r
for each analog input. It also allows retrieving the name of the analog input\r
\95 const uint8_t * ACE_get_channel_name( ace_channel_handle_t channel_handle )\r
\95 channel_type_t ACE_get_channel_type( ace_channel_handle_t channel_handle )\r
\r
- \r
+\r
Post Processing Engine flags\r
The SmartFusion ACE Post Processing Engine (PPE) provides the ability to monitor\r
the state of analog input channels and detect when certain threshold values are\r
\95 ace_flag_handle_t ACE_get_flag_handle (const uint8_t *p_sz_full_flag_name)\r
\95 ace_flag_handle_t ACE_get_channel_first_flag (ace_channel_handle_t channel_handle, uint16_t *iterator)\r
\95 ace_flag_handle_t ACE_get_channel_next_flag (ace_channel_handle_t channel_handle, uint16_t *iterator)\r
- \r
+\r
The current status of a flag can be polled using the following function:\r
\95 int32_t ACE_get_flag_status (ace_flag_handle_t flag_handle)\r
\r
\95 const uint8_t * ACE_get_flag_name (ace_flag_handle_t flag_handle)\r
\95 ace_channel_handle_t ACE_get_flag_channel (ace_flag_handle_t flag_handle)\r
\r
- \r
+\r
Conversion to and from real world units\r
The ACE driver provides a set of conversion functions to convert sample values\r
read from the post processing engine into real world units:\r
PPE sample values. These functions are typically used for dynamically adjusting\r
flags threshold values.\r
\r
- \r
+\r
Sample Sequencing Engine control\r
The ACE driver provides a set of functions for dynamically controlling the\r
Sample Sequencing Engine. These functions are only required for managing multiple\r
sampling sequences. The use of these functions is not required for most applications\r
since the SSE is already configured and running by the time the application starts.\r
\r
- \r
+\r
Sample Sequencing Engine Interrupts Control\r
The ACE driver provides a set of functions for managing interrupts generated by\r
the Sample Sequencing Engine. These functions allow enabling, disabling and clearing\r
interrupt defined as part of the sampling sequence. These functions also allow\r
controlling interrupts generated by the ADCs.\r
\r
- \r
+\r
Comparators control\r
The ACE driver provides a set of functions for managing interrupts generated based\r
on the change of state of the high speed comparators. Functions are also provided\r
to dynamically modify the comparators configuration.\r
\r
- \r
+\r
Sigma Delta Digital to Analog Converters (SDD) control\r
The ACE driver provides functions for controlling the output value of the Sigma\r
Delta DACs (SDD). Functions are also provided for dynamically adjusting the\r
\r
#ifdef __cplusplus\r
extern "C" {\r
-#endif \r
+#endif\r
\r
-#include "../../drivers_config/mss_ace/ace_handles.h"\r
+#include "ace_handles.h"\r
\r
/*-------------------------------------------------------------------------*//**\r
Analog to Digital Converter channel IDs.\r
/*==============================================================================\r
============== Direct Analog Block Configuration and Usage ====================\r
=============================================================================*/\r
- \r
+\r
/*=========================================================================*//**\r
@defgroup group1 Direct Analog Block Configuration and Usage\r
These functions are intended for using the SmartFusion analog block hardware\r
channel identified by the channel_id parameter. This function is provided for\r
test purposes. It must not be used while the Sample Sequencing Engine is\r
running.\r
- \r
+\r
@param channel_id\r
The channel_id parameter identifies the analog input channel to sample.\r
- \r
+\r
@return\r
This function does not return a value.\r
*/\r
/*-------------------------------------------------------------------------*//**\r
The ACE_get_adc_result () function reads the result of the last input channel\r
sampling performed by the ADC identified as parameter.\r
- \r
+\r
@param adc_id\r
The adc_id parameter identifies which of the possible three ADC to read the\r
sample result from.\r
- \r
+\r
@return\r
The ACE_start_adc_sync() function returns the ADC result from the ADC\r
specified as parameter.\r
/*-------------------------------------------------------------------------*//**\r
The sdd_id_t enumeration is used to identify the Sigma Delta DACs to the SDD\r
control functions, ACE_configure_sdd(), ACE_enable_sdd(), ACE_disable_sdd()\r
- and ACE_set_sdd_value(). There is one SDD per analog module. \r
+ and ACE_set_sdd_value(). There is one SDD per analog module.\r
*/\r
typedef enum\r
{\r
\r
/*-------------------------------------------------------------------------*//**\r
The sdd_resolution_t enumeration is used as a parameter to the\r
- ACE_configure_sdd() function to specify DAC resolution of the Sigma Delta DAC. \r
+ ACE_configure_sdd() function to specify DAC resolution of the Sigma Delta DAC.\r
*/\r
typedef enum\r
{\r
more important than accuracy.\r
A call to this function is not required if relying on the configuration\r
selected in the ACE configurator being loaded after reset by the system boot.\r
- \r
+\r
@param sdd_id\r
The sdd_id parameter specifies which Sigma Delta DAC is configured by this\r
function. Allowed values are:\r
- SDD0_OUT\r
- SDD1_OUT\r
- SDD2_OUT\r
- \r
+\r
@param resolution\r
The resolution parameter specifies the desired resolution of the Sigma Delta DAC.\r
Allowed values are:\r
- SDD_8_BITS\r
- SDD_16_BITS\r
- SDD_24_BITS\r
- \r
+\r
@param mode\r
The mode parameter specifies the operating mode of the Sigma Delta DAC. It\r
specifies whether a current or voltage should be generated and whether\r
- SDD_VOLTAGE_MODE\r
- SDD_RETURN_TO_ZERO\r
- SDD_NON_RTZ\r
- \r
+\r
@param sync_update\r
The sync_update parameter specifies whether the SDD output will be updated\r
individually though a call to ACE_set_sdd_value() or synchronously with one\r
);\r
\r
/*-------------------------------------------------------------------------*//**\r
- The ACE_enable_sdd() function is used to enable a Sigma Delta DAC. \r
- \r
+ The ACE_enable_sdd() function is used to enable a Sigma Delta DAC.\r
+\r
@param sdd_id\r
The sdd_id parameter specifies the Sigma Delta DAC to enable.\r
*/\r
\r
/*-------------------------------------------------------------------------*//**\r
The ACE_disable_sdd() function is used to disable a Sigma Delta DAC.\r
- \r
+\r
@param sdd_id\r
The sdd_id parameter specifies the Sigma Delta DAC to disable.\r
*/\r
the SDD resolution into account. A maximum voltage of 2.56V or a maximum\r
current of 256uA will be generated when the sdd_value is set the maximum value\r
allowed by the SDD resolution\r
- \r
+\r
@param sdd_id\r
The sdd_id parameter specifies which Sigma Delta DAC is being set.\r
- \r
+\r
@param sdd_value\r
The sdd_value parameter specifies the value of the Sigma Delta DAC output.\r
It is a fraction of SDD resolution. The voltage/current value generated from\r
subsequently used as parameter to function ACE_get_ppe_sample() used to read\r
the most recent post processed sample for the analog input identified through\r
the channel/service name passed as argument to this function.\r
- \r
+\r
@param p_sz_channel_name\r
The p_sz_channel_name parameter is a zero-terminated string containing the\r
name of the channel/service as entered in the ACE configurator.\r
- \r
+\r
@return\r
This function returns a channel handle. This channel handle is required as\r
parameter to function ACE_get_ppe_sample().\r
It will return INVALID_CHANNEL_HANDLE if the channel/service name is not\r
recognized.\r
- \r
+\r
@code\r
uint16_t adc_result;\r
ace_channel_handle_t at0;\r
/*-------------------------------------------------------------------------*//**\r
The ACE_get_input_channel_handle() function returns the channel handle for\r
the hardware analog input channel specified as parameter.\r
- \r
+\r
@param channel_id\r
The channel_id parameter identifies a hardware analog input of the ACE.\r
- \r
+\r
@return\r
This function returns a channel handle. This channel handle is required as\r
parameter to other ACE driver functions dealing with analog inputs.\r
The ACE_get_ppe_sample() function is used to read the most recent post\r
processed sample for the analog input channel associated with the channel\r
handle passed as parameter.\r
- \r
+\r
@param channel_handle\r
The channel_handle parameter identifies the analog input channel for which\r
this function will return the most recent ADC conversion result adjusted for\r
ACE_get_channel_handle() when the name of the channel is known, or by\r
iterating though all analog input channel using the ACE_get_first_channel()\r
and ACE_get_next_channel().\r
- \r
+\r
@return\r
This function returns a 16 bit value representing the adjusted value of the\r
ADC conversion result for the analog input channel identified by the channel\r
handle passed as parameter. The return value is actually a 12, 10 or 8 bits\r
number depending on the configuration of the ADC.\r
- \r
+\r
@code\r
uint16_t adc_result;\r
ace_channel_handle_t at0;\r
associated with the channel handle passed as parameter. The channel name is\r
the name used in the ACE configurator software tool when adding a service to\r
the ACE.\r
- \r
+\r
@param channel_handle\r
The channel_handle parameter identifies the analog input channel for which\r
we want to retrieve the channel name. The available channel handle values can\r
to ACE_get_channel_handle() when the name of the channel is known, or by\r
iterating though all analog input channel using the ACE_get_first_channel()\r
and ACE_get_next_channel().\r
- \r
+\r
@return\r
This function returns a pointer to a zero-terminated string containing the\r
name of the channel. It returns 0 if the channel handle passed as parameter\r
analog input channel identified by the channel handle passed as parameter.\r
This function allows determining whether the quantity measured through the ADC\r
is a voltage, current or temperature.\r
- \r
+\r
@param channel_handle\r
The channel_handle parameter identifies one of the analog input channels\r
monitored by the ACE. The available channel handle values can be found in the\r
ACE_get_channel_handle() when the name of the channel is known, or by\r
iterating though all analog input channel using the ACE_get_first_channel()\r
and ACE_get_next_channel().\r
- \r
+\r
@return\r
This function returns one of the following values to report the type of\r
quantity measure throught the channel:\r
The ACE_get_channel_count() function returns the total number of configured\r
analog input channels. It is the number of channels available for use as\r
opposed to the theorical number of physical channels supported by the device.\r
- \r
+\r
@return\r
The ACE_get_channel_count() function returns the total number of input\r
channels that were configured in the ACE configurator.\r
The ACE_get_channel_count() function returns 0 if no input channels were\r
configured.\r
- \r
+\r
@code\r
uint32_t inc;\r
uint32_t nb_of_channels;\r
ace_channel_handle_t current_channel;\r
- \r
+\r
nb_of_channels = ACE_get_channel_count();\r
current_channel = ACE_get_first_channel();\r
- \r
+\r
for (inc = 0; inc < nb_of_channels; ++inc)\r
{\r
adc_result = ACE_get_ppe_sample( current_channel );\r
The ACE_get_first_channel() function returns the channel handle of one of the\r
channel controlled by the ACE. This function is used to start iterating though\r
the list of analog input channels handled by the ACE.\r
- \r
+\r
@return\r
The ACE_get_first_channel() function returns the first channel handle found\r
in the ACE driver's internal channel handles list or INVALID_CHANNEL_HANDLE\r
if there are no channels defined in the ACE configuration.\r
- \r
+\r
@code\r
uint32_t inc;\r
uint32_t nb_of_channels;\r
ace_channel_handle_t current_channel;\r
- \r
+\r
nb_of_channels = ACE_get_channel_count();\r
current_channel = ACE_get_first_channel();\r
- \r
+\r
for (inc = 0; inc < nb_of_channels; ++inc)\r
{\r
adc_result = ACE_get_ppe_sample( current_channel );\r
The ACE_get_next_channel() returns the channel handle of the channel following\r
the one passed as parameter. This function is used to iterate through the list\r
of analog input channels handled by the ACE.\r
- \r
+\r
@param channel_handle\r
The channel_handle parameter identifies from which channel the driver should\r
look in its channel handle list to return the next channel handle. The\r
channel_handle returned by a previous call to ACE_get_first_channel(). The\r
second and subsequent calls to ACE_get_next_channel() would typically use\r
the channel_handle returned by a previous call to ACE_get_next_channel().\r
- \r
+\r
@return\r
The ACE_get_next_channel() function returns the channel handle of the channel\r
following the one passed as parameter or INVALID_CHANNEL_HANDLE if the end of\r
the channels list has been reached.\r
- \r
+\r
@code\r
uint32_t inc;\r
uint32_t nb_of_channels;\r
ace_channel_handle_t current_channel;\r
- \r
+\r
nb_of_channels = ACE_get_channel_count();\r
current_channel = ACE_get_first_channel();\r
- \r
+\r
for (inc = 0; inc < nb_of_channels; ++inc)\r
{\r
adc_result = ACE_get_ppe_sample( current_channel );\r
Sequencing Engine sequence identified by the sequence name passed as parameter.\r
The sequence handler can then be used as parameter to other SSE sequence control\r
functions to identify the sequence to control.\r
- \r
+\r
@param p_sz_sequence_name\r
The p_sz_sequence_name parameter is a pointer to a zero-terminated string\r
containing the name of the sampling sequence for which we want to retrieve\r
the handle.\r
- \r
+\r
@return\r
The ACE_get_sse_seq_handle() function returns the handle used to identify\r
the sequence passed as parameter with other ACE driver sampling sequence\r
control functions. It returns INVALID_SSE_SEQ_HANDLE if the sequence name\r
passed as parameter is not recognized.\r
- \r
+\r
@code\r
sse_sequence_handle_t sse_seq_handle;\r
sse_seq_handle = ACE_get_sse_seq_handle("ProcedureA");\r
The ACE_load_sse() function loads the ACE Sample Sequencing Engine (SSE) RAM\r
with the microcode implementing the sampling sequence identified by the SSE\r
sequence handler passed as parameter.\r
- \r
+\r
@param sequence\r
The sequence parameter is the SSE sequence handler identifying the sampling\r
sequence to load into the ACE SSE. The value for this handler is retrieved\r
before the loop part of the sequence is started.\r
You must ensure that the sampling sequence has been loaded into the ACE's SSE\r
before calling this function.\r
- \r
+\r
@param sequence\r
The sequence parameter is the SSE sequence handler identifying the sampling\r
sequence to load into the ACE SSE. The value for this handler is retrieved\r
intialization phase of the sequence.\r
This function would typically be called after stopping the sampling sequence\r
using the ACE_stop_see() function or with non-repeating sequences.\r
- \r
+\r
@param sequence\r
The sequence parameter is the SSE sequence handler identifying the sampling\r
sequence to load into the ACE SSE. The value for this handler is retrieved\r
/*-------------------------------------------------------------------------*//**\r
The ACE_stop_sse() function stops execution of the Sample Sequencing Engine\r
(SSE) sequence indentified by the sequence handle passed as parameter.\r
- \r
+\r
@param sequence\r
The sequence parameter is the SSE sequence handle identifying the sampling\r
sequence to load into the ACE SSE. The value for this handler is retrieved\r
sampling sequence identified by the sequence handle passed as parameter to\r
resume execution. This function is typically used to restart execution of\r
a sequence at the point where it was stopped through a call to ACE_stop_sse().\r
- \r
+\r
@param sequence\r
The sequence parameter is the SSE sequence handler identifying the sampling\r
sequence to load into the ACE SSE. The value for this handler is retrieved\r
post processed samples within the ACE hardware. It is intended for use when\r
switching between sampling sequences and using peripheral DMA. It avoids\r
receiving stale samples generated as a result of a previous sampling sequence.\r
- \r
+\r
The example below shows how this function can be used to ensure that no sample\r
generated as a result of sampling sequence sequence_a will be generated once\r
sampling sequence_b is started. Please note that it is important to stop the\r
ACE_clear_sample_pipeline();\r
ACE_start_sse(sequence_b);\r
@endcode\r
- \r
+\r
The example below shows how to ensure that the first sample read through PDMA\r
will be from the first channel in the sampling sequence.\r
@code\r
ACE_restart_sse(sequence_a);\r
PDMA_start\r
(\r
- PDMA_CHANNEL_0, \r
- PDMA_ACE_PPE_DATAOUT, \r
- (uint32_t)g_samples_buffer[g_pdma_buffer_idx], \r
+ PDMA_CHANNEL_0,\r
+ PDMA_ACE_PPE_DATAOUT,\r
+ (uint32_t)g_samples_buffer[g_pdma_buffer_idx],\r
SAMPLES_BUFFER_SIZE\r
);\r
@endcode\r
/*-------------------------------------------------------------------------*//**\r
The ACE_enable_sse_irq() function enables the Sample Sequencing Engine (SSE)\r
interrupt source specified as parameter to generate interrupts.\r
- \r
+\r
@param sse_irq_id\r
The sse_irq_id parameter identifies the SSE interrupt source controlled by\r
this function.\r
/*-------------------------------------------------------------------------*//**\r
The ACE_disable_sse_irq() function disables the Sample Sequencing Engine\r
(SSE) interrupt source specified as parameter from generating interrupts.\r
- \r
+\r
@param sse_irq_id\r
The sse_irq_id parameter identifies the SSE interrupt source controlled by\r
this function.\r
/*-------------------------------------------------------------------------*//**\r
The ACE_clear_sse_irq() function clears the Sampling Sequencing Engine (SSE)\r
interrupt specified as parameter.\r
- \r
+\r
@param sse_irq_id\r
The sse_irq_id parameter identifies the SSE interrupt source controlled by\r
this function.\r
The ACE_set_comp_reference() function is used to select the reference input\r
of a temperature monitor block comparator. The reference input of a temperature\r
monitor can be an ADC direct input or one of the SDD's output.\r
- \r
+\r
@param comp_id\r
The comp_id parameter specifies the comparator for which to select the\r
- reference input. Since only temperature monitor block comparators have a \r
+ reference input. Since only temperature monitor block comparators have a\r
selectable reference input, allowed values are:\r
- CMP1\r
- CMP3\r
- CMP7\r
- CMP9\r
- CMP11\r
- \r
+\r
@param reference\r
The reference parameter specify the signal that will be used as reference\r
by the comparator. Allowed values are:\r
The ACE_set_comp_hysteresis() function is used to set the hysteresis of a\r
comparator. There are four possible hystereris settings: no hysteresis,\r
+/-10mV, +/-30mV or +/-100mV.\r
- \r
+\r
@param comp_id\r
The comp_id parameter specifies the comparator for which this function will\r
set the hyteresis.\r
- \r
+\r
@param hysteresis\r
- The hysteresis parameter specifies the hysteresis that will be applied to \r
+ The hysteresis parameter specifies the hysteresis that will be applied to\r
the comparator's input. Allowed values are:\r
- NO_HYSTERESIS\r
- HYSTERESIS_10_MV\r
- HYSTERESIS_30_MV\r
- HYSTERESIS_100_MV\r
- \r
+\r
*/\r
void ACE_set_comp_hysteresis\r
(\r
/*-------------------------------------------------------------------------*//**\r
The ACE_enable_comp() function is used to enable the comparator specified as\r
parameter.\r
- \r
+\r
@param comp_id\r
The comp_id parameter specifies which comparator will be enabled by a call\r
to this function.\r
/*-------------------------------------------------------------------------*//**\r
The ACE_disable_comp() function is used to disable the comparator specified as\r
parameter.\r
- \r
+\r
@param comp_id\r
The comp_id parameter specifies which comparator will be disabled by a call\r
to this function.\r
- void ACE_Comp9_Rise_IRQHandler( void );\r
- void ACE_Comp10_Rise_IRQHandler( void );\r
- void ACE_Comp11_Rise_IRQHandler( void );\r
- \r
+\r
@param comp_id\r
The comp_id parameter specifies which comparator will be enabled to generate\r
rising interrupts.\r
The ACE_disable_comp_rise_irq() function is used to disable interrupts from\r
being generated when the positive input of the comparator specified as parameter\r
rises above the negative input of the comparator.\r
- \r
+\r
@param comp_id\r
The comp_id parameter specifies which comparator will be disabled from\r
generating rising interrupts.\r
/*-------------------------------------------------------------------------*//**\r
The ACE_clear_comp_rise_irq() function is used to clear rise interrupts. This\r
function is typically called as part of the rise interrupt service routine.\r
- \r
+\r
@param comp_id\r
The comp_id parameter specifies the comparator for which to clear the rise\r
interrupt.\r
- \r
+\r
Example:\r
@code\r
void ACE_Comp1_Rise_IRQHandler( void )\r
- void ACE_Comp9_Fall_IRQHandler( void );\r
- void ACE_Comp10_Fall_IRQHandler( void );\r
- void ACE_Comp11_Fall_IRQHandler( void );\r
- \r
+\r
@param comp_id\r
The comp_id parameter specifies which comparator will be enabled to generate\r
fall interrupts.\r
The ACE_disable_comp_fall_irq() function is used to disable interrupts from\r
being generated when the positive input of the comparator specified as parameter\r
falls below the negative input of the comparator.\r
- \r
+\r
@param comp_id\r
The comp_id parameter specifies which comparator will be disabled from\r
generating fall interrupts.\r
/*-------------------------------------------------------------------------*//**\r
The ACE_clear_comp_fall_irq() function is used to clear fall interrupts. This\r
function is typically called as part of the fall interrupt service routine.\r
- \r
+\r
@param comp_id\r
The comp_id parameter specifies the comparator for which to clear the fall\r
interrupt.\r
- \r
+\r
Example:\r
@code\r
void ACE_Comp1_Fall_IRQHandler( void )\r
status. It returns a 32 bit value indicating which comparators experienced a\r
fall and/or rise event. These status bits can be cleared using the\r
ACE_clear_comp_rise_irq() and ACE_clear_comp_fall_irq() functions.\r
- \r
+\r
@return\r
The return value is a 32 bit numnber where bits 0 to 11 indicate which\r
comparator experienced a fall event and bits 21 to 23 indicate which\r
The ACE_is_hysteresis_flag() function indicates if an hysteresis is applied\r
to the analog input sample value when determining the state of the flag\r
identified as parameter.\r
- \r
+\r
@param flag_handle\r
The flag_handle parameter identifies one of the flags generated based on the\r
value of an analog input channel. The available flag handle values can be\r
ACE_get_flag_handle() when the name of the flag is known, or by iterating\r
though all flags associated with an analog input channel using the\r
ACE_get_channel_first_flag() and ACE_get_channel_next_flag().\r
- \r
+\r
@return\r
This function returns the value one if a hysteresis is applied to the channel\r
sample values as part of determining the state of the flag identified as\r
The ACE_is_under_flag() function indicates whether a flag is triggered when the\r
monitored analog input falls below the flag's threshold level or above the\r
flag's threshold level.\r
- \r
+\r
@param flag_handle\r
The flag_handle parameter identifies one of the flags generated based on the\r
value of an analog input channel. The available flag handle values can be\r
ACE_get_flag_handle() when the name of the flag is known, or by iterating\r
though all flags associated with an analog input channel using the\r
ACE_get_channel_first_flag() and ACE_get_channel_next_flag().\r
- \r
+\r
@return\r
This function returns the value one if the flag identified as parameter\r
triggers as a result of the monitored input falling below the flag's\r
over flag configured with a 100 millivolts hysteresis will result in the flag\r
being asserted when the voltage reaches 1.1 volts and deasserted when the\r
voltage falls below 0.9 volt.\r
- \r
+\r
@param flag_handle\r
The flag_handle parameter identifies one of the flags generated based on the\r
value of an analog input channel. The available flag handle values can be\r
ACE_get_flag_handle() when the name of the flag is known, or by iterating\r
though all flags associated with an analog input channel using the\r
ACE_get_channel_first_flag() and ACE_get_channel_next_flag().\r
- \r
+\r
@param new_threshold\r
The new_threshold parameter specifies the new threshold level that must be\r
reached in order for the flag to be raised. The value of this parameter is\r
the sample value resulting from a post processing engine conversion of the\r
desired analog input threshold level.\r
- \r
+\r
Example:\r
The function below sets the threshold of the flag specified as parameter to\r
1 volt.\r
{\r
uint16_t new_threshold;\r
ace_channel_handle_t channel_handle;\r
- \r
+\r
channel_handle = ACE_get_flag_channel(flag_handle);\r
new_threshold = ACE_convert_from_mV(channel_handle, 1000);\r
ACE_set_flag_threshold(flag_handle, new_threshold);\r
ACE_get_flag_handle() when the name of the flag is known, or by iterating\r
though all flags associated with an analog input channel using the\r
ACE_get_channel_first_flag() and ACE_get_channel_next_flag().\r
- \r
+\r
@param adc_hysteresis\r
The adc_hysteresis parameter is the value to add and subtract to the\r
threshold value to obtain the hysteresis high and low limits triggering flag\r
configurator for one of the analog inputs and one of the flags associated\r
with that input.\r
The method used to compute the adc_hysteresis value will work for all\r
- input types including ABPS inputs where zero Volts is not equivalent to a \r
+ input types including ABPS inputs where zero Volts is not equivalent to a\r
PPE sample value of zero.\r
- \r
+\r
@code\r
ace_channel_handle_t channel_handle;\r
ace_flag_handle_t flag_handle;\r
uint16_t adc_hysteresis;\r
uint16_t upper_limit;\r
uint16_t lower_limit;\r
- \r
+\r
channel_handle = VoltageMonitor;\r
flag_handle = VoltageMonitor_OVER_1V;\r
- \r
+\r
upper_limit = ACE_convert_from_mV(channel_handle, 100);\r
lower_limit = ACE_convert_from_mV(channel_handle, 0);\r
- \r
+\r
if (upper_limit > lower_limit)\r
{\r
adc_hysteresis = upper_limit - lower_limit;\r
{\r
adc_hysteresis = lower_limit - upper_limit;\r
}\r
- \r
+\r
ACE_set_flag_hysteresis(flag_handle, adc_hysteresis);\r
@endcode\r
*/\r
ACE_get_flag_handle() when the name of the flag is known, or by iterating\r
though all flags associated with an analog input channel using the\r
ACE_get_channel_first_flag() and ACE_get_channel_next_flag().\r
- \r
+\r
@param assertion_value\r
The assertion_value parameter is the Post Processing Engine sample value that\r
must be reached for the flag, identified through the flag_handle parameter,\r
intended to be used where the threshold value is not centered within the\r
hysteresis window. They allow specifying the actual threshold values at which\r
the flag will be asserted and deasserted.\r
- \r
+\r
@param flag_handle\r
The flag_handle parameter identifies one of the flags generated based on the\r
value of an analog input channel. The available flag handle values can be\r
ACE_get_flag_handle() when the name of the flag is known, or by iterating\r
though all flags associated with an analog input channel using the\r
ACE_get_channel_first_flag() and ACE_get_channel_next_flag().\r
- \r
+\r
@param assertion_value\r
The assertion_value parameter is the Post Processing Engine sample value\r
that must be reached for the flag, identified through the flag_handle\r
analog input channel sample values when generating flags. It sets the\r
hysteresis for all flags generated based on the value of the analog input\r
channel identified by the channel handle passed as first parameter.\r
- \r
+\r
@param channel_handle\r
The channel_handle parameter identifies one of the analog input channels\r
monitored by the ACE. The available channel handle values can be found in\r
/*-------------------------------------------------------------------------*//**\r
*\r
*/\r
- \r
+\r
/*==============================================================================\r
================================== Flags ======================================\r
=============================================================================*/\r
by the flag name passed as parameter. The flag handle obtained through this\r
function is then used as parameter to other flag control functions to identify\r
which flag is to be controlled by the called function.\r
- \r
+\r
@param p_sz_full_flag_name\r
The p_sz_full_flag_name parameter is a pointer to a zero-terminated string\r
holding the name of the flag as specified in the ACE configurator. The full\r
For example, the full name for the flag called "CriticalOver" raised when\r
the input channel called "MainSupply" reaches a critical level would be\r
named "MainSupply:CriticalOver".\r
- \r
+\r
@return\r
The ACE_get_flag_handle() returns the flag handle associated with the flag\r
name passed as parameter. It returns INVALID_FLAG_HANDLE when the flag name\r
The ACE_get_flag_status() function returns the current status of the flag\r
specified as parameter. The flag is identified through the name specified in\r
the ACE configurator when the flag was created.\r
- \r
+\r
@param flag_handle\r
The flag_handle parameter identifies one of the flags generated based on the\r
value of an analog input channel. The available flag handle values can be\r
ACE_get_flag_handle() when the name of the flag is known, or by iterating\r
though all flags associated with an analog input channel using the\r
ACE_get_channel_first_flag() and ACE_get_channel_next_flag().\r
- \r
+\r
@return\r
The ACE_get_flag_status() function returns one of the following values\r
depending on the current status of the flag:\r
sampled on the analog input channel identified as parameter are enabled to\r
generate interrupts by this function. It enables flag interrupts both at the\r
ACE PEE flag and Cortex-M3 interrupt controller levels.\r
- \r
+\r
@param channel_handle\r
The channel_handle parameter identifies one of the analog input channels\r
monitored by the ACE. The available channel handle values can be found in the\r
generating interrupts by this function. The interrupt is only disabled at the\r
ACE PPE flag level in order to avoid disabling other cahnnel's flag interrupts\r
which may happen to use the same ACE threshold interrupt line.\r
- \r
+\r
@param channel_handle\r
The channel_handle parameter identifies one of the analog input channels\r
monitored by the ACE. The available channel handle values can be found in the\r
sampled on the analog input channel identified as parameter are cleared by\r
this function. This function would typically be used before enabling the flag\r
interrupts in order to ignore past events.\r
- \r
+\r
@param channel_handle\r
The channel_handle parameter identifies one of the analog input channels\r
monitored by the ACE. The available channel handle values can be found in the\r
generated flags specified as parameter to interrupt the Cortex-M3 processor.\r
It enables flag interrupts both at the ACE PPE flag and Cortex-M3 interrupt\r
controller levels.\r
- \r
+\r
@param flag_handle\r
The flag_handle parameter identifies one of the flags generated based on the\r
value of an analog input channel. The available flag handle values can be\r
generated flags from interrupting the Cortex-M3. The interrupt is only\r
disabled at the ACE PPE flag level in order to avoid disabling other flags\r
interrupts which may happen to use the same ACE threshold interrupt line.\r
- \r
+\r
@param flag_handle\r
The flag_handle parameter identifies one of the flags generated based on the\r
value of an analog input channel. The available flag handle values can be\r
The ACE_clear_flag_irq() function clears the interrupt for the flag specified\r
as parameter. This function would typically be used before enabling the flag\r
interrupt in order to ignore past events.\r
- \r
+\r
@param flag_handle\r
The flag_handle parameter identifies one of the flags generated based on the\r
value of an analog input channel. The available flag handle values can be\r
/*-------------------------------------------------------------------------*//**\r
The ACE_get_flag_name() function returns the name of the flag identified by\r
the flag handle passed as parameter.\r
- \r
+\r
@param flag_handle\r
The flag_handle parameter identifies one of the flags generated based on the\r
value of an analog input channel. The available flag handle values can be\r
ACE_get_flag_handle() when the name of the flag is known, or by iterating\r
though all flags associated with an analog input channel using the\r
ACE_get_channel_first_flag() and ACE_get_channel_next_flag().\r
- \r
+\r
@return\r
The ACE_get_flag_name() function returns a pointer to a zero-terminated\r
string containing the name of the flag identified by the flag handle passed\r
The ACE_get_flag_channel() function returns the handle of the channel\r
monitored in order to generate the flag identified by the flag handle passed\r
as parameter.\r
- \r
+\r
@param flag_handle\r
The flag_handle parameter identifies one of the flags generated based on the\r
value of an analog input channel. The available flag handle values can be\r
ACE_get_flag_handle() when the name of the flag is known, or by iterating\r
though all flags associated with an analog input channel using the\r
ACE_get_channel_first_flag() and ACE_get_channel_next_flag().\r
- \r
+\r
@return\r
The ACE_get_flag_channel() function returns a channel handle identifying the\r
analog input channel monitored by the flag passed as parameter.\r
associated with the input channel specified by the channel_handle parameter.\r
It indicates how many flags are generated based on the value of the specified\r
analog input channel.\r
- \r
+\r
@param channel_handle\r
The channel_handle parameter identifies one of the analog input channels\r
monitored by the ACE. The available channel handle values can be found in\r
ACE_get_channel_handle() when the name of the channel is known, or by\r
iterating though all analog input channel using the ACE_get_first_channel()\r
and ACE_get_next_channel().\r
- \r
+\r
@return\r
The ACE_get_channel_flag_count() function returns the total number of flags\r
that are generated based on the value of the specified analog input channel.\r
The ACE_get_channel_flag_count() function returns 0 if no input channels were\r
configured.\r
- \r
+\r
Example\r
@code\r
uint32_t inc;\r
uint16_t flag_iterator;\r
ace_flag_handle_t current_flag;\r
ace_channel_handle_t channel_handle;\r
- \r
+\r
nb_of_flags = ACE_get_channel_flag_count(channel_handle);\r
current_flag = ACE_get_channel_first_flag(channel_handle, &flag_iterator);\r
- \r
+\r
for (inc = 0; inc < nb_of_flags; ++inc)\r
{\r
current_flag = ACE_get_channel_next_flag(channel_handle, &flag_iterator);\r
pointed to by the second function parameter. The iterator can be used\r
subsequently as a parameter to the ACE_get_channel_next_flag() function to\r
iterate through all flags associated with the analog input channel.\r
- \r
+\r
@param channel_handle\r
The channel_handle parameter identifies one of the analog input channels\r
monitored by the ACE. The available channel handle values can be found in the\r
ACE_get_channel_handle() when the name of the channel is known, or by\r
iterating though all analog input channel using the ACE_get_first_channel()\r
and ACE_get_next_channel().\r
- \r
+\r
@param iterator\r
The iterator parameter is a pointer to a uint16_t iterator variable. The\r
value of the iterator variable will be set by the ACE_get_channel_first_flag()\r
functions so that it can be used in subsequent calls to\r
ACE_get_channel_next_flag() to keep track of the current location in the\r
list of flags associated with the analog input channel.\r
- \r
+\r
@return\r
The ACE_get_channel_first_flag() function returns a flag handle identifying\r
one of the flags generated based on the value of the analog input channel\r
identified by the channel_handle parameter. It returns INVALID_FLAG_HANDLE\r
if no flags are generated based on the analog input channel input or if the\r
channel handle is invalid.\r
- \r
+\r
Example\r
@code\r
uint32_t inc;\r
uint16_t flag_iterator;\r
ace_flag_handle_t current_flag;\r
ace_channel_handle_t channel_handle;\r
- \r
+\r
nb_of_flags = ACE_get_channel_flag_count(channel_handle);\r
current_flag = ACE_get_channel_first_flag(channel_handle, &flag_iterator);\r
- \r
+\r
for (inc = 0; inc < nb_of_flags; ++inc)\r
{\r
current_flag = ACE_get_channel_next_flag(channel_handle, &flag_iterator);\r
associated with the analog input channel identified by the channel handle\r
passed as parameter. The retrieved flag handle is the next one in the driver's\r
internal flag list based on the iterator parameter.\r
- \r
+\r
@param channel_handle\r
The channel_handle parameter identifies one of the analog input channels\r
monitored by the ACE. The available channel handle values can be found in the\r
ACE_get_channel_handle() when the name of the channel is known, or by\r
iterating though all analog input channel using the ACE_get_first_channel()\r
and ACE_get_next_channel().\r
- \r
+\r
@param iterator\r
The iterator parameter is a pointer to a uint16_t iterator variable. The value\r
of the iterator variable will be set by the ACE_get_channel_first_flag()\r
functions so that it can be used in subsequent calls to\r
ACE_get_channel_next_flag() to keep track of the current location in the list\r
of flags associated with the analog input channel.\r
- \r
+\r
Example\r
@code\r
uint32_t inc;\r
uint16_t flag_iterator;\r
ace_flag_handle_t current_flag;\r
ace_channel_handle_t channel_handle;\r
- \r
+\r
nb_of_flags = ACE_get_channel_flag_count(channel_handle);\r
current_flag = ACE_get_channel_first_flag(channel_handle, &flag_iterator);\r
- \r
+\r
for (inc = 0; inc < nb_of_flags; ++inc)\r
{\r
current_flag = ACE_get_channel_next_flag(channel_handle, &flag_iterator);\r
with the ACE driver and associated with a particular flag through the\r
ACE_register_flag_isr() function. The ACE driver will call the flag handler\r
function when the associated flag is raised.\r
- \r
+\r
Declaring and Implementing PPE Flag Handler Functions\r
PPE flag handler functions should follow the following prototype:\r
void my_flag_handler ( ace_flag_handle_t flag_handle );\r
The actual name of the PPE flag handler is unimportant. You can use any name of\r
- your choice for the PPE flag handler. \r
+ your choice for the PPE flag handler.\r
The flag_handle parameter passes the handle of the raised flag to the flag\r
handler function.\r
*/\r
The ACE_register_flag_isr() function is used to register a handler function\r
with the ACE driver. The registered function will be called by the ACE driver\r
when the associated flag is raised by the ACE post processing engine.\r
- \r
+\r
@param flag_handle\r
The flag_handle parameter identifies one of the flags generated based on the\r
value of an analog input channel. The available flag handle values can be\r
ACE_get_flag_handle() when the name of the flag is known, or by iterating\r
though all flags associated with an analog input channel using the\r
ACE_get_channel_first_flag() and ACE_get_channel_next_flag().\r
- \r
+\r
@param flag_isr\r
The flag_isr parameter is a pointer to a flag handler function with the\r
- following prototype: \r
- void handler_function_name(ace_flag_handle_t flag_handle) \r
+ following prototype:\r
+ void handler_function_name(ace_flag_handle_t flag_handle)\r
The flag handler function is called by the ACE driver as part of the relevant\r
post processing engine flag interrupt service routine. It does not need to\r
handle flag interrupt clearing as this is done by the ACE driver.\r
\r
- \r
+\r
@code\r
void my_critical_handler( void );\r
- \r
+\r
void system_init( void )\r
{\r
ace_flag_handle_t flag_handle;\r
- \r
+\r
flag_handle = ACE_get_flag_handle( "MainSupply:CriticalLevel" );\r
ACE_register_flag_isr( flag_handle, my_critical_handler );\r
ACE_enable_flag_irq( flag_handle );\r
}\r
- \r
+\r
void my_critical_handler( ace_flag_handle_t flag_handle )\r
{\r
panic( flag_handle );\r
}\r
- \r
+\r
@endcode\r
*/\r
void ACE_register_flag_isr\r
channel through the ACE_register_channel_flags_isr() function. The ACE driver\r
will call the channel flags handler function when one of the flags for the\r
associated ADC input channel is raised.\r
- \r
+\r
Declaring and Implementing PPE Channel Flag Handler Functions\r
PPE channel flag handler functions should follow the following prototype:\r
void my_channel_flag_handler ( ace_flag_handle_t flag_handle );\r
handler will be called by the ACE driver when one of the flag generated based\r
on the value of the analog input channel identified by the channel handle\r
passed as parameter is asserted.\r
- \r
+\r
@param channel_handle\r
The channel_handle parameter identifies one of the analog input channels\r
monitored by the ACE. The available channel handle values can be found in the\r
ACE_get_channel_handle() when the name of the channel is known, or by\r
iterating though all analog input channel using the ACE_get_first_channel()\r
and ACE_get_next_channel().\r
- \r
+\r
@param channel_flag_isr\r
The channel_flag_isr parameter is pointer to a function taking a flag handle\r
- as parameter. \r
- void handler_function_name(ace_flag_handle_t flag_handle) \r
+ as parameter.\r
+ void handler_function_name(ace_flag_handle_t flag_handle)\r
The flag handler function is called by the ACE driver as part of the relevant\r
post processing engine flag interrupt service routine. It does not need to\r
handle flag interrupt clearing as this is done by the ACE driver.\r
- \r
+\r
Example\r
The example below demonstrates the use of the ACE_register_channel_flags_isr()\r
function in a system where the ACE is configured to have an analog input\r
channels named "MainSupply" with one flag named "Critical" generated based\r
on the value of "MainSupply" channel. The names "MainSupply" and "Critical"\r
- were user selected in the ACE configurator. \r
+ were user selected in the ACE configurator.\r
@code\r
void main_supply_handler (ace_flag_handle_t flag_handle);\r
- \r
+\r
void system_init(void)\r
{\r
ACE_register_channel_flag_isr(MainSupply, main_supply_handler);\r
ACE_enable_channel_flags_irq(MainSupply);\r
}\r
- \r
+\r
void main_supply_handler (ace_flag_handle_t flag_handle)\r
{\r
if (MainSupply_Critical == flag_handle)\r
panic(flag_handle);\r
}\r
}\r
- \r
+\r
@endcode\r
*/\r
void ACE_register_channel_flags_isr\r
registered with the ACE driver through the ACE_register_global_flags_isr()\r
function. The ACE driver will call the global flags handler function when any\r
flag for any ADC input channel is raised.\r
- \r
+\r
Declaring and Implementing Global Flag Handler Functions\r
PPE global flag handler functions should follow the following prototype:\r
- void my_global_flag_handler( \r
- ace_flag_handle_t flag_handle, \r
- ace_channel_handle_t channel_handle \r
+ void my_global_flag_handler(\r
+ ace_flag_handle_t flag_handle,\r
+ ace_channel_handle_t channel_handle\r
);\r
The actual name of the PPE global flag handler is unimportant. You can use any\r
name of your choice for the PPE global flag handler. The flag_handle parameter\r
The ACE_register_global_flags_isr() function is used to register a global\r
flag handler function with the ACE driver. The registered global handler will\r
be called when any flag interrupt is generated.\r
- \r
+\r
@param global_flag_isr\r
The global_flag_isr parameter is a pointer to a function taking a flag\r
handle and channel handle as parameter.\r
ACE_get_channel_handle() when the name of the channel is known, or by\r
iterating though all analog input channel using the ACE_get_first_channel()\r
and ACE_get_next_channel().\r
- \r
+\r
@param sample_value\r
The sample_value parameter is the result of an analog to digital conversion.\r
- \r
+\r
@return\r
The ACE_convert_adc_input_to_mV() returns the number of millivolts derived\r
from the ADC sample value passed as parameter.\r
/*-------------------------------------------------------------------------*//**\r
The ACE_convert_to_mV() function converts a PPE sample value into milli-Volts.\r
It handles prescaling adjusments based on ACE configuration for ABPS inputs.\r
- \r
+\r
@param channel_handle\r
The channel_handle parameter identifies one of the analog input channels\r
monitored by the ACE. The available channel handle values can be found in the\r
ACE_get_channel_handle() when the name of the channel is known, or by\r
iterating though all analog input channel using the ACE_get_first_channel()\r
and ACE_get_next_channel().\r
- \r
+\r
@param sample_value\r
The sample_value parameter is the result of an analog to digital conversion.\r
- \r
+\r
@return\r
The ACE_convert_to_mV() returns the number of millivolts derived from the\r
PPE sample value passed as parameter. The returned value can be either\r
The ACE_convert_to_mA() function converts a PPE sample value into milli-Amps.\r
The result of the conversion is only meaningful if the PPE sample value\r
results from the conversion of a current monitor input.\r
- \r
+\r
@param channel_handle\r
The channel_handle parameter identifies one of the analog input channels\r
monitored by the ACE. The available channel handle values can be found in the\r
ACE_get_channel_handle() when the name of the channel is known, or by\r
iterating though all analog input channel using the ACE_get_first_channel()\r
and ACE_get_next_channel().\r
- \r
+\r
@param sample_value\r
The sample_value parameter is the result of an analog to digital conversion\r
of the voltage generated by a current monitor analog block.\r
- \r
+\r
@return\r
The ACE_convert_to_mA() returns the number of milliamps derived from the\r
PPE sample value passed as parameter.\r
The ACE_convert_to_Kelvin() function converts a PPE sample value into degrees\r
Kelvin. The result of the conversion is only meaningful if the PPE sample value\r
results from the conversion of a temperature monitor input.\r
- \r
+\r
@param channel_handle\r
The channel_handle parameter identifies one of the analog input channels\r
monitored by the ACE. The available channel handle values can be found in the\r
ACE_get_channel_handle() when the name of the channel is known, or by\r
iterating though all analog input channel using the ACE_get_first_channel()\r
and ACE_get_next_channel().\r
- \r
+\r
@param sample_value\r
The sample_value parameter is the result of an analog to digital conversion\r
of the voltage generated by a temperature monitor analog block.\r
- \r
+\r
@return\r
The ACE_convert_to_Kelvin() returns the number of degrees Kelvin derived\r
from the PPE sample value passed as parameter.\r
The ACE_convert_to_Celsius() function converts a PPE sample value into tenths\r
of degrees Celsius. The result of the conversion is only meaningful if the PPE\r
sample value results from the conversion of a temperature monitor input.\r
- \r
+\r
@param channel_handle\r
The channel_handle parameter identifies one of the analog input channels\r
monitored by the ACE. The available channel handle values can be found in the\r
ACE_get_channel_handle() when the name of the channel is known, or by\r
iterating though all analog input channel using the ACE_get_first_channel()\r
and ACE_get_next_channel().\r
- \r
+\r
@param sample_value\r
The sample_value parameter is the result of an analog to digital conversion\r
of the voltage generated by a temperature monitor analog block.\r
- \r
+\r
@return\r
The ACE_convert_to_Celsius() returns the number of tenths of degrees Celsius\r
derived from the PPE sample value passed as parameter.\r
The ACE_convert_to_Fahrenheit() function converts a PPE sample value into\r
degrees Fahrenheit. The result of the conversion is only meaningful if the PPE\r
sample value results from the conversion of a temperature monitor input.\r
- \r
+\r
@param channel_handle\r
The channel_handle parameter identifies one of the analog input channels\r
monitored by the ACE. The available channel handle values can be found in the\r
ACE_get_channel_handle() when the name of the channel is known, or by\r
iterating though all analog input channel using the ACE_get_first_channel()\r
and ACE_get_next_channel().\r
- \r
+\r
@param sample_value\r
The sample_value parameter is the result of an analog to digital conversion\r
of the voltage generated by a temperature monitor analog block.\r
- \r
+\r
@return\r
The ACE_convert_to_Fahrenheit() returns the number of degrees Fahrenheit\r
derived from the PPE sample value passed as parameter.\r
This function is intended for use when directly controlling the ADC, not when\r
using samples read from the PPE. It does not account for prescaling taking\r
place before the ADC hardware input.\r
- \r
+\r
@param channel_handle\r
The channel_handle parameter identifies one of the analog input channels\r
monitored by the ACE. The available channel handle values can be found in the\r
ACE_get_channel_handle() when the name of the channel is known, or by\r
iterating though all analog input channel using the ACE_get_first_channel()\r
and ACE_get_next_channel().\r
- \r
+\r
@param voltage\r
The voltage parameter is the milli-Volts voltage value for which we want this\r
function to return the associated ADC sample result value.\r
- \r
+\r
@return\r
The ACE_convert_mV_to_adc_value() returns the ADC sample value that would be\r
produced if the analog input channel identified by channel_handle was set to\r
voltage value on the analog input channel specified as parameter.\r
This function handles prescaling adjusments based on ACE configuration for\r
ABPS inputs.\r
- \r
+\r
@param channel_handle\r
The channel_handle parameter identifies one of the analog input channels\r
monitored by the ACE. The available channel handle values can be found in the\r
ACE_get_channel_handle() when the name of the channel is known, or by\r
iterating though all analog input channel using the ACE_get_first_channel()\r
and ACE_get_next_channel().\r
- \r
+\r
@param voltage\r
The voltage parameter is the milli-Volts voltage value for which we want this\r
function to return the associated PPE sample result value.\r
- \r
+\r
@return\r
The ACE_convert_from_mV() returns the PPE sample value that would be produced\r
if the analog input channel identified by channel_handle was set to the\r
current value on the analog input channel specified as parameter.\r
The result of the conversion is only meaningful if the analog input channel\r
specified as parameter is configured as a current monitoring channel.\r
- \r
+\r
@param channel_handle\r
The channel_handle parameter identifies one of the analog input channels\r
monitored by the ACE. The available channel handle values can be found in the\r
ACE_get_channel_handle() when the name of the channel is known, or by\r
iterating though all analog input channel using the ACE_get_first_channel()\r
and ACE_get_next_channel().\r
- \r
+\r
@param current\r
The current parameter is the milli-Amps current value for which we want this\r
function to return the associated PPE sample result value.\r
- \r
+\r
@return\r
The ACE_convert_from_mA() returns the PPE sample value that would be produced\r
if the analog input channel identified by channel_handle was set to the\r
temperature value on the analog input channel specified as parameter.\r
The result of the conversion is only meaningful if the analog input channel\r
specified as parameter is configured as a temperature monitoring channel.\r
- \r
+\r
@param channel_handle\r
The channel_handle parameter identifies one of the analog input channels\r
monitored by the ACE. The available channel handle values can be found in the\r
ACE_get_channel_handle() when the name of the channel is known, or by\r
iterating though all analog input channel using the ACE_get_first_channel()\r
and ACE_get_next_channel().\r
- \r
+\r
@param temperature\r
The temperature parameter is the degrees Kelvin temperature value for which\r
we want this function to return the associated PPE sample result value.\r
- \r
+\r
@return\r
The ACE_convert_from_Kelvin() returns the PPE sample value that would be\r
produced if the analog input channel identified by channel_handle was set to\r
temperature value on the analog input channel specified as parameter.\r
The result of the conversion is only meaningful if the analog input channel\r
specified as parameter is configured as a temperature monitoring channel.\r
- \r
+\r
@param channel_handle\r
The channel_handle parameter identifies one of the analog input channels\r
monitored by the ACE. The available channel handle values can be found in the\r
ACE_get_channel_handle() when the name of the channel is known, or by\r
iterating though all analog input channel using the ACE_get_first_channel()\r
and ACE_get_next_channel().\r
- \r
+\r
@param temperature\r
The temperature parameter is the degrees Celsius temperature value for which\r
we want this function to return the associated PPE sample result value.\r
- \r
+\r
@return\r
The ACE_convert_from_Celsius() returns the PPE sample value that would be\r
produced if the analog input channel identified by channel_handle was set to\r
this temperature value on the analog input channel specified as parameter.\r
The result of the conversion is only meaningful if the analog input channel\r
specified as parameter is configured as a temperature monitoring channel.\r
- \r
+\r
@param channel_handle\r
The channel_handle parameter identifies one of the analog input channels\r
monitored by the ACE. The available channel handle values can be found in the\r
ACE_get_channel_handle() when the name of the channel is known, or by\r
iterating though all analog input channel using the ACE_get_first_channel()\r
and ACE_get_next_channel().\r
- \r
+\r
@param temperature\r
The temperature parameter is the degrees Fahrenheit temperature value for\r
which we want this function to return the associated PPE sample result value.\r
- \r
+\r
@return\r
The ACE_convert_from_Fahrenheit() returns the PPE sample value that would be\r
produced if the analog input channel identified by channel_handle was set to\r
The PDMA sampling values are obtained by configuring the PDMA controller to\r
transfer data from the ACE into a memory buffer. The ACE_translate_pdma_value()\r
function is used to interpret the content of that memory buffer.\r
- \r
+\r
Please note that the translation of PDMA data containing raw ADC values from\r
ABPS inputs will result in sample values with an unexpected polarity.\r
The returned sample value will have the opposite polarity to the actual analog\r
the analog front end that are normally hidden by the PPE processing of ADC raw\r
samples. The translation of raw ADC values from analog inputs other than ABPS\r
inputs will result in correct sample values.\r
- \r
+\r
@param pdma_value\r
The pdma_value parameter is a 32-bit value received from the ACE through a\r
- peripheral DMA transfer. \r
- \r
+ peripheral DMA transfer.\r
+\r
@param channel_id\r
The channel_id parameter is a pointer to an ADC channel ID variable. It is\r
used to return the ID of the ADC channel from which the PPE sample value\r
was generated from. This parameter can be set to zero if retrieving the\r
channel ID is not required.\r
- \r
+\r
@return\r
The ACE_translate_pdma_value() returns the PPE sample value extracted from\r
the PDMA sampling value.\r
- \r
+\r
Example:\r
@code\r
uint16_t ppe_value;\r
uint16_t pdma_value;\r
adc_channel_id_t channel_id;\r
ace_channel_handle_t channel_handle;\r
- \r
+\r
pdma_value = get_next_pdma_ace_sample();\r
ppe_value = ACE_translate_pdma_value(pdma_value, &channel_id);\r
channel_handle = ACE_get_input_channel_handle(channel_id);\r
display_value(channel_handle, ppe_value);\r
}\r
@endcode\r
- \r
+\r
*/\r
uint16_t ACE_translate_pdma_value\r
(\r
- ACE_get_default_c_offset()\r
- ACE_set_linear_transform()\r
The post processing engine performs a linear transform on analog input samples\r
- obtained from the sample sequencing engine. The main purpose of this linear \r
+ obtained from the sample sequencing engine. The main purpose of this linear\r
transform is to apply part specific factory calibration to the analog samples\r
in order to achieve high accuracy. A second user specified linear transform\r
can also be optionally applied to the analog samples. This second linear\r
factor of the user defined linear transform applied by the post processing\r
engine to analog samples. The user defined linear transform m factor default\r
value is selected in the ACE configurator tool.\r
- \r
+\r
@param channel_handle\r
The channel_handle parameter identifies one of the analog input channels\r
monitored by the ACE. The available channel handle values can be found in\r
to ACE_get_channel_handle() when the name of the channel is known, or by\r
iterating though all analog input channel using the ACE_get_first_channel()\r
and ACE_get_next_channel().\r
- \r
+\r
@return\r
The ACE_get_default_m_factor() function returns the user transform m factor\r
default value. It is a signed 16-bit number representing a factor in the\r
offset of the user defined linear transform applied by the post processing\r
engine to analog samples. The user defined linear transform c offset default\r
value is selected in the ACE configurator tool.\r
- \r
+\r
@param channel_handle\r
The channel_handle parameter identifies one of the analog input channels\r
monitored by the ACE. The available channel handle values can be found in\r
to ACE_get_channel_handle() when the name of the channel is known, or by\r
iterating though all analog input channel using the ACE_get_first_channel()\r
and ACE_get_next_channel().\r
- \r
+\r
@return\r
The ACE_get_default_c_offset() function returns the user linear transform\92s\r
c offset default value. It is a signed 16-bit number representing a factor\r
linear transform applied to analog input samples by the post processing\r
engine. The linear transform is of the form y = m.x + b where the m factor\r
and c offset are in the range -2 to +1.99993896484375.\r
- \r
+\r
@param channel_handle\r
The channel_handle parameter identifies one of the analog input channels\r
monitored by the ACE. The available channel handle values can be found in\r
to ACE_get_channel_handle() when the name of the channel is known, or by\r
iterating though all analog input channel using the ACE_get_first_channel()\r
and ACE_get_next_channel().\r
- \r
+\r
@param m2\r
The m2 parameter specifies the user defined transform\92s m factor. It is a\r
signed 16-bit number representing a factor in the range -2 to\r
+1.99993896484375. The value of the m2 factor is obtained by multiplying the\r
parameter\92s absolute value by 2^-14. For example, a value of 0x7000\r
represents a 1.75 factor and a value of 0xE000 represents a -0.5 factor.\r
- \r
+\r
@param c2\r
The c2 parameter specifies the user defined transform\92s c offset. It is a\r
signed 16-bit number representing an offset in the range -2 to\r
+1.99993896484375. The value of the c2 offset is obtained by multiplying the\r
parameter\92s absolute value by 2^-14. For example, a value of 0x1000 represents\r
a 0.25 offset and a value of 0xB000 represents a -1.25 offset.\r
- \r
+\r
@code\r
void reset_to_default(ace_channel_handle_t channel_handle)\r
{\r
int16_t m;\r
int16_t c;\r
- \r
+\r
m = ACE_get_default_m_factor(channel_handle);\r
c = ACE_get_default_c_offset(channel_handle);\r
ACE_set_linear_transform(channel_handle, m, c);\r
);\r
\r
/** @} */\r
- \r
+\r
#ifdef __cplusplus\r
}\r
#endif\r
/* Allocating this many buffers will always ensure there is one free as, even\r
though TX_RING_SIZE is set to two, the two Tx descriptors will only ever point\r
to the same buffer. */\r
-#define macNUM_BUFFERS RX_RING_SIZE + TX_RING_SIZE + 1\r
+#define macNUM_BUFFERS RX_RING_SIZE + TX_RING_SIZE\r
#define macBUFFER_SIZE 1488\r
\r
/***************************************************************/\r
configASSERT( usLength <= MSS_MAX_PACKET_SIZE );\r
}\r
\r
- /* Check if second descriptor is free, if it is then the first must\r
- also be free. */\r
- if( ( ( (g_mss_mac.tx_descriptors[ 0 ].descriptor_0) & TDES0_OWN) == TDES0_OWN ) || ( ( (g_mss_mac.tx_descriptors[ 1 ].descriptor_0) & TDES0_OWN) == TDES0_OWN ) )\r
+ taskENTER_CRITICAL();\r
{\r
- error = MAC_BUFFER_IS_FULL;\r
+ /* Check both Tx descriptors are free, meaning the double send has completed. */\r
+ if( ( ( (g_mss_mac.tx_descriptors[ 0 ].descriptor_0) & TDES0_OWN) == TDES0_OWN ) || ( ( (g_mss_mac.tx_descriptors[ 1 ].descriptor_0) & TDES0_OWN) == TDES0_OWN ) )\r
+ {\r
+ error = MAC_BUFFER_IS_FULL;\r
+ }\r
}\r
+ taskEXIT_CRITICAL();\r
\r
+ configASSERT( ( g_mss_mac.tx_desc_index == 0 ) );\r
\r
if( error == MAC_OK )\r
{\r
+ /* Ensure nothing is going to get sent until both descriptors are ready.\r
+ This is done to prevent a Tx end occurring prior to the second descriptor\r
+ being ready. */\r
+ MAC_BITBAND->CSR6_ST = 0u;\r
+\r
/* Assumed TX_RING_SIZE == 2. A #error directive checks this is the\r
case. */\r
- for( ulDescriptor = 0; ulDescriptor < TX_RING_SIZE; ulDescriptor++ )\r
+ taskENTER_CRITICAL();\r
{\r
- g_mss_mac.tx_descriptors[ g_mss_mac.tx_desc_index ].descriptor_1 = 0u;\r
-\r
- if( (g_mss_mac.flags & FLAG_CRC_DISABLE) != 0u ) {\r
- g_mss_mac.tx_descriptors[ g_mss_mac.tx_desc_index ].descriptor_1 |= TDES1_AC;\r
- }\r
-\r
- /* Every buffer can hold a full frame so they are always first and last\r
- descriptor */\r
- g_mss_mac.tx_descriptors[ g_mss_mac.tx_desc_index ].descriptor_1 |= TDES1_LS | TDES1_FS | TDES1_IC;\r
-\r
- /* set data size */\r
- g_mss_mac.tx_descriptors[ g_mss_mac.tx_desc_index ].descriptor_1 |= usLength;\r
-\r
- /* reset end of ring */\r
- g_mss_mac.tx_descriptors[TX_RING_SIZE-1].descriptor_1 |= TDES1_TER;\r
-\r
- if( usLength > MSS_TX_BUFF_SIZE ) /* FLAG_EXCEED_LIMIT */\r
+ for( ulDescriptor = 0; ulDescriptor < TX_RING_SIZE; ulDescriptor++ )\r
{\r
- usLength = (uint16_t)MSS_TX_BUFF_SIZE;\r
- }\r
-\r
- /* The data buffer is assigned to the Tx descriptor. */\r
- g_mss_mac.tx_descriptors[ g_mss_mac.tx_desc_index ].buffer_1 = ( unsigned long ) uip_buf;\r
-\r
- /* update counters */\r
- desc = g_mss_mac.tx_descriptors[ g_mss_mac.tx_desc_index ].descriptor_0;\r
- if( (desc & TDES0_LO) != 0u ) {\r
- g_mss_mac.statistics.tx_loss_of_carrier++;\r
- }\r
- if( (desc & TDES0_NC) != 0u ) {\r
- g_mss_mac.statistics.tx_no_carrier++;\r
- }\r
- if( (desc & TDES0_LC) != 0u ) {\r
- g_mss_mac.statistics.tx_late_collision++;\r
- }\r
- if( (desc & TDES0_EC) != 0u ) {\r
- g_mss_mac.statistics.tx_excessive_collision++;\r
- }\r
- if( (desc & TDES0_UF) != 0u ) {\r
- g_mss_mac.statistics.tx_underflow_error++;\r
- }\r
- g_mss_mac.statistics.tx_collision_count +=\r
- (desc >> TDES0_CC_OFFSET) & TDES0_CC_MASK;\r
-\r
- /* Give ownership of descriptor to the MAC */\r
- g_mss_mac.tx_descriptors[ g_mss_mac.tx_desc_index ].descriptor_0 = RDES0_OWN;\r
- \r
- g_mss_mac.tx_desc_index = (g_mss_mac.tx_desc_index + 1u) % (uint32_t)TX_RING_SIZE;\r
- \r
- MAC_start_transmission();\r
- MAC->CSR1 = 1u;\r
- } \r
+ g_mss_mac.tx_descriptors[ g_mss_mac.tx_desc_index ].descriptor_1 = 0u;\r
+ \r
+ if( (g_mss_mac.flags & FLAG_CRC_DISABLE) != 0u ) {\r
+ g_mss_mac.tx_descriptors[ g_mss_mac.tx_desc_index ].descriptor_1 |= TDES1_AC;\r
+ }\r
+ \r
+ /* Every buffer can hold a full frame so they are always first and last\r
+ descriptor */\r
+ g_mss_mac.tx_descriptors[ g_mss_mac.tx_desc_index ].descriptor_1 |= TDES1_LS | TDES1_FS;\r
+ \r
+ /* set data size */\r
+ g_mss_mac.tx_descriptors[ g_mss_mac.tx_desc_index ].descriptor_1 |= usLength;\r
+ \r
+ /* reset end of ring */\r
+ g_mss_mac.tx_descriptors[TX_RING_SIZE-1].descriptor_1 |= TDES1_TER;\r
+ \r
+ if( usLength > MSS_TX_BUFF_SIZE ) /* FLAG_EXCEED_LIMIT */\r
+ {\r
+ usLength = (uint16_t)MSS_TX_BUFF_SIZE;\r
+ }\r
+ \r
+ /* The data buffer is assigned to the Tx descriptor. */\r
+ g_mss_mac.tx_descriptors[ g_mss_mac.tx_desc_index ].buffer_1 = ( unsigned long ) uip_buf;\r
+ \r
+ /* update counters */\r
+ desc = g_mss_mac.tx_descriptors[ g_mss_mac.tx_desc_index ].descriptor_0;\r
+ if( (desc & TDES0_LO) != 0u ) {\r
+ g_mss_mac.statistics.tx_loss_of_carrier++;\r
+ }\r
+ if( (desc & TDES0_NC) != 0u ) {\r
+ g_mss_mac.statistics.tx_no_carrier++;\r
+ }\r
+ if( (desc & TDES0_LC) != 0u ) {\r
+ g_mss_mac.statistics.tx_late_collision++;\r
+ }\r
+ if( (desc & TDES0_EC) != 0u ) {\r
+ g_mss_mac.statistics.tx_excessive_collision++;\r
+ }\r
+ if( (desc & TDES0_UF) != 0u ) {\r
+ g_mss_mac.statistics.tx_underflow_error++;\r
+ }\r
+ g_mss_mac.statistics.tx_collision_count +=\r
+ (desc >> TDES0_CC_OFFSET) & TDES0_CC_MASK;\r
+ \r
+ /* Give ownership of descriptor to the MAC */\r
+ g_mss_mac.tx_descriptors[ g_mss_mac.tx_desc_index ].descriptor_0 = TDES0_OWN;\r
+ \r
+ g_mss_mac.tx_desc_index = (g_mss_mac.tx_desc_index + 1u) % (uint32_t)TX_RING_SIZE;\r
+ } \r
+ }\r
+ taskEXIT_CRITICAL();\r
}\r
\r
if (error == MAC_OK)\r
{\r
error = (int32_t)usLength;\r
\r
+ /* Start sending now both descriptors are set up. This is done to\r
+ prevent a Tx end occurring prior to the second descriptor being\r
+ ready. */\r
+ MAC_BITBAND->CSR6_ST = 1u;\r
+ MAC->CSR1 = 1u;\r
+ \r
/* The buffer pointed to by uip_buf is now assigned to a Tx descriptor.\r
Find anothere free buffer for uip_buf. */\r
uip_buf = MAC_obtain_buffer();\r
* will keep trying to read till time_out expires or data is read, if MSS_MAC_BLOCKING\r
* value is given as time_out, function will wait for the reception to complete.\r
*\r
- * @param instance Pointer to a MAC_instance_t structure\r
- * @param pacData The pointer to the packet data.\r
+ * @param pacData The pointer to the packet data.\r
* @param time_out Time out value in milli seconds for receiving.\r
* if value is #MSS_MAC_BLOCKING, there will be no time out.\r
* if value is #MSS_MAC_NONBLOCKING, function will return immediately\r
(desc & (CSR8_MFO_MASK|CSR8_MFC_MASK));\r
\r
/* Give ownership of descriptor to the MAC */\r
- g_mss_mac.rx_descriptors[ g_mss_mac.rx_desc_index ].descriptor_0 =\r
- RDES0_OWN;\r
+ g_mss_mac.rx_descriptors[ g_mss_mac.rx_desc_index ].descriptor_0 = RDES0_OWN;\r
g_mss_mac.rx_desc_index = (g_mss_mac.rx_desc_index + 1u) % RX_RING_SIZE;\r
\r
/* Start receive */\r
*/\r
void MSS_MAC_FreeTxBuffers( void )\r
{\r
- if( ( ( (g_mss_mac.tx_descriptors[ 0 ].descriptor_0) & TDES0_OWN) == 0 ) && ( ( (g_mss_mac.tx_descriptors[ 1 ].descriptor_0) & TDES0_OWN) == 0 ) )\r
+ /* Check the buffers have not already been freed in the first of the\r
+ two Tx interrupts - which could potentially happen if the second Tx completed\r
+ during the interrupt for the first Tx. */\r
+ if( g_mss_mac.tx_descriptors[ 0 ].buffer_1 != NULL )\r
{\r
- MAC_release_buffer( ( unsigned char * ) g_mss_mac.tx_descriptors[ 0 ].buffer_1 );\r
- MAC_release_buffer( ( unsigned char * ) g_mss_mac.tx_descriptors[ 1 ].buffer_1 );\r
+ if( ( ( (g_mss_mac.tx_descriptors[ 0 ].descriptor_0) & TDES0_OWN) == 0 ) && ( ( (g_mss_mac.tx_descriptors[ 1 ].descriptor_0) & TDES0_OWN) == 0 ) )\r
+ {\r
+ configASSERT( g_mss_mac.tx_descriptors[ 0 ].buffer_1 == g_mss_mac.tx_descriptors[ 1 ].buffer_1 );\r
+ MAC_release_buffer( ( unsigned char * ) g_mss_mac.tx_descriptors[ 0 ].buffer_1 );\r
+ \r
+ /* Just to mark the fact that the buffer has already been released. */\r
+ g_mss_mac.tx_descriptors[ 0 ].buffer_1 == NULL;\r
+ }\r
}\r
}\r
\r
*/\r
unsigned char *MAC_obtain_buffer( void )\r
{\r
-long lIndex;\r
+long lIndex, lAttempt = 0, lDescriptor, lBufferIsInUse;\r
unsigned char *pcReturn = NULL;\r
+unsigned char *pcBufferAddress;\r
\r
/* Find and return the address of a buffer that is not being used. Mark\r
the buffer as now in use. */\r
- for( lIndex = 0; lIndex < macNUM_BUFFERS; lIndex++ )\r
+ while( ( lAttempt <= 1 ) && ( pcReturn == NULL ) )\r
{\r
- if( ucMACBufferInUse[ lIndex ] == pdFALSE )\r
+ for( lIndex = 0; lIndex < macNUM_BUFFERS; lIndex++ )\r
{\r
- pcReturn = &( xMACBuffers.ucBuffer[ lIndex ][ 0 ] );\r
- ucMACBufferInUse[ lIndex ] = pdTRUE;\r
- break;\r
+ if( ucMACBufferInUse[ lIndex ] == pdFALSE )\r
+ {\r
+ pcReturn = &( xMACBuffers.ucBuffer[ lIndex ][ 0 ] );\r
+ ucMACBufferInUse[ lIndex ] = pdTRUE;\r
+ break;\r
+ }\r
+ }\r
+ \r
+ if( pcReturn == NULL )\r
+ {\r
+ /* Did not find a buffer. That should not really happen, but could if\r
+ an interrupt was missed. See if any buffers are marked as in use, but\r
+ are not actually in use. */\r
+ for( lIndex = 0; lIndex < macNUM_BUFFERS; lIndex++ )\r
+ {\r
+ pcBufferAddress = &( xMACBuffers.ucBuffer[ lIndex ][ 0 ] );\r
+ lBufferIsInUse = pdFALSE;\r
+ \r
+ /* Is the buffer used by an Rx descriptor? */\r
+ for( lDescriptor = 0; lDescriptor < RX_RING_SIZE; lDescriptor++ )\r
+ {\r
+ if( g_mss_mac.rx_descriptors[ lDescriptor ].buffer_1 == ( uint32_t ) pcBufferAddress )\r
+ {\r
+ /* The buffer is in use by an Rx descriptor. */\r
+ lBufferIsInUse = pdTRUE;\r
+ break;\r
+ }\r
+ }\r
+ \r
+ if( lBufferIsInUse != pdTRUE )\r
+ {\r
+ /* Is the buffer used by an Tx descriptor? */\r
+ for( lDescriptor = 0; lDescriptor < TX_RING_SIZE; lDescriptor++ )\r
+ {\r
+ if( g_mss_mac.tx_descriptors[ lDescriptor ].buffer_1 == ( uint32_t ) pcBufferAddress )\r
+ {\r
+ /* The buffer is in use by an Tx descriptor. */\r
+ lBufferIsInUse = pdTRUE;\r
+ break;\r
+ }\r
+ } \r
+ }\r
+ \r
+ /* If the buffer was not found to be in use by either a Tx or an\r
+ Rx descriptor, but the buffer is marked as in use, then mark the\r
+ buffer to be in it's correct state of "not in use". */\r
+ if( ( lBufferIsInUse == pdFALSE ) && ( ucMACBufferInUse[ lIndex ] == pdTRUE ) )\r
+ {\r
+ ucMACBufferInUse[ lIndex ] = pdFALSE;\r
+ }\r
+ }\r
}\r
+ \r
+ /* If any buffer states were changed it might be that a buffer can now\r
+ be obtained. Try again, but only one more time. */\r
+ lAttempt++;\r
}\r
\r
configASSERT( pcReturn );\r
/***************************************************************************//**\r
* Descriptor structure\r
*/\r
+#include "pack_struct_start.h"\r
typedef struct {\r
volatile uint32_t descriptor_0;\r
volatile uint32_t descriptor_1;\r
volatile uint32_t buffer_1;\r
volatile uint32_t buffer_2;\r
-} MAC_descriptor_t;\r
+} MAC_descriptor_t\r
+#include "pack_struct_end.h"\r
\r
\r
/***************************************************************************//**\r
\r
uint8_t phy_address; /**< MII address of the connected PHY*/\r
\r
+ #include "pack_struct_start.h"\r
struct {\r
uint32_t rx_interrupts; /**< Number of receive interrupts occurred.*/\r
uint32_t rx_filtering_fail; /**< Number of received frames which did not pass\r
uint32_t tx_collision_count; /**< Number of collisions occurred.*/\r
uint32_t tx_underflow_error; /**< Number of occurrences of; the FIFO was empty during\r
the frame transmission.*/\r
- } statistics;\r
+ } statistics\r
+ #include "pack_struct_end.h"\r
} MAC_instance_t\r
#include "net/pack_struct_end.h"\r
\r
/*******************************************************************************\r
* (c) Copyright 2007 Actel Corporation. All rights reserved.\r
- * \r
+ *\r
* Actel:Firmware:MSS_Ethernet_MAC_Driver:2.0.103 configuration.\r
*\r
*/\r
\r
#define BUS_ARBITRATION_SCHEME 0\r
#define PROGRAMMABLE_BURST_LENGTH 0\r
-#define RX_RING_SIZE 4\r
+#define RX_RING_SIZE 5\r
#define SETUP_FRAME_TIME_OUT 10000\r
#define STATE_CHANGE_TIME_OUT 10000\r
#define TX_RING_SIZE 2\r
+++ /dev/null
-/*******************************************************************************\r
- * (c) Copyright 2008 Actel Corporation. All rights reserved.\r
- * \r
- * SmartFusion microcontroller subsystem Peripheral DMA bare metal software\r
- * driver implementation.\r
- *\r
- * SVN $Revision: 2110 $\r
- * SVN $Date: 2010-02-05 15:24:19 +0000 (Fri, 05 Feb 2010) $\r
- */\r
-#include "mss_pdma.h"\r
-#include "../../CMSIS/mss_assert.h"\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif \r
-\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void DMA_IRQHandler( void );\r
-#else\r
-void DMA_IRQHandler( void );\r
-#endif\r
-\r
-/***************************************************************************//**\r
- Offset of the posted writes WRITE_ADJ bits in a PDMA channel's configuration\r
- register.\r
- */\r
-#define CHANNEL_N_POSTED_WRITE_ADJUST_SHIFT 14\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- * Look-up table use to derice a channel's control register value from the\r
- * requested source/destination. This table is incexed on the pdma_src_dest_t\r
- * enumeration.\r
- */\r
-#define CHANNEL_N_CTRL_PDMA_MASK (uint32_t)0x00000001\r
-#define CHANNEL_N_PERIPH_SELECT_SHIFT (uint32_t)23\r
-#define CHANNEL_N_DIRECTION_MASK (uint32_t)0x00000002\r
-\r
-const uint32_t src_dest_to_ctrl_reg_lut[] =\r
-{\r
- CHANNEL_N_CTRL_PDMA_MASK, /* PDMA_FROM_UART_0 */\r
- CHANNEL_N_CTRL_PDMA_MASK | ( (uint32_t)1 << CHANNEL_N_PERIPH_SELECT_SHIFT) | CHANNEL_N_DIRECTION_MASK, /* PDMA_TO_UART_0 */\r
- CHANNEL_N_CTRL_PDMA_MASK | ( (uint32_t)2 << CHANNEL_N_PERIPH_SELECT_SHIFT), /* PDMA_FROM_UART_1 */\r
- CHANNEL_N_CTRL_PDMA_MASK | ( (uint32_t)3 << CHANNEL_N_PERIPH_SELECT_SHIFT) | CHANNEL_N_DIRECTION_MASK, /* PDMA_TO_UART_1 */\r
- CHANNEL_N_CTRL_PDMA_MASK | ( (uint32_t)4 << CHANNEL_N_PERIPH_SELECT_SHIFT), /* PDMA_FROM_SPI_0 */\r
- CHANNEL_N_CTRL_PDMA_MASK | ( (uint32_t)5 << CHANNEL_N_PERIPH_SELECT_SHIFT) | CHANNEL_N_DIRECTION_MASK, /* PDMA_TO_SPI_0 */\r
- CHANNEL_N_CTRL_PDMA_MASK | ( (uint32_t)6 << CHANNEL_N_PERIPH_SELECT_SHIFT), /* PDMA_FROM_SPI_1 */\r
- CHANNEL_N_CTRL_PDMA_MASK | ( (uint32_t)7 << CHANNEL_N_PERIPH_SELECT_SHIFT) | CHANNEL_N_DIRECTION_MASK, /* PDMA_TO_SPI_1 */\r
- CHANNEL_N_CTRL_PDMA_MASK | ( (uint32_t)8 << CHANNEL_N_PERIPH_SELECT_SHIFT), /* PDMA_FROM_FPGA_1 */\r
- CHANNEL_N_CTRL_PDMA_MASK | ( (uint32_t)8 << CHANNEL_N_PERIPH_SELECT_SHIFT) | CHANNEL_N_DIRECTION_MASK, /* PDMA_TO_FPGA_1 */\r
- CHANNEL_N_CTRL_PDMA_MASK | ( (uint32_t)9 << CHANNEL_N_PERIPH_SELECT_SHIFT), /* PDMA_FROM_FPGA_0 */\r
- CHANNEL_N_CTRL_PDMA_MASK | ( (uint32_t)9 << CHANNEL_N_PERIPH_SELECT_SHIFT) | CHANNEL_N_DIRECTION_MASK, /* PDMA_TO_FPGA_0 */\r
- CHANNEL_N_CTRL_PDMA_MASK | ( (uint32_t)10 << CHANNEL_N_PERIPH_SELECT_SHIFT) | CHANNEL_N_DIRECTION_MASK, /* PDMA_TO_ACE */\r
- CHANNEL_N_CTRL_PDMA_MASK | ( (uint32_t)11 << CHANNEL_N_PERIPH_SELECT_SHIFT) /* PDMA_FROM_ACE */\r
-};\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- *\r
- */\r
-#define PDMA_MASTER_ENABLE (uint32_t)0x04\r
-#define PDMA_SOFT_RESET (uint32_t)0x20\r
-\r
-/*-------------------------------------------------------------------------*//**\r
- *\r
- */\r
-#define NB_OF_PDMA_CHANNELS 8\r
-\r
-#define NEXT_CHANNEL_A 0U\r
-#define NEXT_CHANNEL_B 1U\r
-\r
-#define CHANNEL_STOPPED 0U\r
-#define CHANNEL_STARTED 1U\r
-\r
-static uint8_t g_pdma_next_channel[NB_OF_PDMA_CHANNELS];\r
-static uint8_t g_pdma_started_a[NB_OF_PDMA_CHANNELS];\r
-static uint8_t g_pdma_started_b[NB_OF_PDMA_CHANNELS];\r
-static pdma_channel_isr_t g_pdma_isr_table[NB_OF_PDMA_CHANNELS];\r
-static const uint16_t g_pdma_status_mask[NB_OF_PDMA_CHANNELS] =\r
-{\r
- (uint16_t)0x0003, /* PDMA_CHANNEL_0 */\r
- (uint16_t)0x000C, /* PDMA_CHANNEL_1 */\r
- (uint16_t)0x0030, /* PDMA_CHANNEL_2 */\r
- (uint16_t)0x00C0, /* PDMA_CHANNEL_3 */\r
- (uint16_t)0x0300, /* PDMA_CHANNEL_4 */\r
- (uint16_t)0x0C00, /* PDMA_CHANNEL_5 */\r
- (uint16_t)0x3000, /* PDMA_CHANNEL_6 */\r
- (uint16_t)0xC000, /* PDMA_CHANNEL_7 */\r
-};\r
-\r
-\r
-\r
-/***************************************************************************//**\r
- * See mss_pdma.h for description of this function.\r
- */\r
-void PDMA_init( void )\r
-{\r
- int32_t i;\r
- \r
- /* Enable PDMA master access to comms matrix. */\r
- SYSREG->AHB_MATRIX_CR |= PDMA_MASTER_ENABLE;\r
- \r
- /* Reset PDMA block. */\r
- SYSREG->SOFT_RST_CR |= PDMA_SOFT_RESET;\r
- \r
- /* Clear any previously pended MSS PDMA interrupt */\r
- NVIC_ClearPendingIRQ( DMA_IRQn );\r
- \r
- /* Take PDMA controller out of reset*/\r
- SYSREG->SOFT_RST_CR &= ~PDMA_SOFT_RESET;\r
- \r
- /* Initialize channels state information. */\r
- for ( i = 0; i < NB_OF_PDMA_CHANNELS; ++i )\r
- {\r
- g_pdma_next_channel[i] = NEXT_CHANNEL_A;\r
- g_pdma_started_a[i] = CHANNEL_STOPPED;\r
- g_pdma_started_b[i] = CHANNEL_STOPPED;\r
- g_pdma_isr_table[i] = 0;\r
- }\r
-}\r
-\r
-/***************************************************************************//**\r
- * See mss_pdma.h for description of this function.\r
- */\r
-#define CHANNEL_RESET_MASK (uint32_t)0x00000020\r
-\r
-void PDMA_configure\r
-(\r
- pdma_channel_id_t channel_id,\r
- pdma_src_dest_t src_dest,\r
- uint32_t channel_cfg,\r
- uint8_t write_adjust\r
-)\r
-{\r
- /* Reset the channel. */\r
- PDMA->CHANNEL[channel_id].CRTL |= CHANNEL_RESET_MASK;\r
- PDMA->CHANNEL[channel_id].CRTL &= ~CHANNEL_RESET_MASK;\r
-\r
- /* Configure PDMA channel's data source and destination. */\r
- if ( src_dest != PDMA_MEM_TO_MEM )\r
- {\r
- PDMA->CHANNEL[channel_id].CRTL |= src_dest_to_ctrl_reg_lut[src_dest];\r
- }\r
- \r
- /* Configure PDMA channel trnasfer size, priority, source and destination address increment. */\r
- PDMA->CHANNEL[channel_id].CRTL |= channel_cfg;\r
-\r
- /* Posted write adjust. */\r
- PDMA->CHANNEL[channel_id].CRTL |= ((uint32_t)write_adjust << CHANNEL_N_POSTED_WRITE_ADJUST_SHIFT);\r
-}\r
-\r
-/***************************************************************************//**\r
- * See mss_pdma.h for description of this function.\r
- */\r
-#define PAUSE_MASK (uint32_t)0x00000010\r
-\r
-#define BUFFER_B_SELECT_MASK (uint32_t)0x00000004\r
-\r
-#define CLEAR_PORT_A_DONE_MASK (uint32_t)0x00000080\r
-#define CLEAR_PORT_B_DONE_MASK (uint32_t)0x00000100\r
-\r
-#define PORT_A_COMPLETE_MASK (uint32_t)0x00000001\r
-#define PORT_B_COMPLETE_MASK (uint32_t)0x00000002\r
-\r
-void PDMA_start\r
-(\r
- pdma_channel_id_t channel_id,\r
- uint32_t src_addr,\r
- uint32_t dest_addr,\r
- uint16_t transfer_count\r
-)\r
-{\r
- /* Pause transfer. */\r
- PDMA->CHANNEL[channel_id].CRTL |= PAUSE_MASK;\r
- \r
- /* Clear complete transfers. */\r
- if ( PDMA->CHANNEL[channel_id].STATUS & PORT_A_COMPLETE_MASK )\r
- {\r
- PDMA->CHANNEL[channel_id].CRTL |= CLEAR_PORT_A_DONE_MASK;\r
- g_pdma_started_a[channel_id] = CHANNEL_STOPPED;\r
- }\r
- if ( PDMA->CHANNEL[channel_id].STATUS & PORT_B_COMPLETE_MASK )\r
- {\r
- PDMA->CHANNEL[channel_id].CRTL |= CLEAR_PORT_B_DONE_MASK;\r
- g_pdma_started_b[channel_id] = CHANNEL_STOPPED;\r
- }\r
- \r
- /* Load source, destination and transfer count. */\r
- if ( PDMA->CHANNEL[channel_id].STATUS & BUFFER_B_SELECT_MASK )\r
- {\r
- g_pdma_next_channel[channel_id] = NEXT_CHANNEL_A;\r
- g_pdma_started_b[channel_id] = CHANNEL_STARTED;\r
- \r
- PDMA->CHANNEL[channel_id].BUFFER_B_SRC_ADDR = src_addr;\r
- PDMA->CHANNEL[channel_id].BUFFER_B_DEST_ADDR = dest_addr;\r
- PDMA->CHANNEL[channel_id].BUFFER_B_TRANSFER_COUNT = transfer_count;\r
- }\r
- else\r
- {\r
- g_pdma_next_channel[channel_id] = NEXT_CHANNEL_B;\r
- g_pdma_started_a[channel_id] = CHANNEL_STARTED;\r
- \r
- PDMA->CHANNEL[channel_id].BUFFER_A_SRC_ADDR = src_addr;\r
- PDMA->CHANNEL[channel_id].BUFFER_A_DEST_ADDR = dest_addr;\r
- PDMA->CHANNEL[channel_id].BUFFER_A_TRANSFER_COUNT = transfer_count;\r
- }\r
- \r
- /* Start transfer */\r
- PDMA->CHANNEL[channel_id].CRTL &= ~PAUSE_MASK;\r
-}\r
-\r
-/***************************************************************************//**\r
- * See mss_pdma.h for description of this function.\r
- */\r
-void PDMA_load_next_buffer\r
-(\r
- pdma_channel_id_t channel_id,\r
- uint32_t src_addr,\r
- uint32_t dest_addr,\r
- uint16_t transfer_count\r
-)\r
-{\r
- if ( NEXT_CHANNEL_A == g_pdma_next_channel[channel_id] )\r
- {\r
- /* Wait for channel A current transfer completion. */\r
- if ( CHANNEL_STARTED == g_pdma_started_a[channel_id] )\r
- {\r
- uint32_t completed;\r
- uint32_t channel_mask;\r
- channel_mask = (uint32_t)1 << ((uint32_t)channel_id * 2U);\r
- do {\r
- completed = PDMA->BUFFER_STATUS & channel_mask;\r
- } while( !completed );\r
- PDMA->CHANNEL[channel_id].CRTL |= CLEAR_PORT_A_DONE_MASK;\r
- }\r
- /* Load source, destination and transfer count. */\r
- PDMA->CHANNEL[channel_id].BUFFER_A_SRC_ADDR = src_addr;\r
- PDMA->CHANNEL[channel_id].BUFFER_A_DEST_ADDR = dest_addr;\r
- PDMA->CHANNEL[channel_id].BUFFER_A_TRANSFER_COUNT = transfer_count;\r
- \r
- /* Update channel state information. */\r
- g_pdma_next_channel[channel_id] = NEXT_CHANNEL_B;\r
- g_pdma_started_a[channel_id] = CHANNEL_STARTED;\r
- }\r
- else\r
- {\r
- /* Wait for channel B current transfer completion. */\r
- if ( CHANNEL_STARTED == g_pdma_started_b[channel_id] )\r
- {\r
- uint32_t completed;\r
- uint32_t channel_mask;\r
- channel_mask = (uint32_t)1 << (((uint32_t)channel_id * 2U) + 1U);\r
- do {\r
- completed = PDMA->BUFFER_STATUS & channel_mask;\r
- } while( !completed );\r
- PDMA->CHANNEL[channel_id].CRTL |= CLEAR_PORT_B_DONE_MASK;\r
- } \r
- /* Load source, destination and transfer count. */\r
- PDMA->CHANNEL[channel_id].BUFFER_B_SRC_ADDR = src_addr;\r
- PDMA->CHANNEL[channel_id].BUFFER_B_DEST_ADDR = dest_addr;\r
- PDMA->CHANNEL[channel_id].BUFFER_B_TRANSFER_COUNT = transfer_count;\r
- \r
- /* Update channel state information. */\r
- g_pdma_next_channel[channel_id] = NEXT_CHANNEL_A;\r
- g_pdma_started_b[channel_id] = CHANNEL_STARTED;\r
- }\r
-}\r
-\r
-/***************************************************************************//**\r
- * See mss_pdma.h for description of this function.\r
- */\r
-uint32_t PDMA_status\r
-(\r
- pdma_channel_id_t channel_id\r
-)\r
-{\r
- uint32_t status;\r
- \r
- status = PDMA->CHANNEL[channel_id].STATUS & (PORT_A_COMPLETE_MASK | PORT_B_COMPLETE_MASK);\r
- \r
- return status;\r
-}\r
-\r
-/***************************************************************************//**\r
- *\r
- */\r
-#define CHANNEL_0_STATUS_BITS_MASK (uint16_t)0x0003\r
-#define CHANNEL_1_STATUS_BITS_MASK (uint16_t)0x000C\r
-#define CHANNEL_2_STATUS_BITS_MASK (uint16_t)0x0030\r
-#define CHANNEL_3_STATUS_BITS_MASK (uint16_t)0x00C0\r
-#define CHANNEL_4_STATUS_BITS_MASK (uint16_t)0x0300\r
-#define CHANNEL_5_STATUS_BITS_MASK (uint16_t)0x0C00\r
-#define CHANNEL_6_STATUS_BITS_MASK (uint16_t)0x3000\r
-#define CHANNEL_7_STATUS_BITS_MASK (uint16_t)0xC000\r
-\r
-static pdma_channel_id_t get_channel_id_from_status\r
-(\r
- uint16_t status\r
-)\r
-{\r
- pdma_channel_id_t channel_id = PDMA_CHANNEL_0;\r
- \r
- if ( status & CHANNEL_0_STATUS_BITS_MASK )\r
- {\r
- channel_id = PDMA_CHANNEL_0;\r
- }\r
- else if ( status & CHANNEL_1_STATUS_BITS_MASK )\r
- {\r
- channel_id = PDMA_CHANNEL_1;\r
- }\r
- else if ( status & CHANNEL_2_STATUS_BITS_MASK )\r
- {\r
- channel_id = PDMA_CHANNEL_2;\r
- }\r
- else if ( status & CHANNEL_3_STATUS_BITS_MASK )\r
- {\r
- channel_id = PDMA_CHANNEL_3;\r
- }\r
- else if ( status & CHANNEL_4_STATUS_BITS_MASK )\r
- {\r
- channel_id = PDMA_CHANNEL_4;\r
- }\r
- else if ( status & CHANNEL_5_STATUS_BITS_MASK )\r
- {\r
- channel_id = PDMA_CHANNEL_5;\r
- }\r
- else if ( status & CHANNEL_6_STATUS_BITS_MASK )\r
- {\r
- channel_id = PDMA_CHANNEL_6;\r
- }\r
- else if ( status & CHANNEL_7_STATUS_BITS_MASK )\r
- {\r
- channel_id = PDMA_CHANNEL_7;\r
- }\r
- else\r
- {\r
- ASSERT(0);\r
- }\r
- return channel_id;\r
-}\r
-\r
-/***************************************************************************//**\r
- *\r
- */\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void DMA_IRQHandler( void )\r
-#else\r
-void DMA_IRQHandler( void )\r
-#endif\r
-{\r
- uint16_t status;\r
- pdma_channel_id_t channel_id;\r
- \r
- status = (uint16_t)PDMA->BUFFER_STATUS;\r
- \r
- do {\r
- channel_id = get_channel_id_from_status( status );\r
- status &= (uint16_t)~g_pdma_status_mask[channel_id];\r
- if ( 0 != g_pdma_isr_table[channel_id])\r
- {\r
- g_pdma_isr_table[channel_id]();\r
- }\r
- } while ( 0U != status );\r
- \r
- NVIC_ClearPendingIRQ( DMA_IRQn );\r
-}\r
-\r
-/***************************************************************************//**\r
- * See mss_pdma.h for description of this function.\r
- */\r
-void PDMA_set_irq_handler\r
-(\r
- pdma_channel_id_t channel_id,\r
- pdma_channel_isr_t handler\r
-)\r
-{\r
- /* Save address of handler function in PDMA driver ISR lookup table. */\r
- g_pdma_isr_table[channel_id] = handler;\r
- \r
- /* Enable PDMA channel's interrupt. */\r
- PDMA->CHANNEL[channel_id].CRTL |= PDMA_IRQ_ENABLE_MASK;\r
- \r
- /* Enable PDMA interrupt in Cortex-M3 NVIC. */\r
- NVIC_EnableIRQ( DMA_IRQn );\r
-}\r
-\r
-/***************************************************************************//**\r
- * See mss_pdma.h for description of this function.\r
- */\r
-void PDMA_enable_irq( pdma_channel_id_t channel_id )\r
-{\r
- PDMA->CHANNEL[channel_id].CRTL |= PDMA_IRQ_ENABLE_MASK;\r
- NVIC_EnableIRQ( DMA_IRQn );\r
-}\r
-\r
-/***************************************************************************//**\r
- * See mss_pdma.h for description of this function.\r
- */\r
-void PDMA_clear_irq\r
-(\r
- pdma_channel_id_t channel_id\r
-)\r
-{\r
- /* Clear interrupt in PDMA controller. */\r
- PDMA->CHANNEL[channel_id].CRTL |= CLEAR_PORT_A_DONE_MASK;\r
- PDMA->CHANNEL[channel_id].CRTL |= CLEAR_PORT_B_DONE_MASK;\r
- \r
- /* Clear interrupt in Cortex-M3 NVIC. */\r
- NVIC_ClearPendingIRQ( DMA_IRQn );\r
-}\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
+++ /dev/null
-/*******************************************************************************\r
- * (c) Copyright 2008 Actel Corporation. All rights reserved.\r
- * \r
- * SmartFusion microcontroller subsystem Peripheral DMA bare metal software\r
- * driver public API.\r
- *\r
- * SVN $Revision: 2110 $\r
- * SVN $Date: 2010-02-05 15:24:19 +0000 (Fri, 05 Feb 2010) $\r
- */\r
-/*=========================================================================*//**\r
- @mainpage SmartFusion MSS GPIO Bare Metal Driver.\r
-\r
- @section intro_sec Introduction\r
- The SmartFusion Microcontroller Subsystem (MSS) includes an 8 channel\r
- Peripheral DMA (PDMA) controller.\r
- This software driver provides a set of functions for controlling the MSS PDMA\r
- controller as part of a bare metal system where no operating system is available.\r
- This driver can be adapted for use as part of an operating system but the\r
- implementation of the adaptation layer between this driver and the operating\r
- system's driver model is outside the scope of this driver.\r
- \r
- @section theory_op Theory of Operation\r
- The MSS PDMA driver uses the SmartFusion "Cortex Microcontroler Software\r
- Interface Standard - Peripheral Access Layer" (CMSIS-PAL) to access MSS hardware\r
- registers. You must ensure that the SmartFusion CMSIS-PAL is either included\r
- in the software toolchain used to build your project or is included in your\r
- project. The most up-to-date SmartFusion CMSIS-PAL files can be obtained using\r
- the Actel Firmware Catalog.\r
- \r
- The MSS PDMA driver functions are grouped into the following categories:\r
- - Initialization\r
- - Configuration\r
- - DMA transfer control\r
- - Interrupt control\r
- \r
- The MSS PDMA driver is initialized through a call to the PDMA_init() function.\r
- The PDMA_init() function must be called before any other PDMA driver functions\r
- can be called.\r
- \r
- Each PDMA channel is individually configured through a call to the PDMA_configure()\r
- function. Configuration includes:\r
- - channel priority\r
- - transfer size\r
- - source and/or destination address increment\r
- - source or destination of the DMA transfer\r
- PDMA channels can be divided into high and low priority channels. High priority\r
- channels are given more opportunities to perform transfers than low priority\r
- channels when there are continuous high priority channels requests. The ratio\r
- of high priority to low priority PDMA transfers is configurable through the\r
- PDMA_set_priority() function.\r
- PDMA channels can be configured to perform byte (8 bits), half-word (16 bits)\r
- or word (32 bits) transfers.\r
- The source and destination address of a PDMA channel\92s transfers can be\r
- independently configured to increment by 0, 1, 2 or 4 bytes. For example, the\r
- content of a byte buffer located in RAM can be transferred into a peripheral\92s\r
- transmit register by configuring the source address increment to one byte and\r
- no increment of the destination address.\r
- The source or destination of a PDMA channel\92s transfers can be configured to\r
- be one of the MSS peripherals. This allows the PDMA controller to use some\r
- hardware flow control signaling with the peripheral to avoid overrunning the\r
- peripheral\92s data buffer when the peripheral is the destination of the DMA\r
- transfer, or attempting to read data from the peripheral while it is not ready\r
- when the peripheral is the source of the transfer.\r
- A PDMA channel can also be configured to transfer data between two memory\r
- mapped locations (memory to memory). No hardware flow control is used by the\r
- PDMA controller for data transfer in this configuration.\r
- \r
- A DMA transfer can be initiated by a call to the PDMA_start() function after a\r
- PDMA channel has been configured. Once started, further data can be pushed\r
- through the PDMA channel by calling the PDMA_load_next_buffer() function. The\r
- PDMA_load_next_buffer() function can be called every time a call to the\r
- PDMA_status() function indicates that the PDMA channel used for the transfer\r
- has a free buffer or it can be called as a result of a PDMA interrupt.\r
- \r
- A DMA transfer can be paused and resumed through calls to functions PDMA_pause()\r
- and PDMA_resume().\r
- \r
- Your application can manage DMA transfers using interrupts through the use of\r
- the following functions:\r
- - PDMA_set_irq_handler()\r
- - PDMA_enable_irq()\r
- - PDMA_clear_irq()\r
- - PDMA_disable_irq()\r
- The PDMA_set_irq_handler() function is used to register PDMA channel interrupt\r
- handler functions with the driver. You must create and register an interrupt\r
- handler function for each interrupt driven PDMA channel used by the application.\r
- Use the PDMA_enable_irq() function to enable interrupts for the PDMA channels. \r
- Every time a PDMA channel completes the transfer of a buffer it causes a PDMA\r
- interrupt to occur and the PDMA driver will call the interrupt handler\r
- registered by the application for that PDMA channel.\r
- \r
- *//*=========================================================================*/\r
-#ifndef __MSS_PERIPHERAL_DMA_H_\r
-#define __MSS_PERIPHERAL_DMA_H_\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif \r
-\r
-#include "../../CMSIS/a2fxxxm3.h"\r
-\r
-/***************************************************************************//**\r
- The pdma_channel_id_t enumeration is used to identify peripheral DMA channels.\r
- It is used as function parameter to specify the PDMA channel used.\r
- */\r
-typedef enum __pdma_channel_id\r
-{\r
- PDMA_CHANNEL_0 = 0,\r
- PDMA_CHANNEL_1,\r
- PDMA_CHANNEL_2,\r
- PDMA_CHANNEL_3,\r
- PDMA_CHANNEL_4,\r
- PDMA_CHANNEL_5,\r
- PDMA_CHANNEL_6,\r
- PDMA_CHANNEL_7\r
-} pdma_channel_id_t;\r
-\r
-/***************************************************************************//**\r
- The pdma_src_dest_t enumeration is used to specify the source or destination\r
- of transfers on a PDMA channel. It specifies which hardware peripheral will be\r
- the source or destination of DMA transfers. This allows the PDMA controller\r
- to use hardware flow control signals to avoid overrunning a\r
- destination peripheral with data it is not ready to receive, or attempting to\r
- transfer data from a peripheral while it has no data ready to transfer.\r
- The pdma_src_dest_t enumeration can also be used to specify that a PDMA channel\r
- is configured to transfer data between two memory mapped locations\r
- (memory to memory). No hardware data flow control is used by the PDMA\r
- controller in this configuration.\r
- This enumeration is used as parameter to function PDMA_configure().\r
- */\r
-typedef enum __pdma_src_dest\r
-{\r
- PDMA_FROM_UART_0 = 0,\r
- PDMA_TO_UART_0,\r
- PDMA_FROM_UART_1,\r
- PDMA_TO_UART_1,\r
- PDMA_FROM_SPI_0,\r
- PDMA_TO_SPI_0,\r
- PDMA_FROM_SPI_1,\r
- PDMA_TO_SPI_1,\r
- PDMA_FROM_FPGA_1,\r
- PDMA_TO_FPGA_1,\r
- PDMA_FROM_FPGA_0,\r
- PDMA_TO_FPGA_0,\r
- PDMA_TO_ACE,\r
- PDMA_FROM_ACE,\r
- PDMA_MEM_TO_MEM\r
-} pdma_src_dest_t;\r
-\r
-/***************************************************************************//**\r
- The pdma_priority_ratio_t enumeration is used to configure the ratio of high\r
- priority to low priority PDMA channels. This ratio specifies how many DMA\r
- transfer opportunities will be given to high priority channels before a DMA\r
- transfer opportunity is given to a low priority channel when there are\r
- continuous requests from high priority channels. This enumeration is used as\r
- parameter to function PDMA_set_priority_ratio().\r
- */\r
-typedef enum __pdma_priority_ratio_t\r
-{\r
- PDMA_ROUND_ROBIN = 0,\r
- PDMA_RATIO_HIGH_LOW_1_TO_1 = 1,\r
- PDMA_RATIO_HIGH_LOW_3_TO_1 = 3,\r
- PDMA_RATIO_HIGH_LOW_7_TO_1 = 7,\r
- PDMA_RATIO_HIGH_LOW_15_TO_1 = 15,\r
- PDMA_RATIO_HIGH_LOW_31_TO_1 = 31,\r
- PDMA_RATIO_HIGH_LOW_63_TO_1 = 63,\r
- PDMA_RATIO_HIGH_LOW_127_TO_1 = 127,\r
- PDMA_RATIO_HIGH_LOW_255_TO_1 = 255\r
-} pdma_priority_ratio_t;\r
-\r
-\r
-/***************************************************************************//**\r
- The pdma_channel_isr_t type is a pointer to a PDMA channel interrupt handler\r
- function. It specifies the function prototype of functions that can be\r
- registered as PDMA channel interrupt handlers. It is used as parameter to\r
- function PDMA_set_irq_handler().\r
- */\r
-typedef void (*pdma_channel_isr_t)( void );\r
-/***************************************************************************//**\r
- These constants are used to build the channel_cfg parameter of the\r
- PDMA_configure() function. They specify whether a channel is a high or low\r
- priority channel.\r
- */\r
-#define PDMA_LOW_PRIORITY 0x0000\r
-#define PDMA_HIGH_PRIORITY 0x0200\r
-\r
-/***************************************************************************//**\r
- These constants are used to build the channel_cfg parameter of the\r
- PDMA_configure() function. They specify the data width of the transfers\r
- performed by a PDMA channel.\r
- */\r
-#define PDMA_BYTE_TRANSFER 0x0000 /* Byte transfers (8 bits) */\r
-#define PDMA_HALFWORD_TRANSFER 0x0004 /* Half-word transfers (16 bits) */\r
-#define PDMA_WORD_TRANSFER 0x0008 /* Word transfers (32 bits) */\r
-\r
-/***************************************************************************//**\r
- These constants are used to build the channel_cfg parameter of the\r
- PDMA_configure() function. They specify the PDMA channel\92s source and\r
- destination address increment.\r
- */\r
-#define PDMA_NO_INC 0\r
-#define PDMA_INC_SRC_ONE_BYTE 0x0400\r
-#define PDMA_INC_SRC_TWO_BYTES 0x0800\r
-#define PDMA_INC_SRC_FOUR_BYTES 0x0C00\r
-#define PDMA_INC_DEST_ONE_BYTE 0x1000\r
-#define PDMA_INC_DEST_TWO_BYTES 0x2000\r
-#define PDMA_INC_DEST_FOUR_BYTES 0x3000\r
-\r
-/***************************************************************************//**\r
- * Mask for various control register bits.\r
- */\r
-#define PDMA_IRQ_ENABLE_MASK (uint32_t)0x00000040\r
-#define PDMA_PAUSE_MASK (uint32_t)0x00000010\r
-\r
-/***************************************************************************//**\r
- These constants are used to specify the src_addr parameter to the PDMA_start()\r
- and PDMA_load_next_buffer() functions. They specify the receive register\r
- address of peripherals that can be the source of a DMA transfer. \r
- When a PDMA channel is configured for DMA transfers from a peripheral to memory,\r
- the constant specifying that peripheral\92s receive register address must be used\r
- as the src_addr parameter.\r
- */\r
-#define PDMA_SPI0_RX_REGISTER 0x40001010uL\r
-#define PDMA_SPI1_RX_REGISTER 0x40011010uL\r
-#define PDMA_UART0_RX_REGISTER 0x40000000uL\r
-#define PDMA_UART1_RX_REGISTER 0x40010000uL\r
-#define PDMA_ACE_PPE_DATAOUT 0x40021308uL\r
-\r
-/***************************************************************************//**\r
- These constants are used to specify the dest_addr parameter to the PDMA_start()\r
- and PDMA_load_next_buffer() functions. They specify the transmit register\r
- address of peripherals that can be the destination of a DMA transfer. \r
- When a PDMA channel is configured for DMA transfers from memory to a peripheral,\r
- the constant specifying that peripheral\92s transmit register address must be used\r
- as the dest_addr parameter.\r
- */\r
-#define PDMA_SPI0_TX_REGISTER 0x40001014uL\r
-#define PDMA_SPI1_TX_REGISTER 0x40011014uL\r
-#define PDMA_UART0_TX_REGISTER 0x40000000uL\r
-#define PDMA_UART1_TX_REGISTER 0x40010000uL\r
-#define PDMA_ACE_SSE_DATAIN 0x40020700uL\r
-\r
-/***************************************************************************//**\r
- The PDMA_DEFAULT_WRITE_ADJ constant provides a suitable default value for the\r
- PDMA_configure() function write_adjust parameter.\r
- */\r
-#define PDMA_DEFAULT_WRITE_ADJ 10u\r
-\r
-/***************************************************************************//**\r
- The PDMA_init() function initializes the peripheral DMA hardware and driver\r
- internal data. It resets the PDMA and it also clears any pending PDMA\r
- interrupts in the Cortex-M3 interrupt controller. When the function exits, it\r
- takes the PDMA block out of reset.\r
- */\r
-void PDMA_init( void );\r
-\r
-/***************************************************************************//**\r
- The PDMA_configure() function configures a PDMA channel.\r
- It specifies:\r
- - The peripheral which will be the source or destination of the DMA transfer.\r
- - Whether the DMA channel will be a high or low priority channel\r
- - The source and destination address increment that will take place after\r
- each transfer.\r
- \r
- @param channel_id\r
- The channel_id parameter identifies the PDMA channel used by the function.\r
- \r
- @param src_dest\r
- The src_dest parameter specifies the source or destination of the DMA\r
- transfers that will be performed. It can be one of the following:\r
- - PDMA_FROM_UART_0\r
- - PDMA_TO_UART_0\r
- - PDMA_FROM_UART_1\r
- - PDMA_TO_UART_1\r
- - PDMA_FROM_SPI_0\r
- - PDMA_TO_SPI_0\r
- - PDMA_FROM_SPI_1\r
- - PDMA_TO_SPI_1\r
- - PDMA_FROM_FPGA_1\r
- - PDMA_TO_FPGA_1\r
- - PDMA_FROM_FPGA_0\r
- - PDMA_TO_FPGA_0\r
- - PDMA_TO_ACE\r
- - PDMA_FROM_ACE\r
- - PDMA_MEM_TO_MEM\r
- \r
- @param channel_cfg\r
- The channel_cfg parameter specifies the configuration of the PDMA channel.\r
- The configuration includes:\r
- - channel priority\r
- - transfer size\r
- - source and/or destination address increment\r
- The channel_cfg parameter value is a logical OR of:\r
- One of the following to specify the channel priority:\r
- - PDMA_LOW_PRIORITY\r
- - PDMA_HIGH_PRIORITY\r
- One of the following to specify the transfer size:\r
- - PDMA_BYTE_TRANSFER\r
- - PDMA_HALFWORD_TRANSFER\r
- - PDMA_WORD_TRANSFER\r
- One or two of the following to specify the source and/or destination address\r
- increment:\r
- - PDMA_NO_INC\r
- - PDMA_INC_SRC_ONE_BYTE\r
- - PDMA_INC_SRC_TWO_BYTES\r
- - PDMA_INC_SRC_FOUR_BYTES\r
- - PDMA_INC_DEST_ONE_BYTE\r
- - PDMA_INC_DEST_TWO_BYTES\r
- - PDMA_INC_DEST_FOUR_BYTES\r
- \r
- @param write_adjust\r
- The write_adjust parameter specifies the number of Cortex-M3 clock cycles\r
- the PDMA controller will wait before attempting another transfer cycle. This\r
- delay is necessary when peripherals are used as destination of a DMA transfer\r
- to ensure the DMA controller interprets the state of the peripheral\92s ready\r
- signal only after data has actually been written to the peripheral. This delay\r
- accounts for posted writes (dump and run) for write accesses to peripherals. \r
- The effect of posted writes is that if the PDMA performs a write operation to\r
- a peripheral, the data is not actually written into the peripheral until\r
- sometime after the PDMA controller thinks it is written.\r
- A suitable value for write_adjust depends on the target of the DMA transfer.\r
- Guidelines for choosing this value are as follows:\r
- \95 The PDMA_DEFAULT_WRITE_ADJ constant provides a suitable default value\r
- for the write_adjust parameter when the PDMA channel is configured for\r
- transfers with MSS peripherals.\r
- \95 The PDMA_DEFAULT_WRITE_ADJ constant can also be used for DMA transfers\r
- with FPGA fabric implemented peripherals making use of the DMAREADY0 or\r
- DMAREADY1fabric interface signal to indicate that the peripheral is\r
- ready for another DMA transfer.\r
- \95 The write_adjust parameter can be set to zero to achieve maximum transfer\r
- speed for genuine memory to memory transfers. \r
- \95 The internal latency of FPGA implemented peripherals will decide the\r
- write_adjust value for fabric peripherals that do not use the DMAREADY0\r
- or DMAREADY1 fabric interface signals. You need to check the fabric\r
- peripheral documentation for the value to use.\r
- \r
- Example:\r
- @code\r
- PDMA_configure\r
- (\r
- PDMA_CHANNEL_0,\r
- PDMA_TO_SPI_1,\r
- PDMA_LOW_PRIORITY | PDMA_BYTE_TRANSFER | PDMA_INC_SRC_ONE_BYTE,\r
- PDMA_DEFAULT_WRITE_ADJ\r
- );\r
- @endcode\r
- */\r
-void PDMA_configure\r
-(\r
- pdma_channel_id_t channel_id,\r
- pdma_src_dest_t src_dest,\r
- uint32_t channel_cfg,\r
- uint8_t write_adjust\r
-);\r
-\r
-\r
-/***************************************************************************//**\r
- The PDMA_set_priority_ratio() function sets the ratio of high priority to low\r
- priority DMA access opportunities. This ratio is used by the PDMA controller\r
- arbiter to decide which PDMA channel will be given the opportunity to perform\r
- a transfer when multiple PDMA channels are requesting to transfer data at the\r
- same time. The priority ratio specifies how many DMA transfer opportunities\r
- will be given to high priority channels before a DMA transfer opportunity is\r
- given to a low priority channel when there are continuous requests from high\r
- priority channels.\r
- \r
- @param priority_ratio\r
- The priority_ratio parameter specifies the ratio of DMA access opportunities\r
- given to high priority channels versus low priority channels.\r
- Allowed values for this parameter are:\r
- - PDMA_ROUND_ROBIN\r
- - PDMA_RATIO_HIGH_LOW_1_TO_1\r
- - PDMA_RATIO_HIGH_LOW_3_TO_1\r
- - PDMA_RATIO_HIGH_LOW_7_TO_1\r
- - PDMA_RATIO_HIGH_LOW_15_TO_1\r
- - PDMA_RATIO_HIGH_LOW_31_TO_1\r
- - PDMA_RATIO_HIGH_LOW_63_TO_1\r
- - PDMA_RATIO_HIGH_LOW_127_TO_1\r
- - PDMA_RATIO_HIGH_LOW_255_TO_1\r
- \r
- Example:\r
- @code\r
- PDMA_set_priority_ratio( PDMA_ROUND_ROBIN );\r
- @endcode\r
- */\r
-static __INLINE void PDMA_set_priority_ratio\r
-(\r
- pdma_priority_ratio_t priority_ratio\r
-)\r
-{\r
- PDMA->RATIO_HIGH_LOW = (uint32_t)priority_ratio;\r
-}\r
-\r
-/***************************************************************************//**\r
- The PDMA_start() function initiates a DMA transfer. It specifies the source\r
- and destination address of the transfer as well as the number of transfers\r
- that must take place. The source and destination addresses can be the address\r
- of peripheral registers.\r
- \r
- @param channel_id\r
- The channel_id parameter identifies the PDMA channel used by the function.\r
- \r
- @param src_addr\r
- The src_addr parameter specifies the address location of the data to be\r
- transferred. You must ensure that this source address is consistent with the\r
- DMA source configured for the selected channel using the PDMA_configure()\r
- function.\r
- For DMA transfers from MSS peripheral to memory, the following src_addr\r
- parameter values are allowed:\r
- \95 PDMA_SPI0_RX_REGISTER\r
- \95 PDMA_SPI1_RX_REGISTER\r
- \95 PDMA_UART0_RX_REGISTER\r
- \95 PDMA_UART1_RX_REGISTER\r
- \95 PDMA_ACE_PPE_DATAOUT\r
- For DMA transfers from FPGA fabric peripheral to memory, the following\r
- src_addr parameter values are allowed:\r
- \95 An address in the FPGA fabric address space (0x40050000-0x400FFFFF)\r
- For DMA transfers from memory to MSS peripheral, or from memory to FPGA\r
- fabric peripheral, or from memory to memory, the following src_addr\r
- parameter values are allowed:\r
- \95 Any memory mapped address.\r
-\r
- @param dest_addr\r
- The dest_addr parameter specifies the destination address of the PDMA\r
- transfer. You must ensure that this matches with the DMA destination\r
- configured for the selected channel.\r
- For DMA transfers from memory to MSS peripheral, the following dest_addr parameter values are allowed:\r
- \95 PDMA_SPI0_TX_REGISTER\r
- \95 PDMA_SPI1_TX_REGISTER\r
- \95 PDMA_UART0_TX_REGISTER\r
- \95 PDMA_UART1_TX_REGISTER\r
- \95 PDMA_ACE_SSE_DATAIN\r
- For DMA transfers from memory to FPGA fabric peripheral, the following\r
- dest_addr parameter values are allowed:\r
- \95 An address in the FPGA fabric address space (0x40050000-0x400FFFFF)\r
- For DMA transfers from MSS peripheral to memory, or from FPGA fabric\r
- peripheral to memory, or from memory to memory, the following dest_addr\r
- parameter values are allowed:\r
- \95 Any memory mapped address.\r
-\r
- @param transfer_count\r
- The transfer_count parameter specifies the number of transfers to be\r
- performed. It is the number of bytes to transfer if the PDMA channel is\r
- configured for byte transfer, the number of half-words to transfer if the\r
- PDMA channel is configured for half-word transfer, or the number of words\r
- to transfer if the PDMA channel is configured for word transfer.\r
- \r
- Example:\r
- @code\r
- PDMA_start\r
- (\r
- PDMA_CHANNEL_3,\r
- PDMA_SPI1_RX_REGISTER,\r
- (uint32_t)slave_rx_buffer,\r
- sizeof(slave_rx_buffer)\r
- ); \r
- @endcode\r
- */\r
-void PDMA_start\r
-(\r
- pdma_channel_id_t channel_id,\r
- uint32_t src_addr,\r
- uint32_t dest_addr,\r
- uint16_t transfer_count\r
-);\r
-\r
-/***************************************************************************//**\r
- The PDMA_load_next_buffer() function sets the next buffer to be transferred.\r
- This function is called after a transfer has been initiated using the\r
- PDMA_start() function. Its purpose is to keep feeding a PDMA channel with data\r
- buffers.\r
- \r
- @param channel_id\r
- The channel_id parameter identifies the PDMA channel used by the function.\r
- \r
- @param src_addr\r
- The src_addr parameter specifies the address location of the data to be\r
- transferred. You must ensure that this source address is consistent with the\r
- DMA source configured for the selected channel using the PDMA_configure()\r
- function.\r
- For DMA transfers from MSS peripheral to memory, the following src_addr parameter values are allowed:\r
- \95 PDMA_SPI0_RX_REGISTER\r
- \95 PDMA_SPI1_RX_REGISTER\r
- \95 PDMA_UART0_RX_REGISTER\r
- \95 PDMA_UART1_RX_REGISTER\r
- \95 PDMA_ACE_PPE_DATAOUT\r
- For DMA transfers from FPGA fabric peripheral to memory, the following src_addr parameter values are allowed:\r
- \95 An address in the FPGA fabric address space (0x40050000-0x400FFFFF)\r
- For DMA transfers from memory to MSS peripheral, or from memory to FPGA fabric peripheral, or from memory to memory, the following src_addr parameter values are allowed:\r
- \95 Any memory mapped address.\r
-\r
- @param dest_addr\r
- The dest_addr parameter specifies the destination address of the PDMA\r
- transfer. You must ensure that this matches with the DMA destination\r
- configured for the selected channel.\r
- For DMA transfers from memory to MSS peripheral, the following dest_addr parameter values are allowed:\r
- \95 PDMA_SPI0_TX_REGISTER\r
- \95 PDMA_SPI1_TX_REGISTER\r
- \95 PDMA_UART0_TX_REGISTER\r
- \95 PDMA_UART1_TX_REGISTER\r
- \95 PDMA_ACE_SSE_DATAIN\r
- For DMA transfers from memory to FPGA fabric peripheral, the following dest_addr parameter values are allowed:\r
- \95 An address in the FPGA fabric address space (0x40050000-0x400FFFFF)\r
- For DMA transfers from MSS peripheral to memory, or from FPGA fabric peripheral to memory, or from memory to memory, the following dest_addr parameter values are allowed:\r
- \95 Any memory mapped address.\r
- \r
- @param transfer_count\r
- The transfer_count parameter specifies the number of transfers to be\r
- performed. It is the number of bytes to transfer if the PDMA channel is\r
- configured for byte transfer, the number of half-words to transfer if the\r
- PDMA channel is configured for half-word transfer or the number of words to\r
- transfer if the PDMA channel is configured for word transfer.\r
- \r
- Example:\r
- @code\r
- void write_cmd_data\r
- (\r
- mss_spi_instance_t * this_spi,\r
- const uint8_t * cmd_buffer,\r
- uint16_t cmd_byte_size,\r
- uint8_t * data_buffer,\r
- uint16_t data_byte_size\r
- )\r
- {\r
- uint32_t transfer_size;\r
- \r
- transfer_size = cmd_byte_size + data_byte_size;\r
- \r
- MSS_SPI_disable( this_spi );\r
- MSS_SPI_set_transfer_byte_count( this_spi, transfer_size );\r
- \r
- PDMA_start\r
- (\r
- PDMA_CHANNEL_0,\r
- (uint32_t)cmd_buffer,\r
- PDMA_SPI1_TX_REGISTER,\r
- cmd_byte_size\r
- );\r
- \r
- PDMA_load_next_buffer\r
- (\r
- PDMA_CHANNEL_0,\r
- (uint32_t)data_buffer,\r
- PDMA_SPI1_TX_REGISTER,\r
- data_byte_size\r
- );\r
- \r
- MSS_SPI_enable( this_spi );\r
- \r
- while ( !MSS_SPI_tx_done(this_spi) )\r
- {\r
- ;\r
- }\r
- }\r
- @endcode\r
- */\r
-void PDMA_load_next_buffer\r
-(\r
- pdma_channel_id_t channel_id,\r
- uint32_t src_addr,\r
- uint32_t dest_addr,\r
- uint16_t transfer_count\r
-);\r
-\r
-/***************************************************************************//**\r
- The PDMA_status() function returns the status of a DMA channel.\r
- The returned value indicates if transfers have been completed using buffer A\r
- or buffer B of the PDMA hardware block.\r
- \r
- @param channel_id\r
- The channel_id parameter identifies the PDMA channel used by the function.\r
- \r
- @return\r
- bit 0 of the return value indicates if buffer A has been trasnfered. It is\r
- set to 1 if the transfer has completed.\r
- bit 1 of the return value indicates if buffer B has been transfered. It is\r
- set to 1 if the transfer has completed.\r
- */\r
-uint32_t PDMA_status\r
-(\r
- pdma_channel_id_t channel_id\r
-);\r
-\r
-/***************************************************************************//**\r
- The PDMA_pause() function temporarily pauses a PDMA transfer taking place on\r
- the specified PDMA channel. The transfer can later be resumed by using the\r
- PDMA_resume() function.\r
- \r
- @param channel_id\r
- The channel_id parameter identifies the PDMA channel used by the function.\r
- */\r
-static __INLINE void PDMA_pause( pdma_channel_id_t channel_id )\r
-{\r
- PDMA->CHANNEL[channel_id].CRTL |= PDMA_PAUSE_MASK;\r
-}\r
-\r
-/***************************************************************************//**\r
- The PDMA_resume() function resumes a transfer previously paused using the\r
- PDMA_pause() function.\r
- \r
- @param channel_id The channel_id parameter identifies the PDMA channel\r
- used by the function.\r
- */\r
-static __INLINE void PDMA_resume( pdma_channel_id_t channel_id )\r
-{\r
- PDMA->CHANNEL[channel_id].CRTL &= ~PDMA_PAUSE_MASK;\r
-}\r
-\r
-/***************************************************************************//**\r
- The PDMA_enable_irq() enables the PDMA hardware to generate an interrupt when\r
- a DMA transfer completes on the specified PDMA channel. This function also\r
- enables the PDMA interrupt in the Cortex-M3 interrupt controller.\r
- \r
- @param channel_id\r
- The channel_id parameter identifies the PDMA channel used by the function.\r
- */\r
-void PDMA_enable_irq( pdma_channel_id_t channel_id );\r
-\r
-/***************************************************************************//**\r
- The PDMA_disable_irq() disables interrupts for a specific PDMA channel.\r
- \r
- @param channel_id\r
- The channel_id parameter identifies the PDMA channel used by the function.\r
- */\r
-static __INLINE void PDMA_disable_irq( pdma_channel_id_t channel_id )\r
-{\r
- PDMA->CHANNEL[channel_id].CRTL &= ~PDMA_IRQ_ENABLE_MASK;\r
-}\r
-\r
-/***************************************************************************//**\r
- The PDMA_set_irq_handler() function registers a handler function for\r
- interrupts generated on the completion of a transfer on a specific PDMA\r
- channel. This function also enables the PDMA interrupt both in the PDMA\r
- controller and in the Cortex-M3 interrupt controller.\r
- \r
- @param channel_id\r
- The channel_id parameter identifies the PDMA channel used by the function.\r
- \r
- @param handler\r
- The handler parameter is a pointer to the function that will be called when\r
- a transfer completes on the PDMA channel identified by channel_id and the\r
- interrupt is enabled for that channel.\r
- \r
- Example:\r
- @code\r
- void slave_dma_irq_handler( void )\r
- {\r
- if ( g_spi1_rx_buffer[2] == 0x99 )\r
- {\r
- PDMA_load_next_buffer\r
- (\r
- PDMA_CHANNEL_0,\r
- (uint32_t)g_spi1_tx_buffer_b,\r
- PDMA_SPI1_TX_REGISTER,\r
- sizeof(g_spi1_tx_buffer_b)\r
- ); \r
- }\r
- PDMA_disable_irq( PDMA_CHANNEL_3 );\r
- }\r
- \r
- void setup_dma( void )\r
- {\r
- PDMA_init();\r
- PDMA_configure\r
- (\r
- PDMA_CHANNEL_0, \r
- PDMA_TO_SPI_1, \r
- PDMA_LOW_PRIORITY | PDMA_BYTE_TRANSFER | PDMA_INC_SRC_ONE_BYTE\r
- );\r
- PDMA_configure\r
- ( \r
- PDMA_CHANNEL_3,\r
- PDMA_FROM_SPI_1,\r
- PDMA_HIGH_PRIORITY | PDMA_BYTE_TRANSFER | PDMA_INC_DEST_ONE_BYTE\r
- );\r
- PDMA_set_irq_handler( PDMA_CHANNEL_3, slave_dma_irq_handler );\r
- PDMA_start( PDMA_CHANNEL_3, PDMA_SPI1_RX_REGISTER, (uint32_t)g_spi1_rx_buffer, 3 ); \r
- }\r
- @endcode\r
- */\r
-void PDMA_set_irq_handler\r
-(\r
- pdma_channel_id_t channel_id,\r
- pdma_channel_isr_t handler\r
-);\r
-\r
-/***************************************************************************//**\r
- The PDMA_clear_irq() function clears interrupts for a specific PDMA channel.\r
- This function also clears the PDMA interrupt in the Cortex-M3 NVIC.\r
- \r
- @param channel_id\r
- The channel_id parameter identifies the PDMA channel used by the function.\r
- */\r
-void PDMA_clear_irq\r
-(\r
- pdma_channel_id_t channel_id\r
-);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __MSS_PERIPHERAL_DMA_H_ */\r
+++ /dev/null
-/*******************************************************************************\r
- * (c) Copyright 2008 Actel Corporation. All rights reserved.\r
- * \r
- * SmartFusion microcontroller subsystem SPI bare metal software driver\r
- * implementation.\r
- *\r
- * SVN $Revision: 2176 $\r
- * SVN $Date: 2010-02-15 21:04:22 +0000 (Mon, 15 Feb 2010) $\r
- */\r
-#include "mss_spi.h"\r
-#include "../../CMSIS/mss_assert.h"\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif \r
-\r
-/***************************************************************************//**\r
- MSS SPI can operate as master or slave.\r
- */\r
-#define MSS_SPI_MODE_SLAVE (uint32_t)0\r
-#define MSS_SPI_MODE_MASTER (uint32_t)1\r
-\r
-/***************************************************************************//**\r
- * Mask of transfer protocol and SPO, SPH bits within control register.\r
- */\r
-#define PROTOCOL_MODE_MASK (uint32_t)0x030000C0\r
-\r
-/***************************************************************************//**\r
- * Mask of theframe count bits within the SPI control register.\r
- */\r
-#define TXRXDFCOUNT_MASK (uint32_t)0x00FFFF00\r
-#define TXRXDFCOUNT_SHIFT (uint32_t)8\r
-\r
-/***************************************************************************//**\r
- * SPI hardware FIFO depth.\r
- */\r
-#define RX_FIFO_SIZE 4u\r
-\r
-/***************************************************************************//**\r
- Marker used to detect that the configuration has not been selected for a\r
- specific slave when operating as a master.\r
- */\r
-#define NOT_CONFIGURED 0xFFFFFFFF\r
-\r
-/***************************************************************************//**\r
- * SPI instance data structures for SPI0 and SPI1. A pointer to these data\r
- * structures must be used as first parameter to any of the SPI driver functions\r
- * to identify the SPI hardware block that will perform the requested operation.\r
- */\r
-mss_spi_instance_t g_mss_spi0;\r
-mss_spi_instance_t g_mss_spi1;\r
-\r
-/***************************************************************************//**\r
- SPI0 interrupt service routine\r
- */\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void SPI0_IRQHandler( void );\r
-#else\r
-void SPI0_IRQHandler( void );\r
-#endif\r
-\r
-/***************************************************************************//**\r
- SPI1 interrupt service routine\r
- */\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void SPI1_IRQHandler( void );\r
-#else\r
-void SPI1_IRQHandler( void );\r
-#endif\r
-\r
-/***************************************************************************//**\r
- * MSS_SPI_init()\r
- * See "mss_spi.h" for details of how to use this function.\r
- */\r
-void MSS_SPI_init\r
-(\r
- mss_spi_instance_t * this_spi\r
-)\r
-{\r
- uint16_t i;\r
- \r
- ASSERT( (this_spi == &g_mss_spi0) || (this_spi == &g_mss_spi1) );\r
- \r
- if (this_spi == &g_mss_spi0)\r
- {\r
- this_spi->hw_reg = SPI0;\r
- this_spi->hw_reg_bit = SPI0_BITBAND;\r
- this_spi->irqn = SPI0_IRQn;\r
-\r
- /* reset SPI0 */\r
- SYSREG->SOFT_RST_CR |= SYSREG_SPI0_SOFTRESET_MASK;\r
- /* Clear any previously pended SPI0 interrupt */\r
- NVIC_ClearPendingIRQ( SPI0_IRQn );\r
- /* Take SPI0 out of reset. */\r
- SYSREG->SOFT_RST_CR &= ~SYSREG_SPI0_SOFTRESET_MASK;\r
- }\r
- else\r
- {\r
- this_spi->hw_reg = SPI1;\r
- this_spi->hw_reg_bit = SPI1_BITBAND;\r
- this_spi->irqn = SPI1_IRQn;\r
- \r
- /* reset SPI1 */\r
- SYSREG->SOFT_RST_CR |= SYSREG_SPI1_SOFTRESET_MASK;\r
- /* Clear any previously pended SPI1 interrupt */\r
- NVIC_ClearPendingIRQ( SPI1_IRQn );\r
- /* Take SPI1 out of reset. */\r
- SYSREG->SOFT_RST_CR &= ~SYSREG_SPI1_SOFTRESET_MASK;\r
- }\r
- \r
- this_spi->frame_rx_handler = 0U;\r
- this_spi->slave_tx_frame = 0U;\r
- \r
- this_spi->block_rx_handler = 0U;\r
- \r
- this_spi->slave_tx_buffer = 0U;\r
- this_spi->slave_tx_size = 0U;\r
- this_spi->slave_tx_idx = 0U;\r
- \r
- for ( i = 0u; i < (uint16_t)MSS_SPI_MAX_NB_OF_SLAVES; ++i )\r
- {\r
- this_spi->slaves_cfg[i].ctrl_reg = NOT_CONFIGURED;\r
- }\r
-}\r
-\r
-/***************************************************************************//**\r
- * MSS_SPI_configure_slave_mode()\r
- * See "mss_spi.h" for details of how to use this function.\r
- */\r
-void MSS_SPI_configure_slave_mode\r
-(\r
- mss_spi_instance_t * this_spi,\r
- mss_spi_protocol_mode_t protocol_mode,\r
- mss_spi_pclk_div_t clk_rate,\r
- uint8_t frame_bit_length\r
-)\r
-{\r
- ASSERT( (this_spi == &g_mss_spi0) || (this_spi == &g_mss_spi1) );\r
- ASSERT( frame_bit_length <= 32 );\r
- \r
- /* Set the mode. */\r
- this_spi->hw_reg_bit->CTRL_MASTER = MSS_SPI_MODE_SLAVE;\r
-\r
- /* Set the clock rate. */\r
- this_spi->hw_reg_bit->CTRL_ENABLE = 0U;\r
- this_spi->hw_reg->CONTROL = (this_spi->hw_reg->CONTROL & ~PROTOCOL_MODE_MASK) | (uint32_t)protocol_mode;\r
- this_spi->hw_reg->CLK_GEN = (uint32_t)clk_rate;\r
- \r
- /* Set default frame size to byte size and number of data frames to 1. */\r
- this_spi->hw_reg->CONTROL = (this_spi->hw_reg->CONTROL & ~TXRXDFCOUNT_MASK) | ((uint32_t)1 << TXRXDFCOUNT_SHIFT);\r
- this_spi->hw_reg->TXRXDF_SIZE = frame_bit_length;\r
- this_spi->hw_reg_bit->CTRL_ENABLE = 1U;\r
-}\r
-\r
-/***************************************************************************//**\r
- * MSS_SPI_configure_master_mode()\r
- * See "mss_spi.h" for details of how to use this function.\r
- */\r
-void MSS_SPI_configure_master_mode\r
-(\r
- mss_spi_instance_t * this_spi,\r
- mss_spi_slave_t slave,\r
- mss_spi_protocol_mode_t protocol_mode,\r
- mss_spi_pclk_div_t clk_rate,\r
- uint8_t frame_bit_length\r
-)\r
-{\r
- ASSERT( (this_spi == &g_mss_spi0) || (this_spi == &g_mss_spi1) );\r
- ASSERT( slave < MSS_SPI_MAX_NB_OF_SLAVES );\r
- ASSERT( frame_bit_length <= 32 );\r
- \r
- /* Set the mode. */\r
- this_spi->hw_reg_bit->CTRL_ENABLE = 0U;\r
- this_spi->hw_reg_bit->CTRL_MASTER = MSS_SPI_MODE_MASTER;\r
- this_spi->hw_reg_bit->CTRL_ENABLE = 1U;\r
-\r
- /*\r
- * Keep track of the required register configuration for this slave. These\r
- * values will be used by the MSS_SPI_set_slave_select() function to configure\r
- * the master to match the slave being selected.\r
- */\r
- if ( slave < MSS_SPI_MAX_NB_OF_SLAVES ) \r
- {\r
- this_spi->slaves_cfg[slave].ctrl_reg = 0x00000002uL | (uint32_t)protocol_mode | ((uint32_t)1 << TXRXDFCOUNT_SHIFT);\r
- this_spi->slaves_cfg[slave].txrxdf_size_reg = frame_bit_length;\r
- this_spi->slaves_cfg[slave].clk_gen = (uint8_t)clk_rate;\r
- }\r
-}\r
-\r
-/***************************************************************************//**\r
- * MSS_SPI_set_slave_select()\r
- * See "mss_spi.h" for details of how to use this function.\r
- */\r
-void MSS_SPI_set_slave_select\r
-(\r
- mss_spi_instance_t * this_spi,\r
- mss_spi_slave_t slave\r
-)\r
-{\r
- ASSERT( (this_spi == &g_mss_spi0) || (this_spi == &g_mss_spi1) );\r
- \r
- /* This function is only intended to be used with an SPI master. */\r
- ASSERT( this_spi->hw_reg_bit->CTRL_MASTER == MSS_SPI_MODE_MASTER );\r
- ASSERT( this_spi->slaves_cfg[slave].ctrl_reg != NOT_CONFIGURED );\r
-\r
- /* Set the clock rate. */\r
- this_spi->hw_reg_bit->CTRL_ENABLE = 0U;\r
- this_spi->hw_reg->CONTROL = this_spi->slaves_cfg[slave].ctrl_reg;\r
- this_spi->hw_reg->CLK_GEN = this_spi->slaves_cfg[slave].clk_gen;\r
- this_spi->hw_reg->TXRXDF_SIZE = this_spi->slaves_cfg[slave].txrxdf_size_reg;\r
- this_spi->hw_reg_bit->CTRL_ENABLE = 1U;\r
- \r
- /* Set slave select */\r
- this_spi->hw_reg->SLAVE_SELECT |= ((uint32_t)1 << (uint32_t)slave);\r
-}\r
-\r
-/***************************************************************************//**\r
- * MSS_SPI_clear_slave_select()\r
- * See "mss_spi.h" for details of how to use this function.\r
- */\r
-void MSS_SPI_clear_slave_select\r
-(\r
- mss_spi_instance_t * this_spi,\r
- mss_spi_slave_t slave\r
-)\r
-{\r
- ASSERT( (this_spi == &g_mss_spi0) || (this_spi == &g_mss_spi1) );\r
- \r
- /* This function is only intended to be used with an SPI master. */\r
- ASSERT( this_spi->hw_reg_bit->CTRL_MASTER == MSS_SPI_MODE_MASTER );\r
-\r
- this_spi->hw_reg->SLAVE_SELECT &= ~((uint32_t)1 << (uint32_t)slave);\r
-}\r
-\r
-/***************************************************************************//**\r
- * MSS_SPI_transfer_frame()\r
- * See "mss_spi.h" for details of how to use this function.\r
- */\r
-uint32_t MSS_SPI_transfer_frame\r
-(\r
- mss_spi_instance_t * this_spi,\r
- uint32_t tx_bits\r
-)\r
-{\r
- volatile uint32_t dummy;\r
- \r
- ASSERT( (this_spi == &g_mss_spi0) || (this_spi == &g_mss_spi1) );\r
- \r
- /* This function is only intended to be used with an SPI master. */\r
- ASSERT( this_spi->hw_reg_bit->CTRL_MASTER == MSS_SPI_MODE_MASTER );\r
- \r
- /* Flush Rx FIFO. */\r
- while ( this_spi->hw_reg_bit->STATUS_RX_RDY == 1U )\r
- {\r
- dummy = this_spi->hw_reg->RX_DATA;\r
- dummy = dummy; /* Prevent Lint warning. */\r
- }\r
- \r
- /* Send frame. */\r
- this_spi->hw_reg->TX_DATA = tx_bits;\r
- \r
- /* Wait for frame Tx to complete. */\r
- while ( this_spi->hw_reg_bit->STATUS_TX_DONE == 0U )\r
- {\r
- ;\r
- }\r
- \r
- /* Read received frame. */\r
- /* Wait for Rx complete. */\r
- while ( this_spi->hw_reg_bit->STATUS_RX_RDY == 0U )\r
- {\r
- ;\r
- }\r
- /* Return Rx data. */\r
- return( this_spi->hw_reg->RX_DATA );\r
-}\r
-\r
-\r
-/***************************************************************************//**\r
- * MSS_SPI_transfer_block()\r
- * See "mss_spi.h" for details of how to use this function.\r
- */\r
-void MSS_SPI_transfer_block\r
-(\r
- mss_spi_instance_t * this_spi,\r
- const uint8_t * cmd_buffer,\r
- uint16_t cmd_byte_size,\r
- uint8_t * rd_buffer,\r
- uint16_t rd_byte_size\r
-)\r
-{\r
- uint16_t transfer_idx = 0U;\r
- uint16_t tx_idx;\r
- uint16_t rx_idx;\r
- uint32_t frame_count;\r
- volatile uint32_t rx_raw;\r
- uint16_t transit = 0U;\r
- \r
- uint16_t transfer_size; /* Total number of bytes transfered. */\r
- \r
- ASSERT( (this_spi == &g_mss_spi0) || (this_spi == &g_mss_spi1) );\r
- \r
- /* This function is only intended to be used with an SPI master. */\r
- ASSERT( this_spi->hw_reg_bit->CTRL_MASTER == MSS_SPI_MODE_MASTER );\r
- \r
- /* Compute number of bytes to transfer. */\r
- transfer_size = cmd_byte_size + rd_byte_size;\r
- \r
- /* Adjust to 1 byte transfer to cater for DMA transfers. */\r
- if ( transfer_size == 0U )\r
- {\r
- frame_count = 1U;\r
- }\r
- else\r
- {\r
- frame_count = transfer_size;\r
- }\r
- \r
- /* Set frame size to 8 bits and the frame count to the tansfer size. */\r
- this_spi->hw_reg_bit->CTRL_ENABLE = 0U;\r
- this_spi->hw_reg->CONTROL = (this_spi->hw_reg->CONTROL & ~TXRXDFCOUNT_MASK) | ( (frame_count << TXRXDFCOUNT_SHIFT) & TXRXDFCOUNT_MASK);\r
- this_spi->hw_reg->TXRXDF_SIZE = 8U;\r
- this_spi->hw_reg_bit->CTRL_ENABLE = 1U;\r
-\r
- /* Flush the receive FIFO. */\r
- while ( !this_spi->hw_reg_bit->STATUS_RX_FIFO_EMPTY )\r
- {\r
- rx_raw = this_spi->hw_reg->RX_DATA;\r
- }\r
- \r
- tx_idx = 0u;\r
- rx_idx = 0u;\r
- if ( tx_idx < cmd_byte_size )\r
- {\r
- this_spi->hw_reg->TX_DATA = cmd_buffer[tx_idx];\r
- ++tx_idx;\r
- ++transit;\r
- }\r
- else\r
- {\r
- if ( tx_idx < transfer_size )\r
- {\r
- this_spi->hw_reg->TX_DATA = 0x00U;\r
- ++tx_idx;\r
- ++transit;\r
- }\r
- }\r
- /* Perform the remainder of the transfer by sending a byte every time a byte\r
- * has been received. This should ensure that no Rx overflow can happen in\r
- * case of an interrupt occurs during this function. */\r
- while ( transfer_idx < transfer_size )\r
- {\r
- if ( !this_spi->hw_reg_bit->STATUS_RX_FIFO_EMPTY )\r
- {\r
- /* Process received byte. */\r
- rx_raw = this_spi->hw_reg->RX_DATA;\r
- if ( transfer_idx >= cmd_byte_size )\r
- {\r
- if ( rx_idx < rd_byte_size )\r
- {\r
- rd_buffer[rx_idx] = (uint8_t)rx_raw; \r
- }\r
- ++rx_idx;\r
- }\r
- ++transfer_idx;\r
- --transit;\r
- }\r
-\r
- if ( !this_spi->hw_reg_bit->STATUS_TX_FIFO_FULL )\r
- {\r
- if (transit < RX_FIFO_SIZE)\r
- {\r
- /* Send another byte. */\r
- if ( tx_idx < cmd_byte_size )\r
- {\r
- this_spi->hw_reg->TX_DATA = cmd_buffer[tx_idx];\r
- ++tx_idx;\r
- ++transit;\r
- }\r
- else\r
- {\r
- if ( tx_idx < transfer_size )\r
- {\r
- this_spi->hw_reg->TX_DATA = 0x00U;\r
- ++tx_idx;\r
- ++transit;\r
- }\r
- }\r
- }\r
- }\r
- }\r
-}\r
-\r
-/***************************************************************************//**\r
- * MSS_SPI_set_frame_rx_handler()\r
- * See "mss_spi.h" for details of how to use this function.\r
- */\r
-void MSS_SPI_set_frame_rx_handler\r
-(\r
- mss_spi_instance_t * this_spi,\r
- mss_spi_frame_rx_handler_t rx_handler\r
-)\r
-{\r
- ASSERT( (this_spi == &g_mss_spi0) || (this_spi == &g_mss_spi1) );\r
- \r
- /* This function is only intended to be used with an SPI slave. */\r
- ASSERT( this_spi->hw_reg_bit->CTRL_MASTER == MSS_SPI_MODE_SLAVE );\r
- \r
- /* Disable block Rx handler as they are mutually exclusive. */\r
- this_spi->block_rx_handler = 0U;\r
- \r
- /* Keep a copy of the pointer to the rx hnadler function. */\r
- this_spi->frame_rx_handler = rx_handler;\r
- \r
- /* Enable Rx interrupt. */\r
- this_spi->hw_reg_bit->CTRL_RX_INT_EN = 1U;\r
- NVIC_EnableIRQ( this_spi->irqn );\r
-}\r
-\r
-/***************************************************************************//**\r
- * MSS_SPI_set_slave_tx_frame()\r
- * See "mss_spi.h" for details of how to use this function.\r
- */\r
-void MSS_SPI_set_slave_tx_frame\r
-(\r
- mss_spi_instance_t * this_spi,\r
- uint32_t frame_value\r
-)\r
-{\r
- ASSERT( (this_spi == &g_mss_spi0) || (this_spi == &g_mss_spi1) );\r
-\r
- /* This function is only intended to be used with an SPI slave. */\r
- ASSERT( this_spi->hw_reg_bit->CTRL_MASTER == MSS_SPI_MODE_SLAVE );\r
- \r
- /* Disable slave block tx buffer as it is mutually exclusive with frame\r
- * level handling. */ \r
- this_spi->slave_tx_buffer = 0U;\r
- this_spi->slave_tx_size = 0U;\r
- this_spi->slave_tx_idx = 0U;\r
- \r
- /* Keep a copy of the slave tx frame value. */\r
- this_spi->slave_tx_frame = frame_value;\r
- \r
- /* Load frame into Tx data register. */\r
- this_spi->hw_reg->TX_DATA = this_spi->slave_tx_frame;\r
- \r
- /* Enable Tx Done interrupt in order to reload the slave Tx frame after each\r
- * time it has been sent. */\r
- this_spi->hw_reg_bit->CTRL_TX_INT_EN = 1U;\r
- NVIC_EnableIRQ( this_spi->irqn );\r
-}\r
-\r
-/***************************************************************************//**\r
- * MSS_SPI_set_slave_block_buffers()\r
- * See "mss_spi.h" for details of how to use this function.\r
- */\r
-void MSS_SPI_set_slave_block_buffers\r
-(\r
- mss_spi_instance_t * this_spi,\r
- const uint8_t * tx_buffer,\r
- uint32_t tx_buff_size,\r
- uint8_t * rx_buffer,\r
- uint32_t rx_buff_size,\r
- mss_spi_block_rx_handler_t block_rx_handler\r
-)\r
-{\r
- uint32_t frame_count;\r
- \r
- ASSERT( (this_spi == &g_mss_spi0) || (this_spi == &g_mss_spi1) );\r
- \r
- /* This function is only intended to be used with an SPI slave. */\r
- ASSERT( this_spi->hw_reg_bit->CTRL_MASTER == MSS_SPI_MODE_SLAVE );\r
- \r
- /* Disable Rx frame handler as it is mutually exclusive with block rx handler. */\r
- this_spi->frame_rx_handler = 0U;\r
- \r
- /* Keep a copy of the pointer to the block rx handler function. */\r
- this_spi->block_rx_handler = block_rx_handler;\r
- \r
- this_spi->slave_rx_buffer = rx_buffer;\r
- this_spi->slave_rx_size = rx_buff_size;\r
- this_spi->slave_rx_idx = 0U;\r
- \r
- /**/\r
- this_spi->slave_tx_buffer = tx_buffer;\r
- this_spi->slave_tx_size = tx_buff_size;\r
- this_spi->slave_tx_idx = 0U;\r
-\r
- frame_count = rx_buff_size;\r
- \r
- /**/\r
- this_spi->hw_reg_bit->CTRL_ENABLE = 0U;\r
- this_spi->hw_reg->CONTROL = (this_spi->hw_reg->CONTROL & ~TXRXDFCOUNT_MASK) | (frame_count << TXRXDFCOUNT_SHIFT);\r
- this_spi->hw_reg->TXRXDF_SIZE = 8U;\r
- this_spi->hw_reg_bit->CTRL_ENABLE = 1U;\r
- \r
- /* Load the transmit FIFO. */\r
- while ( !(this_spi->hw_reg_bit->STATUS_TX_FIFO_FULL) && ( this_spi->slave_tx_idx < this_spi->slave_tx_size ) )\r
- {\r
- this_spi->hw_reg->TX_DATA = this_spi->slave_tx_buffer[this_spi->slave_tx_idx];\r
- ++this_spi->slave_tx_idx;\r
- }\r
- \r
- /* Enable Rx interrupt. */\r
- this_spi->hw_reg_bit->CTRL_RX_INT_EN = 1U;\r
- NVIC_EnableIRQ( this_spi->irqn );\r
-}\r
-\r
-/***************************************************************************//**\r
- * SPI interrupt service routine.\r
- */\r
-static void mss_spi_isr\r
-(\r
- mss_spi_instance_t * this_spi\r
-)\r
-{\r
- uint32_t rx_frame;\r
- \r
- ASSERT( (this_spi == &g_mss_spi0) || (this_spi == &g_mss_spi1) );\r
- \r
- if ( this_spi->hw_reg_bit->MIS_RX_RDY )\r
- {\r
- while( !this_spi->hw_reg_bit->STATUS_RX_FIFO_EMPTY )\r
- {\r
- rx_frame = this_spi->hw_reg->RX_DATA;\r
- if ( this_spi->frame_rx_handler != 0U )\r
- {\r
- /* Single frame handling mode. */\r
- this_spi->frame_rx_handler( rx_frame );\r
- }\r
- else \r
- {\r
- if ( this_spi->block_rx_handler != 0U )\r
- {\r
- /* Block handling mode. */\r
- if ( this_spi->slave_rx_idx < this_spi->slave_rx_size )\r
- {\r
- this_spi->slave_rx_buffer[this_spi->slave_rx_idx] = (uint8_t)rx_frame;\r
- ++this_spi->slave_rx_idx;\r
- if ( this_spi->slave_rx_idx == this_spi->slave_rx_size )\r
- {\r
- (*this_spi->block_rx_handler)( this_spi->slave_rx_buffer, this_spi->slave_rx_size );\r
- }\r
- }\r
- }\r
- }\r
- \r
- /* Feed transmit FIFO. */\r
- if ( !(this_spi->hw_reg_bit->STATUS_TX_FIFO_FULL) && ( this_spi->slave_tx_idx < this_spi->slave_tx_size ) )\r
- {\r
- this_spi->hw_reg->TX_DATA = this_spi->slave_tx_buffer[this_spi->slave_tx_idx];\r
- ++this_spi->slave_tx_idx;\r
- }\r
- }\r
- this_spi->hw_reg_bit->INT_CLEAR_RX_RDY = 1U;\r
- }\r
- \r
- if ( this_spi->hw_reg_bit->MIS_TX_DONE )\r
- {\r
- if ( this_spi->slave_tx_buffer != 0U )\r
- {\r
- this_spi->hw_reg->TX_DATA = this_spi->slave_tx_buffer[this_spi->slave_tx_idx];\r
- ++this_spi->slave_tx_idx;\r
- if ( this_spi->slave_tx_idx >= this_spi->slave_tx_size )\r
- {\r
- this_spi->slave_tx_idx = 0U;\r
- }\r
- }\r
- else\r
- {\r
- /* Reload slave tx frame into Tx data register. */\r
- this_spi->hw_reg->TX_DATA = this_spi->slave_tx_frame;\r
- }\r
- }\r
-}\r
-\r
-/***************************************************************************//**\r
- * SPIO interrupt service routine.\r
- * Please note that the name of this ISR is defined as part of the SmartFusion\r
- * CMSIS startup code.\r
- */\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void SPI0_IRQHandler( void )\r
-#else\r
-void SPI0_IRQHandler( void )\r
-#endif\r
-{\r
- mss_spi_isr( &g_mss_spi0 );\r
- NVIC_ClearPendingIRQ( SPI0_IRQn );\r
-}\r
-\r
-/***************************************************************************//**\r
- * SPI1 interrupt service routine.\r
- * Please note that the name of this ISR is defined as part of the SmartFusion\r
- * CMSIS startup code.\r
- */\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void SPI1_IRQHandler( void )\r
-#else\r
-void SPI1_IRQHandler( void )\r
-#endif\r
-{\r
- mss_spi_isr( &g_mss_spi1 );\r
- NVIC_ClearPendingIRQ( SPI1_IRQn );\r
-}\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
+++ /dev/null
-/***************************************************************************//**\r
- * (c) Copyright 2008 Actel Corporation. All rights reserved.\r
- * \r
- * SmartFusion microcontroller subsystem SPI bare metal software driver public API.\r
- *\r
- * The microcontroller subsystem SPI driver provides functions for implementing\r
- * SPI master or SPI slave operations. These operations can be one of two\r
- * classes: SPI frame operation or block transfer operations.\r
- * Frame operations allow transferring SPI frames from 4 to 32 bits long. Block\r
- * operations allow transferring blocks of data organized as 8 bit bytes. \r
- *\r
- * SVN $Revision: 2189 $\r
- * SVN $Date: 2010-02-16 22:02:32 +0000 (Tue, 16 Feb 2010) $\r
- */\r
-/*=========================================================================*//**\r
- @mainpage SmartFusion MSS SPI Bare Metal Driver.\r
-\r
- @section intro_sec Introduction\r
- The SmartFusion\99 microcontroller subsystem (MSS) includes two serial\r
- peripheral interface SPI peripherals for serial communication. This driver\r
- provides a set of functions for controlling the MSS SPIs as part of a bare\r
- metal system where no operating system is available. These drivers can be\r
- adapted for use as part of an operating system, but the implementation of the\r
- adaptation layer between this driver and the operating system's driver model\r
- is outside the scope of this driver.\r
- \r
- @section hw_dependencies Hardware Flow Dependencies\r
- The configuration of all features of the MSS SPIs is covered by this driver\r
- with the exception of the SmartFusion IOMUX configuration. SmartFusion allows\r
- multiple non-concurrent uses of some external pins through IOMUX configuration.\r
- This feature allows optimization of external pin usage by assigning external\r
- pins for use by either the microcontroller subsystem or the FPGA fabric. The\r
- MSS SPIs serial signals are routed through IOMUXes to the SmartFusion device\r
- external pins. These IOMUXes are automatically configured correctly by the MSS\r
- configurator tool in the hardware flow when the MSS SPIs are enabled in that\r
- tool. You must ensure that the MSS SPIs are enabled by the MSS configurator\r
- tool in the hardware flow; otherwise the serial inputs and outputs will not be\r
- connected to the chip's external pins. For more information on IOMUX, refer to\r
- the IOMUX section of the SmartFusion Datasheet.\r
- The base address, register addresses and interrupt number assignment for the\r
- MSS SPI blocks are defined as constants in the SmartFusion CMSIS-PAL. You must\r
- ensure that the SmartFusion CMSIS-PAL is either included in the software tool\r
- chain used to build your project or is included in your project.\r
- \r
- @section theory_op Theory of Operation\r
- The MSS SPI driver functions are grouped into the following categories:\r
- \95 Initialization\r
- \95 Configuration for either master or slave operations\r
- \95 SPI master frame transfer control\r
- \95 SPI master block transfer control\r
- \95 SPI slave frame transfer control\r
- \95 SPI slave block transfer control\r
- \95 DMA block transfer\r
- Frame transfers allow the MSS SPI to write or read up to 32 bits of data in a\r
- SPI transaction. For example, a frame transfer of 12 bits might be used to\r
- read the result of an ADC conversion from a SPI analog to digital converter.\r
- Block transfers allow the MSS SPI to write or read a number of bytes in a SPI\r
- transaction. Block transfer transactions allow data transfers in multiples of\r
- 8 bits (8, 16, 24, 32, 40\85). Block transfers are typically used with byte\r
- oriented devices like SPI FLASH devices.\r
-\r
- Initialization \r
- The MSS SPI driver is initialized through a call to the MSS_SPI_init()\r
- function. The MSS_SPI_init() function takes only one parameter, a pointer\r
- to one of two global data structures used by the driver to store state\r
- information for each MSS SPI. A pointer to these data structures is also\r
- used as first parameter to any of the driver functions to identify which MSS\r
- SPI will be used by the called function. The names of these two data\r
- structures are g_mss_spi0 and g_mss_spi1. Therefore any call to an MSS SPI\r
- driver function should be of the form MSS_SPI_function_name( &g_mss_spi0, ... )\r
- or MSS_SPI_function_name( &g_mss_spi1, ... ).\r
- The MSS_SPI_init() function resets the specified MSS SPI hardware block and\r
- clears any pending interrupts from that MSS SPI in the Cortex-M3 NVIC.\r
- The MSS_SPI_init() function must be called before any other MSS SPI driver\r
- functions can be called.\r
-\r
- Configuration\r
- A MSS SPI block can operate either as a master or slave SPI device. There\r
- are two distinct functions for configuring a MSS SPI block for master or\r
- slave operations.\r
-\r
- Master configuration\r
- The MSS_SPI_configure_master_mode() function configures the specified MSS\r
- SPI block for operations as a SPI master. It must be called once for each\r
- remote SPI slave device the MSS SPI block will communicate with. It is used\r
- to provide the following information about each SPI slave\92s communication\r
- characteristics:\r
- \95 The SPI protocol mode\r
- \95 The SPI clock speed\r
- \95 The frame bit length\r
- This information is held by the driver and will be used to alter the\r
- configuration of the MSS SPI block each time a slave is selected through a\r
- call to MSS_SPI_set_slave_select(). The SPI protocol mode defines the\r
- initial state of the clock signal at the start of a transaction and which\r
- clock edge will be used to sample the data signal, or it defines whether the\r
- SPI block will operate in TI synchronous serial mode or in NSC MICROWIRE mode.\r
-\r
- Slave configuration\r
- The MSS_SPI_configure_slave_mode() function configures the specified MSS SPI\r
- block for operations as a SPI slave. It configures the following SPI\r
- communication characteristics:\r
- \95 The SPI protocol mode \r
- \95 The SPI clock speed\r
- \95 The frame bit length\r
- The SPI protocol mode defines the initial state of the clock signal at the\r
- start of a transaction and which clock edge will be used to sample the data\r
- signal, or it defines whether the SPI block will operate in TI synchronous\r
- serial mode or in NSC MICROWIRE mode.\r
-\r
- SPI master frame transfer control\r
- The following functions are used as part of SPI master frame transfers:\r
- \95 MSS_SPI_set_slave_select()\r
- \95 MSS_SPI_transfer_frame()\r
- \95 MSS_SPI_clear_slave_select()\r
- The master must first select the target slave through a call to\r
- MSS_SPI_set_slave_select(). This causes the relevant slave select line to\r
- become asserted while data is clocked out onto the SPI data line.\r
- A call to is then made to function MSS_SPI_transfer_frame() specifying and\r
- the value of the data frame to be sent.\r
- The function MSS_SPI_clear_slave_select() can be used after the transfer is\r
- complete to prevent this slave select line from being asserted during\r
- subsequent SPI transactions. A call to this function is only required if the\r
- master is communicating with multiple slave devices.\r
-\r
- SPI master block transfer control\r
- The following functions are used as part of SPI master block transfers:\r
- \95 MSS_SPI_set_slave_select()\r
- \95 MSS_SPI_clear_slave_select()\r
- \95 MSS_SPI_transfer_block()\r
- The master must first select the target slave through a call to\r
- MSS_SPI_set_slave_select(). This causes the relevant slave select line to\r
- become asserted while data is clocked out onto the SPI data line.\r
- Alternatively a GPIO can be used to control the state of the target slave\r
- device\92s chip select signal.\r
- A call to is then made to function MSS_SPI_transfer_block (). The\r
- parameters of this function specify:\r
- \95 the number of bytes to be transmitted\r
- \95 a pointer to the buffer containing the data to be transmitted\r
- \95 the number of bytes to be received\r
- \95 a pointer to the buffer where received data will be stored\r
- The number of bytes to be transmitted can be set to zero to indicate that\r
- the transfer is purely a block read transfer. The number of bytes to be\r
- received can be set to zero to specify that the transfer is purely a block\r
- write transfer.\r
- The function MSS_SPI_clear_slave_select() can be used after the transfer is\r
- complete to prevent this slave select line from being asserted during\r
- subsequent SPI transactions. A call to this function is only required if the\r
- master is communicating with multiple slave devices.\r
- \r
- SPI slave frame transfer control\r
- The following functions are used as part of SPI slave frame transfers:\r
- \95 MSS_SPI_set_slave_tx_frame()\r
- \95 MSS_SPI_set_frame_rx_handler()\r
- The MSS_SPI_set_slave_tx_frame() function specifies the frame data that will\r
- be returned to the SPI master. The frame data specified through this\r
- function is the value that will be read over the SPI bus by the remote SPI\r
- master when it initiates a transaction. A call to MSS_SPI_set_slave_tx_frame()\r
- is only required if the MSS SPI slave is the target of SPI read transactions,\r
- i.e. if data is meant to be read from the SmartFusion device over SPI.\r
- The MSS_SPI_set_frame_rx_handler() function specifies the receive handler\r
- function that will called when a frame of data has been received by the MSS\r
- SPI when it is configured as a slave. The receive handler function specified\r
- through this call will process the frame data written, over the SPI bus, to\r
- the MSS SPI slave by the remote SPI master. The receive handler function must\r
- be implemented as part of the application. It is only required if the MSS SPI\r
- slave is the target of SPI frame write transactions.\r
-\r
- SPI slave block transfer control\r
- The following functions are used as part of SPI slave block transfers:\r
- \95 MSS_SPI_set_slave_block_buffers()\r
- The MSS_SPI_set_slave_block_buffers() function is used to configure a MSS SPI\r
- slave for block transfer operations. It specifies:\r
- \95 The buffer containing the data that will be returned to the remote SPI master\r
- \95 The buffer where data received from the remote SPI master will be stored\r
- \95 The handler function that will be called after the receive buffer is filled\r
-\r
- DMA block transfer control\r
- The following functions are used as part of MSS SPI DMA transfers:\r
- \95 MSS_SPI_disable()\r
- \95 MSS_SPI_set_transfer_byte_count()\r
- \95 MSS_SPI_enable()\r
- \95 MSS_SPI_tx_done()\r
- The MSS SPI must first be disabled through a call to function MSS_SPI_disable().\r
- The number of bytes to be transferred is then set through a call to function\r
- MSS_SPI_set_transfer_byte_count(). The DMA transfer is then initiated by a call\r
- to the MSS_PDMA_start() function provided by the MSS PDMA driver. The actual\r
- DMA transfer will only start once the MSS SPI block has been re-enabled through\r
- a call to MSS_SPI_enable(). The completion of the DMA driven SPI transfer can\r
- be detected through a call to MSS_SPI_tx_done(). The direction of the SPI\r
- transfer, write or read, depends on the DMA channel configuration. A SPI write\r
- transfer occurs when the DMA channel is configured to write data to the MSS SPI\r
- block. A SPI read transfer occurs when the DMA channel is configured to read data\r
- from the MSS SPI block.\r
-\r
- *//*=========================================================================*/\r
-#ifndef MSS_SPI_H_\r
-#define MSS_SPI_H_\r
-\r
-#include "../../CMSIS/a2fxxxm3.h"\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif \r
-\r
-/***************************************************************************//**\r
- This defines the function prototype that must be followed by MSS SPI slave\r
- frame receive handler functions. These functions are registered with the MSS\r
- SPI driver through the MSS_SPI_set_frame_rx_handler () function.\r
- \r
- Declaring and Implementing Slave Frame Receive Handler Functions:\r
- Slave frame receive handler functions should follow the following prototype:\r
- void slave_frame_receive_handler ( uint32_t rx_frame );\r
- The actual name of the receive handler is unimportant. You can use any name\r
- of your choice for the receive frame handler. The rx_frame parameter will\r
- contain the value of the received frame.\r
- */\r
-typedef void (*mss_spi_frame_rx_handler_t)( uint32_t rx_frame );\r
-\r
-/***************************************************************************//**\r
- This defines the function prototype that must be followed by MSS SPI slave\r
- block receive handler functions. These functions are registered with the MSS\r
- SPI driver through the MSS_SPI_set_slave_block_buffers() function.\r
- \r
- Declaring and Implementing Slave Block Receive Handler Functions\r
- Slave block receive handler functions should follow the following prototype:\r
- void mss_spi_block_rx_handler ( uint8_t * rx_buff, uint16_t rx_size );\r
- The actual name of the receive handler is unimportant. You can use any name\r
- of your choice for the receive frame handler. The rx_buff parameter will\r
- contain a pointer to the start of the received block. The rx_size parameter\r
- will contain the number of bytes of the received block.\r
-\r
- */\r
-typedef void (*mss_spi_block_rx_handler_t)( uint8_t * rx_buff, uint32_t rx_size );\r
-\r
-/***************************************************************************//**\r
- This enumeration is used to define the settings for the SPI protocol mode\r
- bits, CPHA and CPOL. It is used as a parameter to the MSS_SPI_configure_master_mode()\r
- and MSS_SPI_configure_slave_mode() functions.\r
- \r
- - MSS_SPI_MODE0:\r
- Clock starts low, data read on clock's rising edge, data changes on\r
- falling edge.\r
- \r
- - MSS_SPI_MODE1:\r
- Clock starts low, data read on clock's falling edge, data changes on\r
- rising edge.\r
- \r
- - MSS_SPI_MODE2:\r
- Clock starts high, data read on clock's falling edge, data changes on\r
- rising edge.\r
- \r
- - MSS_SPI_MODE3:\r
- Clock starts high, data read on clock's rising edge, data changes on\r
- falling edge.\r
- \r
- - MSS_TI_MODE: \r
- TI syncronous serial mode. Slave select is pulsed at start of transfer.\r
- \r
- - MSS_NSC_MODE:\r
- NSC Microwire mode.\r
- */\r
-typedef enum __mss_spi_protocol_mode_t\r
-{\r
- MSS_SPI_MODE0 = 0x00000000,\r
- MSS_SPI_TI_MODE = 0x00000004,\r
- MSS_SPI_NSC_MODE = 0x00000008,\r
- MSS_SPI_MODE2 = 0x01000000,\r
- MSS_SPI_MODE1 = 0x02000000,\r
- MSS_SPI_MODE3 = 0x03000000\r
-} mss_spi_protocol_mode_t;\r
-\r
-/***************************************************************************//**\r
- This enumeration specifies the divider to be applied to the the APB bus clock\r
- in order to generate the SPI clock. It is used as parameter to the\r
- MSS_SPI_configure_master_mode() and MSS_SPI_configure_slave_mode()functions.\r
- */\r
- typedef enum __mss_spi_pclk_div_t\r
- {\r
- MSS_SPI_PCLK_DIV_2 = 0,\r
- MSS_SPI_PCLK_DIV_4 = 1,\r
- MSS_SPI_PCLK_DIV_8 = 2,\r
- MSS_SPI_PCLK_DIV_16 = 3,\r
- MSS_SPI_PCLK_DIV_32 = 4,\r
- MSS_SPI_PCLK_DIV_64 = 5,\r
- MSS_SPI_PCLK_DIV_128 = 6,\r
- MSS_SPI_PCLK_DIV_256 = 7\r
-} mss_spi_pclk_div_t;\r
-\r
-/***************************************************************************//**\r
- This enumeration is used to select a specific SPI slave device (0 to 7). It is\r
- used as a parameter to the MSS_SPI_configure_master_mode(),\r
- MSS_SPI_set_slave_select() and MSS_SPI_clear_slave_select () functions.\r
- */\r
- typedef enum __mss_spi_slave_t\r
- {\r
- MSS_SPI_SLAVE_0 = 0,\r
- MSS_SPI_SLAVE_1 = 1,\r
- MSS_SPI_SLAVE_2 = 2,\r
- MSS_SPI_SLAVE_3 = 3,\r
- MSS_SPI_SLAVE_4 = 4,\r
- MSS_SPI_SLAVE_5 = 5,\r
- MSS_SPI_SLAVE_6 = 6,\r
- MSS_SPI_SLAVE_7 = 7,\r
- MSS_SPI_MAX_NB_OF_SLAVES = 8\r
-} mss_spi_slave_t;\r
-\r
-/***************************************************************************//**\r
- This constant defines a frame size of 8 bits when configuring an MSS SPI to\r
- perform block transfer data transactions.\r
- It must be used as the value for the frame_bit_length parameter of function\r
- MSS_SPI_configure_master_mode() when performing block transfers between the\r
- MSS SPI master and the target SPI slave.\r
- It must also be used as the value for the frame_bit_length parameter of\r
- function MSS_SPI_configure_slave_mode() when performing block transfers\r
- between the MSS SPI slave and the remote SPI master.\r
- */\r
-#define MSS_SPI_BLOCK_TRANSFER_FRAME_SIZE 8\r
-\r
-/***************************************************************************//**\r
- The mss_spi_slave_cfg_t holds the MSS SPI configuration that must be used to\r
- communicate with a specific SPI slave.\r
- */\r
-typedef struct __mss_spi_slave_cfg_t\r
-{\r
- uint32_t ctrl_reg;\r
- uint8_t txrxdf_size_reg;\r
- uint8_t clk_gen;\r
-} mss_spi_slave_cfg_t;\r
-\r
-/***************************************************************************//**\r
- There is one instance of this structure for each of the microcontroller\r
- subsystem's SPIs. Instances of this structure are used to identify a specific\r
- SPI. A pointer to an instance of the mss_spi_instance_t structure is passed as\r
- the first parameter to MSS SPI driver functions to identify which SPI should\r
- perform the requested operation.\r
- */\r
-typedef struct __mss_spi_instance_t\r
-{\r
- /* CMSIS related defines identifying the SPI hardware. */\r
- SPI_TypeDef * hw_reg; /*!< Pointer to SPI registers. */\r
- SPI_BitBand_TypeDef * hw_reg_bit; /*!< Pointer to SPI registers bit band area. */\r
- IRQn_Type irqn; /*!< SPI's Cortex-M3 NVIC interrupt number. */\r
- \r
- /* Internal transmit state: */\r
- const uint8_t * slave_tx_buffer; /*!< Pointer to slave transmit buffer. */\r
- uint32_t slave_tx_size; /*!< Size of slave transmit buffer. */\r
- uint32_t slave_tx_idx; /*!< Current index into slave transmit buffer. */\r
- \r
- /* Internal receive state: */\r
- uint8_t * slave_rx_buffer; /*!< Pointer to buffer where data received by a slave will be stored. */\r
- uint32_t slave_rx_size; /*!< Slave receive buffer size. */\r
- uint32_t slave_rx_idx; /*!< Current index into slave receive buffer. */\r
- \r
- /* Configuration for each target slave. */\r
- mss_spi_slave_cfg_t slaves_cfg[MSS_SPI_MAX_NB_OF_SLAVES];\r
- \r
- /** Slave received frame handler: */\r
- mss_spi_frame_rx_handler_t frame_rx_handler; /*!< Pointer to function that will be called when a frame is received when the SPI block is configured as slave. */\r
- \r
- uint32_t slave_tx_frame; /*!< Value of the data frame that will be transmited when the SPI block is configured as slave. */\r
- \r
- /* Slave block rx handler: */\r
- mss_spi_block_rx_handler_t block_rx_handler; /*!< Pointer to the function that will be called when a data block has been received. */\r
-\r
-} mss_spi_instance_t;\r
-\r
-/***************************************************************************//**\r
- This instance of mss_spi_instance_t holds all data related to the operations\r
- performed by MSS SPI 0. A pointer to g_mss_spi0 is passed as the first\r
- parameter to MSS SPI driver functions to indicate that MSS SPI 0 should\r
- perform the requested operation.\r
- */\r
-extern mss_spi_instance_t g_mss_spi0;\r
-\r
-/***************************************************************************//**\r
- This instance of mss_spi_instance_t holds all data related to the operations\r
- performed by MSS SPI 1. A pointer to g_mss_spi1 is passed as the first\r
- parameter to MSS SPI driver functions to indicate that MSS SPI 1 should\r
- perform the requested operation.\r
- */\r
-extern mss_spi_instance_t g_mss_spi1;\r
-\r
-/***************************************************************************//**\r
- The MSS_SPI_init() function initializes and hardware and data structures of\r
- one of the SmartFusion MSS SPIs. The MSS_SPI_init() function must be called\r
- before any other MSS SPI driver functions can be called.\r
- \r
- @param this_spi\r
- The this_spi parameter is a pointer to an mss_spi_instance_t structure\r
- identifying the MSS SPI hardware block to be initialized. There are two such\r
- data structures, g_mss_spi0 and g_mss_spi1, associated with MSS SPI 0 and\r
- MSS SPI 1 respectively. This parameter must point to either the g_mss_spi0\r
- or g_mss_spi1 global data structure defined within the SPI driver.\r
- \r
- Example:\r
- @code\r
- MSS_SPI_init( &g_mss_spi0 );\r
- @endcode\r
- */\r
-void MSS_SPI_init\r
-(\r
- mss_spi_instance_t * this_spi\r
-);\r
-\r
-/***************************************************************************//**\r
- The MSS_SPI_configure_slave_mode() function configure a MSS SPI block for\r
- operations as a slave SPI device. It configures the SPI hardware with the\r
- selected SPI protocol mode and clock speed.\r
- \r
- @param this_spi\r
- The this_spi parameter is a pointer to an mss_spi_instance_t structure\r
- identifying the MSS SPI hardware block to be initialized. There are two such\r
- data structures, g_mss_spi0 and g_mss_spi1, associated with MSS SPI 0 and\r
- MSS SPI 1 respectively. This parameter must point to either the g_mss_spi0\r
- or g_mss_spi1 global data structure defined within the SPI driver.\r
- \r
- @param protocol_mode\r
- Serial peripheral interface operating mode. Allowed values are:\r
- - MSS_SPI_MODE0\r
- - MSS_SPI_MODE1\r
- - MSS_SPI_MODE2\r
- - MSS_SPI_MODE3\r
- - MSS_TI_MODE\r
- - MSS_NSC_MODE\r
- \r
- @param clk_rate\r
- Divider value used to generate serial interface clock signal from PCLK.\r
- Allowed values are:\r
- - MSS_SPI_PCLK_DIV_2\r
- - MSS_SPI_PCLK_DIV_4\r
- - MSS_SPI_PCLK_DIV_8\r
- - MSS_SPI_PCLK_DIV_16\r
- - MSS_SPI_PCLK_DIV_32\r
- - MSS_SPI_PCLK_DIV_64\r
- - MSS_SPI_PCLK_DIV_128\r
- - MSS_SPI_PCLK_DIV_256\r
- \r
- @param frame_bit_length\r
- Number of bits making up the frame. The maximum frame length is 32 bits. You\r
- must use the MSS_SPI_BLOCK_TRANSFER_FRAME_SIZE constant as the value for\r
- frame_bit_length when configuring the MSS SPI master for block transfer\r
- transactions with the target SPI slave.\r
- \r
- Example:\r
- @code\r
- MSS_SPI_init( &g_mss_spi0 );\r
- MSS_SPI_configure_slave_mode\r
- (\r
- &g_mss_spi0,\r
- MSS_SPI_MODE2,\r
- MSS_SPI_PCLK_DIV_64,\r
- MSS_SPI_BLOCK_TRANSFER_FRAME_SIZE\r
- );\r
- @endcode\r
- \r
- */ \r
-void MSS_SPI_configure_slave_mode\r
-(\r
- mss_spi_instance_t * this_spi,\r
- mss_spi_protocol_mode_t protocol_mode,\r
- mss_spi_pclk_div_t clk_rate,\r
- uint8_t frame_bit_length\r
-);\r
-\r
-/***************************************************************************//**\r
- The MSS_SPI_configure_master_mode() function configures the protocol mode,\r
- serial clock speed and frame size for a specific target SPI slave device. It\r
- is used when the MSS SPI hardware block is used as a SPI master. This function\r
- must be called once for each target SPI slave the SPI master is going to\r
- communicate with. The SPI master hardware will be configured with the\r
- configuration specified by this function during calls to\r
- MSS_SPI_set_slave_select().\r
- \r
- @param this_spi\r
- The this_spi parameter is a pointer to an mss_spi_instance_t structure\r
- identifying the MSS SPI hardware block to be initialized. There are two such\r
- data structures, g_mss_spi0 and g_mss_spi1, associated with MSS SPI 0 and\r
- MSS SPI 1 respectively. This parameter must point to either the g_mss_spi0\r
- or g_mss_spi1 global data structure defined within the SPI driver.\r
- \r
- \r
- @param slave\r
- The slave parameter is used to identify a target SPI slave. The driver will\r
- hold the MSS SPI master configuration required to communicate with this\r
- slave, as specified by the other function parameters. Allowed values are:\r
- \95 MSS_SPI_SLAVE_0\r
- \95 MSS_SPI_SLAVE_1\r
- \95 MSS_SPI_SLAVE_2\r
- \95 MSS_SPI_SLAVE_3\r
- \95 MSS_SPI_SLAVE_4\r
- \95 MSS_SPI_SLAVE_5\r
- \95 MSS_SPI_SLAVE_6\r
- \95 MSS_SPI_SLAVE_7\r
- \r
- @param protocol_mode\r
- Serial peripheral interface operating mode. Allowed values are:\r
- \95 MSS_SPI_MODE0\r
- \95 MSS_SPI_MODE1\r
- \95 MSS_SPI_MODE2\r
- \95 MSS_SPI_MODE3\r
- \95 MSS_SPI_TI_MODE\r
- \95 MSS_SPI_NSC_MODE\r
- \r
- @param clk_rate\r
- Divider value used to generate serial interface clock signal from PCLK.\r
- Allowed values are:\r
- \95 MSS_SPI_PCLK_DIV_2\r
- \95 MSS_SPI_PCLK_DIV_4\r
- \95 MSS_SPI_PCLK_DIV_8\r
- \95 MSS_SPI_PCLK_DIV_16\r
- \95 MSS_SPI_PCLK_DIV_32\r
- \95 MSS_SPI_PCLK_DIV_64\r
- \95 MSS_SPI_PCLK_DIV_128\r
- \95 MSS_SPI_PCLK_DIV_256\r
- \r
- @param frame_bit_length\r
- Number of bits making up the frame. The maximum frame length is 32 bits. You\r
- must use the MSS_SPI_BLOCK_TRANSFER_FRAME_SIZE constant as the value for\r
- frame_bit_length when configuring the MSS SPI master for block transfer\r
- transactions with the target SPI slave.\r
- \r
- Example:\r
- @code\r
- MSS_SPI_init( &g_mss_spi0 );\r
-\r
- MSS_SPI_configure_master_mode\r
- (\r
- &g_mss_spi0,\r
- MSS_SPI_SLAVE_0,\r
- MSS_SPI_MODE2,\r
- MSS_SPI_PCLK_DIV_64,\r
- 12\r
- );\r
-\r
- MSS_SPI_configure_master_mode\r
- (\r
- &g_mss_spi0,\r
- MSS_SPI_SLAVE_1,\r
- MSS_SPI_TI_MODE,\r
- MSS_SPI_PCLK_DIV_128,\r
- MSS_SPI_BLOCK_TRANSFER_FRAME_SIZE\r
- );\r
- @endcode\r
- */ \r
-void MSS_SPI_configure_master_mode\r
-(\r
- mss_spi_instance_t * this_spi,\r
- mss_spi_slave_t slave,\r
- mss_spi_protocol_mode_t protocol_mode,\r
- mss_spi_pclk_div_t clk_rate,\r
- uint8_t frame_bit_length\r
-);\r
-\r
-/*==============================================================================\r
- * Master functions\r
- *============================================================================*/\r
-\r
-/***************************************************************************//**\r
- The MSS_SPI_slave_select() function is used by a MSS SPI master to select a\r
- specific slave. This function causes the relevant slave select signal to be\r
- asserted.\r
- \r
- @param this_spi\r
- The this_spi parameter is a pointer to an mss_spi_instance_t structure\r
- identifying the MSS SPI hardware block to be initialized. There are two such\r
- data structures, g_mss_spi0 and g_mss_spi1, associated with MSS SPI 0 and\r
- MSS SPI 1 respectively. This parameter must point to either the g_mss_spi0\r
- or g_mss_spi1 global data structure defined within the SPI driver.\r
- \r
- \r
- @param slave\r
- The slave parameter is one of mss_spi_slave_t enumerated constants\r
- identifying a slave.\r
- \r
- Example:\r
- @code\r
- const uint8_t frame_size = 25;\r
- const uint32_t master_tx_frame = 0x0100A0E1;\r
-\r
- MSS_SPI_init( &g_mss_spi0 );\r
- MSS_SPI_configure_master_mode\r
- (\r
- &g_mss_spi0,\r
- MSS_SPI_SLAVE_0,\r
- MSS_SPI_MODE1,\r
- MSS_SPI_PCLK_DIV_256,\r
- frame_size\r
- );\r
-\r
- MSS_SPI_set_slave_select( &g_mss_spi0, MSS_SPI_SLAVE_0 );\r
- MSS_SPI_transfer_frame( &g_mss_spi0, master_tx_frame );\r
- MSS_SPI_clear_slave_select( &g_mss_spi0, MSS_SPI_SLAVE_0 );\r
- @endcode\r
- */\r
-void MSS_SPI_set_slave_select\r
-(\r
- mss_spi_instance_t * this_spi,\r
- mss_spi_slave_t slave\r
-);\r
-\r
-/***************************************************************************//**\r
- The MSS_SPI_clear_slave_select() function is used by a MSS SPI Master to\r
- deselect a specific slave. This function causes the relevant slave select\r
- signal to be de-asserted.\r
- \r
- @param this_spi\r
- The this_spi parameter is a pointer to an mss_spi_instance_t structure\r
- identifying the MSS SPI hardware block to be initialized. There are two such\r
- data structures, g_mss_spi0 and g_mss_spi1, associated with MSS SPI 0 and\r
- MSS SPI 1 respectively. This parameter must point to either the g_mss_spi0\r
- or g_mss_spi1 global data structure defined within the SPI driver.\r
- \r
- \r
- @param slave\r
- The slave parameter is one of mss_spi_slave_t enumerated constants\r
- identifying a slave.\r
- \r
- Example:\r
- @code\r
- const uint8_t frame_size = 25;\r
- const uint32_t master_tx_frame = 0x0100A0E1;\r
-\r
- MSS_SPI_init( &g_mss_spi0 );\r
- MSS_SPI_configure_master_mode\r
- (\r
- &g_mss_spi0,\r
- MSS_SPI_SLAVE_0,\r
- MSS_SPI_MODE1,\r
- MSS_SPI_PCLK_DIV_256,\r
- frame_size\r
- );\r
- MSS_SPI_set_slave_select( &g_mss_spi0, MSS_SPI_SLAVE_0 );\r
- MSS_SPI_transfer_frame( &g_mss_spi0, master_tx_frame );\r
- MSS_SPI_clear_slave_select( &g_mss_spi0, MSS_SPI_SLAVE_0 );\r
- @endcode\r
- */\r
-void MSS_SPI_clear_slave_select\r
-(\r
- mss_spi_instance_t * this_spi,\r
- mss_spi_slave_t slave\r
-);\r
-\r
-/***************************************************************************//**\r
- The MSS_SPI_disable() function is used to temporarily disable a MSS SPI\r
- hardware block. This function is typically used in conjunction with the\r
- SPI_set_transfer_byte_count() function to setup a DMA controlled SPI transmit\r
- transaction as the SPI_set_transfer_byte_count() function must only be used\r
- when the MSS SPI hardware is disabled.\r
- \r
- @param this_spi\r
- The this_spi parameter is a pointer to an mss_spi_instance_t structure\r
- identifying the MSS SPI hardware block to be initialized. There are two such\r
- data structures, g_mss_spi0 and g_mss_spi1, associated with MSS SPI 0 and\r
- MSS SPI 1 respectively. This parameter must point to either the g_mss_spi0\r
- or g_mss_spi1 global data structure defined within the SPI driver.\r
- \r
- Example:\r
- @code\r
- uint32_t transfer_size;\r
- uint8_t tx_buffer[8] = { 1, 2, 3, 4, 5, 6, 7, 8 };\r
- \r
- transfer_size = sizeof(tx_buffer);\r
- \r
- MSS_SPI_disable( &g_mss_spi0 );\r
- MSS_SPI_set_transfer_byte_count( &g_mss_spi0, transfer_size );\r
- PDMA_start\r
- (\r
- PDMA_CHANNEL_0,\r
- (uint32_t)tx_buffer,\r
- PDMA_SPI1_TX_REGISTER,\r
- transfer_size\r
- );\r
- MSS_SPI_enable( &g_mss_spi0 );\r
- \r
- while ( !MSS_SPI_tx_done( &g_mss_spi0 ) )\r
- {\r
- ;\r
- }\r
- @endcode\r
- */\r
-static __INLINE void MSS_SPI_disable\r
-(\r
- mss_spi_instance_t * this_spi\r
-)\r
-{\r
- this_spi->hw_reg_bit->CTRL_ENABLE = 0;\r
-}\r
-\r
-/***************************************************************************//**\r
- The MSS_SPI_enable() function is used to re-enable a MSS SPI hardware block\r
- after it was disabled using the SPI_disable() function.\r
- \r
- @param this_spi\r
- The this_spi parameter is a pointer to an mss_spi_instance_t structure\r
- identifying the MSS SPI hardware block to be initialized. There are two such\r
- data structures, g_mss_spi0 and g_mss_spi1, associated with MSS SPI 0 and\r
- MSS SPI 1 respectively. This parameter must point to either the g_mss_spi0\r
- or g_mss_spi1 global data structure defined within the SPI driver.\r
- \r
- Example:\r
- @code\r
- uint32_t transfer_size;\r
- uint8_t tx_buffer[8] = { 1, 2, 3, 4, 5, 6, 7, 8 };\r
- \r
- transfer_size = sizeof(tx_buffer);\r
- \r
- MSS_SPI_disable( &g_mss_spi0 );\r
- MSS_SPI_set_transfer_byte_count( &g_mss_spi0, transfer_size );\r
- PDMA_start\r
- (\r
- PDMA_CHANNEL_0,\r
- (uint32_t)tx_buffer,\r
- PDMA_SPI1_TX_REGISTER,\r
- transfer_size\r
- );\r
- MSS_SPI_enable( &g_mss_spi0 );\r
- \r
- while ( !MSS_SPI_tx_done( &g_mss_spi0 ) )\r
- {\r
- ;\r
- }\r
- @endcode\r
- */\r
-static __INLINE void MSS_SPI_enable\r
-(\r
- mss_spi_instance_t * this_spi\r
-)\r
-{\r
- this_spi->hw_reg_bit->CTRL_ENABLE = 1;\r
-}\r
-\r
-/***************************************************************************//**\r
- The MSS_SPI_set_transfer_byte_count() function is used as part of setting up\r
- a SPI transfer using DMA. It specifies the number of bytes that must be\r
- transferred before MSS_SPI_tx_done() indicates that the transfer is complete.\r
- \r
- @param this_spi\r
- The this_spi parameter is a pointer to an mss_spi_instance_t structure\r
- identifying the MSS SPI hardware block to be initialized. There are two such\r
- data structures, g_mss_spi0 and g_mss_spi1, associated with MSS SPI 0 and\r
- MSS SPI 1 respectively. This parameter must point to either the g_mss_spi0\r
- or g_mss_spi1 global data structure defined within the SPI driver.\r
- \r
- \r
- @param byte_count\r
- The byte_count parameter specifies the number of bytes that must be\r
- transferred by the SPI hardware block considering that a transaction has\r
- been completed.\r
- \r
- Example:\r
- @code\r
- uint32_t transfer_size;\r
- uint8_t tx_buffer[8] = { 1, 2, 3, 4, 5, 6, 7, 8 };\r
- \r
- transfer_size = sizeof(tx_buffer);\r
- \r
- MSS_SPI_disable( &g_mss_spi0 );\r
- \r
- MSS_SPI_set_transfer_byte_count( &g_mss_spi0, transfer_size );\r
- \r
- PDMA_start( PDMA_CHANNEL_0, (uint32_t)tx_buffer, 0x40011014, transfer_size );\r
- \r
- MSS_SPI_enable( &g_mss_spi0 );\r
- \r
- while ( !MSS_SPI_tx_done( &g_mss_spi0) )\r
- {\r
- ;\r
- }\r
- @endcode\r
- */\r
-static __INLINE void MSS_SPI_set_transfer_byte_count\r
-(\r
- mss_spi_instance_t * this_spi,\r
- uint16_t byte_count\r
-)\r
-{\r
- const uint32_t TXRXDFCOUNT_SHIFT = 8U;\r
- const uint32_t TXRXDFCOUNT_MASK = 0x00FFFF00U;\r
- \r
- this_spi->hw_reg->CONTROL = (this_spi->hw_reg->CONTROL & ~TXRXDFCOUNT_MASK) | ( (byte_count << TXRXDFCOUNT_SHIFT) & TXRXDFCOUNT_MASK);\r
- this_spi->hw_reg->TXRXDF_SIZE = 8U;\r
-}\r
-\r
-/***************************************************************************//**\r
- The MSS_SPI_tx_done() function is used to find out if a DMA controlled transfer\r
- has completed.\r
- \r
- @param this_spi\r
- The this_spi parameter is a pointer to an mss_spi_instance_t structure\r
- identifying the MSS SPI hardware block to be initialized. There are two such\r
- data structures, g_mss_spi0 and g_mss_spi1, associated with MSS SPI 0 and\r
- MSS SPI 1 respectively. This parameter must point to either the g_mss_spi0\r
- or g_mss_spi1 global data structure defined within the SPI driver.\r
- \r
- Example:\r
- @code\r
- uint32_t transfer_size;\r
- uint8_t tx_buffer[8] = { 1, 2, 3, 4, 5, 6, 7, 8 };\r
- \r
- transfer_size = sizeof(tx_buffer);\r
- \r
- MSS_SPI_disable( &g_mss_spi0 );\r
- \r
- MSS_SPI_set_transfer_byte_count( &g_mss_spi0, transfer_size );\r
- \r
- PDMA_start\r
- (\r
- PDMA_CHANNEL_0,\r
- (uint32_t)tx_buffer,\r
- PDMA_SPI1_TX_REGISTER,\r
- transfer_size\r
- );\r
- \r
- MSS_SPI_enable( &g_mss_spi0 );\r
- \r
- while ( !MSS_SPI_tx_done(&g_mss_spi0) )\r
- {\r
- ;\r
- }\r
- @endcode\r
- */\r
-static __INLINE uint32_t MSS_SPI_tx_done\r
-(\r
- mss_spi_instance_t * this_spi\r
-)\r
-{\r
- return this_spi->hw_reg_bit->STATUS_TX_DONE;\r
-}\r
-\r
-/***************************************************************************//**\r
- The MSS_SPI_transfer_frame() function is used by a MSS SPI master to transmit\r
- and receive a frame up to 32 bits long. This function is typically used for\r
- transactions with a SPI slave where the number of transmit and receive bits is\r
- not divisible by 8.\r
- \r
- @param this_spi\r
- The this_spi parameter is a pointer to an mss_spi_instance_t structure\r
- identifying the MSS SPI hardware block to be initialized. There are two such\r
- data structures, g_mss_spi0 and g_mss_spi1, associated with MSS SPI 0 and\r
- MSS SPI 1 respectively. This parameter must point to either the g_mss_spi0\r
- or g_mss_spi1 global data structure defined within the SPI driver.\r
- \r
- \r
- @param tx_bits\r
- The tx_bits parameter is a 32 bits word containing the value that will be\r
- transmitted.\r
- Note: The bit length of the value to be transmitted to the slave must be\r
- specified as the frame_bit_length parameter in a previous call to\r
- the MSS_SPI_configure_master() function.\r
-\r
- @return\r
- This function returns a 32 bits word containing the value that is received\r
- from the slave.\r
- \r
- Example:\r
- @code\r
- const uint8_t frame_size = 25;\r
- const uint32_t master_tx_frame = 0x0100A0E1;\r
- uint32_t master_rx;\r
- \r
- MSS_SPI_init( &g_mss_spi0 );\r
- MSS_SPI_configure_master_mode\r
- (\r
- &g_mss_spi0,\r
- MSS_SPI_SLAVE_0,\r
- MSS_SPI_MODE1,\r
- MSS_SPI_PCLK_DIV_256,\r
- frame_size\r
- );\r
- \r
- MSS_SPI_set_slave_select( &g_mss_spi0, MSS_SPI_SLAVE_0 );\r
- master_rx = MSS_SPI_transfer_frame( &g_mss_spi0, master_tx_frame );\r
- MSS_SPI_clear_slave_select( &g_mss_spi0, MSS_SPI_SLAVE_0 );\r
- @endcode\r
- */\r
-uint32_t MSS_SPI_transfer_frame\r
-(\r
- mss_spi_instance_t * this_spi,\r
- uint32_t tx_bits\r
-);\r
-\r
-/***************************************************************************//**\r
- The MSS_SPI_transfer_block() function is used by MSS SPI masters to transmit\r
- and receive blocks of data organized as a specified number of bytes. It can be\r
- used for:\r
- \95 Writing a data block to a slave\r
- \95 Reading a data block from a slave\r
- \95 Sending a command to a slave followed by reading the outcome of the\r
- command in a single SPI transaction. This function can be used alongside\r
- Peripheral DMA functions to perform the actual moving to and from the SPI\r
- hardware block using Peripheral DMA.\r
- \r
- @param this_spi\r
- The this_spi parameter is a pointer to an mss_spi_instance_t structure\r
- identifying the MSS SPI hardware block to be initialized. There are two such\r
- data structures, g_mss_spi0 and g_mss_spi1, associated with MSS SPI 0 and\r
- MSS SPI 1 respectively. This parameter must point to either the g_mss_spi0\r
- or g_mss_spi1 global data structure defined within the SPI driver.\r
- \r
- \r
- @param cmd_buffer\r
- The cmd_buffer parameter is a pointer to the buffer containing the data that\r
- will be sent by the master from the beginning of the transfer. This pointer\r
- can be null (0) if the master does not need to send a command before reading\r
- data or if the command part of the transfer is written to the SPI hardware\r
- block using DMA.\r
- \r
- @param cmd_byte_size\r
- The cmd_byte_size parameter specifies the number of bytes contained in\r
- cmd_buffer that will be sent. A value of 0 indicates that no data needs to\r
- be sent to the slave. A non-zero value while the cmd_buffer pointer is 0 is\r
- used to indicate that the command data will be written to the SPI hardware\r
- block using DMA.\r
- \r
- @param rd_buffer\r
- The rd_buffer parameter is a pointer to the buffer where the data received\r
- from the slave after the command has been sent will be stored.\r
- \r
- @param rd_byte_size\r
- The rd_byte_size parameter specifies the number of bytes to be received from\r
- the slave and stored in the rd_buffer. A value of 0 indicates that no data\r
- is to be read from the slave. A non-zero value while the rd_buffer pointer\r
- is null (0) is used to specify the receive size when using DMA to read from\r
- the slave. \r
- Note: All bytes received from the slave, including the bytes received\r
- while the command is sent, will be read through DMA.\r
- \r
- Polled write transfer example:\r
- @code\r
- uint8_t master_tx_buffer[MASTER_TX_BUFFER] = \r
- {\r
- 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A\r
- };\r
- MSS_SPI_init( &g_mss_spi0 );\r
- MSS_SPI_configure_master_mode\r
- (\r
- &g_mss_spi0,\r
- MSS_SPI_SLAVE_0,\r
- MSS_SPI_MODE1,\r
- MSS_SPI_PCLK_DIV_256,\r
- MSS_SPI_BLOCK_TRANSFER_FRAME_SIZE\r
- );\r
- \r
- MSS_SPI_set_slave_select( &g_mss_spi0, MSS_SPI_SLAVE_0 );\r
- MSS_SPI_transfer_block\r
- (\r
- &g_mss_spi0,\r
- master_tx_buffer,\r
- sizeof(master_tx_buffer),\r
- 0,\r
- 0\r
- );\r
- MSS_SPI_clear_slave_select( &g_mss_spi0, MSS_SPI_SLAVE_0 );\r
- @endcode\r
- \r
- DMA transfer example:\r
- In this example the transmit and receive buffers are not specified as part of\r
- the call to MSS_SPI_transfer_block(). MSS_SPI_transfer_block() will only\r
- prepare the MSS SPI hardware for a transfer. The MSS SPI transmit hardware\r
- FIFO is filled using one DMA channel and a second DMA channel is used to read\r
- the content of the MSS SPI receive hardware FIFO. The transmit and receive\r
- buffers are specified by two separate calls to PDMA_start() to initiate DMA\r
- transfers on the channel used for transmit data and the channel used for\r
- receive data. \r
- @code\r
- uint8_t master_tx_buffer[MASTER_RX_BUFFER] =\r
- {\r
- 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA\r
- };\r
- uint8_t slave_rx_buffer[MASTER_RX_BUFFER] = \r
- {\r
- 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A\r
- };\r
- MSS_SPI_init( &g_mss_spi0 );\r
-\r
- MSS_SPI_configure_master_mode\r
- (\r
- &g_mss_spi0,\r
- MSS_SPI_SLAVE_0,\r
- MSS_SPI_MODE1,\r
- MSS_SPI_PCLK_DIV_256,\r
- MSS_SPI_BLOCK_TRANSFER_FRAME_SIZE\r
- );\r
- MSS_SPI_set_slave_select( &g_mss_spi0, MSS_SPI_SLAVE_0 );\r
- MSS_SPI_transfer_block( &g_mss_spi0, 0, 0, 0, 0 );\r
- PDMA_start\r
- (\r
- PDMA_CHANNEL_1,\r
- PDMA_SPI0_RX_REGISTER,\r
- (uint32_t)master_rx_buffer,\r
- sizeof(master_rx_buffer)\r
- ); \r
- PDMA_start\r
- (\r
- PDMA_CHANNEL_2,\r
- (uint32_t)master_tx_buffer,\r
- PDMA_SPI0_TX_REGISTER,\r
- sizeof(master_tx_buffer)\r
- ); \r
- while( PDMA_status(PDMA_CHANNEL_1) == 0 )\r
- {\r
- ;\r
- }\r
- MSS_SPI_clear_slave_select( &g_mss_spi0, MSS_SPI_SLAVE_0 );\r
- @endcode\r
- */\r
-void MSS_SPI_transfer_block\r
-(\r
- mss_spi_instance_t * this_spi,\r
- const uint8_t * cmd_buffer,\r
- uint16_t cmd_byte_size,\r
- uint8_t * rd_buffer,\r
- uint16_t rd_byte_size\r
-);\r
-\r
-/*==============================================================================\r
- * Slave functions\r
- *============================================================================*/\r
-\r
-/***************************************************************************//**\r
- The MSS_SPI_set_frame_rx_handler() function is used by MSS SPI slaves to\r
- specify the receive handler function that will be called by the MSS SPI driver\r
- interrupt handler when a a frame of data is received by the MSS SPI slave.\r
- \r
- @param this_spi\r
- The this_spi parameter is a pointer to an mss_spi_instance_t structure\r
- identifying the MSS SPI hardware block to be initialized. There are two such\r
- data structures, g_mss_spi0 and g_mss_spi1, associated with MSS SPI 0 and\r
- MSS SPI 1 respectively. This parameter must point to either the g_mss_spi0\r
- or g_mss_spi1 global data structure defined within the SPI driver.\r
- \r
- \r
- @param rx_handler\r
- The rx_handler parameter is a pointer to the frame receive handler that must\r
- be called when a frame is received by the MSS SPI slave.\r
- \r
- Example:\r
- @code\r
- uint32_t g_slave_rx_frame = 0;\r
-\r
- void slave_frame_handler( uint32_t rx_frame )\r
- {\r
- g_slave_rx_frame = rx_frame;\r
- }\r
-\r
- int setup_slave( void )\r
- {\r
- const uint16_t frame_size = 25;\r
- MSS_SPI_init( &g_mss_spi1 );\r
- MSS_SPI_configure_slave_mode\r
- (\r
- &g_mss_spi0,\r
- MSS_SPI_MODE2,\r
- MSS_SPI_PCLK_DIV_64,\r
- frame_size\r
- );\r
- MSS_SPI_set_frame_rx_handler( &g_mss_spi1, slave_frame_handler );\r
- }\r
- @endcode\r
- */\r
-void MSS_SPI_set_frame_rx_handler\r
-(\r
- mss_spi_instance_t * this_spi,\r
- mss_spi_frame_rx_handler_t rx_handler\r
-);\r
-\r
-/***************************************************************************//**\r
- The MSS_SPI_set_slave_tx_frame() function is used by MSS SPI slaves to specify\r
- the frame that will be transmitted when a transaction is initiated by the SPI\r
- master.\r
- \r
- @param this_spi\r
- The this_spi parameter is a pointer to an mss_spi_instance_t structure\r
- identifying the MSS SPI hardware block to be initialized. There are two such\r
- data structures, g_mss_spi0 and g_mss_spi1, associated with MSS SPI 0 and\r
- MSS SPI 1 respectively. This parameter must point to either the g_mss_spi0\r
- or g_mss_spi1 global data structure defined within the SPI driver.\r
- \r
- \r
- @param frame_value\r
- The frame_value parameter contains the value of the frame to be sent to the\r
- master.\r
- Note: The bit length of the value to be transmitted to the master must be\r
- specified as the frame_bit_length parameter in a previous call to\r
- the MSS_SPI_configure_slave() function.\r
-\r
- Example:\r
- @code\r
- const uint16_t frame_size = 25;\r
- const uint32_t slave_tx_frame = 0x0110F761;\r
- uint32_t master_rx;\r
-\r
- MSS_SPI_init( &g_mss_spi1 );\r
- MSS_SPI_configure_slave_mode\r
- (\r
- &g_mss_spi0,\r
- MSS_SPI_MODE2,\r
- MSS_SPI_PCLK_DIV_64,\r
- frame_size\r
- );\r
- MSS_SPI_set_slave_tx_frame( &g_mss_spi1, slave_tx_frame );\r
- @endcode\r
- */\r
-void MSS_SPI_set_slave_tx_frame\r
-(\r
- mss_spi_instance_t * this_spi,\r
- uint32_t frame_value\r
-);\r
-\r
-/***************************************************************************//**\r
- The MSS_SPI_set_slave_block_buffers() function is used to configure an MSS\r
- SPI slave for block transfer operations. It specifies one or more of the\r
- following:\r
- \95 The data that will be transmitted when accessed by a master.\r
- \95 The buffer where data received from a master will be stored.\r
- \95 The handler function that must be called after the receive buffer has been\r
- filled.\r
- \95 The number of bytes that must be received from the master before the receive\r
- handler function is called.\r
- These parameters allow the following use cases:\r
- \95 Slave performing an action after receiving a block of data from a master\r
- containing a command. The action will be performed by the receive handling\r
- based on the content of the receive data buffer.\r
- \95 Slave returning a block of data to the master. The type of information is\r
- always the same but the actual values change over time. For example,\r
- returning the voltage of a predefined set of analog inputs.\r
- \95 Slave returning data based on a command contained in the first part of the\r
- SPI transaction. For example, reading the voltage of the analog input\r
- specified by the first data byte by the master. This is achieved by setting\r
- the rx_buff_size parameter to the number of received bytes making up the\r
- command.\r
- \r
- @param this_spi\r
- The this_spi parameter is a pointer to an mss_spi_instance_t structure\r
- identifying the MSS SPI hardware block to be initialized. There are two such\r
- data structures, g_mss_spi0 and g_mss_spi1, associated with MSS SPI 0 and\r
- MSS SPI 1 respectively. This parameter must point to either the g_mss_spi0\r
- or g_mss_spi1 global data structure defined within the SPI driver.\r
- \r
- \r
- @param tx_buffer\r
- The tx_buffer parameter is a pointer to a buffer containing the data that\r
- will be sent to the master. This parameter can be set to 0 if the MSS SPI\r
- slave is not intended to be the target of SPI read transactions or if DMA\r
- is used to transfer SPI read data into the MSS SPI slave.\r
- \r
- @param tx_buff_size\r
- The tx_buff_size parameter specifies the number of bytes contained in the\r
- tx_buffer. This parameter can be set to 0 if the MSS SPI slave is not\r
- intended to be the target of SPI read transactions or if DMA is used to\r
- transfer SPI read data into the MSS SPI slave.\r
- \r
- @param rx_buffer\r
- The rx_buffer parameter is a pointer to the buffer where data received from\r
- the master will be stored. This parameter can be set to 0 if the MSS SPI\r
- slave is not intended to be the target of SPI write or write-read\r
- transactions. It can also set to 0 if the MSS SPI slave uses DMA to handle\r
- data written to it.\r
- \r
- @param rx_buff_size\r
- The rx_buff_size parameter specifies the size of the receive buffer. It is\r
- also the number of bytes that must be received before the receive handler\r
- is called, if a receive handler is specified using the block_rx_handler\r
- parameter. This parameter can be set to 0 if the MSS SPI slave is not\r
- intended to be the target of SPI write or write-read transactions. It can\r
- also set to 0 if the MSS SPI slave uses DMA to handle data written to it.\r
- \r
- @param block_rx_handler\r
- The block_rx_handler parameter is a pointer to a function that will be\r
- called when the receive buffer has been filled. This parameter can be set\r
- to 0 if the MSS SPI slave is not intended to be the target of SPI write or\r
- write-read transactions. It can also set to 0 if the MSS SPI slave uses DMA\r
- to handle data written to it.\r
- \r
- Slave performing operation based on master command:\r
- In this example the SPI slave is configured to receive 10 bytes of data or\r
- command from the SPI slave and process the data received from the master.\r
- @code\r
- uint32_t nb_of_rx_handler_calls = 0;\r
- \r
- void spi1_block_rx_handler_b\r
- (\r
- uint8_t * rx_buff,\r
- uint16_t rx_size\r
- )\r
- {\r
- ++nb_of_rx_handler_calls;\r
- }\r
- \r
- void setup_slave( void )\r
- {\r
- uint8_t slave_rx_buffer[10] = \r
- {\r
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00\r
- };\r
- \r
- MSS_SPI_init( &g_mss_spi1 );\r
- MSS_SPI_configure_slave_mode\r
- ( \r
- &g_mss_spi0,\r
- MSS_SPI_MODE2,\r
- MSS_SPI_PCLK_DIV_64,\r
- MSS_SPI_BLOCK_TRANSFER_FRAME_SIZE\r
- );\r
- \r
- MSS_SPI_set_slave_block_buffers\r
- (\r
- &g_mss_spi1,\r
- 0,\r
- 0,\r
- slave_rx_buffer,\r
- sizeof(master_tx_buffer),\r
- spi1_block_rx_handler_b\r
- );\r
- }\r
- @endcode\r
- \r
- Slave responding to command example:\r
- In this example the slave will return data based on a command sent by the\r
- master. The first part of the transaction is handled using polled mode where\r
- each byte returned to the master is written as part of the interrupt service\r
- routine. The second part of the transaction, where the slave returns data\r
- based on the command value, is sent using a DMA transfer initiated by the\r
- receive handler. \r
- @code\r
- static uint8_t g_spi1_tx_buffer_b[SLAVE_TX_BUFFER_SIZE] =\r
- {\r
- 5, 6, 7, 8, 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5\r
- };\r
- \r
- void spi1_block_rx_handler\r
- (\r
- uint8_t * rx_buff,\r
- uint16_t rx_size\r
- )\r
- {\r
- if ( rx_buff[2] == 0x99 )\r
- {\r
- PDMA_start\r
- (\r
- PDMA_CHANNEL_0,\r
- (uint32_t)g_spi1_tx_buffer_b,\r
- 0x40011014,\r
- sizeof(g_spi1_tx_buffer_b)\r
- ); \r
- }\r
- }\r
- \r
- void setup_slave( void )\r
- {\r
- uint8_t slave_preamble[8] = { 9, 10, 11, 12, 13, 14, 16, 16 };\r
-\r
- MSS_SPI_init( &g_mss_spi1 );\r
- MSS_SPI_configure_slave_mode\r
- (\r
- &g_mss_spi0,\r
- MSS_SPI_MODE2,\r
- MSS_SPI_PCLK_DIV_64,\r
- MSS_SPI_BLOCK_TRANSFER_FRAME_SIZE\r
- );\r
- \r
- PDMA_init();\r
- PDMA_configure\r
- (\r
- PDMA_CHANNEL_0, \r
- TO_SPI_1,\r
- LOW_PRIORITY | BYTE_TRANSFER | INC_SRC_ONE_BYTE\r
- );\r
- \r
- MSS_SPI_set_slave_block_buffers\r
- (\r
- &g_mss_spi1,\r
- slave_preamble,\r
- 4,\r
- g_spi1_rx_buffer,\r
- sizeof(g_spi1_rx_buffer),\r
- spi1_block_rx_handler\r
- );\r
- }\r
- @endcode\r
- */\r
-void MSS_SPI_set_slave_block_buffers\r
-(\r
- mss_spi_instance_t * this_spi,\r
- const uint8_t * tx_buffer,\r
- uint32_t tx_buff_size,\r
- uint8_t * rx_buffer,\r
- uint32_t rx_buff_size,\r
- mss_spi_block_rx_handler_t block_rx_handler\r
-);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* MSS_SPI_H_*/\r
+++ /dev/null
-/*******************************************************************************\r
- * (c) Copyright 2007 Actel Corporation. All rights reserved.\r
- *\r
- * SmartFusion Microcontroller Subsystem UART bare metal software driver\r
- * implementation.\r
- *\r
- * SVN $Revision: 1898 $\r
- * SVN $Date: 2009-12-21 17:27:57 +0000 (Mon, 21 Dec 2009) $\r
- */\r
-#include "mss_uart.h"\r
-#include "../../CMSIS/mss_assert.h"\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif \r
-\r
-/*******************************************************************************\r
- * defines\r
- */\r
-#define TX_READY 0x01U\r
-#define TX_COMPLETE 0U\r
-\r
-#define TX_FIFO_SIZE 16U\r
-\r
-#define FCR_TRIG_LEVEL_MASK 0xC0U\r
-\r
-#define IIRF_MASK 0x0FU\r
-\r
-/*******************************************************************************\r
- * Possible values for Interrupt Identification Register Field.\r
- */\r
-#define IIRF_MODEM_STATUS 0x00U \r
-#define IIRF_THRE 0x02U\r
-#define IIRF_RX_DATA 0x04U\r
-#define IIRF_RX_LINE_STATUS 0x06U\r
-#define IIRF_DATA_TIMEOUT 0x0CU\r
-\r
-/*******************************************************************************\r
- * Cortex-M3 interrupt handler functions implemented as part of the MSS UART\r
- * driver.\r
- */\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void UART0_IRQHandler( void );\r
-#else\r
-void UART0_IRQHandler( void );\r
-#endif\r
-\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void UART1_IRQHandler( void );\r
-#else\r
-void UART1_IRQHandler( void );\r
-#endif\r
-\r
-/*******************************************************************************\r
- * Local functions.\r
- */\r
-static void MSS_UART_isr( mss_uart_instance_t * this_uart );\r
-\r
-/*******************************************************************************\r
- *\r
- */\r
-mss_uart_instance_t g_mss_uart0;\r
-mss_uart_instance_t g_mss_uart1;\r
-\r
-/***************************************************************************//**\r
- * UART_init.\r
- * Initialises the UART with default configuration.\r
- */\r
-void \r
-MSS_UART_init\r
-(\r
- mss_uart_instance_t* this_uart, \r
- uint32_t baud_rate,\r
- uint8_t line_config\r
-)\r
-{\r
- uint16_t baud_value;\r
- uint32_t pclk_freq;\r
-\r
- /* The driver expects g_mss_uart0 and g_mss_uart1 to be the only \r
- * mss_uart_instance_t instances used to identfy UART0 and UART1. */\r
- ASSERT( (this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1) );\r
- \r
- /* Force the value of the CMSIS global variables holding the various system\r
- * clock frequencies to be updated. */\r
- SystemCoreClockUpdate();\r
- \r
- if ( this_uart == &g_mss_uart0 )\r
- {\r
- this_uart->hw_reg = UART0;\r
- this_uart->hw_reg_bit = UART0_BITBAND;\r
- this_uart->irqn = UART0_IRQn;\r
-\r
- pclk_freq = g_FrequencyPCLK0;\r
- \r
- /* reset UART0 */\r
- SYSREG->SOFT_RST_CR |= SYSREG_UART0_SOFTRESET_MASK;\r
- /* Clear any previously pended UART0 interrupt */\r
- NVIC_ClearPendingIRQ( UART0_IRQn );\r
- /* Take UART0 out of reset. */\r
- SYSREG->SOFT_RST_CR &= ~SYSREG_UART0_SOFTRESET_MASK;\r
- }\r
- else\r
- {\r
- this_uart->hw_reg = UART1;\r
- this_uart->hw_reg_bit = UART1_BITBAND;\r
- this_uart->irqn = UART1_IRQn;\r
-\r
- pclk_freq = g_FrequencyPCLK1;\r
- \r
- /* Reset UART1 */\r
- SYSREG->SOFT_RST_CR |= SYSREG_UART1_SOFTRESET_MASK;\r
- /* Clear any previously pended UART1 interrupt */\r
- NVIC_ClearPendingIRQ( UART1_IRQn );\r
- /* Take UART1 out of reset. */\r
- SYSREG->SOFT_RST_CR &= ~SYSREG_UART1_SOFTRESET_MASK;\r
- }\r
- \r
- /* disable interrupts */\r
- this_uart->hw_reg->IER = 0U;\r
-\r
- /*\r
- * Compute baud value based on requested baud rate and PCLK frequency.\r
- * The baud value is computed using the following equation:\r
- * baud_value = PCLK_Frequency / (baud_rate * 16)\r
- * The baud value is rounded up or down depending on what would be the remainder\r
- * of the divide by 16 operation.\r
- */\r
- baud_value = (uint16_t)(pclk_freq / baud_rate);\r
- if ( baud_value & 0x00000008U )\r
- {\r
- /* remainder above 0.5 */\r
- baud_value = (baud_value >> 4U) + 1U;\r
- }\r
- else\r
- {\r
- /* remainder below 0.5 */\r
- baud_value = (baud_value >> 4U);\r
- }\r
-\r
- /* set divisor latch */\r
- this_uart->hw_reg_bit->LCR_DLAB = (uint32_t)1;\r
-\r
- /* msb of baud value */\r
- this_uart->hw_reg->DMR = (uint8_t)(baud_value >> 8);\r
- /* lsb of baud value */\r
- this_uart->hw_reg->DLR = (uint8_t)baud_value;\r
-\r
- /* reset divisor latch */\r
- this_uart->hw_reg_bit->LCR_DLAB = (uint32_t)0;\r
-\r
- /* set the line control register (bit length, stop bits, parity) */\r
- this_uart->hw_reg->LCR = line_config;\r
- \r
- /* FIFO configuration */\r
- this_uart->hw_reg->FCR = (uint8_t)MSS_UART_FIFO_SINGLE_BYTE;\r
- \r
- /* disable loopback */\r
- this_uart->hw_reg_bit->MCR_LOOP = (uint32_t)0;\r
-\r
- /* Instance setup */\r
- this_uart->tx_buff_size = TX_COMPLETE;\r
- this_uart->tx_buffer = (const uint8_t *)0;\r
- this_uart->tx_idx = 0U;\r
- \r
- this_uart->rx_handler = (mss_uart_rx_handler_t)0;\r
-}\r
-\r
-/***************************************************************************//**\r
- * See mss_uart.h for details of how to use this function.\r
- */\r
-void \r
-MSS_UART_polled_tx\r
-( \r
- mss_uart_instance_t * this_uart, \r
- const uint8_t * pbuff,\r
- uint32_t tx_size\r
-)\r
-{\r
- uint32_t char_idx;\r
- uint32_t status;\r
-\r
- ASSERT( (this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1) );\r
- \r
- for ( char_idx = 0U; char_idx < tx_size; char_idx++ )\r
- {\r
- /* Wait for UART to become ready to transmit. */\r
- do {\r
- status = this_uart->hw_reg_bit->LSR_THRE;\r
- } while ( (status & TX_READY) == 0U );\r
- /* Send next character in the buffer. */\r
- this_uart->hw_reg->THR = pbuff[char_idx];\r
- }\r
-}\r
-\r
-/***************************************************************************//**\r
- * See mss_uart.h for details of how to use this function.\r
- */\r
-void \r
-MSS_UART_polled_tx_string\r
-( \r
- mss_uart_instance_t * this_uart, \r
- const uint8_t * p_sz_string\r
-)\r
-{\r
- uint32_t char_idx;\r
- uint32_t status;\r
-\r
- ASSERT( (this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1) );\r
- \r
- char_idx = 0U;\r
- \r
- while ( p_sz_string[char_idx] != 0U )\r
- {\r
- /* Wait for UART to become ready to transmit. */\r
- do {\r
- status = this_uart->hw_reg_bit->LSR_THRE;\r
- } while ( (status & TX_READY) == 0U);\r
- /* Send next character in the buffer. */\r
- this_uart->hw_reg->THR = p_sz_string[char_idx];\r
- ++char_idx;\r
- }\r
-}\r
-\r
-/***************************************************************************//**\r
- * See mss_uart.h for details of how to use this function.\r
- */\r
-void \r
-MSS_UART_irq_tx\r
-( \r
- mss_uart_instance_t * this_uart, \r
- const uint8_t * pbuff,\r
- uint32_t tx_size\r
-)\r
-{\r
- ASSERT( (this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1) );\r
- \r
- if ( tx_size > 0U )\r
- {\r
- /*Initialise the transmit info for the UART instance with the arguments.*/\r
- this_uart->tx_buffer = pbuff;\r
- this_uart->tx_buff_size = tx_size;\r
- this_uart->tx_idx = (uint16_t)0;\r
- \r
- /* enables TX interrupt */\r
- this_uart->hw_reg_bit->IER_ETBEI = (uint32_t)1;\r
- \r
- /* Enable UART instance interrupt in Cortex-M3 NVIC. */\r
- NVIC_EnableIRQ( this_uart->irqn );\r
- }\r
-}\r
-\r
-/***************************************************************************//**\r
- * See mss_uart.h for details of how to use this function.\r
- */\r
-int8_t \r
-MSS_UART_tx_complete\r
-( \r
- mss_uart_instance_t * this_uart \r
-)\r
-{\r
- int8_t ret_value = 0;\r
- uint32_t transmit_empty = this_uart->hw_reg_bit->LSR_TEMT;\r
- \r
- ASSERT( (this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1) );\r
-\r
- if ( ( TX_COMPLETE == this_uart->tx_buff_size ) && transmit_empty )\r
- {\r
- ret_value = 1;\r
- }\r
- \r
- return ret_value;\r
-}\r
-\r
-\r
-/***************************************************************************//**\r
- * See mss_uart.h for details of how to use this function.\r
- */\r
-size_t\r
-MSS_UART_get_rx\r
-(\r
- mss_uart_instance_t * this_uart,\r
- uint8_t * rx_buff,\r
- size_t buff_size\r
-)\r
-{\r
- size_t rx_size = 0U;\r
- \r
- ASSERT( (this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1) );\r
-\r
- while (( this_uart->hw_reg_bit->LSR_DR != 0U) && ( rx_size < buff_size ) )\r
- {\r
- rx_buff[rx_size] = this_uart->hw_reg->RBR;\r
- ++rx_size;\r
- }\r
- \r
- return rx_size;\r
-}\r
-\r
-/***************************************************************************//**\r
- * Interrupt service routine triggered by the Transmitter Holding Register\r
- * Empty (THRE) interrupt or Received Data Available (RDA). \r
- * On THRE irq this routine will transmit the data from the transmit buffer. \r
- * When all bytes are transmitted, this routine disables the THRE interrupt\r
- * and resets the transmit counter.\r
- * On RDA irq this routine will call the user's receive handler routine previously\r
- * registered with the UART driver through a call to UART_set_rx_handler().\r
- */\r
-static void \r
-MSS_UART_isr\r
-( \r
- mss_uart_instance_t * this_uart \r
-)\r
-{\r
- uint8_t iirf;\r
- uint32_t tx_empty;\r
- \r
- ASSERT( (this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1) );\r
-\r
- iirf = this_uart->hw_reg->IIR & IIRF_MASK;\r
- \r
- switch ( iirf )\r
- {\r
- case IIRF_MODEM_STATUS:\r
- break;\r
- \r
- case IIRF_THRE: /* Transmitter Holding Register Empty */\r
- tx_empty = this_uart->hw_reg_bit->LSR_TEMT;\r
- \r
- if ( tx_empty )\r
- {\r
- uint32_t i;\r
- uint32_t fill_size = TX_FIFO_SIZE;\r
- uint32_t tx_remain = this_uart->tx_buff_size - this_uart->tx_idx;\r
- if ( tx_remain < TX_FIFO_SIZE )\r
- {\r
- fill_size = tx_remain;\r
- }\r
- /* Fill up FIFO */\r
- for ( i = 0U; i < fill_size; ++i )\r
- {\r
- this_uart->hw_reg->THR = this_uart->tx_buffer[this_uart->tx_idx];\r
- ++this_uart->tx_idx;\r
- }\r
- }\r
- else\r
- {\r
- this_uart->hw_reg->THR = this_uart->tx_buffer[this_uart->tx_idx];\r
- ++this_uart->tx_idx;\r
- }\r
- \r
- if ( this_uart->tx_idx == this_uart->tx_buff_size )\r
- {\r
- this_uart->tx_buff_size = TX_COMPLETE;\r
- /* disables TX interrupt */\r
- this_uart->hw_reg_bit->IER_ETBEI = 0U;\r
- }\r
- break;\r
- \r
- case IIRF_RX_DATA: /* Received Data Available */\r
- case IIRF_DATA_TIMEOUT:\r
- if (this_uart->rx_handler != 0)\r
- {\r
- (*(this_uart->rx_handler))();\r
- }\r
- break;\r
- \r
- case IIRF_RX_LINE_STATUS:\r
- break;\r
- \r
- default:\r
- /* Disable other interrupts */\r
- this_uart->hw_reg_bit->IER_ELSI = 0U;\r
- this_uart->hw_reg_bit->IER_EDSSI = 0U;\r
- break;\r
- }\r
-}\r
-\r
-/***************************************************************************//**\r
- * See mss_uart.h for details of how to use this function.\r
- */\r
-void\r
-MSS_UART_set_rx_handler\r
-(\r
- mss_uart_instance_t * this_uart,\r
- mss_uart_rx_handler_t handler,\r
- mss_uart_rx_trig_level_t trigger_level\r
-)\r
-{\r
- ASSERT( (this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1) );\r
- \r
- this_uart->rx_handler = handler;\r
- \r
- /* Set the receive interrupt trigger level. */\r
- this_uart->hw_reg->FCR = (this_uart->hw_reg->FCR & (uint8_t)(~((uint8_t)FCR_TRIG_LEVEL_MASK))) | (uint8_t)trigger_level;\r
- \r
- /* Enable receive interrupt. */\r
- this_uart->hw_reg_bit->IER_ERBFI = 1U;\r
- \r
- /* Enable UART instance interrupt in Cortex-M3 NVIC. */\r
- NVIC_EnableIRQ( this_uart->irqn );\r
-}\r
-\r
-/***************************************************************************//**\r
- * See mss_uart.h for details of how to use this function.\r
- */\r
-void\r
-MSS_UART_set_loopback\r
-(\r
- mss_uart_instance_t * this_uart,\r
- mss_uart_loopback_t loopback\r
-)\r
-{\r
- ASSERT( (this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1) );\r
- \r
- if ( loopback == MSS_UART_LOOPBACK_OFF )\r
- {\r
- this_uart->hw_reg_bit->MCR_LOOP = 0U;\r
- }\r
- else\r
- {\r
- this_uart->hw_reg_bit->MCR_LOOP = 1U;\r
- }\r
-}\r
-\r
-/***************************************************************************//**\r
- * UART0 interrupt service routine.\r
- * UART0_IRQHandler is included within the Cortex-M3 vector table as part of the\r
- * Fusion 2 CMSIS.\r
- */\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void UART0_IRQHandler( void )\r
-#else\r
-void UART0_IRQHandler( void )\r
-#endif\r
-{\r
- MSS_UART_isr( &g_mss_uart0 );\r
- NVIC_ClearPendingIRQ( UART0_IRQn );\r
-}\r
-\r
-/***************************************************************************//**\r
- * UART1 interrupt service routine.\r
- * UART2_IRQHandler is included within the Cortex-M3 vector table as part of the\r
- * Fusion 2 CMSIS.\r
- */\r
-#if defined(__GNUC__)\r
-__attribute__((__interrupt__)) void UART1_IRQHandler( void )\r
-#else\r
-void UART1_IRQHandler( void )\r
-#endif\r
-{\r
- MSS_UART_isr( &g_mss_uart1 );\r
- NVIC_ClearPendingIRQ( UART1_IRQn );\r
-}\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
+++ /dev/null
-/*******************************************************************************\r
- * (c) Copyright 2007 Actel Corporation. All rights reserved.\r
- *\r
- * SmartFusion Microcontroller Subsystem UART bare metal software driver public API.\r
- *\r
- * SVN $Revision: 1942 $\r
- * SVN $Date: 2009-12-22 17:48:07 +0000 (Tue, 22 Dec 2009) $\r
- */\r
-/*=========================================================================*//**\r
- @mainpage SmartFusion MSS UART Bare Metal Driver.\r
-\r
- @section intro_sec Introduction\r
- The SmartFusion MicroController Subsystem (MSS) includes two UART peripherals\r
- for serial communications.\r
- This driver provides a set of functions for controlling the MSS UARTs as part\r
- of a bare metal system where no operating system is available. These drivers\r
- can be adapted for use as part of an operating system but the implementation\r
- of the adaptation layer between this driver and the operating system's driver\r
- model is outside the scope of this driver.\r
- \r
- @section hw_dependencies Hardware Flow Dependencies\r
- The configuration of all features of the MSS UARTs is covered by this driver\r
- with the exception of the SmartFusion IOMUX configuration. SmartFusion allows\r
- multiple non-concurrent uses of some external pins through IOMUX configuration.\r
- This feature allows optimization of external pin usage by assigning external\r
- pins for use by either the microcontroller subsystem or the FPGA fabric. The\r
- MSS UARTs serial signals are routed through IOMUXes to the SmartFusion device\r
- external pins. These IOMUXes are configured automatically by the MSS\r
- configurator tool in the hardware flow correctly when the MSS UARTs are enabled\r
- in that tool. You must ensure that the MSS UARTs are enabled by the MSS\r
- configurator tool in the hardware flow; otherwise the serial inputs and outputs\r
- will not be connected to the chip's external pins. For more information on\r
- IOMUX, refer to the IOMUX section of the SmartFusion Datasheet.\r
- The base address, register addresses and interrupt number assignment for the MSS\r
- UART blocks are defined as constants in the SmartFusion CMSIS-PAL You must ensure\r
- that the SmartFusion CMSIS-PAL is either included in the software tool chain used\r
- to build your project or is included in your project.\r
-\r
- \r
- @section theory_op Theory of Operation\r
- The MSS UART driver uses the SmartFusion "Cortex Microcontroler Software\r
- Interface Standard - Peripheral Access Layer" (CMSIS-PAL) to access hadware\r
- registers. You must ensure that the SmartFusion CMSIS-PAL is either included\r
- in the software toolchain used to build your project or is included in your\r
- project. The most up to date SmartFusion CMSIS-PAL files can be obtained using\r
- the Actel Firmware Catalog.\r
- \r
- The MSS UART driver functions are logically grouped into three groups:\r
- - Initialization functions\r
- - Polled transmit and receive functions\r
- - Interrupt driven transmit and receive functions\r
- \r
- The MSS UART driver is initialized through a call to the UART_init() function.\r
- This function takes the UART's configuration as parameters. The UART_init()\r
- function must be called before any other UART driver functions can be called.\r
- The first parameter of the UART_init() function is a pointer to one of two\r
- global data structures used to store state information for each UART driver.\r
- A pointer to these data structures is also used as first parameter to any of\r
- the driver functions to identify which UART will be used by the called\r
- function. The name of these two data structures are g_mss_uart0 and\r
- g_mss_uart1. Therefore any call to a MSS UART function should be of the form\r
- UART_function_name( &g_mss_uart0, ... ) or UART_function_name( &g_mss_uart1, ... ).\r
- The two SmartFusion MSS UARTs can also be configured to loop back to each\r
- other using the MSS_set_loopback() function for debugging purposes.\r
- \r
- Polled operations where the processor constantly poll the UART registers state\r
- in order to control data transmit or data receive is performed using functions:\r
- - MSS_UART_polled_tx()\r
- - MSS_UART_get_rx()\r
- \r
- Interrupt driven operations where the processor sets up transmit or receive\r
- then returns to performing some other operation until an interrupts occurs\r
- indicating that its attention is required is performed using functions:\r
- - MSS_UART_irq_tx()\r
- - MSS_UART_tx_complete()\r
- - MSS_UART_set_rx_handler()\r
- - MSS_UART_get_rx()\r
- Interrupt driven transmit is initiated by a call to MSS_UART_irq_tx() specifying\r
- the block of data to transmit. The processor can then perform some other\r
- operation and later inquire whether transmit has completed by calling the\r
- MSS_UART_tx_complete() function.\r
- Interrupt driven receive is performed by first registering a receive handler\r
- function that will be called by the driver whenever receive data is available.\r
- This receive handler function in turns calls the MSS_UART_get_rx() function to\r
- actually read the received data.\r
- \r
- *//*=========================================================================*/\r
-#ifndef __MSS_UART_H_\r
-#define __MSS_UART_H_ 1\r
-\r
-#include "../../CMSIS/a2fxxxm3.h"\r
-#include <stddef.h>\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif \r
-\r
-/***************************************************************************//**\r
- Baud rates.\r
- The following definitions are used to specify standard baud rates as a\r
- parameter to the MSS_UART_init() function.\r
- */\r
-#define MSS_UART_110_BAUD 110\r
-#define MSS_UART_300_BAUD 300\r
-#define MSS_UART_1200_BAUD 1200\r
-#define MSS_UART_2400_BAUD 2400\r
-#define MSS_UART_4800_BAUD 4800\r
-#define MSS_UART_9600_BAUD 9600\r
-#define MSS_UART_19200_BAUD 19200\r
-#define MSS_UART_38400_BAUD 38400\r
-#define MSS_UART_57600_BAUD 57600\r
-#define MSS_UART_115200_BAUD 115200\r
-#define MSS_UART_230400_BAUD 230400\r
-#define MSS_UART_460800_BAUD 460800\r
-#define MSS_UART_921600_BAUD 921600\r
-\r
-/***************************************************************************//**\r
- Data bits length values.\r
- \r
- The following defines are used to build the value of the MSS_UART_init()\r
- function line_config parameter.\r
- */\r
-#define MSS_UART_DATA_5_BITS 0x00\r
-#define MSS_UART_DATA_6_BITS 0x01\r
-#define MSS_UART_DATA_7_BITS 0x02\r
-#define MSS_UART_DATA_8_BITS 0x03\r
-\r
-/***************************************************************************//**\r
- Parity values\r
- The following defines are used to build the value of the MSS_UART_init()\r
- function line_config parameter.\r
- */\r
-#define MSS_UART_NO_PARITY 0x00\r
-#define MSS_UART_ODD_PARITY 0x08\r
-#define MSS_UART_EVEN_PARITY 0x18\r
-#define MSS_UART_STICK_PARITY_0 0x38\r
-#define MSS_UART_STICK_PARITY_1 0x28\r
-\r
-/***************************************************************************//**\r
- Stop bit values\r
- The following defines are used to build the value of the MSS_UART_init()\r
- function line_config parameter.\r
- */\r
-#define MSS_UART_ONE_STOP_BIT 0x00\r
-#define MSS_UART_ONEHALF_STOP_BIT 0x04\r
-#define MSS_UART_TWO_STOP_BITS 0x04\r
-\r
-/***************************************************************************//**\r
- FIFO trigger sizes\r
- This enumeration specifies the number of bytes that must be received before a\r
- receive interrupt is generated. This enumeration provides the allowed values for\r
- the MSS_UART_set_rx_handler() function trigger_level parameter.\r
- */\r
-typedef enum __mss_uart_rx_trig_level_t {\r
- MSS_UART_FIFO_SINGLE_BYTE = 0x00,\r
- MSS_UART_FIFO_FOUR_BYTES = 0x40,\r
- MSS_UART_FIFO_EIGHT_BYTES = 0x80,\r
- MSS_UART_FIFO_FOURTEEN_BYTES = 0xC0\r
-} mss_uart_rx_trig_level_t;\r
-\r
-/***************************************************************************//**\r
- Loopback.\r
- This enumeration is used as parameter to function MSS_UART_set_loopback(). It\r
- specifies the loopback configuration of the UARTs. Using MSS_UART_LOOPBACK_ON\r
- as parameter to function MSS_UART_set_loopback() will set up the UART to locally\r
- loopback its Tx and Rx lines.\r
- */\r
-typedef enum __mss_uart_loopback_t {\r
- MSS_UART_LOOPBACK_OFF = 0,\r
- MSS_UART_LOOPBACK_ON = 1\r
-} mss_uart_loopback_t;\r
-\r
-/***************************************************************************//**\r
- Receive handler prototype.\r
- This typedef specifies the prototype of functions that can be registered with\r
- this driver as receive handler functions.\r
- */\r
-typedef void (*mss_uart_rx_handler_t)(void);\r
-\r
-/***************************************************************************//**\r
- mss_uart_instance_t.\r
- \r
- There is one instance of this structure for each instance of the Microcontroller\r
- Subsystem's UARTs. Instances of this structure are used to identify a specific\r
- UART. A pointer to an instance of the mss_uart_instance_t structure is passed\r
- as the first parameter to MSS UART driver functions to identify which UART\r
- should perform the requested operation.\r
- */\r
-typedef struct {\r
- /* CMSIS related defines identifying the UART hardware. */\r
- UART_TypeDef * hw_reg; /*!< Pointer to UART registers. */\r
- UART_BitBand_TypeDef * hw_reg_bit; /*!< Pointer to UART registers bit band area. */\r
- IRQn_Type irqn; /*!< UART's Cortex-M3 NVIC interrupt number. */\r
- \r
- /* transmit related info (used with interrupt driven trnasmit): */\r
- const uint8_t * tx_buffer; /*!< Pointer to transmit buffer. */\r
- uint32_t tx_buff_size; /*!< Transmit buffer size. */\r
- uint32_t tx_idx; /*!< Index within trnamit buffer of next byte to transmit.*/\r
- \r
- /* receive interrupt handler:*/\r
- mss_uart_rx_handler_t rx_handler; /*!< Pointer to user registered received handler. */\r
-} mss_uart_instance_t;\r
-\r
-/***************************************************************************//**\r
- This instance of mss_uart_instance_t holds all data related to the operations\r
- performed by UART0. A pointer to g_mss_uart0 is passed as the first parameter\r
- to MSS UART driver functions to indicate that UART0 should perform the requested\r
- operation.\r
- */\r
-extern mss_uart_instance_t g_mss_uart0;\r
-\r
-/***************************************************************************//**\r
- This instance of mss_uart_instance_t holds all data related to the operations\r
- performed by UART1. A pointer to g_mss_uart1 is passed as the first parameter\r
- to MSS UART driver functions to indicate that UART1 should perform the requested\r
- operation.\r
- */\r
-extern mss_uart_instance_t g_mss_uart1;\r
-\r
-/***************************************************************************//**\r
- The MSS_UART_init() function initializes and configures one of the SmartFusion\r
- MSS UARTs with the configuration passed as a parameter. The configuration\r
- parameters are the baud_rate which is used to generate the baud value and the\r
- line_config which is used to specify the line configuration (bit length, stop\r
- bits and parity).\r
- \r
- Example:\r
- @code\r
- #include "mss_uart.h"\r
- \r
- int main(void)\r
- {\r
- MSS_UART_init\r
- (\r
- &g_mss_uart0,\r
- MSS_UART_57600_BAUD,\r
- MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT\r
- );\r
- return(0);\r
- }\r
- @endcode\r
- \r
- @param this_uart\r
- The this_uart parameter is a pointer to an mss_uart_instance_t structure\r
- identifying the MSS UART hardware block to be initialized. There are two\r
- such data structures, g_mss_uart0 and g_mss_uart1, associated with MSS UART0\r
- and MSS UART1 respectively. This parameter must point to either the\r
- g_mss_uart0 or g_mss_uart1 global data structure defined within the UART\r
- driver.\r
- \r
- \r
- @param baud_rate\r
- The baud_rate parameter specifies the baud rate. It can be specified for\r
- common baud rates' using the following defines:\r
- - MSS_UART_110_BAUD\r
- - MSS_UART_300_BAUD\r
- - MSS_UART_1200_BAUD\r
- - MSS_UART_2400_BAUD\r
- - MSS_UART_4800_BAUD\r
- - MSS_UART_9600_BAUD\r
- - MSS_UART_19200_BAUD\r
- - MSS_UART_38400_BAUD\r
- - MSS_UART_57600_BAUD\r
- - MSS_UART_115200_BAUD\r
- - MSS_UART_230400_BAUD\r
- - MSS_UART_460800_BAUD\r
- - MSS_UART_921600_BAUD \r
- Alternatively, any non standard baud rate can be specified by simply passing\r
- the actual required baud rate as value for this parameter.\r
- \r
- @param line_config\r
- The line_config parameter is the line configuration specifying the bit length,\r
- number of stop bits and parity settings. This is a logical OR of one of the\r
- following to specify the transmit/receive data bit length: \r
- - MSS_UART_DATA_5_BITS\r
- - MSS_UART_DATA_6_BITS,\r
- - MSS_UART_DATA_7_BITS\r
- - MSS_UART_DATA_8_BITS\r
- with one of the following to specify the parity setting:\r
- - MSS_UART_NO_PARITY\r
- - MSS_UART_EVEN_PARITY\r
- - MSS_UART_ODD_PARITY\r
- - MSS_UART_STICK_PARITY_0\r
- - MSS_UART_STICK_PARITY_1\r
- with one of the following to specify the number of stop bits:\r
- - MSS_UART_ONE_STOP_BIT\r
- - MSS_UART_ONEHALF_STOP_BIT\r
- - MSS_UART_TWO_STOP_BITS\r
- \r
- @return\r
- This function does not return a value.\r
- */\r
-void\r
-MSS_UART_init\r
-(\r
- mss_uart_instance_t* this_uart,\r
- uint32_t baud_rate,\r
- uint8_t line_config\r
-);\r
-\r
-/***************************************************************************//**\r
- The function MSS_UART_polled_tx() is used to transmit data. It transfers the\r
- contents of the transmitter data buffer, passed as a function parameter, into\r
- the UART's hardware transmitter FIFO. It returns when the full content of the\r
- transmit data buffer has been transferred to the UART's transmit FIFO. \r
- \r
- @param this_uart\r
- The this_uart parameter is a pointer to an mss_uart_instance_t structure\r
- identifying the MSS UART hardware block that will perform the requested\r
- function. There are two such data structures, g_mss_uart0 and g_mss_uart1,\r
- associated with MSS UART0 and MSS UART1. This parameter must point to either\r
- the g_mss_uart0 or g_mss_uart1 global data structure defined within the UART\r
- driver.\r
- \r
- @param pbuff\r
- The pbuff parameter is a pointer to a buffer containing the data to be\r
- transmitted.\r
- \r
- @param tx_size\r
- The tx_size parameter specifies the size, in bytes, of the data to be\r
- transmitted.\r
- \r
- @return This function does not return a value.\r
- */\r
-void \r
-MSS_UART_polled_tx\r
-( \r
- mss_uart_instance_t * this_uart, \r
- const uint8_t * pbuff,\r
- uint32_t tx_size\r
-);\r
-\r
-/***************************************************************************//**\r
- The function MSS_UART_polled_tx_string() is used to transmit a zero-terminated\r
- string. It transfers the text found starting at the address pointed to by\r
- p_sz_string into the UART's hardware transmitter FIFO. It returns when the\r
- complete string has been transferred to the UART's transmit FIFO. \r
- \r
- @param this_uart\r
- The this_uart parameter is a pointer to an mss_uart_instance_t structure\r
- identifying the MSS UART hardware block that will perform the requested\r
- function. There are two such data structures, g_mss_uart0 and g_mss_uart1,\r
- associated with MSS UART0 and MSS UART1. This parameter must point to either\r
- the g_mss_uart0 or g_mss_uart1 global data structure defined within the UART\r
- driver.\r
- \r
- @param p_sz_string\r
- The p_sz_string parameter is a pointer to a buffer containing the\r
- zero-terminated string to be transmitted.\r
- \r
- @return This function does not return a value.\r
- */\r
-void \r
-MSS_UART_polled_tx_string\r
-( \r
- mss_uart_instance_t * this_uart, \r
- const uint8_t * p_sz_string\r
-);\r
-\r
-\r
-/***************************************************************************//**\r
- The function MSS_UART_irq_tx() is used to initiate interrupt driven transmit. It\r
- returns immediately after making a note of the transmit buffer location and\r
- enabling transmit interrupts both at the UART and Cortex-M3 NVIC level.\r
- This function takes a pointer to a memory buffer containing the data to\r
- transmit as parameter. The memory buffer specified through this pointer\r
- should remain allocated and contain the data to transmit until the transmit\r
- completion has been detected through calls to function MSS_UART_tx_complete().\r
- NOTE: The MSS_UART_irq_tx() function also enables the Transmitter Holding\r
- Register Empty (THRE) interrupt and the UART instance interrupt in the\r
- Cortex-M3 NVIC as part of its implementation.\r
- \r
- Example:\r
- @code\r
- #include "mss_uart.h"\r
- \r
- int main(void)\r
- {\r
- uint8_t tx_buff[10] = "abcdefghi";\r
- MSS_UART_init( &g_mss_uart0, MSS_UART_57600_BAUD, MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT );\r
- MSS_UART_irq_tx( &g_mss_uart0, tx_buff, sizeof(tx_buff));\r
- while ( 0 == MSS_UART_tx_complete( &g_mss_uart0 ) )\r
- {\r
- ;\r
- }\r
- return(0);\r
- }\r
- @endcode\r
- \r
- @param this_uart\r
- The this_uart parameter is a pointer to an mss_uart_instance_t structure\r
- identifying the MSS UART hardware block that will perform the requested\r
- function. There are two such data structures, g_mss_uart0 and g_mss_uart1,\r
- associated with MSS UART0 and MSS UART1. This parameter must point to either\r
- the g_mss_uart0 or g_mss_uart1 global data structure defined within the UART\r
- driver.\r
- \r
- @param pbuff\r
- The pbuff parameter is a pointer to a buffer containing the data to be\r
- transmitted.\r
- \r
- @param tx_size\r
- The tx_size parameter specifies the size, in bytes, of the data to be\r
- transmitted.\r
- \r
- @return\r
- This function does not return a value.\r
- */\r
-void \r
-MSS_UART_irq_tx\r
-( \r
- mss_uart_instance_t * this_uart, \r
- const uint8_t * pbuff,\r
- uint32_t tx_size\r
-);\r
-\r
-/***************************************************************************//**\r
- The MSS_UART_tx_complete() function is used to find out if interrupt driven\r
- transmit previously initiated through a call to MSS_UART_irq_tx() is complete.\r
- This is typically used to find out when it is safe to reuse or release the\r
- memory buffer holding transmit data.\r
- \r
- @param this_uart\r
- The this_uart parameter is a pointer to an mss_uart_instance_t structure\r
- identifying the MSS UART hardware block that will perform the requested\r
- function. There are two such data structures, g_mss_uart0 and g_mss_uart1,\r
- associated with MSS UART0 and MSS UART1. This parameter must point to either\r
- the g_mss_uart0 or g_mss_uart1 global data structure defined within the UART\r
- driver.\r
- \r
- @return\r
- This function return a non-zero value if transmit has completed, otherwise\r
- it returns zero.\r
- \r
- Example:\r
- See the MSS_UART_irq_tx() function for an example that uses the\r
- MSS_UART_tx_complete() function.\r
- */\r
-int8_t\r
-MSS_UART_tx_complete\r
-(\r
- mss_uart_instance_t * this_uart\r
-);\r
-\r
-/***************************************************************************//**\r
- The MSS_UART_get_rx() function is used to read the content of a UART's receive\r
- FIFO. It can be used in polled mode where it is called at regular interval\r
- to find out if any data has been received or in interrupt driven mode where\r
- it is called as part of a receive handler called by the driver as a result of\r
- data being received. This function is non-blocking and will return 0\r
- immediately if no data has been received.\r
- NOTE: In interrupt driven mode you should call the MSS_UART_get_rx() function\r
- as part of the receive handler function that you register with the MSS UART\r
- driver through a call to MSS_UART_set_rx_handler().\r
- \r
- @param this_uart\r
- The this_uart parameter is a pointer to an mss_uart_instance_t structure\r
- identifying the MSS UART hardware block that will perform the requested\r
- function. There are two such data structures, g_mss_uart0 and g_mss_uart1,\r
- associated with MSS UART0 and MSS UART1. This parameter must point to either\r
- the g_mss_uart0 or g_mss_uart1 global data structure defined within the UART\r
- driver.\r
- \r
- @param rx_buff\r
- The rx_buff parameter is a pointer to a buffer where the received data will\r
- be copied.\r
- \r
- @param buff_size\r
- The buff_size parameter specifies the size of the receive buffer in bytes.\r
- \r
- @return\r
- This function return the number of bytes that were copied into the rx_buff\r
- buffer. It returns 0 if no data has been received.\r
- \r
- Polled mode example:\r
- @code\r
- int main( void )\r
- {\r
- uint8_t rx_buff[RX_BUFF_SIZE];\r
- uint32_t rx_idx = 0;\r
- \r
- MSS_UART_init( &g_mss_uart0, MSS_UART_57600_BAUD, MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT );\r
- \r
- while( 1 )\r
- {\r
- rx_size = MSS_UART_get_rx( &g_mss_uart0, rx_buff, sizeof(rx_buff) );\r
- if (rx_size > 0)\r
- {\r
- process_rx_data( rx_buff, rx_size );\r
- }\r
- task_a();\r
- task_b();\r
- }\r
- return 0;\r
- }\r
- @endcode\r
- \r
- Interrupt driven example:\r
- @code\r
- int main( void )\r
- {\r
- MSS_UART_init( &g_mss_uart1, MSS_UART_57600_BAUD, MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT );\r
- MSS_UART_set_rx_handler( &g_mss_uart1, uart1_rx_handler, MSS_UART_FIFO_SINGLE_BYTE );\r
- \r
- while( 1 )\r
- {\r
- task_a();\r
- task_b();\r
- }\r
- return 0;\r
- }\r
- \r
- void uart1_rx_handler( void )\r
- {\r
- uint8_t rx_buff[RX_BUFF_SIZE];\r
- uint32_t rx_idx = 0;\r
- rx_size = MSS_UART_get_rx( &g_mss_uart1, rx_buff, sizeof(rx_buff) );\r
- process_rx_data( rx_buff, rx_size );\r
- }\r
- @endcode\r
- */\r
-size_t\r
-MSS_UART_get_rx\r
-(\r
- mss_uart_instance_t * this_uart,\r
- uint8_t * rx_buff,\r
- size_t buff_size\r
-);\r
-\r
-/***************************************************************************//**\r
- The MSS_UART_set_rx_handler() function is used to register a receive handler\r
- function which will be called by the driver when a UART Received Data Available\r
- (RDA) interrupt occurs. You must create and register the handler function to\r
- suit your application. The MSS_UART_set_rx_handler() function also enables the UART\r
- Received Data Available interrupt and the UART instance interrupt in the\r
- Cortex-M3 NVIC as part of its implementation.\r
- \r
- @param this_uart\r
- The this_uart parameter is a pointer to an mss_uart_instance_t structure\r
- identifying the MSS UART hardware block that will perform the requested\r
- function. There are two such data structures, g_mss_uart0 and g_mss_uart1,\r
- associated with MSS UART0 and MSS UART1. This parameter must point to either\r
- the g_mss_uart0 or g_mss_uart1 global data structure defined within the UART\r
- driver.\r
- \r
- @param handler\r
- The handler parameter is a pointer to a receive handler function provided\r
- by your application which will be called as a result of a UART Received\r
- Data Available interrupt.\r
- \r
- @param trigger_level\r
- The trigger_level parameter is the receive FIFO trigger level. This specifies\r
- the number of bytes that must be received before the UART triggers a Received\r
- Data Available interrupt. \r
- \r
- @return\r
- This function does not return a value.\r
- \r
- Example:\r
- @code\r
- #include "mss_uart.h"\r
- \r
- #define RX_BUFF_SIZE 64\r
- \r
- uint8_t g_rx_buff[RX_BUFF_SIZE];\r
- \r
- void uart0_rx_handler( void )\r
- {\r
- MSS_UART_get_rx( &g_mss_uart, &g_rx_buff[g_rx_idx], sizeof(g_rx_buff) );\r
- }\r
- \r
- int main(void)\r
- {\r
- MSS_UART_init( &g_mss_uart0, MSS_UART_57600_BAUD, MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT );\r
- MSS_UART_set_rx_handler( &g_mss_uart0, uart0_rx_handler, MSS_UART_FIFO_SINGLE_BYTE );\r
- \r
- while ( 1 )\r
- {\r
- ;\r
- }\r
- return(0);\r
- }\r
- @endcode\r
- */\r
-void\r
-MSS_UART_set_rx_handler\r
-(\r
- mss_uart_instance_t * this_uart,\r
- mss_uart_rx_handler_t handler,\r
- mss_uart_rx_trig_level_t trigger_level\r
-);\r
-\r
-/***************************************************************************//**\r
- The MSS_UART_set_loopback() function is used to locally loopback the Tx and Rx\r
- lines of a UART.\r
- This is not to be confused with the loopback of UART0 to UART1 which can be\r
- achieved through the microcontroller subsystem's system registers\r
- \r
- @param this_uart\r
- The this_uart parameter is a pointer to an mss_uart_instance_t structure\r
- identifying the MSS UART hardware block that will perform the requested\r
- function. There are two such data structures, g_mss_uart0 and g_mss_uart1,\r
- associated with MSS UART0 and MSS UART1. This parameter must point to either\r
- the g_mss_uart0 or g_mss_uart1 global data structure defined within the UART\r
- driver.\r
- \r
- @param loopback\r
- The loopback parameter indicates whether or not the UART's transmit and receive lines\r
- should be looped back. Allowed values are:\r
- - MSS_UART_LOOPBACK_ON\r
- - MSS_UART_LOOPBACK_OFF\r
- @return\r
- This function does not return a value.\r
- */\r
-void\r
-MSS_UART_set_loopback\r
-(\r
- mss_uart_instance_t * this_uart,\r
- mss_uart_loopback_t loopback\r
-);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __MSS_UART_H_ */\r
#include "apps/httpd/httpd.h"\r
#include "apps/httpd/httpd-cgi.h"\r
#include "apps/httpd/httpd-fs.h"\r
+#include "mss_ace.h"\r
\r
#include <stdio.h>\r
#include <string.h>\r
static unsigned short generate_io_state( void *arg )\r
{\r
extern long lParTestGetLEDState( unsigned long ulLED );\r
+ unsigned short usRawVoltage;\r
+ const ace_channel_handle_t xVoltageChannel = ( ace_channel_handle_t ) 0;\r
+\r
( void ) arg;\r
\r
/* Are the dynamically setable LEDs currently on or off? */\r
pcStatus = "";\r
}\r
\r
- sprintf( uip_appdata, "<input type=\"checkbox\" name=\"LED0\" value=\"1\" %s>LED<p><p>", pcStatus );\r
+ usRawVoltage = ( unsigned short ) ACE_get_ppe_sample( xVoltageChannel ); \r
+ sprintf( uip_appdata, "<input type=\"checkbox\" name=\"LED0\" value=\"1\" %s>LED<p><p><p>Raw voltage input is %d", pcStatus, usRawVoltage );\r
\r
return strlen( uip_appdata );\r
}\r
xTaskCreate( prvQueueReceiveTask, ( signed char * ) "Rx", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_RECEIVE_TASK_PRIORITY, NULL );\r
xTaskCreate( prvQueueSendTask, ( signed char * ) "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL );\r
\r
- /* Create the software timer that is responsible for turning off the LED \r
- if the button is not pushed within 5000ms, as described at the top of \r
+ /* Create the software timer that is responsible for turning off the LED\r
+ if the button is not pushed within 5000ms, as described at the top of\r
this file. */\r
xLEDTimer = xTimerCreate( ( const signed char * ) "LEDTimer", /* A text name, purely to help debugging. */\r
( 5000 / portTICK_RATE_MS ), /* The timer period, in this case 5000ms (5s). */\r
if( ulReceivedValue == 100UL )\r
{\r
/* NOTE - accessing the LED port should use a critical section\r
- because it is accessed from multiple tasks, and the button interrupt \r
- - in this trivial case, for simplicity, the critical section is \r
+ because it is accessed from multiple tasks, and the button interrupt\r
+ - in this trivial case, for simplicity, the critical section is\r
omitted. */\r
if( ( ulGPIOState & mainTASK_CONTROLLED_LED ) != 0 )\r
{\r
\r
static void prvSetupHardware( void )\r
{\r
+ SystemCoreClockUpdate();\r
+\r
/* Disable the Watch Dog Timer */\r
MSS_WD_disable( );\r
\r
{\r
/* Called if a call to pvPortMalloc() fails because there is insufficient\r
free memory available in the FreeRTOS heap. pvPortMalloc() is called\r
- internally by FreeRTOS API functions that create tasks, queues, software \r
+ internally by FreeRTOS API functions that create tasks, queues, software\r
timers, and semaphores. The size of the FreeRTOS heap is set by the\r
configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */\r
for( ;; );\r
volatile size_t xFreeStackSpace;\r
\r
/* This function is called on each cycle of the idle task. In this case it\r
- does nothing useful, other than report the amout of FreeRTOS heap that \r
+ does nothing useful, other than report the amout of FreeRTOS heap that\r
remains unallocated. */\r
xFreeStackSpace = xPortGetFreeHeapSize();\r
\r
reduced accordingly. */\r
}\r
}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vMainConfigureTimerForRunTimeStats( void )\r
+{\r
+ /* This function is not used by the Blinky build configuration, but needs\r
+ to be defined as the Blinky and Full build configurations share a\r
+ FreeRTOSConfig.h header file. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+unsigned long ulGetRunTimeCounterValue( void )\r
+{\r
+ /* This function is not used by the Blinky build configuration, but needs\r
+ to be defined as the Blinky and Full build configurations share a\r
+ FreeRTOSConfig.h header file. */\r
+ return 0UL;\r
+}\r
+\r
#include "mss_gpio.h"\r
#include "mss_watchdog.h"\r
#include "mss_timer.h"\r
+#include "mss_ace.h"\r
#include "oled.h"\r
\r
/* Common demo includes. */\r
\r
/* Configure the GPIO for the LEDs. */\r
vParTestInitialise();\r
+ \r
+ /* ACE Initialization */\r
+ ACE_init();\r
\r
/* Setup the GPIO and the NVIC for the switch used in this simple demo. */\r
NVIC_SetPriority( GPIO8_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );\r
MSS_TIM64_start();\r
}\r
/*-----------------------------------------------------------*/\r
+\r
unsigned long ulGetRunTimeCounterValue( void )\r
{\r
unsigned long long ullCurrentValue;\r
void vuIP_Task( void *pvParameters )\r
{\r
portBASE_TYPE i;\r
-unsigned long ulNewEvent = 0UL;\r
-unsigned long ulUIP_Events = 0UL;\r
+unsigned long ulNewEvent = 0UL, ulUIP_Events = 0UL;\r
+long lPacketLength;\r
\r
/* Just to prevent compiler warnings about the unused parameter. */\r
( void ) pvParameters;\r
for( ;; )\r
{\r
/* Is there received data ready to be processed? */\r
- uip_len = MSS_MAC_rx_packet();\r
+ lPacketLength = MSS_MAC_rx_packet();\r
\r
/* Statements to be executed if data has been received on the Ethernet. */\r
- if( ( uip_len > 0 ) && ( uip_buf != NULL ) )\r
+ if( ( lPacketLength > 0 ) && ( uip_buf != NULL ) )\r
{\r
+ uip_len = ( u16_t ) lPacketLength;\r
+ \r
/* Standard uIP loop taken from the uIP manual. */\r
if( xHeader->type == htons( UIP_ETHTYPE_IP ) )\r
{\r
xEMACEventQueue = xQueueCreate( uipEVENT_QUEUE_LENGTH, sizeof( unsigned long ) );\r
\r
/* Create and start the uIP timers. */\r
- xARPTimer = xTimerCreate( ( const signed char * const ) "ARPTimer", /* Just a name that is helpful for debugging, not used by the kernel. */\r
+ xARPTimer = xTimerCreate( ( signed char * ) "ARPTimer", /* Just a name that is helpful for debugging, not used by the kernel. */\r
( 10000UL / portTICK_RATE_MS ), /* Timer period. */\r
pdTRUE, /* Autor-reload. */\r
( void * ) uipARP_TIMER,\r
prvUIPTimerCallback\r
);\r
\r
- xPeriodicTimer = xTimerCreate( ( const signed char * const ) "PeriodicTimer",\r
+ xPeriodicTimer = xTimerCreate( ( signed char * ) "PeriodicTimer",\r
( 500UL / portTICK_RATE_MS ),\r
pdTRUE, /* Autor-reload. */\r
( void * ) uipPERIODIC_TIMER,\r
{\r
const long lMaxAttempts = 10;\r
long lAttempt;\r
-const portTickType xShortDelay = ( 10 / portTICK_RATE_MS );\r
+const portTickType xShortDelay = ( 5 / portTICK_RATE_MS );\r
\r
/* Try to send data to the Ethernet. Keep trying for a while if data cannot\r
be sent immediately. Note that this will actually cause the data to be sent\r
projects / freertos / commitdiff