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+<scannerInfoProvider id="specsFile">\r
+<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>\r
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+</profile>\r
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+<buildOutputProvider>\r
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+<parser enabled="true"/>\r
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+<scannerInfoProvider id="specsFile">\r
+<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>\r
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+</profile>\r
+<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">\r
+<buildOutputProvider>\r
+<openAction enabled="true" filePath=""/>\r
+<parser enabled="true"/>\r
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+<scannerInfoProvider id="specsFile">\r
+<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>\r
+<parser enabled="true"/>\r
+</scannerInfoProvider>\r
+</profile>\r
+</scannerConfigBuildInfo>\r
+</storageModule>\r
+<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>\r
+<storageModule moduleId="org.eclipse.cdt.core.language.mapping"/>\r
+<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>\r
+</cconfiguration>\r
+</storageModule>\r
+<storageModule moduleId="cdtBuildSystem" version="4.0.0">\r
+<project id="RTOSDemo_RDB1768.com.crt.advproject.projecttype.exe.469488889" name="Executable" projectType="com.crt.advproject.projecttype.exe"/>\r
+</storageModule>\r
+<storageModule moduleId="com.crt.config">\r
+<projectStorage><?xml version="1.0" encoding="UTF-8"?> \r
+<TargetConfig> \r
+<Properties property_0="" property_1="" property_2="" property_3="NXP" property_4="LPC1768" property_count="5" version="1"/> \r
+<infoList vendor="NXP"><info chip="LPC1768" match_id="0x00013f37,0x26013F37" name="LPC1768" package="lpc17_lqfp100.xml"><chip><name>LPC1768</name> \r
+<family>LPC17xx</family> \r
+<vendor>NXP (formerly Philips)</vendor> \r
+<reset board="None" core="Real" sys="Real"/> \r
+<clock changeable="TRUE" freq="20MHz" is_accurate="TRUE"/> \r
+<memory can_program="true" id="Flash" is_ro="true" type="Flash"/> \r
+<memory id="RAM" type="RAM"/> \r
+<memory id="Periph" is_volatile="true" type="Peripheral"/> \r
+<memoryInstance derived_from="Flash" id="MFlash512" location="0x00000000" size="0x80000"/> \r
+<memoryInstance derived_from="RAM" id="RamLoc32" location="0x10000000" size="0x8000"/> \r
+<memoryInstance derived_from="RAM" id="RamAHB32" location="0x2007c000" size="0x8000"/> \r
+<prog_flash blocksz="0x1000" location="0" maxprgbuff="0x1000" progwithcode="TRUE" size="0x10000"/> \r
+<prog_flash blocksz="0x8000" location="0x10000" maxprgbuff="0x1000" progwithcode="TRUE" size="0x70000"/> \r
+<peripheralInstance derived_from="LPC17_NVIC" determined="infoFile" id="NVIC" location="0xE000E000"/> \r
+<peripheralInstance derived_from="TIMER" determined="infoFile" enable="SYSCTL.PCONP.PCTIM0&amp;0x1" id="TIMER0" location="0x40004000"/> \r
+<peripheralInstance derived_from="TIMER" determined="infoFile" enable="SYSCTL.PCONP.PCTIM1&amp;0x1" id="TIMER1" location="0x40008000"/> \r
+<peripheralInstance derived_from="TIMER" determined="infoFile" enable="SYSCTL.PCONP.PCTIM2&amp;0x1" id="TIMER2" location="0x40090000"/> \r
+<peripheralInstance derived_from="TIMER" determined="infoFile" enable="SYSCTL.PCONP.PCTIM3&amp;0x1" id="TIMER3" location="0x40094000"/> \r
+<peripheralInstance derived_from="FGPIO" determined="infoFile" enable="SYSCTL.PCONP.PCGPIO&amp;0x1" id="GPIO0" location="0x2009C000"/> \r
+<peripheralInstance derived_from="FGPIO" determined="infoFile" enable="SYSCTL.PCONP.PCGPIO&amp;0x1" id="GPIO1" location="0x2009C020"/> \r
+<peripheralInstance derived_from="FGPIO" determined="infoFile" enable="SYSCTL.PCONP.PCGPIO&amp;0x1" id="GPIO2" location="0x2009C040"/> \r
+<peripheralInstance derived_from="FGPIO" determined="infoFile" enable="SYSCTL.PCONP.PCGPIO&amp;0x1" id="GPIO3" location="0x2009C060"/> \r
+<peripheralInstance derived_from="FGPIO" determined="infoFile" enable="SYSCTL.PCONP.PCGPIO&amp;0x1" id="GPIO4" location="0x2009C080"/> \r
+<peripheralInstance derived_from="LPC17_I2S" determined="infoFile" enable="SYSCTL.PCONP&amp;0x08000000" id="I2S" location="0x400A8000"/> \r
+<peripheralInstance derived_from="LPC17_SYSCTL" determined="infoFile" id="SYSCTL" location="0x400FC000"/> \r
+<peripheralInstance derived_from="LPC17_DAC" determined="infoFile" enable="PCB.PINSEL1.P0_26&amp;0x2=2" id="DAC" location="0x4008C000"/> \r
+<peripheralInstance derived_from="LPC1xxx_UART" determined="infoFile" enable="SYSCTL.PCONP.PCUART0&amp;0x1" id="UART0" location="0x4000C000"/> \r
+<peripheralInstance derived_from="LPC1xxx_UART_MODEM" determined="infoFile" enable="SYSCTL.PCONP.PCUART1&amp;0x1" id="UART1" location="0x40010000"/> \r
+<peripheralInstance derived_from="LPC1xxx_UART" determined="infoFile" enable="SYSCTL.PCONP.PCUART2&amp;0x1" id="UART2" location="0x40098000"/> \r
+<peripheralInstance derived_from="LPC1xxx_UART" determined="infoFile" enable="SYSCTL.PCONP.PCAURT3&amp;0x1" id="UART3" location="0x4009C000"/> \r
+<peripheralInstance derived_from="SPI" determined="infoFile" enable="SYSCTL.PCONP.PCSPI&amp;0x1" id="SPI" location="0x40020000"/> \r
+<peripheralInstance derived_from="LPC17_SSP" determined="infoFile" enable="SYSCTL.PCONP.PCSSP0&amp;0x1" id="SSP0" location="0x40088000"/> \r
+<peripheralInstance derived_from="LPC17_SSP" determined="infoFile" enable="SYSCTL.PCONP.PCSSP1&amp;0x1" id="SSP1" location="0x40030000"/> \r
+<peripheralInstance derived_from="LPC17_ADC" determined="infoFile" enable="SYSCTL.PCONP.PCAD&amp;0x1" id="ADC" location="0x40034000"/> \r
+<peripheralInstance derived_from="LPC17_USBINTST" determined="infoFile" enable="USBCLKCTL.USBClkCtrl&amp;0x12" id="USBINTSTAT" location="0x400fc1c0"/> \r
+<peripheralInstance derived_from="LPC17_USB_CLK_CTL" determined="infoFile" id="USBCLKCTL" location="0x5000cff4"/> \r
+<peripheralInstance derived_from="LPC17_USBDEV" determined="infoFile" enable="USBCLKCTL.USBClkSt&amp;0x12=0x12" id="USBDEV" location="0x5000C200"/> \r
+<peripheralInstance derived_from="LPC17_PWM" determined="infoFile" enable="SYSCTL.PCONP.PWM1&amp;0x1" id="PWM" location="0x40018000"/> \r
+<peripheralInstance derived_from="LPC17_I2C" determined="infoFile" enable="SYSCTL.PCONP.PCI2C0&amp;0x1" id="I2C0" location="0x4001C000"/> \r
+<peripheralInstance derived_from="LPC17_I2C" determined="infoFile" enable="SYSCTL.PCONP.PCI2C1&amp;0x1" id="I2C1" location="0x4005C000"/> \r
+<peripheralInstance derived_from="LPC17_I2C" determined="infoFile" enable="SYSCTL.PCONP.PCI2C2&amp;0x1" id="I2C2" location="0x400A0000"/> \r
+<peripheralInstance derived_from="LPC17_DMA" determined="infoFile" enable="SYSCTL.PCONP.PCGPDMA&amp;0x1" id="DMA" location="0x50004000"/> \r
+<peripheralInstance derived_from="LPC17_ENET" determined="infoFile" enable="SYSCTL.PCONP.PCENET&amp;0x1" id="ENET" location="0x50000000"/> \r
+<peripheralInstance derived_from="CM3_DCR" determined="infoFile" id="DCR" location="0xE000EDF0"/> \r
+<peripheralInstance derived_from="LPC17_PCB" determined="infoFile" id="PCB" location="0x4002c000"/> \r
+<peripheralInstance derived_from="LPC17_QEI" determined="infoFile" enable="SYSCTL.PCONP.PCQEI&amp;0x1" id="QEI" location="0x400bc000"/> \r
+<peripheralInstance derived_from="LPC17_USBHOST" determined="infoFile" enable="USBCLKCTL.USBClkSt&amp;0x11=0x11" id="USBHOST" location="0x5000C000"/> \r
+<peripheralInstance derived_from="LPC17_USBOTG" determined="infoFile" enable="USBCLKCTL.USBClkSt&amp;0x1c=0x1c" id="USBOTG" location="0x5000C000"/> \r
+<peripheralInstance derived_from="LPC17_RTC" determined="infoFile" enable="SYSCTL.PCONP.PCRTC&amp;0x1" id="RTC" location="0x40024000"/> \r
+<peripheralInstance derived_from="MPU" determined="infoFile" id="MPU" location="0xE000ED90"/> \r
+<peripheralInstance derived_from="LPC1x_WDT" determined="infoFile" id="WDT" location="0x40000000"/> \r
+</chip> \r
+<processor><name gcc_name="cortex-m3">Cortex-M3</name> \r
+<family>Cortex-M</family> \r
+</processor> \r
+<link href="nxp_lpcxxxx_peripheral.xme" show="embed" type="simple"/> \r
+</info> \r
+</infoList> \r
+</TargetConfig></projectStorage>\r
+</storageModule>\r
+</cproject>\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
+<projectDescription>\r
+ <name>RTOSDemo_MPU_RDB1768</name>\r
+ <comment></comment>\r
+ <projects>\r
+ </projects>\r
+ <buildSpec>\r
+ <buildCommand>\r
+ <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>\r
+ <triggers>clean,full,incremental,</triggers>\r
+ <arguments>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.cleanBuildTarget</key>\r
+ <value>clean</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.enableCleanBuild</key>\r
+ <value>true</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.append_environment</key>\r
+ <value>true</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>?name?</key>\r
+ <value></value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.stopOnError</key>\r
+ <value>true</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.buildCommand</key>\r
+ <value>make</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.contents</key>\r
+ <value>org.eclipse.cdt.make.core.activeConfigSettings</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.buildLocation</key>\r
+ <value>${workspace_loc:/RTOSDemo_RDB1768/Debug}</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>\r
+ <value>true</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.enableFullBuild</key>\r
+ <value>true</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.enableAutoBuild</key>\r
+ <value>false</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.fullBuildTarget</key>\r
+ <value>all</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.buildArguments</key>\r
+ <value></value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.autoBuildTarget</key>\r
+ <value>all</value>\r
+ </dictionary>\r
+ </arguments>\r
+ </buildCommand>\r
+ <buildCommand>\r
+ <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>\r
+ <arguments>\r
+ </arguments>\r
+ </buildCommand>\r
+ </buildSpec>\r
+ <natures>\r
+ <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>\r
+ <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>\r
+ <nature>org.eclipse.cdt.core.cnature</nature>\r
+ </natures>\r
+</projectDescription>\r
--- /dev/null
+REM This file should be executed from the command line prior to the first\r
+REM build. It will be necessary to refresh the Eclipse project once the\r
+REM .bat file has been executed (normally just press F5 to refresh).\r
+\r
+REM Copies all the required files from their location within the standard\r
+REM FreeRTOS directory structure to under the Eclipse project directory.\r
+REM This permits the Eclipse project to be used in 'managed' mode and without\r
+REM having to setup any linked resources.\r
+\r
+REM Have the files already been copied?\r
+IF EXIST src\FreeRTOS Goto END\r
+\r
+ REM Create the required directory structure.\r
+ MD src\FreeRTOS\r
+ MD src\FreeRTOS\include \r
+ MD src\FreeRTOS\portable\GCC\ARM_CM3_MPU\r
+ MD src\FreeRTOS\portable\MemMang \r
+ \r
+ REM Copy the core kernel files.\r
+ copy ..\..\Source\tasks.c src\FreeRTOS\r
+ copy ..\..\Source\queue.c src\FreeRTOS\r
+ copy ..\..\Source\list.c src\FreeRTOS\r
+ \r
+ REM Copy the common header files\r
+\r
+ copy ..\..\Source\include\*.* src\FreeRTOS\include\r
+ \r
+ REM Copy the portable layer files\r
+ copy ..\..\Source\portable\GCC\ARM_CM3_MPU\*.* src\FreeRTOS\portable\GCC\ARM_CM3_MPU\r
+ \r
+ REM Copy the basic memory allocation files\r
+ copy ..\..\Source\portable\MemMang\heap_2.c src\FreeRTOS\portable\MemMang\r
+\r
+: END
\ No newline at end of file
--- /dev/null
+/*\r
+ FreeRTOS V5.4.2 - Copyright (C) 2009 Real Time Engineers Ltd.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under \r
+ the terms of the GNU General Public License (version 2) as published by the \r
+ Free Software Foundation and modified by the FreeRTOS exception.\r
+ **NOTE** The exception to the GPL is included to allow you to distribute a\r
+ combined work that includes FreeRTOS without being obliged to provide the \r
+ source code for proprietary components outside of the FreeRTOS kernel. \r
+ Alternative commercial license and support terms are also available upon \r
+ request. See the licensing section of http://www.FreeRTOS.org for full \r
+ license details.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT\r
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details.\r
+\r
+ You should have received a copy of the GNU General Public License along\r
+ with FreeRTOS; if not, write to the Free Software Foundation, Inc., 59\r
+ Temple Place, Suite 330, Boston, MA 02111-1307 USA.\r
+\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * Looking for a quick start? Then check out the FreeRTOS eBook! *\r
+ * See http://www.FreeRTOS.org/Documentation for details *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ Please ensure to read the configuration and relevant port sections of the\r
+ online documentation.\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+#include "LPC17xx.h"\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 0\r
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )\r
+#define configUSE_TICK_HOOK 1\r
+#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 99000000 )\r
+#define configTICK_RATE_HZ ( ( portTickType ) 1000 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 80 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 5 * 1024 ) )\r
+#define configMAX_TASK_NAME_LEN ( 12 )\r
+#define configUSE_TRACE_FACILITY 1\r
+#define configUSE_16_BIT_TICKS 0\r
+#define configIDLE_SHOULD_YIELD 0\r
+#define configUSE_CO_ROUTINES 0\r
+#define configUSE_MUTEXES 1\r
+\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+#define configUSE_COUNTING_SEMAPHORES 0\r
+#define configUSE_ALTERNATIVE_API 0\r
+#define configCHECK_FOR_STACK_OVERFLOW 0\r
+#define configUSE_RECURSIVE_MUTEXES 1\r
+#define configQUEUE_REGISTRY_SIZE 10\r
+#define configGENERATE_RUN_TIME_STATS 0\r
+#define configUSE_MALLOC_FAILED_HOOK 1\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 1\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskCleanUpResources 0\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+#define INCLUDE_uxTaskGetStackHighWaterMark 1\r
+\r
+/* Use the system definition, if there is one */\r
+#ifdef __NVIC_PRIO_BITS\r
+ #define configPRIO_BITS __NVIC_PRIO_BITS\r
+#else\r
+ #define configPRIO_BITS 5 /* 32 priority levels */\r
+#endif\r
+\r
+/* The lowest priority. */\r
+#define configKERNEL_INTERRUPT_PRIORITY ( 31 << (8 - configPRIO_BITS) )\r
+/* Priority 5, or 160 as only the top three bits are implemented. */\r
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( 5 << (8 - configPRIO_BITS) )\r
+\r
+\r
+#define pvPortMallocAligned( x, puxStackBuffer ) ( ( puxStackBuffer == NULL ) ? ( pvPortMalloc( x ) ) : ( puxStackBuffer ) )\r
+#define vPortFreeAligned( x ) ( void ) x\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
--- /dev/null
+//*****************************************************************************\r
+// +--+ \r
+// | ++----+ \r
+// +-++ | \r
+// | | \r
+// +-+--+ | \r
+// | +--+--+ \r
+// +----+ Copyright (c) 2009 Code Red Technologies Ltd. \r
+//\r
+// font.h - header file for font data contained in system_fixed_be_8_15.c\r
+//\r
+// Software License Agreement\r
+// \r
+// The software is owned by Code Red Technologies and/or its suppliers, and is \r
+// protected under applicable copyright laws. All rights are reserved. Any \r
+// use in violation of the foregoing restrictions may subject the user to criminal \r
+// sanctions under applicable laws, as well as to civil liability for the breach \r
+// of the terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// USE OF THIS SOFTWARE FOR COMMERCIAL DEVELOPMENT AND/OR EDUCATION IS SUBJECT\r
+// TO A CURRENT END USER LICENSE AGREEMENT (COMMERCIAL OR EDUCATIONAL) WITH\r
+// CODE RED TECHNOLOGIES LTD. \r
+\r
+#ifndef FONT_H_\r
+#define FONT_H_\r
+\r
+extern const unsigned char font_data_table[];\r
+extern const unsigned char font_index_table[];\r
+\r
+#endif /*FONT_H_*/\r
--- /dev/null
+//*****************************************************************************\r
+// +--+ \r
+// | ++----+ \r
+// +-++ | \r
+// | | \r
+// +-+--+ | \r
+// | +--+--+ \r
+// +----+ Copyright (c) 2009 Code Red Technologies Ltd. \r
+//\r
+// lcd.c contains various routines to plot to the LCD display on the RDB1768\r
+// development board.\r
+//\r
+// Software License Agreement\r
+// \r
+// The software is owned by Code Red Technologies and/or its suppliers, and is \r
+// protected under applicable copyright laws. All rights are reserved. Any \r
+// use in violation of the foregoing restrictions may subject the user to criminal \r
+// sanctions under applicable laws, as well as to civil liability for the breach \r
+// of the terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// USE OF THIS SOFTWARE FOR COMMERCIAL DEVELOPMENT AND/OR EDUCATION IS SUBJECT\r
+// TO A CURRENT END USER LICENSE AGREEMENT (COMMERCIAL OR EDUCATIONAL) WITH\r
+// CODE RED TECHNOLOGIES LTD. \r
+\r
+#include "lcd_commands.h"\r
+#include "lcd.h"\r
+#include "lcd_driver.h"\r
+#include "font.h"\r
+\r
+#include <stdlib.h> // to provice abs() function\r
+\r
+// Routine to draw a filled rectangle to the LCD.\r
+// Two corners of rectangle are at (xmin,ymin) and (xmax,ymax).\r
+// The Rectangle is filled with the RGB565 color specified\r
+void LCD_FilledRect(int xmin,int xmax,int ymin,int ymax,int color)\r
+{\r
+ int i;\r
+\r
+ // Specify to LCD controller coordinates we are writing to...\r
+ LCDdriver_WriteCom(DD_CASET); // Set the column address\r
+ LCDdriver_WriteData(xmin); // min address\r
+ LCDdriver_WriteData(xmax); // max address\r
+ LCDdriver_WriteCom(DD_RASET); // Set the row address\r
+ LCDdriver_WriteData(ymin + 1); // min address\r
+ LCDdriver_WriteData(ymax + 1); // max address\r
+ LCDdriver_WriteCom(DD_RAMWR); // RAM Write command\r
+\r
+ // Plot the color data to the LCD buffer\r
+ for(i = ((xmax - xmin + 1) * (ymax - ymin + 1)); i > 0; i--)\r
+ {\r
+ LCDdriver_WriteData(color >> 8); // top 8 bits of RGB565 color\r
+ LCDdriver_WriteData(color); // bottom 8 bits of RGB565 color\r
+ }\r
+}\r
+\r
+// Routine to draw an unfilled rectangle to the LCD.\r
+// Two corners of rectangle are at (xmin,ymin) and (xmax,ymax).\r
+// The Rectangle is drawn in the RGB565 color specified\r
+void LCD_Rect(int xmin,int xmax,int ymin,int ymax,int color)\r
+{\r
+ // Draw 4 lines of rectange as 4 filled rectanges, each of 1 pixel wide\r
+ LCD_FilledRect(xmin,xmin,ymin,ymax,color);\r
+ LCD_FilledRect(xmax,xmax,ymin,ymax,color);\r
+ LCD_FilledRect(xmin,xmax,ymin,ymin,color);\r
+ LCD_FilledRect(xmin,xmax,ymax,ymax,color);\r
+}\r
+\r
+\r
+\r
+// Plot a point on the screen in the 6:5:6 color format\r
+void LCD_PlotPoint(int x,int y,int color)\r
+{\r
+ LCDdriver_WriteCom(DD_CASET); // Set the column address \r
+ LCDdriver_WriteData(x); // min address\r
+ LCDdriver_WriteData(x); // max address\r
+ LCDdriver_WriteCom(DD_RASET); // Set the row address\r
+ LCDdriver_WriteData(y + 1); // min address\r
+ LCDdriver_WriteData(y + 1); // max address\r
+ LCDdriver_WriteCom(DD_RAMWR); // RAM Write command\r
+ LCDdriver_WriteData(color >> 8); // top 8 bits of RGB565 color\r
+ LCDdriver_WriteData(color); // top 8 bits of RGB565 color\r
+}\r
+\r
+// Routine to draw a filled circle to the LCD.\r
+// The centre of the circle is at (x0,y0) and the circle has the \r
+// specifed radius. The circle is filled with the RGB565 color \r
+// The circle is drawn using the "Midpoint circle algorithm", \r
+// also known as "Bresenham's circle algorithm". In order to fill\r
+// the circle, the algorithm has been modifed to draw a line between\r
+// each two points, rather than plotting the two points individually.\r
+void LCD_FilledCircle (int x0, int y0, int radius, int color)\r
+{\r
+ int f = 1 - radius;\r
+ int ddF_x = 1;\r
+ int ddF_y = -2 * radius;\r
+ int x = 0;\r
+ int y = radius;\r
+ \r
+ LCD_FilledRect(x0, x0 ,y0 - radius,y0 + radius, color); \r
+ LCD_FilledRect(x0 - radius, x0 + radius ,y0,y0, color); \r
+ \r
+ while(x < y)\r
+ {\r
+ if(f >= 0) \r
+ {\r
+ y--;\r
+ ddF_y += 2;\r
+ f += ddF_y;\r
+ }\r
+ x++;\r
+ ddF_x += 2;\r
+ f += ddF_x; \r
+\r
+ LCD_FilledRect(x0-x, x0+x ,y0 +y, y0 + y, color); \r
+ LCD_FilledRect(x0-x, x0+x ,y0 - y, y0 - y, color); \r
+ LCD_FilledRect(x0-y, x0+y ,y0 + x, y0 + x, color); \r
+ LCD_FilledRect(x0-y, x0+y ,y0 - x, y0 - x, color); \r
+ }\r
+}\r
+\r
+// Routine to draw an unfilled circle to the LCD.\r
+// The centre of the circle is at (x0,y0) and the circle has the \r
+// specifed radius. The circle is drawn in the RGB565 color \r
+// The circle is drawn using the "Midpoint circle algorithm", \r
+// also known as "Bresenham's circle algorithm". \r
+void LCD_Circle (int x0, int y0, int radius, int color)\r
+{\r
+ int f = 1 - radius;\r
+ int ddF_x = 1;\r
+ int ddF_y = -2 * radius;\r
+ int x = 0;\r
+ int y = radius;\r
+\r
+ LCD_PlotPoint(x0, y0 + radius, color);\r
+ LCD_PlotPoint(x0, y0 - radius, color);\r
+ LCD_PlotPoint(x0 + radius, y0, color);\r
+ LCD_PlotPoint(x0 - radius, y0, color);\r
+\r
+ while(x < y)\r
+ {\r
+ if(f >= 0) \r
+ {\r
+ y--;\r
+ ddF_y += 2;\r
+ f += ddF_y;\r
+ }\r
+ x++;\r
+ ddF_x += 2;\r
+ f += ddF_x; \r
+ LCD_PlotPoint(x0 + x, y0 + y, color);\r
+ LCD_PlotPoint(x0 - x, y0 + y, color);\r
+ LCD_PlotPoint(x0 + x, y0 - y, color);\r
+ LCD_PlotPoint(x0 - x, y0 - y, color);\r
+ LCD_PlotPoint(x0 + y, y0 + x, color);\r
+ LCD_PlotPoint(x0 - y, y0 + x, color);\r
+ LCD_PlotPoint(x0 + y, y0 - x, color);\r
+ LCD_PlotPoint(x0 - y, y0 - x, color);\r
+ }\r
+}\r
+\r
+// Routine to draw a line in the RGB565 color to the LCD.\r
+// The line is drawn from (xmin,ymin) to (xmax,ymax).\r
+// The algorithm used to draw the line is "Bresenham's line\r
+// algorithm". \r
+#define SWAP(a, b) a ^= b; b ^= a; a ^= b; \r
+\r
+void LCD_Line (int xmin,int xmax,int ymin,int ymax,int color)\r
+{\r
+ int Dx = xmax - xmin; \r
+ int Dy = ymax - ymin;\r
+ int steep = (abs(Dy) >= abs(Dx));\r
+ if (steep) {\r
+ SWAP(xmin, ymin);\r
+ SWAP(xmax, ymax);\r
+ // recompute Dx, Dy after swap\r
+ Dx = xmax - xmin;\r
+ Dy = ymax - ymin;\r
+ }\r
+ int xstep = 1;\r
+ if (Dx < 0) {\r
+ xstep = -1;\r
+ Dx = -Dx;\r
+ }\r
+ int ystep = 1;\r
+ if (Dy < 0) {\r
+ ystep = -1; \r
+ Dy = -Dy; \r
+ }\r
+ int TwoDy = 2*Dy; \r
+ int TwoDyTwoDx = TwoDy - 2*Dx; // 2*Dy - 2*Dx\r
+ int E = TwoDy - Dx; //2*Dy - Dx\r
+ int y = ymin;\r
+ int xDraw, yDraw;\r
+ int x;\r
+ for (x = xmin; x != xmax; x += xstep) { \r
+ if (steep) { \r
+ xDraw = y;\r
+ yDraw = x;\r
+ } else { \r
+ xDraw = x;\r
+ yDraw = y;\r
+ }\r
+ // plot\r
+ LCD_PlotPoint(xDraw, yDraw, color);\r
+ // next\r
+ if (E > 0) {\r
+ E += TwoDyTwoDx; //E += 2*Dy - 2*Dx;\r
+ y = y + ystep;\r
+ } else {\r
+ E += TwoDy; //E += 2*Dy;\r
+ }\r
+ }\r
+}\r
+\r
+// Routine to clear the LCD.\r
+// Implemented by drawing a black rectangle across the whole screen\r
+void LCD_ClearScreen(void)\r
+{ \r
+ LCD_FilledRect (0,LCD_MAX_X,0 , LCD_MAX_Y, COLOR_BLACK);\r
+}\r
+\r
+\r
+\r
+// Routine to write a single character to screen in the font pointed\r
+// to by pBitMap. This routine is intended to be used via the \r
+// LCD_PrintChar() and LCD_PrintString() routines, rather than called\r
+// directly from user code.\r
+void LCD_WriteBitMap8x15(int x, int y, int height, int width, unsigned char *pBitMap, int color)\r
+{\r
+ int xmax = x + width - 1; // start at zero\r
+ int ymax = y + height - 1; // start at zero\r
+ int iRow, iCol;\r
+ unsigned char ucRowData;\r
+ \r
+ LCDdriver_WriteCom(DD_CASET); // Column address set\r
+ LCDdriver_WriteData(x); // Start column\r
+ LCDdriver_WriteData(xmax); // End column\r
+ LCDdriver_WriteCom(DD_RASET); // Row address set\r
+ LCDdriver_WriteData(y); // Start row\r
+ LCDdriver_WriteData(ymax); // End row\r
+ LCDdriver_WriteCom(DD_RAMWR); // Memory write\r
+ \r
+ \r
+ for(iRow=0;iRow<height;iRow++)\r
+ {\r
+ ucRowData = *pBitMap++;\r
+ \r
+ for(iCol=0;iCol<width;iCol++)\r
+ {\r
+\r
+ // Look at each input bitmap bit\r
+ // and write as a black-pixel or\r
+ // a color-pixel.\r
+ \r
+ if(ucRowData & 0x80) // 'color pixel'\r
+ {\r
+ LCDdriver_WriteData(color >> 8); \r
+ LCDdriver_WriteData(color);\r
+ }\r
+ else // black pixel\r
+ {\r
+ LCDdriver_WriteData(0x00);\r
+ LCDdriver_WriteData(0x00);\r
+ }\r
+ \r
+ ucRowData = ucRowData<<1;\r
+ }\r
+ }\r
+\r
+}\r
+\r
+\r
+// Prints the character 'c' to the LCD in the appropriate color.\r
+void LCD_PrintChar(int x, int y, unsigned char c, int color )\r
+{\r
+ const unsigned char index = font_index_table[c];\r
+ const unsigned int offset = index * 15;\r
+ unsigned char *pData = (unsigned char *)&font_data_table[offset]; \r
+\r
+ LCD_WriteBitMap8x15(x, y, 15, 8, pData, color);\r
+}\r
+\r
+// Prints the string to the LCD in the appropriate color.\r
+void LCD_PrintString(int x, int y, char *pcString, int iStrLen, int color)\r
+{\r
+ unsigned char index;\r
+ unsigned int offset;\r
+ unsigned char *pData;\r
+ unsigned char c;\r
+ int i;\r
+ \r
+ for(i=0;i<iStrLen;i++)\r
+ {\r
+ c = pcString[i];\r
+ if(c==0)\r
+ break;\r
+ index = font_index_table[c];\r
+ offset = index * 15;\r
+ pData = (unsigned char *)&font_data_table[offset];\r
+\r
+ LCD_WriteBitMap8x15(x, y, 15, 8, pData, color); \r
+ x += 8;\r
+ }\r
+ \r
+}
\ No newline at end of file
--- /dev/null
+//*****************************************************************************\r
+// +--+ \r
+// | ++----+ \r
+// +-++ | \r
+// | | \r
+// +-+--+ | \r
+// | +--+--+ \r
+// +----+ Copyright (c) 2009 Code Red Technologies Ltd. \r
+//\r
+// lcd.h - Routines containing primitives for writing to the LCD\r
+//\r
+//\r
+// Software License Agreement\r
+// \r
+// The software is owned by Code Red Technologies and/or its suppliers, and is \r
+// protected under applicable copyright laws. All rights are reserved. Any \r
+// use in violation of the foregoing restrictions may subject the user to criminal \r
+// sanctions under applicable laws, as well as to civil liability for the breach \r
+// of the terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// USE OF THIS SOFTWARE FOR COMMERCIAL DEVELOPMENT AND/OR EDUCATION IS SUBJECT\r
+// TO A CURRENT END USER LICENSE AGREEMENT (COMMERCIAL OR EDUCATIONAL) WITH\r
+// CODE RED TECHNOLOGIES LTD. \r
+\r
+\r
+#ifndef LCD_H_\r
+#define LCD_H_\r
+\r
+// Define size of LCD screen.\r
+\r
+#define LCD_MAX_X 128\r
+#define LCD_MAX_Y 128\r
+\r
+// Translates a 24-bit RGB color to RGB565\r
+#define TRANSLATE24BIT_TO_RGB565(c) ((((c) & 0x00ff0000) >> 19) | \\r
+ ((((c) & 0x0000ff00) >> 5) & 0x000007e0) | \\r
+ ((((c) & 0x000000ff) << 8) & 0x0000f800))\r
+\r
+// Define a basic set of 24bit colors, based on the standard "websafe" set\r
+#define COLOR24_AQUA 0x00FFFF\r
+#define COLOR24_GREY 0x808080\r
+#define COLOR24_NAVY 0x000080 \r
+#define COLOR24_SILVER 0xC0C0C0\r
+#define COLOR24_BLACK 0x000000 \r
+#define COLOR24_GREEN 0x008000 \r
+#define COLOR24_OLIVE 0x808000 \r
+#define COLOR24_TEAL 0x008080\r
+#define COLOR24_BLUE 0x0000FF \r
+#define COLOR24_LIME 0x00FF00 \r
+#define COLOR24_PURPLE 0x800080 \r
+#define COLOR24_WHITE 0xFFFFFF\r
+#define COLOR24_FUCHSIA 0xFF00FF \r
+#define COLOR24_MAROON 0x800000 \r
+#define COLOR24_RED 0xFF0000\r
+#define COLOR24_YELLOW 0xFFFF00\r
+\r
+// Create a set of RGB565 colors that can be used directly within code\r
+#define COLOR_AQUA TRANSLATE24BIT_TO_RGB565(COLOR24_AQUA)\r
+#define COLOR_GREY TRANSLATE24BIT_TO_RGB565(COLOR24_GREY)\r
+#define COLOR_NAVY TRANSLATE24BIT_TO_RGB565(COLOR24_NAVY) \r
+#define COLOR_SILVER TRANSLATE24BIT_TO_RGB565(COLOR24_SILVER)\r
+#define COLOR_BLACK TRANSLATE24BIT_TO_RGB565(COLOR24_BLACK) \r
+#define COLOR_GREEN TRANSLATE24BIT_TO_RGB565(COLOR24_GREEN) \r
+#define COLOR_OLIVE TRANSLATE24BIT_TO_RGB565(COLOR24_OLIVE) \r
+#define COLOR_TEAL TRANSLATE24BIT_TO_RGB565(COLOR24_TEAL)\r
+#define COLOR_BLUE TRANSLATE24BIT_TO_RGB565(COLOR24_BLUE) \r
+#define COLOR_LIME TRANSLATE24BIT_TO_RGB565(COLOR24_LIME) \r
+#define COLOR_PURPLE TRANSLATE24BIT_TO_RGB565(COLOR24_PURPLE) \r
+#define COLOR_WHITE TRANSLATE24BIT_TO_RGB565(COLOR24_WHITE)\r
+#define COLOR_FUCHSIA TRANSLATE24BIT_TO_RGB565(COLOR24_FUCHSIA) \r
+#define COLOR_MAROON TRANSLATE24BIT_TO_RGB565(COLOR24_MAROON) \r
+#define COLOR_RED TRANSLATE24BIT_TO_RGB565(COLOR24_RED)\r
+#define COLOR_YELLOW TRANSLATE24BIT_TO_RGB565(COLOR24_YELLOW)\r
+\r
+\r
+void LCD_Line (int xmin,int xmax,int ymin,int ymax,int color);\r
+void LCD_FilledRect(int xmin,int xmax,int ymin,int ymax,int color);\r
+void LCD_Rect(int xmin,int xmax,int ymin,int ymax,int color);\r
+void LCD_WriteBitMap8x15(int x, int y, int height, int width, unsigned char *pBitMap, int color);\r
+void LCD_PlotPoint(int x,int y,int color);\r
+void LCD_Circle (int x0, int y0, int radius, int color);\r
+void LCD_FilledCircle (int x0, int y0, int radius, int color);\r
+void LCD_ClearScreen(void);\r
+void LCD_WriteBitMap8x15(int x, int y, int height, int width, unsigned char *pBitMap, int color);\r
+void LCD_PrintChar(int x, int y, unsigned char c, int color );\r
+void LCD_PrintString(int x, int y, char *pcString, int iStrLen, int color);\r
+\r
+\r
+#endif /*LCD_H_*/
\ No newline at end of file
--- /dev/null
+//*****************************************************************************\r
+// +--+ \r
+// | ++----+ \r
+// +-++ | \r
+// | | \r
+// +-+--+ | \r
+// | +--+--+ \r
+// +----+ Copyright (c) 2009 Code Red Technologies Ltd. \r
+//\r
+// lcd_commands.h contains defines mapping onto the commands accepted by the\r
+// Sitronix ST7637 LCD Controller/driver used on the RDB1768 development board.//\r
+//\r
+// Software License Agreement\r
+// \r
+// The software is owned by Code Red Technologies and/or its suppliers, and is \r
+// protected under applicable copyright laws. All rights are reserved. Any \r
+// use in violation of the foregoing restrictions may subject the user to criminal \r
+// sanctions under applicable laws, as well as to civil liability for the breach \r
+// of the terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// USE OF THIS SOFTWARE FOR COMMERCIAL DEVELOPMENT AND/OR EDUCATION IS SUBJECT\r
+// TO A CURRENT END USER LICENSE AGREEMENT (COMMERCIAL OR EDUCATIONAL) WITH\r
+// CODE RED TECHNOLOGIES LTD. \r
+\r
+#ifndef LCD_COMMANDS_H_\r
+#define LCD_COMMANDS_H_\r
+\r
+#define DD_NOP 0x00\r
+#define DD_SWRESET 0x01 //SW reset the display\r
+#define DD_SLPIN 0x10 //Sleep in and booster off\r
+#define DD_SLPOUT 0x11 //Sleep out and booster on\r
+#define DD_NORON 0x13 //Partial mode off (Normal mode on)\r
+#define DD_DISPOFF 0x28 //Display Off\r
+#define DD_DISPON 0x29 //Display On\r
+#define DD_CASET 0x2a //Column address set\r
+#define DD_RASET 0x2b //Row address set\r
+#define DD_RAMWR 0x2c //Memory write\r
+#define DD_MADCTR 0x36 //Memory Data Access Control\r
+#define DD_COLORMOD 0x3a //Set the color mode for the display \r
+#define DD_ColScanDir 0xb7 //Set the column scanning direction\r
+#define DD_VopSet 0xc0 //LCD supply voltage set\r
+#define DD_BiasSel 0xc3 //Bias selection\r
+#define DD_BstMbpXSel 0xc4 //Booster setting\r
+#define DD_AUTOLOADSET 0xd7 //Control auto load of ROM data\r
+#define DD_EPCTIN 0xe0 //OTP control RD/WR\r
+#define DD_EPREAD 0xe3 //OTP read\r
+#define DD_EPCTOUT 0xe1 //OTP control cancel\r
+\r
+\r
+#endif /*LCD_COMMANDS_H_*/\r
--- /dev/null
+//*****************************************************************************\r
+// +--+ \r
+// | ++----+ \r
+// +-++ | \r
+// | | \r
+// +-+--+ | \r
+// | +--+--+ \r
+// +----+ Copyright (c) 2009 Code Red Technologies Ltd. \r
+//\r
+// lcd_driver.c contains the lowest level access routines for the Sitronix\r
+// ST7637 LCD Controller/driver used on the RDB1768 development board.\r
+//\r
+//\r
+// Software License Agreement\r
+// \r
+// The software is owned by Code Red Technologies and/or its suppliers, and is \r
+// protected under applicable copyright laws. All rights are reserved. Any \r
+// use in violation of the foregoing restrictions may subject the user to criminal \r
+// sanctions under applicable laws, as well as to civil liability for the breach \r
+// of the terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// USE OF THIS SOFTWARE FOR COMMERCIAL DEVELOPMENT AND/OR EDUCATION IS SUBJECT\r
+// TO A CURRENT END USER LICENSE AGREEMENT (COMMERCIAL OR EDUCATIONAL) WITH\r
+// CODE RED TECHNOLOGIES LTD. \r
+\r
+#include "NXP/LPC17xx/LPC17xx.h"\r
+#include "lcd_driver.h"\r
+#include "lcd_commands.h"\r
+\r
+// Bits within GPIO port 2 used for LCD driver\r
+#define LCD_CSB_PIN (1<<13)\r
+#define LCD_A0_PIN (1<<8)\r
+#define LCD_WR_PIN (1<<11)\r
+#define LCD_RD_PIN (1<<12)\r
+#define LCD_DATA_PIN 0xff\r
+\r
+// Bit within GPIO port 3 used for LCD driver\r
+#define LCD_RESB_PIN (1<<25)\r
+\r
+// Bits to configure as outputs for driving LCD\r
+#define LCD_PORT2_DIRECTIONS (LCD_CSB_PIN | LCD_A0_PIN | LCD_WR_PIN | LCD_RD_PIN | LCD_DATA_PIN)\r
+#define LCD_PORT3_DIRECTIONS (LCD_RESB_PIN)\r
+\r
+// Define names for GPIO port 2 and 3 registers to better indicate in code\r
+// the operation being carried out on the LCD driver hardware.\r
+#define LCD_DATA_CLR FIO2CLR\r
+#define LCD_DATA_SET FIO2SET\r
+\r
+#define LCD_CSB_CLR FIO2CLR\r
+#define LCD_CSB_SET FIO2SET\r
+\r
+#define LCD_RESB_CLR FIO3CLR\r
+#define LCD_RESB_SET FIO3SET\r
+\r
+#define LCD_A0_CLR FIO2CLR\r
+#define LCD_A0_SET FIO2SET\r
+\r
+#define LCD_WR_CLR FIO2CLR\r
+#define LCD_WR_SET FIO2SET\r
+\r
+#define LCD_RD_CLR FIO2CLR\r
+#define LCD_RD_SET FIO2SET\r
+\r
+// Routine to write data to LCD driver. Normally called in combination\r
+// with LCDdriver_WriteCom() routine\r
+void LCDdriver_WriteData(unsigned char LCD_Data)\r
+{\r
+ LCD_DATA_CLR = LCD_DATA_PIN; \r
+ LCD_DATA_SET = LCD_Data;\r
+ LCD_CSB_CLR = LCD_CSB_PIN;\r
+ LCD_WR_CLR = LCD_WR_PIN;\r
+ LCD_WR_SET = LCD_WR_PIN;\r
+ LCD_CSB_SET = LCD_CSB_PIN;\r
+}\r
+\r
+// Routine to configure set LCD driver to accept particular command.\r
+// A call to this routine will normally be followed by a call\r
+// to LCDdriver_WriteData() to transfer appropriate parameters to driver.\r
+void LCDdriver_WriteCom(unsigned char LCD_Command)\r
+{\r
+ LCD_DATA_CLR = LCD_DATA_PIN; \r
+ LCD_DATA_SET = LCD_Command;\r
+ LCD_A0_CLR = LCD_A0_PIN;\r
+ LCD_CSB_CLR = LCD_CSB_PIN;\r
+ LCD_WR_CLR = LCD_WR_PIN;\r
+ LCD_WR_SET = LCD_WR_PIN;\r
+ LCD_CSB_SET = LCD_CSB_PIN;\r
+ LCD_A0_SET = LCD_A0_PIN;\r
+}\r
+\r
+// Function to add short delays in writing things to the LCD.\r
+void ms_delay(int n)\r
+{\r
+ volatile int d;\r
+ for (d=0; d<n*3000; d++){}\r
+}\r
+\r
+\r
+// Initialize GPIO connection to the LCD driver\r
+void LCDdriver_ConfigGPIOtoLCD(void)\r
+{\r
+ // set direction to outputs \r
+ FIO2DIR |= LCD_PORT2_DIRECTIONS; \r
+ FIO3DIR |= LCD_PORT3_DIRECTIONS;\r
+ \r
+ // Set GPIO outputs connected to LCD to default values\r
+ LCD_CSB_SET = LCD_CSB_PIN;\r
+ LCD_A0_SET = LCD_A0_PIN;\r
+ LCD_WR_SET = LCD_WR_PIN;\r
+ LCD_RD_SET = LCD_RD_PIN;\r
+ LCD_RESB_SET = LCD_RESB_PIN;\r
+ LCD_DATA_CLR = 0xff; // data bus to zero \r
+\r
+}\r
+\r
+\r
+// Initialisation routine to set up LCD\r
+void LCDdriver_initialisation(void)\r
+{\r
+ int i; // temp loop variable\r
+ \r
+ LCDdriver_ConfigGPIOtoLCD(); // Initialize the GPIO for the display\r
+\r
+ LCDdriver_WriteCom(DD_SWRESET); // SW reset\r
+ ms_delay(120); // Small delay\r
+\r
+ LCDdriver_WriteCom(DD_AUTOLOADSET); // disable auto loading of mask rom data\r
+ LCDdriver_WriteData(0xBF);\r
+\r
+ LCDdriver_WriteCom(DD_EPCTIN); // OTP control mode=read\r
+ LCDdriver_WriteData(0x00);\r
+ ms_delay(10); // Small delay\r
+\r
+ LCDdriver_WriteCom(DD_EPREAD); // Start the OTP read.\r
+ ms_delay(20); // Small delay\r
+\r
+ LCDdriver_WriteCom(DD_EPCTOUT); // Cancel the OTP read (20ms should have been enough)\r
+\r
+ LCDdriver_WriteCom(DD_DISPOFF); // display off\r
+\r
+ LCDdriver_WriteCom(DD_SLPOUT); // Exit sleep mode.\r
+ ms_delay(50); // Small delay\r
+\r
+ LCDdriver_WriteCom(DD_VopSet); // set LCD operating voltage to 14V.\r
+ LCDdriver_WriteData(0x04);\r
+ LCDdriver_WriteData(0x01);\r
+\r
+ LCDdriver_WriteCom(DD_BiasSel); // Select an LCD bias voltage ratio of 1/12.\r
+ LCDdriver_WriteData(0x00);\r
+\r
+ LCDdriver_WriteCom(DD_BstMbpXSel); // x8 booster circuit on\r
+ LCDdriver_WriteData(0x07);\r
+\r
+ LCDdriver_WriteCom(DD_ColScanDir); // Invert the column scan direction for the panel.\r
+ LCDdriver_WriteData(0xC0);\r
+\r
+ LCDdriver_WriteCom(DD_COLORMOD); // 16bpp, 5-6-5 data input mode.\r
+ LCDdriver_WriteData(0x05);\r
+ \r
+ LCDdriver_WriteCom(DD_MADCTR); // mem scan direction\r
+ LCDdriver_WriteData(0x00);\r
+ \r
+ LCDdriver_WriteCom(DD_DISPON); // display on\r
+\r
+ // Now Clear the Screen\r
+ LCDdriver_WriteCom(DD_CASET);\r
+ LCDdriver_WriteData(0x00);\r
+ LCDdriver_WriteData(0x7F);\r
+\r
+ LCDdriver_WriteCom(DD_RASET);\r
+ LCDdriver_WriteData(0x01);\r
+ LCDdriver_WriteData(0x80);\r
+\r
+ LCDdriver_WriteCom(DD_RAMWR);\r
+ for(i = 0; i < (128 * 128); i++)\r
+ {\r
+ LCDdriver_WriteData(0x00);\r
+ LCDdriver_WriteData(0x00);\r
+ }\r
+\r
+ LCDdriver_WriteCom(DD_NORON); // normal operation mode\r
+}\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+//*****************************************************************************\r
+// +--+ \r
+// | ++----+ \r
+// +-++ | \r
+// | | \r
+// +-+--+ | \r
+// | +--+--+ \r
+// +----+ Copyright (c) 2009 Code Red Technologies Ltd. \r
+//\r
+// lcd_driver.h - Header file for driver for the lowest level access routines\r
+// for the Sitronix ST7637 LCD Controller/driver used on the RDB1768 \r
+// development board.\r
+//\r
+// Software License Agreement\r
+// \r
+// The software is owned by Code Red Technologies and/or its suppliers, and is \r
+// protected under applicable copyright laws. All rights are reserved. Any \r
+// use in violation of the foregoing restrictions may subject the user to criminal \r
+// sanctions under applicable laws, as well as to civil liability for the breach \r
+// of the terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// USE OF THIS SOFTWARE FOR COMMERCIAL DEVELOPMENT AND/OR EDUCATION IS SUBJECT\r
+// TO A CURRENT END USER LICENSE AGREEMENT (COMMERCIAL OR EDUCATIONAL) WITH\r
+// CODE RED TECHNOLOGIES LTD. \r
+\r
+#ifndef LCD_DRIVER_H_\r
+#define LCD_DRIVER_H_\r
+\r
+void LCDdriver_WriteData(unsigned char LCD_Data);\r
+void LCDdriver_WriteCom(unsigned char LCD_Command);\r
+void LCDdriver_initialisation(void);\r
+\r
+#endif /*LCD_DRIVER_H_*/\r
--- /dev/null
+/*******************************************************************************************\r
+ Data table provides the bitmap data of each character.\r
+\r
+ To get the starting data offset of character 'A', you can use the following expression:\r
+\r
+ const unsigned char index = index_table['A'];\r
+ const unsigned int offset = offset_table[index];\r
+ const unsigned char *pData = data_table[offset];\r
+\r
+ *******************************************************************************************/\r
+const unsigned char font_data_table[] = {\r
+\r
+/* character 0x0020 (' '): (width=8, offset=0) */\r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x0021 ('!'): (width=8, offset=15) */\r
+0x00, 0x00, 0x00, 0x18, 0x3C, 0x3C, 0x3C, 0x18, \r
+0x18, 0x00, 0x18, 0x18, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x0022 ('"'): (width=8, offset=30) */\r
+0x00, 0x00, 0x00, 0x66, 0x66, 0x66, 0x00, 0x00, \r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x0023 ('#'): (width=8, offset=45) */\r
+0x00, 0x00, 0x00, 0x36, 0x36, 0x7F, 0x36, 0x36, \r
+0x36, 0x7F, 0x36, 0x36, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x0024 ('$'): (width=8, offset=60) */\r
+0x00, 0x18, 0x18, 0x3C, 0x66, 0x60, 0x30, 0x18, \r
+0x0C, 0x06, 0x66, 0x3C, 0x18, 0x18, 0x00, \r
+\r
+/* character 0x0025 ('%'): (width=8, offset=75) */\r
+0x00, 0x00, 0x70, 0xD8, 0xDA, 0x76, 0x0C, 0x18, \r
+0x30, 0x6E, 0x5B, 0x1B, 0x0E, 0x00, 0x00, \r
+\r
+/* character 0x0026 ('&'): (width=8, offset=90) */\r
+0x00, 0x00, 0x00, 0x38, 0x6C, 0x6C, 0x38, 0x60, \r
+0x6F, 0x66, 0x66, 0x3B, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x0027 ('''): (width=8, offset=105) */\r
+0x00, 0x00, 0x00, 0x18, 0x18, 0x18, 0x00, 0x00, \r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x0028 ('('): (width=8, offset=120) */\r
+0x00, 0x00, 0x00, 0x0C, 0x18, 0x18, 0x30, 0x30, \r
+0x30, 0x30, 0x30, 0x18, 0x18, 0x0C, 0x00, \r
+\r
+/* character 0x0029 (')'): (width=8, offset=135) */\r
+0x00, 0x00, 0x00, 0x30, 0x18, 0x18, 0x0C, 0x0C, \r
+0x0C, 0x0C, 0x0C, 0x18, 0x18, 0x30, 0x00, \r
+\r
+/* character 0x002A ('*'): (width=8, offset=150) */\r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x36, 0x1C, 0x7F, \r
+0x1C, 0x36, 0x00, 0x00, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x002B ('+'): (width=8, offset=165) */\r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x18, 0x7E, \r
+0x18, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x002C (','): (width=8, offset=180) */\r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \r
+0x00, 0x00, 0x1C, 0x1C, 0x0C, 0x18, 0x00, \r
+\r
+/* character 0x002D ('-'): (width=8, offset=195) */\r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7E, \r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x002E ('.'): (width=8, offset=210) */\r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \r
+0x00, 0x00, 0x1C, 0x1C, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x002F ('/'): (width=8, offset=225) */\r
+0x00, 0x00, 0x00, 0x06, 0x06, 0x0C, 0x0C, 0x18, \r
+0x18, 0x30, 0x30, 0x60, 0x60, 0x00, 0x00, \r
+\r
+/* character 0x0030 ('0'): (width=8, offset=240) */\r
+0x00, 0x00, 0x00, 0x1E, 0x33, 0x37, 0x37, 0x33, \r
+0x3B, 0x3B, 0x33, 0x1E, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x0031 ('1'): (width=8, offset=255) */\r
+0x00, 0x00, 0x00, 0x0C, 0x1C, 0x7C, 0x0C, 0x0C, \r
+0x0C, 0x0C, 0x0C, 0x0C, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x0032 ('2'): (width=8, offset=270) */\r
+0x00, 0x00, 0x00, 0x3C, 0x66, 0x66, 0x06, 0x0C, \r
+0x18, 0x30, 0x60, 0x7E, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x0033 ('3'): (width=8, offset=285) */\r
+0x00, 0x00, 0x00, 0x3C, 0x66, 0x66, 0x06, 0x1C, \r
+0x06, 0x66, 0x66, 0x3C, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x0034 ('4'): (width=8, offset=300) */\r
+0x00, 0x00, 0x00, 0x30, 0x30, 0x36, 0x36, 0x36, \r
+0x66, 0x7F, 0x06, 0x06, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x0035 ('5'): (width=8, offset=315) */\r
+0x00, 0x00, 0x00, 0x7E, 0x60, 0x60, 0x60, 0x7C, \r
+0x06, 0x06, 0x0C, 0x78, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x0036 ('6'): (width=8, offset=330) */\r
+0x00, 0x00, 0x00, 0x1C, 0x18, 0x30, 0x7C, 0x66, \r
+0x66, 0x66, 0x66, 0x3C, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x0037 ('7'): (width=8, offset=345) */\r
+0x00, 0x00, 0x00, 0x7E, 0x06, 0x0C, 0x0C, 0x18, \r
+0x18, 0x30, 0x30, 0x30, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x0038 ('8'): (width=8, offset=360) */\r
+0x00, 0x00, 0x00, 0x3C, 0x66, 0x66, 0x76, 0x3C, \r
+0x6E, 0x66, 0x66, 0x3C, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x0039 ('9'): (width=8, offset=375) */\r
+0x00, 0x00, 0x00, 0x3C, 0x66, 0x66, 0x66, 0x66, \r
+0x3E, 0x0C, 0x18, 0x38, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x003A (':'): (width=8, offset=390) */\r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x1C, 0x1C, 0x00, \r
+0x00, 0x00, 0x1C, 0x1C, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x003B (';'): (width=8, offset=405) */\r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x1C, 0x1C, 0x00, \r
+0x00, 0x00, 0x1C, 0x1C, 0x0C, 0x18, 0x00, \r
+\r
+/* character 0x003C ('<'): (width=8, offset=420) */\r
+0x00, 0x00, 0x00, 0x06, 0x0C, 0x18, 0x30, 0x60, \r
+0x30, 0x18, 0x0C, 0x06, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x003D ('='): (width=8, offset=435) */\r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7E, 0x00, \r
+0x7E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x003E ('>'): (width=8, offset=450) */\r
+0x00, 0x00, 0x00, 0x60, 0x30, 0x18, 0x0C, 0x06, \r
+0x0C, 0x18, 0x30, 0x60, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x003F ('?'): (width=8, offset=465) */\r
+0x00, 0x00, 0x00, 0x3C, 0x66, 0x66, 0x0C, 0x18, \r
+0x18, 0x00, 0x18, 0x18, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x0040 ('@'): (width=8, offset=480) */\r
+0x00, 0x00, 0x00, 0x7E, 0xC3, 0xC3, 0xCF, 0xDB, \r
+0xDB, 0xCF, 0xC0, 0x7F, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x0041 ('A'): (width=8, offset=495) */\r
+0x00, 0x00, 0x00, 0x18, 0x3C, 0x66, 0x66, 0x66, \r
+0x7E, 0x66, 0x66, 0x66, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x0042 ('B'): (width=8, offset=510) */\r
+0x00, 0x00, 0x00, 0x7C, 0x66, 0x66, 0x66, 0x7C, \r
+0x66, 0x66, 0x66, 0x7C, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x0043 ('C'): (width=8, offset=525) */\r
+0x00, 0x00, 0x00, 0x3C, 0x66, 0x66, 0x60, 0x60, \r
+0x60, 0x66, 0x66, 0x3C, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x0044 ('D'): (width=8, offset=540) */\r
+0x00, 0x00, 0x00, 0x78, 0x6C, 0x66, 0x66, 0x66, \r
+0x66, 0x66, 0x6C, 0x78, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x0045 ('E'): (width=8, offset=555) */\r
+0x00, 0x00, 0x00, 0x7E, 0x60, 0x60, 0x60, 0x7C, \r
+0x60, 0x60, 0x60, 0x7E, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x0046 ('F'): (width=8, offset=570) */\r
+0x00, 0x00, 0x00, 0x7E, 0x60, 0x60, 0x60, 0x7C, \r
+0x60, 0x60, 0x60, 0x60, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x0047 ('G'): (width=8, offset=585) */\r
+0x00, 0x00, 0x00, 0x3C, 0x66, 0x66, 0x60, 0x60, \r
+0x6E, 0x66, 0x66, 0x3E, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x0048 ('H'): (width=8, offset=600) */\r
+0x00, 0x00, 0x00, 0x66, 0x66, 0x66, 0x66, 0x7E, \r
+0x66, 0x66, 0x66, 0x66, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x0049 ('I'): (width=8, offset=615) */\r
+0x00, 0x00, 0x00, 0x3C, 0x18, 0x18, 0x18, 0x18, \r
+0x18, 0x18, 0x18, 0x3C, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x004A ('J'): (width=8, offset=630) */\r
+0x00, 0x00, 0x00, 0x06, 0x06, 0x06, 0x06, 0x06, \r
+0x06, 0x66, 0x66, 0x3C, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x004B ('K'): (width=8, offset=645) */\r
+0x00, 0x00, 0x00, 0x66, 0x66, 0x6C, 0x6C, 0x78, \r
+0x6C, 0x6C, 0x66, 0x66, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x004C ('L'): (width=8, offset=660) */\r
+0x00, 0x00, 0x00, 0x60, 0x60, 0x60, 0x60, 0x60, \r
+0x60, 0x60, 0x60, 0x7E, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x004D ('M'): (width=8, offset=675) */\r
+0x00, 0x00, 0x00, 0x63, 0x63, 0x77, 0x6B, 0x6B, \r
+0x6B, 0x63, 0x63, 0x63, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x004E ('N'): (width=8, offset=690) */\r
+0x00, 0x00, 0x00, 0x63, 0x63, 0x73, 0x7B, 0x6F, \r
+0x67, 0x63, 0x63, 0x63, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x004F ('O'): (width=8, offset=705) */\r
+0x00, 0x00, 0x00, 0x3C, 0x66, 0x66, 0x66, 0x66, \r
+0x66, 0x66, 0x66, 0x3C, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x0050 ('P'): (width=8, offset=720) */\r
+0x00, 0x00, 0x00, 0x7C, 0x66, 0x66, 0x66, 0x7C, \r
+0x60, 0x60, 0x60, 0x60, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x0051 ('Q'): (width=8, offset=735) */\r
+0x00, 0x00, 0x00, 0x3C, 0x66, 0x66, 0x66, 0x66, \r
+0x66, 0x66, 0x66, 0x3C, 0x0C, 0x06, 0x00, \r
+\r
+/* character 0x0052 ('R'): (width=8, offset=750) */\r
+0x00, 0x00, 0x00, 0x7C, 0x66, 0x66, 0x66, 0x7C, \r
+0x6C, 0x66, 0x66, 0x66, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x0053 ('S'): (width=8, offset=765) */\r
+0x00, 0x00, 0x00, 0x3C, 0x66, 0x60, 0x30, 0x18, \r
+0x0C, 0x06, 0x66, 0x3C, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x0054 ('T'): (width=8, offset=780) */\r
+0x00, 0x00, 0x00, 0x7E, 0x18, 0x18, 0x18, 0x18, \r
+0x18, 0x18, 0x18, 0x18, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x0055 ('U'): (width=8, offset=795) */\r
+0x00, 0x00, 0x00, 0x66, 0x66, 0x66, 0x66, 0x66, \r
+0x66, 0x66, 0x66, 0x3C, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x0056 ('V'): (width=8, offset=810) */\r
+0x00, 0x00, 0x00, 0x66, 0x66, 0x66, 0x66, 0x66, \r
+0x66, 0x66, 0x3C, 0x18, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x0057 ('W'): (width=8, offset=825) */\r
+0x00, 0x00, 0x00, 0x63, 0x63, 0x63, 0x6B, 0x6B, \r
+0x6B, 0x36, 0x36, 0x36, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x0058 ('X'): (width=8, offset=840) */\r
+0x00, 0x00, 0x00, 0x66, 0x66, 0x34, 0x18, 0x18, \r
+0x2C, 0x66, 0x66, 0x66, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x0059 ('Y'): (width=8, offset=855) */\r
+0x00, 0x00, 0x00, 0x66, 0x66, 0x66, 0x66, 0x3C, \r
+0x18, 0x18, 0x18, 0x18, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x005A ('Z'): (width=8, offset=870) */\r
+0x00, 0x00, 0x00, 0x7E, 0x06, 0x06, 0x0C, 0x18, \r
+0x30, 0x60, 0x60, 0x7E, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x005B ('['): (width=8, offset=885) */\r
+0x00, 0x00, 0x00, 0x3C, 0x30, 0x30, 0x30, 0x30, \r
+0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x3C, \r
+\r
+/* character 0x005C ('\'): (width=8, offset=900) */\r
+0x00, 0x00, 0x00, 0x60, 0x60, 0x30, 0x30, 0x18, \r
+0x18, 0x0C, 0x0C, 0x06, 0x06, 0x00, 0x00, \r
+\r
+/* character 0x005D (']'): (width=8, offset=915) */\r
+0x00, 0x00, 0x00, 0x3C, 0x0C, 0x0C, 0x0C, 0x0C, \r
+0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x3C, \r
+\r
+/* character 0x005E ('^'): (width=8, offset=930) */\r
+0x00, 0x18, 0x3C, 0x66, 0x00, 0x00, 0x00, 0x00, \r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x005F ('_'): (width=8, offset=945) */\r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, \r
+\r
+/* character 0x0060 ('`'): (width=8, offset=960) */\r
+0x00, 0x38, 0x18, 0x0C, 0x00, 0x00, 0x00, 0x00, \r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x0061 ('a'): (width=8, offset=975) */\r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x06, 0x06, \r
+0x3E, 0x66, 0x66, 0x3E, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x0062 ('b'): (width=8, offset=990) */\r
+0x00, 0x00, 0x00, 0x60, 0x60, 0x7C, 0x66, 0x66, \r
+0x66, 0x66, 0x66, 0x7C, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x0063 ('c'): (width=8, offset=1005) */\r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x66, 0x60, \r
+0x60, 0x60, 0x66, 0x3C, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x0064 ('d'): (width=8, offset=1020) */\r
+0x00, 0x00, 0x00, 0x06, 0x06, 0x3E, 0x66, 0x66, \r
+0x66, 0x66, 0x66, 0x3E, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x0065 ('e'): (width=8, offset=1035) */\r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x66, 0x66, \r
+0x7E, 0x60, 0x60, 0x3C, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x0066 ('f'): (width=8, offset=1050) */\r
+0x00, 0x00, 0x00, 0x1E, 0x30, 0x30, 0x30, 0x7E, \r
+0x30, 0x30, 0x30, 0x30, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x0067 ('g'): (width=8, offset=1065) */\r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x3E, 0x66, 0x66, \r
+0x66, 0x66, 0x66, 0x3E, 0x06, 0x06, 0x7C, \r
+\r
+/* character 0x0068 ('h'): (width=8, offset=1080) */\r
+0x00, 0x00, 0x00, 0x60, 0x60, 0x7C, 0x66, 0x66, \r
+0x66, 0x66, 0x66, 0x66, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x0069 ('i'): (width=8, offset=1095) */\r
+0x00, 0x00, 0x18, 0x18, 0x00, 0x78, 0x18, 0x18, \r
+0x18, 0x18, 0x18, 0x7E, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x006A ('j'): (width=8, offset=1110) */\r
+0x00, 0x00, 0x0C, 0x0C, 0x00, 0x3C, 0x0C, 0x0C, \r
+0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x78, \r
+\r
+/* character 0x006B ('k'): (width=8, offset=1125) */\r
+0x00, 0x00, 0x00, 0x60, 0x60, 0x66, 0x66, 0x6C, \r
+0x78, 0x6C, 0x66, 0x66, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x006C ('l'): (width=8, offset=1140) */\r
+0x00, 0x00, 0x00, 0x78, 0x18, 0x18, 0x18, 0x18, \r
+0x18, 0x18, 0x18, 0x7E, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x006D ('m'): (width=8, offset=1155) */\r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x7E, 0x6B, 0x6B, \r
+0x6B, 0x6B, 0x6B, 0x63, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x006E ('n'): (width=8, offset=1170) */\r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x7C, 0x66, 0x66, \r
+0x66, 0x66, 0x66, 0x66, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x006F ('o'): (width=8, offset=1185) */\r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x66, 0x66, \r
+0x66, 0x66, 0x66, 0x3C, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x0070 ('p'): (width=8, offset=1200) */\r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x7C, 0x66, 0x66, \r
+0x66, 0x66, 0x66, 0x7C, 0x60, 0x60, 0x60, \r
+\r
+/* character 0x0071 ('q'): (width=8, offset=1215) */\r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x3E, 0x66, 0x66, \r
+0x66, 0x66, 0x66, 0x3E, 0x06, 0x06, 0x06, \r
+\r
+/* character 0x0072 ('r'): (width=8, offset=1230) */\r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x66, 0x6E, 0x70, \r
+0x60, 0x60, 0x60, 0x60, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x0073 ('s'): (width=8, offset=1245) */\r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x3E, 0x60, 0x60, \r
+0x3C, 0x06, 0x06, 0x7C, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x0074 ('t'): (width=8, offset=1260) */\r
+0x00, 0x00, 0x00, 0x30, 0x30, 0x7E, 0x30, 0x30, \r
+0x30, 0x30, 0x30, 0x1E, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x0075 ('u'): (width=8, offset=1275) */\r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x66, 0x66, 0x66, \r
+0x66, 0x66, 0x66, 0x3E, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x0076 ('v'): (width=8, offset=1290) */\r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x66, 0x66, 0x66, \r
+0x66, 0x66, 0x3C, 0x18, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x0077 ('w'): (width=8, offset=1305) */\r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x63, 0x6B, 0x6B, \r
+0x6B, 0x6B, 0x36, 0x36, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x0078 ('x'): (width=8, offset=1320) */\r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x66, 0x66, 0x3C, \r
+0x18, 0x3C, 0x66, 0x66, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x0079 ('y'): (width=8, offset=1335) */\r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x66, 0x66, 0x66, \r
+0x66, 0x66, 0x66, 0x3C, 0x0C, 0x18, 0xF0, \r
+\r
+/* character 0x007A ('z'): (width=8, offset=1350) */\r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x7E, 0x06, 0x0C, \r
+0x18, 0x30, 0x60, 0x7E, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x007B ('{'): (width=8, offset=1365) */\r
+0x00, 0x00, 0x00, 0x0C, 0x18, 0x18, 0x18, 0x30, \r
+0x60, 0x30, 0x18, 0x18, 0x18, 0x0C, 0x00, \r
+\r
+/* character 0x007C ('|'): (width=8, offset=1380) */\r
+0x00, 0x00, 0x00, 0x18, 0x18, 0x18, 0x18, 0x18, \r
+0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, \r
+\r
+/* character 0x007D ('}'): (width=8, offset=1395) */\r
+0x00, 0x00, 0x00, 0x30, 0x18, 0x18, 0x18, 0x0C, \r
+0x06, 0x0C, 0x18, 0x18, 0x18, 0x30, 0x00, \r
+\r
+/* character 0x007E ('~'): (width=8, offset=1410) */\r
+0x00, 0x00, 0x00, 0x71, 0xDB, 0x8E, 0x00, 0x00, \r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \r
+\r
+/* character 0x007F ('\7f'): (width=8, offset=1425) */\r
+0x00, 0x00, 0x00, 0x7E, 0x7E, 0x7E, 0x7E, 0x7E, \r
+0x7E, 0x7E, 0x7E, 0x7E, 0x00, 0x00, 0x00, \r
+\r
+};\r
+\r
+\r
+/*******************************************************************************************\r
+ Index table is used to find the mapping index of a character.\r
+\r
+ If you can find a simple mathematical expression for index mapping, you can use that.\r
+ If you do not have such a mathematical expression, this index table is just for you.\r
+\r
+ To get the index of character 'A', you can use the following expression:\r
+\r
+ const unsigned char index = index_table['A'];\r
+\r
+ *******************************************************************************************/\r
+const unsigned char font_index_table[] = {\r
+/* index hexcode decimal char */\r
+/* ===== ======= ======= ==== */\r
+ 0, /* 00 0 . */\r
+ 0, /* 01 1 . */\r
+ 0, /* 02 2 . */\r
+ 0, /* 03 3 . */\r
+ 0, /* 04 4 . */\r
+ 0, /* 05 5 . */\r
+ 0, /* 06 6 . */\r
+ 0, /* 07 7 . */\r
+ 0, /* 08 8 . */\r
+ 0, /* 09 9 . */\r
+ 0, /* 0A 10 . */\r
+ 0, /* 0B 11 . */\r
+ 0, /* 0C 12 . */\r
+ 0, /* 0D 13 . */\r
+ 0, /* 0E 14 . */\r
+ 0, /* 0F 15 . */\r
+ 0, /* 10 16 . */\r
+ 0, /* 11 17 . */\r
+ 0, /* 12 18 . */\r
+ 0, /* 13 19 . */\r
+ 0, /* 14 20 . */\r
+ 0, /* 15 21 . */\r
+ 0, /* 16 22 . */\r
+ 0, /* 17 23 . */\r
+ 0, /* 18 24 . */\r
+ 0, /* 19 25 . */\r
+ 0, /* 1A 26 . */\r
+ 0, /* 1B 27 . */\r
+ 0, /* 1C 28 . */\r
+ 0, /* 1D 29 . */\r
+ 0, /* 1E 30 . */\r
+ 0, /* 1F 31 . */\r
+ 0, /* 20 32 */\r
+ 1, /* 21 33 ! */\r
+ 2, /* 22 34 " */\r
+ 3, /* 23 35 # */\r
+ 4, /* 24 36 $ */\r
+ 5, /* 25 37 % */\r
+ 6, /* 26 38 & */\r
+ 7, /* 27 39 ' */\r
+ 8, /* 28 40 ( */\r
+ 9, /* 29 41 ) */\r
+ 10, /* 2A 42 * */\r
+ 11, /* 2B 43 + */\r
+ 12, /* 2C 44 , */\r
+ 13, /* 2D 45 - */\r
+ 14, /* 2E 46 . */\r
+ 15, /* 2F 47 / */\r
+ 16, /* 30 48 0 */\r
+ 17, /* 31 49 1 */\r
+ 18, /* 32 50 2 */\r
+ 19, /* 33 51 3 */\r
+ 20, /* 34 52 4 */\r
+ 21, /* 35 53 5 */\r
+ 22, /* 36 54 6 */\r
+ 23, /* 37 55 7 */\r
+ 24, /* 38 56 8 */\r
+ 25, /* 39 57 9 */\r
+ 26, /* 3A 58 : */\r
+ 27, /* 3B 59 ; */\r
+ 28, /* 3C 60 < */\r
+ 29, /* 3D 61 = */\r
+ 30, /* 3E 62 > */\r
+ 31, /* 3F 63 ? */\r
+ 32, /* 40 64 @ */\r
+ 33, /* 41 65 A */\r
+ 34, /* 42 66 B */\r
+ 35, /* 43 67 C */\r
+ 36, /* 44 68 D */\r
+ 37, /* 45 69 E */\r
+ 38, /* 46 70 F */\r
+ 39, /* 47 71 G */\r
+ 40, /* 48 72 H */\r
+ 41, /* 49 73 I */\r
+ 42, /* 4A 74 J */\r
+ 43, /* 4B 75 K */\r
+ 44, /* 4C 76 L */\r
+ 45, /* 4D 77 M */\r
+ 46, /* 4E 78 N */\r
+ 47, /* 4F 79 O */\r
+ 48, /* 50 80 P */\r
+ 49, /* 51 81 Q */\r
+ 50, /* 52 82 R */\r
+ 51, /* 53 83 S */\r
+ 52, /* 54 84 T */\r
+ 53, /* 55 85 U */\r
+ 54, /* 56 86 V */\r
+ 55, /* 57 87 W */\r
+ 56, /* 58 88 X */\r
+ 57, /* 59 89 Y */\r
+ 58, /* 5A 90 Z */\r
+ 59, /* 5B 91 [ */\r
+ 60, /* 5C 92 \ */\r
+ 61, /* 5D 93 ] */\r
+ 62, /* 5E 94 ^ */\r
+ 63, /* 5F 95 _ */\r
+ 64, /* 60 96 ` */\r
+ 65, /* 61 97 a */\r
+ 66, /* 62 98 b */\r
+ 67, /* 63 99 c */\r
+ 68, /* 64 100 d */\r
+ 69, /* 65 101 e */\r
+ 70, /* 66 102 f */\r
+ 71, /* 67 103 g */\r
+ 72, /* 68 104 h */\r
+ 73, /* 69 105 i */\r
+ 74, /* 6A 106 j */\r
+ 75, /* 6B 107 k */\r
+ 76, /* 6C 108 l */\r
+ 77, /* 6D 109 m */\r
+ 78, /* 6E 110 n */\r
+ 79, /* 6F 111 o */\r
+ 80, /* 70 112 p */\r
+ 81, /* 71 113 q */\r
+ 82, /* 72 114 r */\r
+ 83, /* 73 115 s */\r
+ 84, /* 74 116 t */\r
+ 85, /* 75 117 u */\r
+ 86, /* 76 118 v */\r
+ 87, /* 77 119 w */\r
+ 88, /* 78 120 x */\r
+ 89, /* 79 121 y */\r
+ 90, /* 7A 122 z */\r
+ 91, /* 7B 123 { */\r
+ 92, /* 7C 124 | */\r
+ 93, /* 7D 125 } */\r
+ 94, /* 7E 126 ~ */\r
+ 95, /* 7F 127 \7f */\r
+ 0, /* 80 128 ? */\r
+ 0, /* 81 129 � */\r
+ 0, /* 82 130 ? */\r
+ 0, /* 83 131 ? */\r
+ 0, /* 84 132 ? */\r
+ 0, /* 85 133 ? */\r
+ 0, /* 86 134 ? */\r
+ 0, /* 87 135 ? */\r
+ 0, /* 88 136 ? */\r
+ 0, /* 89 137 ? */\r
+ 0, /* 8A 138 ? */\r
+ 0, /* 8B 139 ? */\r
+ 0, /* 8C 140 ? */\r
+ 0, /* 8D 141 � */\r
+ 0, /* 8E 142 ? */\r
+ 0, /* 8F 143 � */\r
+ 0, /* 90 144 � */\r
+ 0, /* 91 145 ? */\r
+ 0, /* 92 146 ? */\r
+ 0, /* 93 147 ? */\r
+ 0, /* 94 148 ? */\r
+ 0, /* 95 149 ? */\r
+ 0, /* 96 150 ? */\r
+ 0, /* 97 151 ? */\r
+ 0, /* 98 152 ? */\r
+ 0, /* 99 153 ? */\r
+ 0, /* 9A 154 ? */\r
+ 0, /* 9B 155 ? */\r
+ 0, /* 9C 156 ? */\r
+ 0, /* 9D 157 � */\r
+ 0, /* 9E 158 ? */\r
+ 0, /* 9F 159 ? */\r
+ 0, /* A0 160 � */\r
+ 0, /* A1 161 � */\r
+ 0, /* A2 162 � */\r
+ 0, /* A3 163 � */\r
+ 0, /* A4 164 � */\r
+ 0, /* A5 165 � */\r
+ 0, /* A6 166 � */\r
+ 0, /* A7 167 � */\r
+ 0, /* A8 168 � */\r
+ 0, /* A9 169 � */\r
+ 0, /* AA 170 � */\r
+ 0, /* AB 171 � */\r
+ 0, /* AC 172 � */\r
+ 0, /* AD 173 � */\r
+ 0, /* AE 174 � */\r
+ 0, /* AF 175 � */\r
+ 0, /* B0 176 � */\r
+ 0, /* B1 177 � */\r
+ 0, /* B2 178 � */\r
+ 0, /* B3 179 � */\r
+ 0, /* B4 180 � */\r
+ 0, /* B5 181 � */\r
+ 0, /* B6 182 � */\r
+ 0, /* B7 183 � */\r
+ 0, /* B8 184 � */\r
+ 0, /* B9 185 � */\r
+ 0, /* BA 186 � */\r
+ 0, /* BB 187 � */\r
+ 0, /* BC 188 � */\r
+ 0, /* BD 189 � */\r
+ 0, /* BE 190 � */\r
+ 0, /* BF 191 � */\r
+ 0, /* C0 192 � */\r
+ 0, /* C1 193 � */\r
+ 0, /* C2 194 � */\r
+ 0, /* C3 195 � */\r
+ 0, /* C4 196 � */\r
+ 0, /* C5 197 � */\r
+ 0, /* C6 198 � */\r
+ 0, /* C7 199 � */\r
+ 0, /* C8 200 � */\r
+ 0, /* C9 201 � */\r
+ 0, /* CA 202 � */\r
+ 0, /* CB 203 � */\r
+ 0, /* CC 204 � */\r
+ 0, /* CD 205 � */\r
+ 0, /* CE 206 � */\r
+ 0, /* CF 207 � */\r
+ 0, /* D0 208 � */\r
+ 0, /* D1 209 � */\r
+ 0, /* D2 210 � */\r
+ 0, /* D3 211 � */\r
+ 0, /* D4 212 � */\r
+ 0, /* D5 213 � */\r
+ 0, /* D6 214 � */\r
+ 0, /* D7 215 � */\r
+ 0, /* D8 216 � */\r
+ 0, /* D9 217 � */\r
+ 0, /* DA 218 � */\r
+ 0, /* DB 219 � */\r
+ 0, /* DC 220 � */\r
+ 0, /* DD 221 � */\r
+ 0, /* DE 222 � */\r
+ 0, /* DF 223 � */\r
+ 0, /* E0 224 � */\r
+ 0, /* E1 225 � */\r
+ 0, /* E2 226 � */\r
+ 0, /* E3 227 � */\r
+ 0, /* E4 228 � */\r
+ 0, /* E5 229 � */\r
+ 0, /* E6 230 � */\r
+ 0, /* E7 231 � */\r
+ 0, /* E8 232 � */\r
+ 0, /* E9 233 � */\r
+ 0, /* EA 234 � */\r
+ 0, /* EB 235 � */\r
+ 0, /* EC 236 � */\r
+ 0, /* ED 237 � */\r
+ 0, /* EE 238 � */\r
+ 0, /* EF 239 � */\r
+ 0, /* F0 240 � */\r
+ 0, /* F1 241 � */\r
+ 0, /* F2 242 � */\r
+ 0, /* F3 243 � */\r
+ 0, /* F4 244 � */\r
+ 0, /* F5 245 � */\r
+ 0, /* F6 246 � */\r
+ 0, /* F7 247 � */\r
+ 0, /* F8 248 � */\r
+ 0, /* F9 249 � */\r
+ 0, /* FA 250 � */\r
+ 0, /* FB 251 � */\r
+ 0, /* FC 252 � */\r
+ 0, /* FD 253 � */\r
+ 0, /* FE 254 � */\r
+ 0, /* FF 255 � */\r
+};\r
+\r
+\r
+\r
--- /dev/null
+#ifndef __LPC17xx_H\r
+#define __LPC17xx_H\r
+\r
+/* System Control Block (SCB) includes:\r
+ Flash Accelerator Module, Clocking and Power Control, External Interrupts,\r
+ Reset, System Control and Status\r
+*/\r
+#define SCB_BASE_ADDR 0x400FC000\r
+\r
+#define PCONP_PCTIM0 0x00000002\r
+#define PCONP_PCTIM1 0x00000004\r
+#define PCONP_PCUART0 0x00000008\r
+#define PCONP_PCUART1 0x00000010\r
+#define PCONP_PCPWM1 0x00000040\r
+#define PCONP_PCI2C0 0x00000080\r
+#define PCONP_PCSPI 0x00000100\r
+#define PCONP_PCRTC 0x00000200\r
+#define PCONP_PCSSP1 0x00000400\r
+#define PCONP_PCAD 0x00001000\r
+#define PCONP_PCCAN1 0x00002000\r
+#define PCONP_PCCAN2 0x00004000\r
+#define PCONP_PCGPIO 0x00008000\r
+#define PCONP_PCRIT 0x00010000\r
+#define PCONP_PCMCPWM 0x00020000\r
+#define PCONP_PCQEI 0x00040000\r
+#define PCONP_PCI2C1 0x00080000\r
+#define PCONP_PCSSP0 0x00200000\r
+#define PCONP_PCTIM2 0x00400000\r
+#define PCONP_PCTIM3 0x00800000\r
+#define PCONP_PCUART2 0x01000000\r
+#define PCONP_PCUART3 0x02000000\r
+#define PCONP_PCI2C2 0x04000000\r
+#define PCONP_PCI2S 0x08000000\r
+#define PCONP_PCGPDMA 0x20000000\r
+#define PCONP_PCENET 0x40000000\r
+#define PCONP_PCUSB 0x80000000\r
+\r
+#define PLLCON_PLLE 0x00000001\r
+#define PLLCON_PLLC 0x00000002\r
+#define PLLCON_MASK 0x00000003\r
+\r
+#define PLLCFG_MUL1 0x00000000\r
+#define PLLCFG_MUL2 0x00000001\r
+#define PLLCFG_MUL3 0x00000002\r
+#define PLLCFG_MUL4 0x00000003\r
+#define PLLCFG_MUL5 0x00000004\r
+#define PLLCFG_MUL6 0x00000005\r
+#define PLLCFG_MUL7 0x00000006\r
+#define PLLCFG_MUL8 0x00000007\r
+#define PLLCFG_MUL9 0x00000008\r
+#define PLLCFG_MUL10 0x00000009\r
+#define PLLCFG_MUL11 0x0000000A\r
+#define PLLCFG_MUL12 0x0000000B\r
+#define PLLCFG_MUL13 0x0000000C\r
+#define PLLCFG_MUL14 0x0000000D\r
+#define PLLCFG_MUL15 0x0000000E\r
+#define PLLCFG_MUL16 0x0000000F\r
+#define PLLCFG_MUL17 0x00000010\r
+#define PLLCFG_MUL18 0x00000011\r
+#define PLLCFG_MUL19 0x00000012\r
+#define PLLCFG_MUL20 0x00000013\r
+#define PLLCFG_MUL21 0x00000014\r
+#define PLLCFG_MUL22 0x00000015\r
+#define PLLCFG_MUL23 0x00000016\r
+#define PLLCFG_MUL24 0x00000017\r
+#define PLLCFG_MUL25 0x00000018\r
+#define PLLCFG_MUL26 0x00000019\r
+#define PLLCFG_MUL27 0x0000001A\r
+#define PLLCFG_MUL28 0x0000001B\r
+#define PLLCFG_MUL29 0x0000001C\r
+#define PLLCFG_MUL30 0x0000001D\r
+#define PLLCFG_MUL31 0x0000001E\r
+#define PLLCFG_MUL32 0x0000001F\r
+#define PLLCFG_MUL33 0x00000020\r
+#define PLLCFG_MUL34 0x00000021\r
+#define PLLCFG_MUL35 0x00000022\r
+#define PLLCFG_MUL36 0x00000023\r
+\r
+#define PLLCFG_DIV1 0x00000000\r
+#define PLLCFG_DIV2 0x00010000\r
+#define PLLCFG_DIV3 0x00020000\r
+#define PLLCFG_DIV4 0x00030000\r
+#define PLLCFG_DIV5 0x00040000\r
+#define PLLCFG_DIV6 0x00050000\r
+#define PLLCFG_DIV7 0x00060000\r
+#define PLLCFG_DIV8 0x00070000\r
+#define PLLCFG_DIV9 0x00080000\r
+#define PLLCFG_DIV10 0x00090000\r
+#define PLLCFG_MASK 0x00FF7FFF\r
+\r
+#define PLLSTAT_MSEL_MASK 0x00007FFF\r
+#define PLLSTAT_NSEL_MASK 0x00FF0000\r
+\r
+#define PLLSTAT_PLLE (1 << 24)\r
+#define PLLSTAT_PLLC (1 << 25)\r
+#define PLLSTAT_PLOCK (1 << 26)\r
+\r
+#define PLLFEED_FEED1 0x000000AA\r
+#define PLLFEED_FEED2 0x00000055\r
+\r
+#define NVIC_IRQ_WDT 0u // IRQ0, exception number 16\r
+#define NVIC_IRQ_TIMER0 1u // IRQ1, exception number 17\r
+#define NVIC_IRQ_TIMER1 2u // IRQ2, exception number 18\r
+#define NVIC_IRQ_TIMER2 3u // IRQ3, exception number 19\r
+#define NVIC_IRQ_TIMER3 4u // IRQ4, exception number 20\r
+#define NVIC_IRQ_UART0 5u // IRQ5, exception number 21\r
+#define NVIC_IRQ_UART1 6u // IRQ6, exception number 22\r
+#define NVIC_IRQ_UART2 7u // IRQ7, exception number 23\r
+#define NVIC_IRQ_UART3 8u // IRQ8, exception number 24\r
+#define NVIC_IRQ_PWM1 9u // IRQ9, exception number 25\r
+#define NVIC_IRQ_I2C0 10u // IRQ10, exception number 26\r
+#define NVIC_IRQ_I2C1 11u // IRQ11, exception number 27\r
+#define NVIC_IRQ_I2C2 12u // IRQ12, exception number 28\r
+#define NVIC_IRQ_SPI 13u // IRQ13, exception number 29\r
+#define NVIC_IRQ_SSP0 14u // IRQ14, exception number 30\r
+#define NVIC_IRQ_SSP1 15u // IRQ15, exception number 31\r
+#define NVIC_IRQ_PLL0 16u // IRQ16, exception number 32\r
+#define NVIC_IRQ_RTC 17u // IRQ17, exception number 33\r
+#define NVIC_IRQ_EINT0 18u // IRQ18, exception number 34\r
+#define NVIC_IRQ_EINT1 19u // IRQ19, exception number 35\r
+#define NVIC_IRQ_EINT2 20u // IRQ20, exception number 36\r
+#define NVIC_IRQ_EINT3 21u // IRQ21, exception number 37\r
+#define NVIC_IRQ_ADC 22u // IRQ22, exception number 38\r
+#define NVIC_IRQ_BOD 23u // IRQ23, exception number 39\r
+#define NVIC_IRQ_USB 24u // IRQ24, exception number 40\r
+#define NVIC_IRQ_CAN 25u // IRQ25, exception number 41\r
+#define NVIC_IRQ_GPDMA 26u // IRQ26, exception number 42\r
+#define NVIC_IRQ_I2S 27u // IRQ27, exception number 43\r
+#define NVIC_IRQ_ETHERNET 28u // IRQ28, exception number 44\r
+#define NVIC_IRQ_RIT 29u // IRQ29, exception number 45\r
+#define NVIC_IRQ_MCPWM 30u // IRQ30, exception number 46\r
+#define NVIC_IRQ_QE 31u // IRQ31, exception number 47\r
+#define NVIC_IRQ_PLL1 32u // IRQ32, exception number 48\r
+#define NVIC_IRQ_USB_ACT 33u // IRQ33, exception number 49\r
+#define NVIC_IRQ_CAN_ACT 34u // IRQ34, exception number 50\r
+\r
+\r
+#endif // __LPC17xx_H\r
+\r
+\r
+#ifndef CMSIS_17xx_H\r
+#define CMSIS_17xx_H\r
+\r
+/******************************************************************************\r
+ * @file: LPC17xx.h\r
+ * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Header File for\r
+ * NXP LPC17xx Device Series\r
+ * @version: V1.1\r
+ * @date: 14th May 2009\r
+ *----------------------------------------------------------------------------\r
+ *\r
+ * Copyright (C) 2008 ARM Limited. All rights reserved.\r
+ *\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M3\r
+ * processor based microcontrollers. This file can be freely distributed\r
+ * within development tools that are supporting such ARM based processors.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+\r
+\r
+#ifndef __LPC17xx_H__\r
+#define __LPC17xx_H__\r
+\r
+/*\r
+ * ==========================================================================\r
+ * ---------- Interrupt Number Definition -----------------------------------\r
+ * ==========================================================================\r
+ */\r
+\r
+typedef enum IRQn\r
+{\r
+/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/\r
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */\r
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */\r
+ BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */\r
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */\r
+ SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */\r
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */\r
+ PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */\r
+\r
+/****** LPC17xx Specific Interrupt Numbers *******************************************************/\r
+ WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */\r
+ TIMER0_IRQn = 1, /*!< Timer0 Interrupt */\r
+ TIMER1_IRQn = 2, /*!< Timer1 Interrupt */\r
+ TIMER2_IRQn = 3, /*!< Timer2 Interrupt */\r
+ TIMER3_IRQn = 4, /*!< Timer3 Interrupt */\r
+ UART0_IRQn = 5, /*!< UART0 Interrupt */\r
+ UART1_IRQn = 6, /*!< UART1 Interrupt */\r
+ UART2_IRQn = 7, /*!< UART2 Interrupt */\r
+ UART3_IRQn = 8, /*!< UART3 Interrupt */\r
+ PWM1_IRQn = 9, /*!< PWM1 Interrupt */\r
+ I2C0_IRQn = 10, /*!< I2C0 Interrupt */\r
+ I2C1_IRQn = 11, /*!< I2C1 Interrupt */\r
+ I2C2_IRQn = 12, /*!< I2C2 Interrupt */\r
+ SPI_IRQn = 13, /*!< SPI Interrupt */\r
+ SSP0_IRQn = 14, /*!< SSP0 Interrupt */\r
+ SSP1_IRQn = 15, /*!< SSP1 Interrupt */\r
+ PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */\r
+ RTC_IRQn = 17, /*!< Real Time Clock Interrupt */\r
+ EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */\r
+ EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */\r
+ EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */\r
+ EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */\r
+ ADC_IRQn = 22, /*!< A/D Converter Interrupt */\r
+ BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */\r
+ USB_IRQn = 24, /*!< USB Interrupt */\r
+ CAN_IRQn = 25, /*!< CAN Interrupt */\r
+ DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */\r
+ I2S_IRQn = 27, /*!< I2S Interrupt */\r
+ ENET_IRQn = 28, /*!< Ethernet Interrupt */\r
+ RIT_IRQn = 29, /*!< Repetitive Interrupt Timer Interrupt */\r
+ MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */\r
+ QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */\r
+ PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */\r
+} IRQn_Type;\r
+\r
+\r
+/*\r
+ * ==========================================================================\r
+ * ----------- Processor and Core Peripheral Section ------------------------\r
+ * ==========================================================================\r
+ */\r
+\r
+/* Configuration of the Cortex-M3 Processor and Core Peripherals */\r
+#define __MPU_PRESENT 1 /*!< MPU present or not */\r
+#define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */\r
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */\r
+\r
+\r
+//#include "..\core_cm3.h" /* Cortex-M3 processor and core peripherals */\r
+#include "core_cm3.h"\r
+#include "system_LPC17xx.h" /* System Header */\r
+\r
+\r
+\r
+/**\r
+ * Initialize the system clock\r
+ *\r
+ * @param none\r
+ * @return none\r
+ *\r
+ * @brief Setup the microcontroller system.\r
+ * Initialize the System and update the SystemFrequency variable.\r
+ */\r
+extern void SystemInit (void);\r
+\r
+\r
+/******************************************************************************/\r
+/* Device Specific Peripheral registers structures */\r
+/******************************************************************************/\r
+\r
+/*------------- System Control (SC) ------------------------------------------*/\r
+typedef struct\r
+{\r
+ __IO uint32_t FLASHCFG; /* Flash Accelerator Module */\r
+ uint32_t RESERVED0[31];\r
+ __IO uint32_t PLL0CON; /* Clocking and Power Control */\r
+ __IO uint32_t PLL0CFG;\r
+ __I uint32_t PLL0STAT;\r
+ __O uint32_t PLL0FEED;\r
+ uint32_t RESERVED1[4];\r
+ __IO uint32_t PLL1CON;\r
+ __IO uint32_t PLL1CFG;\r
+ __I uint32_t PLL1STAT;\r
+ __O uint32_t PLL1FEED;\r
+ uint32_t RESERVED2[4];\r
+ __IO uint32_t PCON;\r
+ __IO uint32_t PCONP;\r
+ uint32_t RESERVED3[15];\r
+ __IO uint32_t CCLKCFG;\r
+ __IO uint32_t USBCLKCFG;\r
+ __IO uint32_t CLKSRCSEL;\r
+ uint32_t RESERVED4[12];\r
+ __IO uint32_t EXTINT; /* External Interrupts */\r
+ uint32_t RESERVED5;\r
+ __IO uint32_t EXTMODE;\r
+ __IO uint32_t EXTPOLAR;\r
+ uint32_t RESERVED6[12];\r
+ __IO uint32_t RSID; /* Reset */\r
+ uint32_t RESERVED7[7];\r
+ __IO uint32_t SCS; /* Syscon Miscellaneous Registers */\r
+ __IO uint32_t IRCTRIM; /* Clock Dividers */\r
+ __IO uint32_t PCLKSEL0;\r
+ __IO uint32_t PCLKSEL1;\r
+ uint32_t RESERVED8[4];\r
+ __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */\r
+ uint32_t RESERVED9;\r
+ __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */\r
+ } SC_TypeDef;\r
+\r
+/*------------- Pin Connect Block (PINCON) -----------------------------------*/\r
+typedef struct\r
+{\r
+ __IO uint32_t PINSEL0;\r
+ __IO uint32_t PINSEL1;\r
+ __IO uint32_t PINSEL2;\r
+ __IO uint32_t PINSEL3;\r
+ __IO uint32_t PINSEL4;\r
+ __IO uint32_t PINSEL5;\r
+ __IO uint32_t PINSEL6;\r
+ __IO uint32_t PINSEL7;\r
+ __IO uint32_t PINSEL8;\r
+ __IO uint32_t PINSEL9;\r
+ __IO uint32_t PINSEL10;\r
+ uint32_t RESERVED0[5];\r
+ __IO uint32_t PINMODE0;\r
+ __IO uint32_t PINMODE1;\r
+ __IO uint32_t PINMODE2;\r
+ __IO uint32_t PINMODE3;\r
+ __IO uint32_t PINMODE4;\r
+ __IO uint32_t PINMODE5;\r
+ __IO uint32_t PINMODE6;\r
+ __IO uint32_t PINMODE7;\r
+ __IO uint32_t PINMODE8;\r
+ __IO uint32_t PINMODE9;\r
+ __IO uint32_t PINMODE_OD0;\r
+ __IO uint32_t PINMODE_OD1;\r
+ __IO uint32_t PINMODE_OD2;\r
+ __IO uint32_t PINMODE_OD3;\r
+ __IO uint32_t PINMODE_OD4;\r
+} PINCON_TypeDef;\r
+\r
+/*------------- General Purpose Input/Output (GPIO) --------------------------*/\r
+typedef struct\r
+{\r
+ __IO uint32_t FIODIR;\r
+ uint32_t RESERVED0[3];\r
+ __IO uint32_t FIOMASK;\r
+ __IO uint32_t FIOPIN;\r
+ __IO uint32_t FIOSET;\r
+ __O uint32_t FIOCLR;\r
+} GPIO_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ __I uint32_t IntStatus;\r
+ __I uint32_t IO0IntStatR;\r
+ __I uint32_t IO0IntStatF;\r
+ __O uint32_t IO0IntClr;\r
+ __IO uint32_t IO0IntEnR;\r
+ __IO uint32_t IO0IntEnF;\r
+ uint32_t RESERVED0[3];\r
+ __I uint32_t IO2IntStatR;\r
+ __I uint32_t IO2IntStatF;\r
+ __O uint32_t IO2IntClr;\r
+ __IO uint32_t IO2IntEnR;\r
+ __IO uint32_t IO2IntEnF;\r
+} GPIOINT_TypeDef;\r
+\r
+/*------------- Timer (TIM) --------------------------------------------------*/\r
+typedef struct\r
+{\r
+ __IO uint32_t IR;\r
+ __IO uint32_t TCR;\r
+ __IO uint32_t TC;\r
+ __IO uint32_t PR;\r
+ __IO uint32_t PC;\r
+ __IO uint32_t MCR;\r
+ __IO uint32_t MR0;\r
+ __IO uint32_t MR1;\r
+ __IO uint32_t MR2;\r
+ __IO uint32_t MR3;\r
+ __IO uint32_t CCR;\r
+ __I uint32_t CR0;\r
+ __I uint32_t CR1;\r
+ uint32_t RESERVED0[2];\r
+ __IO uint32_t EMR;\r
+ uint32_t RESERVED1[24];\r
+ __IO uint32_t CTCR;\r
+} TIM_TypeDef;\r
+\r
+/*------------- Pulse-Width Modulation (PWM) ---------------------------------*/\r
+typedef struct\r
+{\r
+ __IO uint32_t IR;\r
+ __IO uint32_t TCR;\r
+ __IO uint32_t TC;\r
+ __IO uint32_t PR;\r
+ __IO uint32_t PC;\r
+ __IO uint32_t MCR;\r
+ __IO uint32_t MR0;\r
+ __IO uint32_t MR1;\r
+ __IO uint32_t MR2;\r
+ __IO uint32_t MR3;\r
+ __IO uint32_t CCR;\r
+ __I uint32_t CR0;\r
+ __I uint32_t CR1;\r
+ __I uint32_t CR2;\r
+ __I uint32_t CR3;\r
+ __IO uint32_t MR4;\r
+ __IO uint32_t MR5;\r
+ __IO uint32_t MR6;\r
+ __IO uint32_t PCR;\r
+ __IO uint32_t LER;\r
+ uint32_t RESERVED0[7];\r
+ __IO uint32_t CTCR;\r
+} PWM_TypeDef;\r
+\r
+/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/\r
+typedef struct\r
+{\r
+ union {\r
+ __I uint8_t RBR;\r
+ __O uint8_t THR;\r
+ __IO uint8_t DLL;\r
+ uint32_t RESERVED0;\r
+ };\r
+ union {\r
+ __IO uint8_t DLM;\r
+ __IO uint32_t IER;\r
+ };\r
+ union {\r
+ __I uint32_t IIR;\r
+ __O uint8_t FCR;\r
+ };\r
+ __IO uint8_t LCR;\r
+ uint8_t RESERVED1[7];\r
+ __IO uint8_t LSR;\r
+ uint8_t RESERVED2[7];\r
+ __IO uint8_t SCR;\r
+ uint8_t RESERVED3[3];\r
+ __IO uint32_t ACR;\r
+ __IO uint8_t ICR;\r
+ uint8_t RESERVED4[3];\r
+ __IO uint8_t FDR;\r
+ uint8_t RESERVED5[7];\r
+ __IO uint8_t TER;\r
+ uint8_t RESERVED6[27];\r
+ __IO uint8_t RS485CTRL;\r
+ uint8_t RESERVED7[3];\r
+ __IO uint8_t ADRMATCH;\r
+} UART_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ union {\r
+ __I uint8_t RBR;\r
+ __O uint8_t THR;\r
+ __IO uint8_t DLL;\r
+ uint32_t RESERVED0;\r
+ };\r
+ union {\r
+ __IO uint8_t DLM;\r
+ __IO uint32_t IER;\r
+ };\r
+ union {\r
+ __I uint32_t IIR;\r
+ __O uint8_t FCR;\r
+ };\r
+ __IO uint8_t LCR;\r
+ uint8_t RESERVED1[3];\r
+ __IO uint8_t MCR;\r
+ uint8_t RESERVED2[3];\r
+ __IO uint8_t LSR;\r
+ uint8_t RESERVED3[3];\r
+ __IO uint8_t MSR;\r
+ uint8_t RESERVED4[3];\r
+ __IO uint8_t SCR;\r
+ uint8_t RESERVED5[3];\r
+ __IO uint32_t ACR;\r
+ uint32_t RESERVED6;\r
+ __IO uint32_t FDR;\r
+ uint32_t RESERVED7;\r
+ __IO uint8_t TER;\r
+ uint8_t RESERVED8[27];\r
+ __IO uint8_t RS485CTRL;\r
+ uint8_t RESERVED9[3];\r
+ __IO uint8_t ADRMATCH;\r
+ uint8_t RESERVED10[3];\r
+ __IO uint8_t RS485DLY;\r
+} UART1_TypeDef;\r
+\r
+/*------------- Serial Peripheral Interface (SPI) ----------------------------*/\r
+typedef struct\r
+{\r
+ __IO uint32_t SPCR;\r
+ __I uint32_t SPSR;\r
+ __IO uint32_t SPDR;\r
+ __IO uint32_t SPCCR;\r
+ uint32_t RESERVED0[3];\r
+ __IO uint32_t SPINT;\r
+} SPI_TypeDef;\r
+\r
+/*------------- Synchronous Serial Communication (SSP) -----------------------*/\r
+typedef struct\r
+{\r
+ __IO uint32_t CR0;\r
+ __IO uint32_t CR1;\r
+ __IO uint32_t DR;\r
+ __I uint32_t SR;\r
+ __IO uint32_t CPSR;\r
+ __IO uint32_t IMSC;\r
+ __IO uint32_t RIS;\r
+ __IO uint32_t MIS;\r
+ __IO uint32_t ICR;\r
+ __IO uint32_t DMACR;\r
+} SSP_TypeDef;\r
+\r
+/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/\r
+typedef struct\r
+{\r
+ __IO uint32_t I2CONSET;\r
+ __I uint32_t I2STAT;\r
+ __IO uint32_t I2DAT;\r
+ __IO uint32_t I2ADR0;\r
+ __IO uint32_t I2SCLH;\r
+ __IO uint32_t I2SCLL;\r
+ __O uint32_t I2CONCLR;\r
+ __IO uint32_t MMCTRL;\r
+ __IO uint32_t I2ADR1;\r
+ __IO uint32_t I2ADR2;\r
+ __IO uint32_t I2ADR3;\r
+ __I uint32_t I2DATA_BUFFER;\r
+ __IO uint32_t I2MASK0;\r
+ __IO uint32_t I2MASK1;\r
+ __IO uint32_t I2MASK2;\r
+ __IO uint32_t I2MASK3;\r
+} I2C_TypeDef;\r
+\r
+/*------------- Inter IC Sound (I2S) -----------------------------------------*/\r
+typedef struct\r
+{\r
+ __IO uint32_t I2SDAO;\r
+ __IO uint32_t I2SDAI;\r
+ __O uint32_t I2STXFIFO;\r
+ __I uint32_t I2SRXFIFO;\r
+ __I uint32_t I2SSTATE;\r
+ __IO uint32_t I2SDMA1;\r
+ __IO uint32_t I2SDMA2;\r
+ __IO uint32_t I2SIRQ;\r
+ __IO uint32_t I2STXRATE;\r
+ __IO uint32_t I2SRXRATE;\r
+ __IO uint32_t I2STXBITRATE;\r
+ __IO uint32_t I2SRXBITRATE;\r
+ __IO uint32_t I2STXMODE;\r
+ __IO uint32_t I2SRXMODE;\r
+} I2S_TypeDef;\r
+\r
+/*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/\r
+typedef struct\r
+{\r
+ __IO uint32_t RICOMPVAL;\r
+ __IO uint32_t RIMASK;\r
+ __IO uint8_t RICTRL;\r
+ uint8_t RESERVED0[3];\r
+ __IO uint32_t RICOUNTER;\r
+} RIT_TypeDef;\r
+\r
+/*------------- Real-Time Clock (RTC) ----------------------------------------*/\r
+typedef struct\r
+{\r
+ __IO uint8_t ILR;\r
+ uint8_t RESERVED0[3];\r
+ __IO uint8_t CCR;\r
+ uint8_t RESERVED1[3];\r
+ __IO uint8_t CIIR;\r
+ uint8_t RESERVED2[3];\r
+ __IO uint8_t AMR;\r
+ uint8_t RESERVED3[3];\r
+ __I uint32_t CTIME0;\r
+ __I uint32_t CTIME1;\r
+ __I uint32_t CTIME2;\r
+ __IO uint8_t SEC;\r
+ uint8_t RESERVED4[3];\r
+ __IO uint8_t MIN;\r
+ uint8_t RESERVED5[3];\r
+ __IO uint8_t HOUR;\r
+ uint8_t RESERVED6[3];\r
+ __IO uint8_t DOM;\r
+ uint8_t RESERVED7[3];\r
+ __IO uint8_t DOW;\r
+ uint8_t RESERVED8[3];\r
+ __IO uint16_t DOY;\r
+ uint16_t RESERVED9;\r
+ __IO uint8_t MONTH;\r
+ uint8_t RESERVED10[3];\r
+ __IO uint16_t YEAR;\r
+ uint16_t RESERVED11;\r
+ __IO uint32_t CALIBRATION;\r
+ __IO uint32_t GPREG0;\r
+ __IO uint32_t GPREG1;\r
+ __IO uint32_t GPREG2;\r
+ __IO uint32_t GPREG3;\r
+ __IO uint32_t GPREG4;\r
+ __IO uint8_t WAKEUPDIS;\r
+ uint8_t RESERVED12[3];\r
+ __IO uint8_t PWRCTRL;\r
+ uint8_t RESERVED13[3];\r
+ __IO uint8_t ALSEC;\r
+ uint8_t RESERVED14[3];\r
+ __IO uint8_t ALMIN;\r
+ uint8_t RESERVED15[3];\r
+ __IO uint8_t ALHOUR;\r
+ uint8_t RESERVED16[3];\r
+ __IO uint8_t ALDOM;\r
+ uint8_t RESERVED17[3];\r
+ __IO uint8_t ALDOW;\r
+ uint8_t RESERVED18[3];\r
+ __IO uint16_t ALDOY;\r
+ uint16_t RESERVED19;\r
+ __IO uint8_t ALMON;\r
+ uint8_t RESERVED20[3];\r
+ __IO uint16_t ALYEAR;\r
+ uint16_t RESERVED21;\r
+} RTC_TypeDef;\r
+\r
+/*------------- Watchdog Timer (WDT) -----------------------------------------*/\r
+typedef struct\r
+{\r
+ __IO uint8_t WDMOD;\r
+ uint8_t RESERVED0[3];\r
+ __IO uint32_t WDTC;\r
+ __O uint8_t WDFEED;\r
+ uint8_t RESERVED1[3];\r
+ __I uint32_t WDTV;\r
+ __IO uint32_t WDCLKSEL;\r
+} WDT_TypeDef;\r
+\r
+/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/\r
+typedef struct\r
+{\r
+ __IO uint32_t ADCR;\r
+ __IO uint32_t ADGDR;\r
+ uint32_t RESERVED0;\r
+ __IO uint32_t ADINTEN;\r
+ __I uint32_t ADDR0;\r
+ __I uint32_t ADDR1;\r
+ __I uint32_t ADDR2;\r
+ __I uint32_t ADDR3;\r
+ __I uint32_t ADDR4;\r
+ __I uint32_t ADDR5;\r
+ __I uint32_t ADDR6;\r
+ __I uint32_t ADDR7;\r
+ __I uint32_t ADSTAT;\r
+ __IO uint32_t ADTRM;\r
+} ADC_TypeDef;\r
+\r
+/*------------- Digital-to-Analog Converter (DAC) ----------------------------*/\r
+typedef struct\r
+{\r
+ __IO uint32_t DACR;\r
+ __IO uint32_t DACCTRL;\r
+ __IO uint16_t DACCNTVAL;\r
+} DAC_TypeDef;\r
+\r
+/*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/\r
+typedef struct\r
+{\r
+ __I uint32_t MCCON;\r
+ __O uint32_t MCCON_SET;\r
+ __O uint32_t MCCON_CLR;\r
+ __I uint32_t MCCAPCON;\r
+ __O uint32_t MCCAPCON_SET;\r
+ __O uint32_t MCCAPCON_CLR;\r
+ __IO uint32_t MCTIM0;\r
+ __IO uint32_t MCTIM1;\r
+ __IO uint32_t MCTIM2;\r
+ __IO uint32_t MCPER0;\r
+ __IO uint32_t MCPER1;\r
+ __IO uint32_t MCPER2;\r
+ __IO uint32_t MCPW0;\r
+ __IO uint32_t MCPW1;\r
+ __IO uint32_t MCPW2;\r
+ __IO uint32_t MCDEADTIME;\r
+ __IO uint32_t MCCCP;\r
+ __IO uint32_t MCCR0;\r
+ __IO uint32_t MCCR1;\r
+ __IO uint32_t MCCR2;\r
+ __I uint32_t MCINTEN;\r
+ __O uint32_t MCINTEN_SET;\r
+ __O uint32_t MCINTEN_CLR;\r
+ __I uint32_t MCCNTCON;\r
+ __O uint32_t MCCNTCON_SET;\r
+ __O uint32_t MCCNTCON_CLR;\r
+ __I uint32_t MCINTFLAG;\r
+ __O uint32_t MCINTFLAG_SET;\r
+ __O uint32_t MCINTFLAG_CLR;\r
+ __O uint32_t MCCAP_CLR;\r
+} MCPWM_TypeDef;\r
+\r
+/*------------- Quadrature Encoder Interface (QEI) ---------------------------*/\r
+typedef struct\r
+{\r
+ __O uint32_t QEICON;\r
+ __I uint32_t QEISTAT;\r
+ __IO uint32_t QEICONF;\r
+ __I uint32_t QEIPOS;\r
+ __IO uint32_t QEIMAXPOS;\r
+ __IO uint32_t CMPOS0;\r
+ __IO uint32_t CMPOS1;\r
+ __IO uint32_t CMPOS2;\r
+ __I uint32_t INXCNT;\r
+ __IO uint32_t INXCMP;\r
+ __IO uint32_t QEILOAD;\r
+ __I uint32_t QEITIME;\r
+ __I uint32_t QEIVEL;\r
+ __I uint32_t QEICAP;\r
+ __IO uint32_t VELCOMP;\r
+ __IO uint32_t FILTER;\r
+ uint32_t RESERVED0[998];\r
+ __O uint32_t QEIIEC;\r
+ __O uint32_t QEIIES;\r
+ __I uint32_t QEIINTSTAT;\r
+ __I uint32_t QEIIE;\r
+ __O uint32_t QEICLR;\r
+ __O uint32_t QEISET;\r
+} QEI_TypeDef;\r
+\r
+/*------------- Controller Area Network (CAN) --------------------------------*/\r
+typedef struct\r
+{\r
+ __IO uint32_t mask[512]; /* ID Masks */\r
+} CANAF_RAM_TypeDef;\r
+\r
+typedef struct /* Acceptance Filter Registers */\r
+{\r
+ __IO uint32_t AFMR;\r
+ __IO uint32_t SFF_sa;\r
+ __IO uint32_t SFF_GRP_sa;\r
+ __IO uint32_t EFF_sa;\r
+ __IO uint32_t EFF_GRP_sa;\r
+ __IO uint32_t ENDofTable;\r
+ __I uint32_t LUTerrAd;\r
+ __I uint32_t LUTerr;\r
+} CANAF_TypeDef;\r
+\r
+typedef struct /* Central Registers */\r
+{\r
+ __I uint32_t CANTxSR;\r
+ __I uint32_t CANRxSR;\r
+ __I uint32_t CANMSR;\r
+} CANCR_TypeDef;\r
+\r
+typedef struct /* Controller Registers */\r
+{\r
+ __IO uint32_t MOD;\r
+ __O uint32_t CMR;\r
+ __IO uint32_t GSR;\r
+ __I uint32_t ICR;\r
+ __IO uint32_t IER;\r
+ __IO uint32_t BTR;\r
+ __IO uint32_t EWL;\r
+ __I uint32_t SR;\r
+ __IO uint32_t RFS;\r
+ __IO uint32_t RID;\r
+ __IO uint32_t RDA;\r
+ __IO uint32_t RDB;\r
+ __IO uint32_t TFI1;\r
+ __IO uint32_t TID1;\r
+ __IO uint32_t TDA1;\r
+ __IO uint32_t TDB1;\r
+ __IO uint32_t TFI2;\r
+ __IO uint32_t TID2;\r
+ __IO uint32_t TDA2;\r
+ __IO uint32_t TDB2;\r
+ __IO uint32_t TFI3;\r
+ __IO uint32_t TID3;\r
+ __IO uint32_t TDA3;\r
+ __IO uint32_t TDB3;\r
+} CAN_TypeDef;\r
+\r
+/*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/\r
+typedef struct /* Common Registers */\r
+{\r
+ __I uint32_t DMACIntStat;\r
+ __I uint32_t DMACIntTCStat;\r
+ __O uint32_t DMACIntTCClear;\r
+ __I uint32_t DMACIntErrStat;\r
+ __O uint32_t DMACIntErrClr;\r
+ __I uint32_t DMACRawIntTCStat;\r
+ __I uint32_t DMACRawIntErrStat;\r
+ __I uint32_t DMACEnbldChns;\r
+ __IO uint32_t DMACSoftBReq;\r
+ __IO uint32_t DMACSoftSReq;\r
+ __IO uint32_t DMACSoftLBReq;\r
+ __IO uint32_t DMACSoftLSReq;\r
+ __IO uint32_t DMACConfig;\r
+ __IO uint32_t DMACSync;\r
+} GPDMA_TypeDef;\r
+\r
+typedef struct /* Channel Registers */\r
+{\r
+ __IO uint32_t DMACCSrcAddr;\r
+ __IO uint32_t DMACCDestAddr;\r
+ __IO uint32_t DMACCLLI;\r
+ __IO uint32_t DMACCControl;\r
+ __IO uint32_t DMACCConfig;\r
+} GPDMACH_TypeDef;\r
+\r
+/*------------- Universal Serial Bus (USB) -----------------------------------*/\r
+typedef struct\r
+{\r
+ __I uint32_t HcRevision; /* USB Host Registers */\r
+ __IO uint32_t HcControl;\r
+ __IO uint32_t HcCommandStatus;\r
+ __IO uint32_t HcInterruptStatus;\r
+ __IO uint32_t HcInterruptEnable;\r
+ __IO uint32_t HcInterruptDisable;\r
+ __IO uint32_t HcHCCA;\r
+ __I uint32_t HcPeriodCurrentED;\r
+ __IO uint32_t HcControlHeadED;\r
+ __IO uint32_t HcControlCurrentED;\r
+ __IO uint32_t HcBulkHeadED;\r
+ __IO uint32_t HcBulkCurrentED;\r
+ __I uint32_t HcDoneHead;\r
+ __IO uint32_t HcFmInterval;\r
+ __I uint32_t HcFmRemaining;\r
+ __I uint32_t HcFmNumber;\r
+ __IO uint32_t HcPeriodicStart;\r
+ __IO uint32_t HcLSTreshold;\r
+ __IO uint32_t HcRhDescriptorA;\r
+ __IO uint32_t HcRhDescriptorB;\r
+ __IO uint32_t HcRhStatus;\r
+ __IO uint32_t HcRhPortStatus1;\r
+ __IO uint32_t HcRhPortStatus2;\r
+ uint32_t RESERVED0[40];\r
+ __I uint32_t Module_ID;\r
+\r
+ __I uint32_t OTGIntSt; /* USB On-The-Go Registers */\r
+ __IO uint32_t OTGIntEn;\r
+ __O uint32_t OTGIntSet;\r
+ __O uint32_t OTGIntClr;\r
+ __IO uint32_t OTGStCtrl;\r
+ __IO uint32_t OTGTmr;\r
+ uint32_t RESERVED1[58];\r
+\r
+ __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */\r
+ __IO uint32_t USBDevIntEn;\r
+ __O uint32_t USBDevIntClr;\r
+ __O uint32_t USBDevIntSet;\r
+\r
+ __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */\r
+ __I uint32_t USBCmdData;\r
+\r
+ __I uint32_t USBRxData; /* USB Device Transfer Registers */\r
+ __O uint32_t USBTxData;\r
+ __I uint32_t USBRxPLen;\r
+ __O uint32_t USBTxPLen;\r
+ __IO uint32_t USBCtrl;\r
+ __O uint32_t USBDevIntPri;\r
+\r
+ __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */\r
+ __IO uint32_t USBEpIntEn;\r
+ __O uint32_t USBEpIntClr;\r
+ __O uint32_t USBEpIntSet;\r
+ __O uint32_t USBEpIntPri;\r
+\r
+ __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/\r
+ __O uint32_t USBEpInd;\r
+ __IO uint32_t USBMaxPSize;\r
+\r
+ __I uint32_t USBDMARSt; /* USB Device DMA Registers */\r
+ __O uint32_t USBDMARClr;\r
+ __O uint32_t USBDMARSet;\r
+ uint32_t RESERVED2[9];\r
+ __IO uint32_t USBUDCAH;\r
+ __I uint32_t USBEpDMASt;\r
+ __O uint32_t USBEpDMAEn;\r
+ __O uint32_t USBEpDMADis;\r
+ __I uint32_t USBDMAIntSt;\r
+ __IO uint32_t USBDMAIntEn;\r
+ uint32_t RESERVED3[2];\r
+ __I uint32_t USBEoTIntSt;\r
+ __O uint32_t USBEoTIntClr;\r
+ __O uint32_t USBEoTIntSet;\r
+ __I uint32_t USBNDDRIntSt;\r
+ __O uint32_t USBNDDRIntClr;\r
+ __O uint32_t USBNDDRIntSet;\r
+ __I uint32_t USBSysErrIntSt;\r
+ __O uint32_t USBSysErrIntClr;\r
+ __O uint32_t USBSysErrIntSet;\r
+ uint32_t RESERVED4[15];\r
+\r
+ __I uint32_t I2C_RX; /* USB OTG I2C Registers */\r
+ __O uint32_t I2C_WO;\r
+ __I uint32_t I2C_STS;\r
+ __IO uint32_t I2C_CTL;\r
+ __IO uint32_t I2C_CLKHI;\r
+ __O uint32_t I2C_CLKLO;\r
+ uint32_t RESERVED5[823];\r
+\r
+ union {\r
+ __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */\r
+ __IO uint32_t OTGClkCtrl;\r
+ } ;\r
+ union {\r
+ __I uint32_t USBClkSt;\r
+ __I uint32_t OTGClkSt;\r
+ };\r
+} USB_TypeDef;\r
+\r
+/*------------- Ethernet Media Access Controller (EMAC) ----------------------*/\r
+typedef struct\r
+{\r
+ __IO uint32_t MAC1; /* MAC Registers */\r
+ __IO uint32_t MAC2;\r
+ __IO uint32_t IPGT;\r
+ __IO uint32_t IPGR;\r
+ __IO uint32_t CLRT;\r
+ __IO uint32_t MAXF;\r
+ __IO uint32_t SUPP;\r
+ __IO uint32_t TEST;\r
+ __IO uint32_t MCFG;\r
+ __IO uint32_t MCMD;\r
+ __IO uint32_t MADR;\r
+ __O uint32_t MWTD;\r
+ __I uint32_t MRDD;\r
+ __I uint32_t MIND;\r
+ uint32_t RESERVED0[2];\r
+ __IO uint32_t SA0;\r
+ __IO uint32_t SA1;\r
+ __IO uint32_t SA2;\r
+ uint32_t RESERVED1[45];\r
+ __IO uint32_t Command; /* Control Registers */\r
+ __I uint32_t Status;\r
+ __IO uint32_t RxDescriptor;\r
+ __IO uint32_t RxStatus;\r
+ __IO uint32_t RxDescriptorNumber;\r
+ __I uint32_t RxProduceIndex;\r
+ __IO uint32_t RxConsumeIndex;\r
+ __IO uint32_t TxDescriptor;\r
+ __IO uint32_t TxStatus;\r
+ __IO uint32_t TxDescriptorNumber;\r
+ __IO uint32_t TxProduceIndex;\r
+ __I uint32_t TxConsumeIndex;\r
+ uint32_t RESERVED2[10];\r
+ __I uint32_t TSV0;\r
+ __I uint32_t TSV1;\r
+ __I uint32_t RSV;\r
+ uint32_t RESERVED3[3];\r
+ __IO uint32_t FlowControlCounter;\r
+ __I uint32_t FlowControlStatus;\r
+ uint32_t RESERVED4[34];\r
+ __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */\r
+ __IO uint32_t RxFilterWoLStatus;\r
+ __IO uint32_t RxFilterWoLClear;\r
+ uint32_t RESERVED5;\r
+ __IO uint32_t HashFilterL;\r
+ __IO uint32_t HashFilterH;\r
+ uint32_t RESERVED6[882];\r
+ __I uint32_t IntStatus; /* Module Control Registers */\r
+ __IO uint32_t IntEnable;\r
+ __O uint32_t IntClear;\r
+ __O uint32_t IntSet;\r
+ uint32_t RESERVED7;\r
+ __IO uint32_t PowerDown;\r
+ uint32_t RESERVED8;\r
+ __IO uint32_t Module_ID;\r
+} EMAC_TypeDef;\r
+\r
+/******************************************************************************/\r
+/* Peripheral memory map */\r
+/******************************************************************************/\r
+/* Base addresses */\r
+#define FLASH_BASE (0x00000000UL)\r
+#define RAM_BASE (0x10000000UL)\r
+#define GPIO_BASE (0x2009C000UL)\r
+#define APB0_BASE (0x40000000UL)\r
+#define APB1_BASE (0x40080000UL)\r
+#define AHB_BASE (0x50000000UL)\r
+#define CM3_BASE (0xE0000000UL)\r
+\r
+/* APB0 peripherals */\r
+#define WDT_BASE (APB0_BASE + 0x00000)\r
+#define TIM0_BASE (APB0_BASE + 0x04000)\r
+#define TIM1_BASE (APB0_BASE + 0x08000)\r
+#define UART0_BASE (APB0_BASE + 0x0C000)\r
+#define UART1_BASE (APB0_BASE + 0x10000)\r
+#define PWM1_BASE (APB0_BASE + 0x18000)\r
+#define I2C0_BASE (APB0_BASE + 0x1C000)\r
+#define SPI_BASE (APB0_BASE + 0x20000)\r
+#define RTC_BASE (APB0_BASE + 0x24000)\r
+#define GPIOINT_BASE (APB0_BASE + 0x28080)\r
+#define PINCON_BASE (APB0_BASE + 0x2C000)\r
+#define SSP1_BASE (APB0_BASE + 0x30000)\r
+#define ADC_BASE (APB0_BASE + 0x34000)\r
+#define CANAF_RAM_BASE (APB0_BASE + 0x38000)\r
+#define CANAF_BASE (APB0_BASE + 0x3C000)\r
+#define CANCR_BASE (APB0_BASE + 0x40000)\r
+#define CAN1_BASE (APB0_BASE + 0x44000)\r
+#define CAN2_BASE (APB0_BASE + 0x48000)\r
+#define I2C1_BASE (APB0_BASE + 0x5C000)\r
+\r
+/* APB1 peripherals */\r
+#define SSP0_BASE (APB1_BASE + 0x08000)\r
+#define DAC_BASE (APB1_BASE + 0x0C000)\r
+#define TIM2_BASE (APB1_BASE + 0x10000)\r
+#define TIM3_BASE (APB1_BASE + 0x14000)\r
+#define UART2_BASE (APB1_BASE + 0x18000)\r
+#define UART3_BASE (APB1_BASE + 0x1C000)\r
+#define I2C2_BASE (APB1_BASE + 0x20000)\r
+#define I2S_BASE (APB1_BASE + 0x28000)\r
+#define RIT_BASE (APB1_BASE + 0x30000)\r
+#define MCPWM_BASE (APB1_BASE + 0x38000)\r
+#define QEI_BASE (APB1_BASE + 0x3C000)\r
+#define SC_BASE (APB1_BASE + 0x7C000)\r
+\r
+/* AHB peripherals */\r
+#define EMAC_BASE (AHB_BASE + 0x00000)\r
+#define GPDMA_BASE (AHB_BASE + 0x04000)\r
+#define GPDMACH0_BASE (AHB_BASE + 0x04100)\r
+#define GPDMACH1_BASE (AHB_BASE + 0x04120)\r
+#define GPDMACH2_BASE (AHB_BASE + 0x04140)\r
+#define GPDMACH3_BASE (AHB_BASE + 0x04160)\r
+#define GPDMACH4_BASE (AHB_BASE + 0x04180)\r
+#define GPDMACH5_BASE (AHB_BASE + 0x041A0)\r
+#define GPDMACH6_BASE (AHB_BASE + 0x041C0)\r
+#define GPDMACH7_BASE (AHB_BASE + 0x041E0)\r
+#define USB_BASE (AHB_BASE + 0x0C000)\r
+\r
+/* GPIOs */\r
+#define GPIO0_BASE (GPIO_BASE + 0x00000)\r
+#define GPIO1_BASE (GPIO_BASE + 0x00020)\r
+#define GPIO2_BASE (GPIO_BASE + 0x00040)\r
+#define GPIO3_BASE (GPIO_BASE + 0x00060)\r
+#define GPIO4_BASE (GPIO_BASE + 0x00080)\r
+\r
+\r
+/******************************************************************************/\r
+/* Peripheral declaration */\r
+/******************************************************************************/\r
+#define SC (( SC_TypeDef *) SC_BASE)\r
+#define GPIO0 (( GPIO_TypeDef *) GPIO0_BASE)\r
+#define GPIO1 (( GPIO_TypeDef *) GPIO1_BASE)\r
+#define GPIO2 (( GPIO_TypeDef *) GPIO2_BASE)\r
+#define GPIO3 (( GPIO_TypeDef *) GPIO3_BASE)\r
+#define GPIO4 (( GPIO_TypeDef *) GPIO4_BASE)\r
+#define WDT (( WDT_TypeDef *) WDT_BASE)\r
+#define TIM0 (( TIM_TypeDef *) TIM0_BASE)\r
+#define TIM1 (( TIM_TypeDef *) TIM1_BASE)\r
+#define TIM2 (( TIM_TypeDef *) TIM2_BASE)\r
+#define TIM3 (( TIM_TypeDef *) TIM3_BASE)\r
+#define RIT (( RIT_TypeDef *) RIT_BASE)\r
+#define UART0 (( UART_TypeDef *) UART0_BASE)\r
+#define UART1 (( UART1_TypeDef *) UART1_BASE)\r
+#define UART2 (( UART_TypeDef *) UART2_BASE)\r
+#define UART3 (( UART_TypeDef *) UART3_BASE)\r
+#define PWM1 (( PWM_TypeDef *) PWM1_BASE)\r
+#define I2C0 (( I2C_TypeDef *) I2C0_BASE)\r
+#define I2C1 (( I2C_TypeDef *) I2C1_BASE)\r
+#define I2C2 (( I2C_TypeDef *) I2C2_BASE)\r
+#define I2S (( I2S_TypeDef *) I2S_BASE)\r
+#define SPI (( SPI_TypeDef *) SPI_BASE)\r
+#define RTC (( RTC_TypeDef *) RTC_BASE)\r
+#define GPIOINT (( GPIOINT_TypeDef *) GPIOINT_BASE)\r
+#define PINCON (( PINCON_TypeDef *) PINCON_BASE)\r
+#define SSP0 (( SSP_TypeDef *) SSP0_BASE)\r
+#define SSP1 (( SSP_TypeDef *) SSP1_BASE)\r
+#define ADC (( ADC_TypeDef *) ADC_BASE)\r
+#define DAC (( DAC_TypeDef *) DAC_BASE)\r
+#define CANAF_RAM ((CANAF_RAM_TypeDef *) CANAF_RAM_BASE)\r
+#define CANAF (( CANAF_TypeDef *) CANAF_BASE)\r
+#define CANCR (( CANCR_TypeDef *) CANCR_BASE)\r
+#define CAN1 (( CAN_TypeDef *) CAN1_BASE)\r
+#define CAN2 (( CAN_TypeDef *) CAN2_BASE)\r
+#define MCPWM (( MCPWM_TypeDef *) MCPWM_BASE)\r
+#define QEI (( QEI_TypeDef *) QEI_BASE)\r
+#define EMAC (( EMAC_TypeDef *) EMAC_BASE)\r
+#define GPDMA (( GPDMA_TypeDef *) GPDMA_BASE)\r
+#define GPDMACH0 (( GPDMACH_TypeDef *) GPDMACH0_BASE)\r
+#define GPDMACH1 (( GPDMACH_TypeDef *) GPDMACH1_BASE)\r
+#define GPDMACH2 (( GPDMACH_TypeDef *) GPDMACH2_BASE)\r
+#define GPDMACH3 (( GPDMACH_TypeDef *) GPDMACH3_BASE)\r
+#define GPDMACH4 (( GPDMACH_TypeDef *) GPDMACH4_BASE)\r
+#define GPDMACH5 (( GPDMACH_TypeDef *) GPDMACH5_BASE)\r
+#define GPDMACH6 (( GPDMACH_TypeDef *) GPDMACH6_BASE)\r
+#define GPDMACH7 (( GPDMACH_TypeDef *) GPDMACH7_BASE)\r
+#define USB (( USB_TypeDef *) USB_BASE)\r
+\r
+#endif // __LPC17xx_H__\r
+\r
+\r
+#endif\r
--- /dev/null
+/******************************************************************************\r
+ * @file: core_cm3.h\r
+ * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Header File\r
+ * @version: V1.20\r
+ * @date: 22. May 2009\r
+ *----------------------------------------------------------------------------\r
+ *\r
+ * Copyright (C) 2009 ARM Limited. All rights reserved.\r
+ *\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-Mx \r
+ * processor based microcontrollers. This file can be freely distributed \r
+ * within development tools that are supporting such ARM based processors. \r
+ *\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#ifndef __CM3_CORE_H__\r
+#define __CM3_CORE_H__\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif \r
+\r
+#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */\r
+#define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */\r
+#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */\r
+\r
+#define __CORTEX_M (0x03) /*!< Cortex core */\r
+\r
+/**\r
+ * Lint configuration \n\r
+ * ----------------------- \n\r
+ *\r
+ * The following Lint messages will be suppressed and not shown: \n\r
+ * \n\r
+ * --- Error 10: --- \n\r
+ * register uint32_t __regBasePri __asm("basepri"); \n\r
+ * Error 10: Expecting ';' \n\r
+ * \n\r
+ * --- Error 530: --- \n\r
+ * return(__regBasePri); \n\r
+ * Warning 530: Symbol '__regBasePri' (line 264) not initialized \n\r
+ * \n\r
+ * --- Error 550: --- \n\r
+ * __regBasePri = (basePri & 0x1ff); \n\r
+ * } \n\r
+ * Warning 550: Symbol '__regBasePri' (line 271) not accessed \n\r
+ * \n\r
+ * --- Error 754: --- \n\r
+ * uint32_t RESERVED0[24]; \n\r
+ * Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced \n\r
+ * \n\r
+ * --- Error 750: --- \n\r
+ * #define __CM3_CORE_H__ \n\r
+ * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced \n\r
+ * \n\r
+ * --- Error 528: --- \n\r
+ * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n\r
+ * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced \n\r
+ * \n\r
+ * --- Error 751: --- \n\r
+ * } InterruptType_Type; \n\r
+ * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced \n\r
+ * \n\r
+ * \n\r
+ * Note: To re-enable a Message, insert a space before 'lint' * \n\r
+ *\r
+ */\r
+\r
+/*lint -save */\r
+/*lint -e10 */\r
+/*lint -e530 */\r
+/*lint -e550 */\r
+/*lint -e754 */\r
+/*lint -e750 */\r
+/*lint -e528 */\r
+/*lint -e751 */\r
+\r
+\r
+#include <stdint.h> /* Include standard types */\r
+\r
+#if defined (__ICCARM__)\r
+ #include <intrinsics.h> /* IAR Intrinsics */\r
+#endif\r
+\r
+\r
+#ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */\r
+#endif\r
+\r
+\r
+\r
+\r
+/**\r
+ * IO definitions\r
+ *\r
+ * define access restrictions to peripheral registers\r
+ */\r
+\r
+#ifdef __cplusplus\r
+#define __I volatile /*!< defines 'read only' permissions */\r
+#else\r
+#define __I volatile const /*!< defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< defines 'write only' permissions */\r
+#define __IO volatile /*!< defines 'read / write' permissions */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ ******************************************************************************/\r
+\r
+\r
+/* System Reset */\r
+#define NVIC_VECTRESET 0 /*!< Vector Reset Bit */\r
+#define NVIC_SYSRESETREQ 2 /*!< System Reset Request */\r
+#define NVIC_AIRCR_VECTKEY (0x5FA << 16) /*!< AIRCR Key for write access */\r
+#define NVIC_AIRCR_ENDIANESS 15 /*!< Endianess */\r
+\r
+/* Core Debug */\r
+#define CoreDebug_DEMCR_TRCENA (1 << 24) /*!< DEMCR TRCENA enable */\r
+#define ITM_TCR_ITMENA 1 /*!< ITM enable */\r
+\r
+\r
+\r
+\r
+/* memory mapping struct for Nested Vectored Interrupt Controller (NVIC) */\r
+typedef struct\r
+{\r
+ __IO uint32_t ISER[8]; /*!< Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[24];\r
+ __IO uint32_t ICER[8]; /*!< Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[24];\r
+ __IO uint32_t ISPR[8]; /*!< Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[24];\r
+ __IO uint32_t ICPR[8]; /*!< Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[24];\r
+ __IO uint32_t IABR[8]; /*!< Interrupt Active bit Register */\r
+ uint32_t RESERVED4[56];\r
+ __IO uint8_t IP[240]; /*!< Interrupt Priority Register, 8Bit wide */\r
+ uint32_t RESERVED5[644];\r
+ __O uint32_t STIR; /*!< Software Trigger Interrupt Register */\r
+} NVIC_Type;\r
+\r
+\r
+/* memory mapping struct for System Control Block */\r
+typedef struct\r
+{\r
+ __I uint32_t CPUID; /*!< CPU ID Base Register */\r
+ __IO uint32_t ICSR; /*!< Interrupt Control State Register */\r
+ __IO uint32_t VTOR; /*!< Vector Table Offset Register */\r
+ __IO uint32_t AIRCR; /*!< Application Interrupt / Reset Control Register */\r
+ __IO uint32_t SCR; /*!< System Control Register */\r
+ __IO uint32_t CCR; /*!< Configuration Control Register */\r
+ __IO uint8_t SHP[12]; /*!< System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
+ __IO uint32_t SHCSR; /*!< System Handler Control and State Register */\r
+ __IO uint32_t CFSR; /*!< Configurable Fault Status Register */\r
+ __IO uint32_t HFSR; /*!< Hard Fault Status Register */\r
+ __IO uint32_t DFSR; /*!< Debug Fault Status Register */\r
+ __IO uint32_t MMFAR; /*!< Mem Manage Address Register */\r
+ __IO uint32_t BFAR; /*!< Bus Fault Address Register */\r
+ __IO uint32_t AFSR; /*!< Auxiliary Fault Status Register */\r
+ __I uint32_t PFR[2]; /*!< Processor Feature Register */\r
+ __I uint32_t DFR; /*!< Debug Feature Register */\r
+ __I uint32_t ADR; /*!< Auxiliary Feature Register */\r
+ __I uint32_t MMFR[4]; /*!< Memory Model Feature Register */\r
+ __I uint32_t ISAR[5]; /*!< ISA Feature Register */\r
+} SCB_Type;\r
+\r
+\r
+/* memory mapping struct for SysTick */\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /*!< SysTick Control and Status Register */\r
+ __IO uint32_t LOAD; /*!< SysTick Reload Value Register */\r
+ __IO uint32_t VAL; /*!< SysTick Current Value Register */\r
+ __I uint32_t CALIB; /*!< SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+\r
+/* memory mapping structur for ITM */\r
+typedef struct\r
+{\r
+ __O union \r
+ {\r
+ __O uint8_t u8; /*!< ITM Stimulus Port 8-bit */\r
+ __O uint16_t u16; /*!< ITM Stimulus Port 16-bit */\r
+ __O uint32_t u32; /*!< ITM Stimulus Port 32-bit */\r
+ } PORT [32]; /*!< ITM Stimulus Port Registers */\r
+ uint32_t RESERVED0[864];\r
+ __IO uint32_t TER; /*!< ITM Trace Enable Register */\r
+ uint32_t RESERVED1[15];\r
+ __IO uint32_t TPR; /*!< ITM Trace Privilege Register */\r
+ uint32_t RESERVED2[15];\r
+ __IO uint32_t TCR; /*!< ITM Trace Control Register */\r
+ uint32_t RESERVED3[29];\r
+ __IO uint32_t IWR; /*!< ITM Integration Write Register */\r
+ __IO uint32_t IRR; /*!< ITM Integration Read Register */\r
+ __IO uint32_t IMCR; /*!< ITM Integration Mode Control Register */\r
+ uint32_t RESERVED4[43];\r
+ __IO uint32_t LAR; /*!< ITM Lock Access Register */\r
+ __IO uint32_t LSR; /*!< ITM Lock Status Register */\r
+ uint32_t RESERVED5[6];\r
+ __I uint32_t PID4; /*!< ITM Product ID Registers */\r
+ __I uint32_t PID5;\r
+ __I uint32_t PID6;\r
+ __I uint32_t PID7;\r
+ __I uint32_t PID0;\r
+ __I uint32_t PID1;\r
+ __I uint32_t PID2;\r
+ __I uint32_t PID3;\r
+ __I uint32_t CID0;\r
+ __I uint32_t CID1;\r
+ __I uint32_t CID2;\r
+ __I uint32_t CID3;\r
+} ITM_Type;\r
+\r
+\r
+/* memory mapped struct for Interrupt Type */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0;\r
+ __I uint32_t ICTR; /*!< Interrupt Control Type Register */\r
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))\r
+ __IO uint32_t ACTLR; /*!< Auxiliary Control Register */\r
+#else\r
+ uint32_t RESERVED1;\r
+#endif\r
+} InterruptType_Type;\r
+\r
+\r
+/* Memory Protection Unit */\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)\r
+typedef struct\r
+{\r
+ __I uint32_t TYPE; /*!< MPU Type Register */\r
+ __IO uint32_t CTRL; /*!< MPU Control Register */\r
+ __IO uint32_t RNR; /*!< MPU Region RNRber Register */\r
+ __IO uint32_t RBAR; /*!< MPU Region Base Address Register */\r
+ __IO uint32_t RASR; /*!< MPU Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A1; /*!< MPU Alias 1 Region Base Address Register */\r
+ __IO uint32_t RASR_A1; /*!< MPU Alias 1 Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A2; /*!< MPU Alias 2 Region Base Address Register */\r
+ __IO uint32_t RASR_A2; /*!< MPU Alias 2 Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A3; /*!< MPU Alias 3 Region Base Address Register */\r
+ __IO uint32_t RASR_A3; /*!< MPU Alias 3 Region Attribute and Size Register */\r
+} MPU_Type;\r
+#endif\r
+\r
+\r
+/* Core Debug Register */\r
+typedef struct\r
+{\r
+ __IO uint32_t DHCSR; /*!< Debug Halting Control and Status Register */\r
+ __O uint32_t DCRSR; /*!< Debug Core Register Selector Register */\r
+ __IO uint32_t DCRDR; /*!< Debug Core Register Data Register */\r
+ __IO uint32_t DEMCR; /*!< Debug Exception and Monitor Control Register */\r
+} CoreDebug_Type;\r
+\r
+\r
+/* Memory mapping of Cortex-M3 Hardware */\r
+#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */\r
+#define ITM_BASE (0xE0000000) /*!< ITM Base Address */\r
+#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */\r
+#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */\r
+#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */\r
+#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */\r
+\r
+#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */\r
+#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */\r
+#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */\r
+#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */\r
+#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */\r
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */\r
+#endif\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ ******************************************************************************/\r
+\r
+\r
+#if defined ( __CC_ARM )\r
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */\r
+\r
+#elif defined ( __GNUC__ )\r
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
+\r
+#elif defined ( __TASKING__ )\r
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
+\r
+#endif\r
+\r
+\r
+/* ################### Compiler specific Intrinsics ########################### */\r
+\r
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r
+/* ARM armcc specific functions */\r
+\r
+#define __enable_fault_irq __enable_fiq\r
+#define __disable_fault_irq __disable_fiq\r
+\r
+#define __NOP __nop\r
+#define __WFI __wfi\r
+#define __WFE __wfe\r
+#define __SEV __sev\r
+#define __ISB() __isb(0)\r
+#define __DSB() __dsb(0)\r
+#define __DMB() __dmb(0)\r
+#define __REV __rev\r
+#define __RBIT __rbit\r
+#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr))\r
+#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr))\r
+#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr))\r
+#define __STREXB(value, ptr) __strex(value, ptr)\r
+#define __STREXH(value, ptr) __strex(value, ptr)\r
+#define __STREXW(value, ptr) __strex(value, ptr)\r
+\r
+\r
+/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */\r
+/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */\r
+/* intrinsic void __enable_irq(); */\r
+/* intrinsic void __disable_irq(); */\r
+\r
+\r
+/**\r
+ * @brief Return the Process Stack Pointer\r
+ *\r
+ * @param none\r
+ * @return uint32_t ProcessStackPointer\r
+ *\r
+ * Return the actual process stack pointer\r
+ */\r
+extern uint32_t __get_PSP(void);\r
+\r
+/**\r
+ * @brief Set the Process Stack Pointer\r
+ *\r
+ * @param uint32_t Process Stack Pointer\r
+ * @return none\r
+ *\r
+ * Assign the value ProcessStackPointer to the MSP \r
+ * (process stack pointer) Cortex processor register\r
+ */\r
+extern void __set_PSP(uint32_t topOfProcStack);\r
+\r
+/**\r
+ * @brief Return the Main Stack Pointer\r
+ *\r
+ * @param none\r
+ * @return uint32_t Main Stack Pointer\r
+ *\r
+ * Return the current value of the MSP (main stack pointer)\r
+ * Cortex processor register\r
+ */\r
+extern uint32_t __get_MSP(void);\r
+\r
+/**\r
+ * @brief Set the Main Stack Pointer\r
+ *\r
+ * @param uint32_t Main Stack Pointer\r
+ * @return none\r
+ *\r
+ * Assign the value mainStackPointer to the MSP \r
+ * (main stack pointer) Cortex processor register\r
+ */\r
+extern void __set_MSP(uint32_t topOfMainStack);\r
+\r
+/**\r
+ * @brief Reverse byte order in unsigned short value\r
+ *\r
+ * @param uint16_t value to reverse\r
+ * @return uint32_t reversed value\r
+ *\r
+ * Reverse byte order in unsigned short value\r
+ */\r
+extern uint32_t __REV16(uint16_t value);\r
+\r
+/*\r
+ * @brief Reverse byte order in signed short value with sign extension to integer\r
+ *\r
+ * @param int16_t value to reverse\r
+ * @return int32_t reversed value\r
+ *\r
+ * Reverse byte order in signed short value with sign extension to integer\r
+ */\r
+extern int32_t __REVSH(int16_t value);\r
+\r
+\r
+#if (__ARMCC_VERSION < 400000)\r
+\r
+/**\r
+ * @brief Remove the exclusive lock created by ldrex\r
+ *\r
+ * @param none\r
+ * @return none\r
+ *\r
+ * Removes the exclusive lock which is created by ldrex.\r
+ */\r
+extern void __CLREX(void);\r
+\r
+/**\r
+ * @brief Return the Base Priority value\r
+ *\r
+ * @param none\r
+ * @return uint32_t BasePriority\r
+ *\r
+ * Return the content of the base priority register\r
+ */\r
+extern uint32_t __get_BASEPRI(void);\r
+\r
+/**\r
+ * @brief Set the Base Priority value\r
+ *\r
+ * @param uint32_t BasePriority\r
+ * @return none\r
+ *\r
+ * Set the base priority register\r
+ */\r
+extern void __set_BASEPRI(uint32_t basePri);\r
+\r
+/**\r
+ * @brief Return the Priority Mask value\r
+ *\r
+ * @param none\r
+ * @return uint32_t PriMask\r
+ *\r
+ * Return the state of the priority mask bit from the priority mask\r
+ * register\r
+ */\r
+extern uint32_t __get_PRIMASK(void);\r
+\r
+/**\r
+ * @brief Set the Priority Mask value\r
+ *\r
+ * @param uint32_t PriMask\r
+ * @return none\r
+ *\r
+ * Set the priority mask bit in the priority mask register\r
+ */\r
+extern void __set_PRIMASK(uint32_t priMask);\r
+\r
+/**\r
+ * @brief Return the Fault Mask value\r
+ *\r
+ * @param none\r
+ * @return uint32_t FaultMask\r
+ *\r
+ * Return the content of the fault mask register\r
+ */\r
+extern uint32_t __get_FAULTMASK(void);\r
+\r
+/**\r
+ * @brief Set the Fault Mask value\r
+ *\r
+ * @param uint32_t faultMask value\r
+ * @return none\r
+ *\r
+ * Set the fault mask register\r
+ */\r
+extern void __set_FAULTMASK(uint32_t faultMask);\r
+\r
+/**\r
+ * @brief Return the Control Register value\r
+ * \r
+ * @param none\r
+ * @return uint32_t Control value\r
+ *\r
+ * Return the content of the control register\r
+ */\r
+extern uint32_t __get_CONTROL(void);\r
+\r
+/**\r
+ * @brief Set the Control Register value\r
+ *\r
+ * @param uint32_t Control value\r
+ * @return none\r
+ *\r
+ * Set the control register\r
+ */\r
+extern void __set_CONTROL(uint32_t control);\r
+\r
+#else /* (__ARMCC_VERSION >= 400000) */\r
+\r
+\r
+/**\r
+ * @brief Remove the exclusive lock created by ldrex\r
+ *\r
+ * @param none\r
+ * @return none\r
+ *\r
+ * Removes the exclusive lock which is created by ldrex.\r
+ */\r
+#define __CLREX __clrex\r
+\r
+/**\r
+ * @brief Return the Base Priority value\r
+ *\r
+ * @param none\r
+ * @return uint32_t BasePriority\r
+ *\r
+ * Return the content of the base priority register\r
+ */\r
+static __INLINE uint32_t __get_BASEPRI(void)\r
+{\r
+ register uint32_t __regBasePri __ASM("basepri");\r
+ return(__regBasePri);\r
+}\r
+\r
+/**\r
+ * @brief Set the Base Priority value\r
+ *\r
+ * @param uint32_t BasePriority\r
+ * @return none\r
+ *\r
+ * Set the base priority register\r
+ */\r
+static __INLINE void __set_BASEPRI(uint32_t basePri)\r
+{\r
+ register uint32_t __regBasePri __ASM("basepri");\r
+ __regBasePri = (basePri & 0x1ff);\r
+}\r
+\r
+/**\r
+ * @brief Return the Priority Mask value\r
+ *\r
+ * @param none\r
+ * @return uint32_t PriMask\r
+ *\r
+ * Return the state of the priority mask bit from the priority mask\r
+ * register\r
+ */\r
+static __INLINE uint32_t __get_PRIMASK(void)\r
+{\r
+ register uint32_t __regPriMask __ASM("primask");\r
+ return(__regPriMask);\r
+}\r
+\r
+/**\r
+ * @brief Set the Priority Mask value\r
+ *\r
+ * @param uint32_t PriMask\r
+ * @return none\r
+ *\r
+ * Set the priority mask bit in the priority mask register\r
+ */\r
+static __INLINE void __set_PRIMASK(uint32_t priMask)\r
+{\r
+ register uint32_t __regPriMask __ASM("primask");\r
+ __regPriMask = (priMask);\r
+}\r
+\r
+/**\r
+ * @brief Return the Fault Mask value\r
+ *\r
+ * @param none\r
+ * @return uint32_t FaultMask\r
+ *\r
+ * Return the content of the fault mask register\r
+ */\r
+static __INLINE uint32_t __get_FAULTMASK(void)\r
+{\r
+ register uint32_t __regFaultMask __ASM("faultmask");\r
+ return(__regFaultMask);\r
+}\r
+\r
+/**\r
+ * @brief Set the Fault Mask value\r
+ *\r
+ * @param uint32_t faultMask value\r
+ * @return none\r
+ *\r
+ * Set the fault mask register\r
+ */\r
+static __INLINE void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+ register uint32_t __regFaultMask __ASM("faultmask");\r
+ __regFaultMask = (faultMask & 1);\r
+}\r
+\r
+/**\r
+ * @brief Return the Control Register value\r
+ * \r
+ * @param none\r
+ * @return uint32_t Control value\r
+ *\r
+ * Return the content of the control register\r
+ */\r
+static __INLINE uint32_t __get_CONTROL(void)\r
+{\r
+ register uint32_t __regControl __ASM("control");\r
+ return(__regControl);\r
+}\r
+\r
+/**\r
+ * @brief Set the Control Register value\r
+ *\r
+ * @param uint32_t Control value\r
+ * @return none\r
+ *\r
+ * Set the control register\r
+ */\r
+static __INLINE void __set_CONTROL(uint32_t control)\r
+{\r
+ register uint32_t __regControl __ASM("control");\r
+ __regControl = control;\r
+}\r
+\r
+#endif /* __ARMCC_VERSION */ \r
+\r
+\r
+\r
+#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/\r
+/* IAR iccarm specific functions */\r
+\r
+#define __enable_irq __enable_interrupt /*!< global Interrupt enable */\r
+#define __disable_irq __disable_interrupt /*!< global Interrupt disable */\r
+\r
+static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); }\r
+static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); }\r
+\r
+#define __NOP __no_operation() /*!< no operation intrinsic in IAR Compiler */ \r
+static __INLINE void __WFI() { __ASM ("wfi"); }\r
+static __INLINE void __WFE() { __ASM ("wfe"); }\r
+static __INLINE void __SEV() { __ASM ("sev"); }\r
+static __INLINE void __CLREX() { __ASM ("clrex"); }\r
+\r
+/* intrinsic void __ISB(void) */\r
+/* intrinsic void __DSB(void) */\r
+/* intrinsic void __DMB(void) */\r
+/* intrinsic void __set_PRIMASK(); */\r
+/* intrinsic void __get_PRIMASK(); */\r
+/* intrinsic void __set_FAULTMASK(); */\r
+/* intrinsic void __get_FAULTMASK(); */\r
+/* intrinsic uint32_t __REV(uint32_t value); */\r
+/* intrinsic uint32_t __REVSH(uint32_t value); */\r
+/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */\r
+/* intrinsic unsigned long __LDREX(unsigned long *); */\r
+\r
+\r
+/**\r
+ * @brief Return the Process Stack Pointer\r
+ *\r
+ * @param none\r
+ * @return uint32_t ProcessStackPointer\r
+ *\r
+ * Return the actual process stack pointer\r
+ */\r
+extern uint32_t __get_PSP(void);\r
+\r
+/**\r
+ * @brief Set the Process Stack Pointer\r
+ *\r
+ * @param uint32_t Process Stack Pointer\r
+ * @return none\r
+ *\r
+ * Assign the value ProcessStackPointer to the MSP \r
+ * (process stack pointer) Cortex processor register\r
+ */\r
+extern void __set_PSP(uint32_t topOfProcStack);\r
+\r
+/**\r
+ * @brief Return the Main Stack Pointer\r
+ *\r
+ * @param none\r
+ * @return uint32_t Main Stack Pointer\r
+ *\r
+ * Return the current value of the MSP (main stack pointer)\r
+ * Cortex processor register\r
+ */\r
+extern uint32_t __get_MSP(void);\r
+\r
+/**\r
+ * @brief Set the Main Stack Pointer\r
+ *\r
+ * @param uint32_t Main Stack Pointer\r
+ * @return none\r
+ *\r
+ * Assign the value mainStackPointer to the MSP \r
+ * (main stack pointer) Cortex processor register\r
+ */\r
+extern void __set_MSP(uint32_t topOfMainStack);\r
+\r
+/**\r
+ * @brief Reverse byte order in unsigned short value\r
+ *\r
+ * @param uint16_t value to reverse\r
+ * @return uint32_t reversed value\r
+ *\r
+ * Reverse byte order in unsigned short value\r
+ */\r
+extern uint32_t __REV16(uint16_t value);\r
+\r
+/**\r
+ * @brief Reverse bit order of value\r
+ *\r
+ * @param uint32_t value to reverse\r
+ * @return uint32_t reversed value\r
+ *\r
+ * Reverse bit order of value\r
+ */\r
+extern uint32_t __RBIT(uint32_t value);\r
+\r
+/**\r
+ * @brief LDR Exclusive\r
+ *\r
+ * @param uint8_t* address\r
+ * @return uint8_t value of (*address)\r
+ *\r
+ * Exclusive LDR command\r
+ */\r
+extern uint8_t __LDREXB(uint8_t *addr);\r
+\r
+/**\r
+ * @brief LDR Exclusive\r
+ *\r
+ * @param uint16_t* address\r
+ * @return uint16_t value of (*address)\r
+ *\r
+ * Exclusive LDR command\r
+ */\r
+extern uint16_t __LDREXH(uint16_t *addr);\r
+\r
+/**\r
+ * @brief LDR Exclusive\r
+ *\r
+ * @param uint32_t* address\r
+ * @return uint32_t value of (*address)\r
+ *\r
+ * Exclusive LDR command\r
+ */\r
+extern uint32_t __LDREXW(uint32_t *addr);\r
+\r
+/**\r
+ * @brief STR Exclusive\r
+ *\r
+ * @param uint8_t *address\r
+ * @param uint8_t value to store\r
+ * @return uint32_t successful / failed\r
+ *\r
+ * Exclusive STR command\r
+ */\r
+extern uint32_t __STREXB(uint8_t value, uint8_t *addr);\r
+\r
+/**\r
+ * @brief STR Exclusive\r
+ *\r
+ * @param uint16_t *address\r
+ * @param uint16_t value to store\r
+ * @return uint32_t successful / failed\r
+ *\r
+ * Exclusive STR command\r
+ */\r
+extern uint32_t __STREXH(uint16_t value, uint16_t *addr);\r
+\r
+/**\r
+ * @brief STR Exclusive\r
+ *\r
+ * @param uint32_t *address\r
+ * @param uint32_t value to store\r
+ * @return uint32_t successful / failed\r
+ *\r
+ * Exclusive STR command\r
+ */\r
+extern uint32_t __STREXW(uint32_t value, uint32_t *addr);\r
+\r
+\r
+\r
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/\r
+/* GNU gcc specific functions */\r
+\r
+static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); }\r
+static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); }\r
+\r
+static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); }\r
+static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); }\r
+\r
+static __INLINE void __NOP() { __ASM volatile ("nop"); }\r
+static __INLINE void __WFI() { __ASM volatile ("wfi"); }\r
+static __INLINE void __WFE() { __ASM volatile ("wfe"); }\r
+static __INLINE void __SEV() { __ASM volatile ("sev"); }\r
+static __INLINE void __ISB() { __ASM volatile ("isb"); }\r
+static __INLINE void __DSB() { __ASM volatile ("dsb"); }\r
+static __INLINE void __DMB() { __ASM volatile ("dmb"); }\r
+static __INLINE void __CLREX() { __ASM volatile ("clrex"); }\r
+\r
+\r
+/**\r
+ * @brief Return the Process Stack Pointer\r
+ *\r
+ * @param none\r
+ * @return uint32_t ProcessStackPointer\r
+ *\r
+ * Return the actual process stack pointer\r
+ */\r
+extern uint32_t __get_PSP(void);\r
+\r
+/**\r
+ * @brief Set the Process Stack Pointer\r
+ *\r
+ * @param uint32_t Process Stack Pointer\r
+ * @return none\r
+ *\r
+ * Assign the value ProcessStackPointer to the MSP \r
+ * (process stack pointer) Cortex processor register\r
+ */\r
+extern void __set_PSP(uint32_t topOfProcStack);\r
+\r
+/**\r
+ * @brief Return the Main Stack Pointer\r
+ *\r
+ * @param none\r
+ * @return uint32_t Main Stack Pointer\r
+ *\r
+ * Return the current value of the MSP (main stack pointer)\r
+ * Cortex processor register\r
+ */\r
+extern uint32_t __get_MSP(void);\r
+\r
+/**\r
+ * @brief Set the Main Stack Pointer\r
+ *\r
+ * @param uint32_t Main Stack Pointer\r
+ * @return none\r
+ *\r
+ * Assign the value mainStackPointer to the MSP \r
+ * (main stack pointer) Cortex processor register\r
+ */\r
+extern void __set_MSP(uint32_t topOfMainStack);\r
+\r
+/**\r
+ * @brief Return the Base Priority value\r
+ *\r
+ * @param none\r
+ * @return uint32_t BasePriority\r
+ *\r
+ * Return the content of the base priority register\r
+ */\r
+extern uint32_t __get_BASEPRI(void);\r
+\r
+/**\r
+ * @brief Set the Base Priority value\r
+ *\r
+ * @param uint32_t BasePriority\r
+ * @return none\r
+ *\r
+ * Set the base priority register\r
+ */\r
+extern void __set_BASEPRI(uint32_t basePri);\r
+\r
+/**\r
+ * @brief Return the Priority Mask value\r
+ *\r
+ * @param none\r
+ * @return uint32_t PriMask\r
+ *\r
+ * Return the state of the priority mask bit from the priority mask\r
+ * register\r
+ */\r
+extern uint32_t __get_PRIMASK(void);\r
+\r
+/**\r
+ * @brief Set the Priority Mask value\r
+ *\r
+ * @param uint32_t PriMask\r
+ * @return none\r
+ *\r
+ * Set the priority mask bit in the priority mask register\r
+ */\r
+extern void __set_PRIMASK(uint32_t priMask);\r
+\r
+/**\r
+ * @brief Return the Fault Mask value\r
+ *\r
+ * @param none\r
+ * @return uint32_t FaultMask\r
+ *\r
+ * Return the content of the fault mask register\r
+ */\r
+extern uint32_t __get_FAULTMASK(void);\r
+\r
+/**\r
+ * @brief Set the Fault Mask value\r
+ *\r
+ * @param uint32_t faultMask value\r
+ * @return none\r
+ *\r
+ * Set the fault mask register\r
+ */\r
+extern void __set_FAULTMASK(uint32_t faultMask);\r
+\r
+/**\r
+ * @brief Return the Control Register value\r
+* \r
+* @param none\r
+* @return uint32_t Control value\r
+ *\r
+ * Return the content of the control register\r
+ */\r
+extern uint32_t __get_CONTROL(void);\r
+\r
+/**\r
+ * @brief Set the Control Register value\r
+ *\r
+ * @param uint32_t Control value\r
+ * @return none\r
+ *\r
+ * Set the control register\r
+ */\r
+extern void __set_CONTROL(uint32_t control);\r
+\r
+/**\r
+ * @brief Reverse byte order in integer value\r
+ *\r
+ * @param uint32_t value to reverse\r
+ * @return uint32_t reversed value\r
+ *\r
+ * Reverse byte order in integer value\r
+ */\r
+extern uint32_t __REV(uint32_t value);\r
+\r
+/**\r
+ * @brief Reverse byte order in unsigned short value\r
+ *\r
+ * @param uint16_t value to reverse\r
+ * @return uint32_t reversed value\r
+ *\r
+ * Reverse byte order in unsigned short value\r
+ */\r
+extern uint32_t __REV16(uint16_t value);\r
+\r
+/*\r
+ * Reverse byte order in signed short value with sign extension to integer\r
+ *\r
+ * @param int16_t value to reverse\r
+ * @return int32_t reversed value\r
+ *\r
+ * @brief Reverse byte order in signed short value with sign extension to integer\r
+ */\r
+extern int32_t __REVSH(int16_t value);\r
+\r
+/**\r
+ * @brief Reverse bit order of value\r
+ *\r
+ * @param uint32_t value to reverse\r
+ * @return uint32_t reversed value\r
+ *\r
+ * Reverse bit order of value\r
+ */\r
+extern uint32_t __RBIT(uint32_t value);\r
+\r
+/**\r
+ * @brief LDR Exclusive\r
+ *\r
+ * @param uint8_t* address\r
+ * @return uint8_t value of (*address)\r
+ *\r
+ * Exclusive LDR command\r
+ */\r
+extern uint8_t __LDREXB(uint8_t *addr);\r
+\r
+/**\r
+ * @brief LDR Exclusive\r
+ *\r
+ * @param uint16_t* address\r
+ * @return uint16_t value of (*address)\r
+ *\r
+ * Exclusive LDR command\r
+ */\r
+extern uint16_t __LDREXH(uint16_t *addr);\r
+\r
+/**\r
+ * @brief LDR Exclusive\r
+ *\r
+ * @param uint32_t* address\r
+ * @return uint32_t value of (*address)\r
+ *\r
+ * Exclusive LDR command\r
+ */\r
+extern uint32_t __LDREXW(uint32_t *addr);\r
+\r
+/**\r
+ * @brief STR Exclusive\r
+ *\r
+ * @param uint8_t *address\r
+ * @param uint8_t value to store\r
+ * @return uint32_t successful / failed\r
+ *\r
+ * Exclusive STR command\r
+ */\r
+extern uint32_t __STREXB(uint8_t value, uint8_t *addr);\r
+\r
+/**\r
+ * @brief STR Exclusive\r
+ *\r
+ * @param uint16_t *address\r
+ * @param uint16_t value to store\r
+ * @return uint32_t successful / failed\r
+ *\r
+ * Exclusive STR command\r
+ */\r
+extern uint32_t __STREXH(uint16_t value, uint16_t *addr);\r
+\r
+/**\r
+ * @brief STR Exclusive\r
+ *\r
+ * @param uint32_t *address\r
+ * @param uint32_t value to store\r
+ * @return uint32_t successful / failed\r
+ *\r
+ * Exclusive STR command\r
+ */\r
+extern uint32_t __STREXW(uint32_t value, uint32_t *addr);\r
+\r
+\r
+#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/\r
+/* TASKING carm specific functions */\r
+\r
+/*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all instrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
+\r
+#endif\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+\r
+\r
+/**\r
+ * @brief Set the Priority Grouping in NVIC Interrupt Controller\r
+ *\r
+ * @param uint32_t priority_grouping is priority grouping field\r
+ * @return none \r
+ *\r
+ * Set the priority grouping field using the required unlock sequence.\r
+ * The parameter priority_grouping is assigned to the field \r
+ * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used.\r
+ * In case of a conflict between priority grouping and available\r
+ * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+ */\r
+static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
+{\r
+ uint32_t reg_value;\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ \r
+ reg_value = SCB->AIRCR; /* read old register configuration */\r
+ reg_value &= ~((0xFFFFU << 16) | (0x0F << 8)); /* clear bits to change */\r
+ reg_value = ((reg_value | NVIC_AIRCR_VECTKEY | (PriorityGroupTmp << 8))); /* Insert write key and priorty group */\r
+ SCB->AIRCR = reg_value;\r
+}\r
+\r
+/**\r
+ * @brief Get the Priority Grouping from NVIC Interrupt Controller\r
+ *\r
+ * @param none\r
+ * @return uint32_t priority grouping field \r
+ *\r
+ * Get the priority grouping from NVIC Interrupt Controller.\r
+ * priority grouping is SCB->AIRCR [10:8] PRIGROUP field.\r
+ */\r
+static __INLINE uint32_t NVIC_GetPriorityGrouping(void)\r
+{\r
+ return ((SCB->AIRCR >> 8) & 0x07); /* read priority grouping field */\r
+}\r
+\r
+/**\r
+ * @brief Enable Interrupt in NVIC Interrupt Controller\r
+ *\r
+ * @param IRQn_Type IRQn specifies the interrupt number\r
+ * @return none \r
+ *\r
+ * Enable a device specific interupt in the NVIC interrupt controller.\r
+ * The interrupt number cannot be a negative value.\r
+ */\r
+static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */\r
+}\r
+\r
+/**\r
+ * @brief Disable the interrupt line for external interrupt specified\r
+ * \r
+ * @param IRQn_Type IRQn is the positive number of the external interrupt\r
+ * @return none\r
+ * \r
+ * Disable a device specific interupt in the NVIC interrupt controller.\r
+ * The interrupt number cannot be a negative value.\r
+ */\r
+static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */\r
+}\r
+\r
+/**\r
+ * @brief Read the interrupt pending bit for a device specific interrupt source\r
+ * \r
+ * @param IRQn_Type IRQn is the number of the device specifc interrupt\r
+ * @return uint32_t 1 if pending interrupt else 0\r
+ *\r
+ * Read the pending register in NVIC and return 1 if its status is pending, \r
+ * otherwise it returns 0\r
+ */\r
+static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */\r
+}\r
+\r
+/**\r
+ * @brief Set the pending bit for an external interrupt\r
+ * \r
+ * @param IRQn_Type IRQn is the Number of the interrupt\r
+ * @return none\r
+ *\r
+ * Set the pending bit for the specified interrupt.\r
+ * The interrupt number cannot be a negative value.\r
+ */\r
+static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */\r
+}\r
+\r
+/**\r
+ * @brief Clear the pending bit for an external interrupt\r
+ *\r
+ * @param IRQn_Type IRQn is the Number of the interrupt\r
+ * @return none\r
+ *\r
+ * Clear the pending bit for the specified interrupt. \r
+ * The interrupt number cannot be a negative value.\r
+ */\r
+static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */\r
+}\r
+\r
+/**\r
+ * @brief Read the active bit for an external interrupt\r
+ *\r
+ * @param IRQn_Type IRQn is the Number of the interrupt\r
+ * @return uint32_t 1 if active else 0\r
+ *\r
+ * Read the active register in NVIC and returns 1 if its status is active, \r
+ * otherwise it returns 0.\r
+ */\r
+static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+ return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */\r
+}\r
+\r
+/**\r
+ * @brief Set the priority for an interrupt\r
+ *\r
+ * @param IRQn_Type IRQn is the Number of the interrupt\r
+ * @param priority is the priority for the interrupt\r
+ * @return none\r
+ *\r
+ * Set the priority for the specified interrupt. The interrupt \r
+ * number can be positive to specify an external (device specific) \r
+ * interrupt, or negative to specify an internal (core) interrupt. \n\r
+ *\r
+ * Note: The priority cannot be set for every core interrupt.\r
+ */\r
+static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if(IRQn < 0) {\r
+ SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */\r
+ else {\r
+ NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */\r
+}\r
+\r
+/**\r
+ * @brief Read the priority for an interrupt\r
+ *\r
+ * @param IRQn_Type IRQn is the Number of the interrupt\r
+ * @return uint32_t priority is the priority for the interrupt\r
+ *\r
+ * Read the priority for the specified interrupt. The interrupt \r
+ * number can be positive to specify an external (device specific) \r
+ * interrupt, or negative to specify an internal (core) interrupt.\r
+ *\r
+ * The returned priority value is automatically aligned to the implemented\r
+ * priority bits of the microcontroller.\r
+ *\r
+ * Note: The priority cannot be set for every core interrupt.\r
+ */\r
+static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if(IRQn < 0) {\r
+ return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */\r
+ else {\r
+ return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */\r
+}\r
+\r
+\r
+/**\r
+ * @brief Encode the priority for an interrupt\r
+ *\r
+ * @param uint32_t PriorityGroup is the used priority group\r
+ * @param uint32_t PreemptPriority is the preemptive priority value (starting from 0)\r
+ * @param uint32_t SubPriority is the sub priority value (starting from 0)\r
+ * @return uint32_t the priority for the interrupt\r
+ *\r
+ * Encode the priority for an interrupt with the given priority group,\r
+ * preemptive priority value and sub priority value.\r
+ * In case of a conflict between priority grouping and available\r
+ * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.\r
+ *\r
+ * The returned priority value can be used for NVIC_SetPriority(...) function\r
+ */\r
+static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
+ \r
+ return (\r
+ ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |\r
+ ((SubPriority & ((1 << (SubPriorityBits )) - 1)))\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ * @brief Decode the priority of an interrupt\r
+ *\r
+ * @param uint32_t Priority the priority for the interrupt\r
+ * @param uint32_t PrioGroup is the used priority group\r
+ * @param uint32_t* pPreemptPrio is the preemptive priority value (starting from 0)\r
+ * @param uint32_t* pSubPrio is the sub priority value (starting from 0)\r
+ * @return none\r
+ *\r
+ * Decode an interrupt priority value with the given priority group to \r
+ * preemptive priority value and sub priority value.\r
+ * In case of a conflict between priority grouping and available\r
+ * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.\r
+ *\r
+ * The priority value can be retrieved with NVIC_GetPriority(...) function\r
+ */\r
+static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
+ \r
+ *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);\r
+ *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);\r
+}\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+\r
+#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0)\r
+\r
+/* SysTick constants */\r
+#define SYSTICK_ENABLE 0 /* Config-Bit to start or stop the SysTick Timer */\r
+#define SYSTICK_TICKINT 1 /* Config-Bit to enable or disable the SysTick interrupt */\r
+#define SYSTICK_CLKSOURCE 2 /* Clocksource has the offset 2 in SysTick Control and Status Register */\r
+#define SYSTICK_MAXCOUNT ((1<<24) -1) /* SysTick MaxCount */\r
+\r
+/**\r
+ * @brief Initialize and start the SysTick counter and its interrupt.\r
+ *\r
+ * @param uint32_t ticks is the number of ticks between two interrupts\r
+ * @return none\r
+ *\r
+ * Initialise the system tick timer and its interrupt and start the\r
+ * system tick timer / counter in free running mode to generate \r
+ * periodical interrupts.\r
+ */\r
+static __INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{ \r
+ if (ticks > SYSTICK_MAXCOUNT) return (1); /* Reload value impossible */\r
+\r
+ SysTick->LOAD = (ticks & SYSTICK_MAXCOUNT) - 1; /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */\r
+ SysTick->VAL = (0x00); /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = (1 << SYSTICK_CLKSOURCE) | (1<<SYSTICK_ENABLE) | (1<<SYSTICK_TICKINT); /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0); /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+\r
+\r
+\r
+\r
+/* ################################## Reset function ############################################ */\r
+\r
+/**\r
+ * @brief Initiate a system reset request.\r
+ *\r
+ * @param none\r
+ * @return none\r
+ *\r
+ * Initialize a system reset request to reset the MCU\r
+ */\r
+static __INLINE void NVIC_SystemReset(void)\r
+{\r
+ SCB->AIRCR = (NVIC_AIRCR_VECTKEY | (SCB->AIRCR & (0x700)) | (1<<NVIC_SYSRESETREQ)); /* Keep priority group unchanged */\r
+ __DSB(); /* Ensure completion of memory access */ \r
+ while(1); /* wait until reset */\r
+}\r
+\r
+\r
+/* ################################## Debug Output function ############################################ */\r
+\r
+\r
+/**\r
+ * @brief Outputs a character via the ITM channel 0\r
+ *\r
+ * @param uint32_t character to output\r
+ * @return uint32_t input character\r
+ *\r
+ * The function outputs a character via the ITM channel 0. \r
+ * The function returns when no debugger is connected that has booked the output. \r
+ * It is blocking when a debugger is connected, but the previous character send is not transmitted. \r
+ */\r
+static __INLINE uint32_t ITM_SendChar (uint32_t ch)\r
+{\r
+ if (ch == '\n') ITM_SendChar('\r');\r
+ \r
+ if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA) &&\r
+ (ITM->TCR & ITM_TCR_ITMENA) &&\r
+ (ITM->TER & (1UL << 0)) ) \r
+ {\r
+ while (ITM->PORT[0].u32 == 0);\r
+ ITM->PORT[0].u8 = (uint8_t) ch;\r
+ } \r
+ return (ch);\r
+}\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CM3_CORE_H__ */\r
+\r
+/*lint -restore */\r
--- /dev/null
+//*****************************************************************************\r
+// +--+ \r
+// | ++----+ \r
+// +-++ | \r
+// | | \r
+// +-+--+ | \r
+// | +--+--+ \r
+// +----+ Copyright (c) 2009 Code Red Technologies Ltd. \r
+//\r
+// Microcontroller Startup code for use with Red Suite\r
+//\r
+// Software License Agreement\r
+// \r
+// The software is owned by Code Red Technologies and/or its suppliers, and is \r
+// protected under applicable copyright laws. All rights are reserved. Any \r
+// use in violation of the foregoing restrictions may subject the user to criminal \r
+// sanctions under applicable laws, as well as to civil liability for the breach \r
+// of the terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// USE OF THIS SOFTWARE FOR COMMERCIAL DEVELOPMENT AND/OR EDUCATION IS SUBJECT\r
+// TO A CURRENT END USER LICENSE AGREEMENT (COMMERCIAL OR EDUCATIONAL) WITH\r
+// CODE RED TECHNOLOGIES LTD. \r
+//\r
+//*****************************************************************************\r
+#define WEAK __attribute__ ((weak))\r
+#define ALIAS(f) __attribute__ ((weak, alias (#f)))\r
+\r
+//*****************************************************************************\r
+//\r
+// Forward declaration of the default handlers.\r
+//\r
+//*****************************************************************************\r
+void Reset_Handler(void);\r
+void ResetISR(void) ALIAS(Reset_Handler);\r
+static void NMI_Handler(void);\r
+static void HardFault_Handler(void);\r
+static void MemManage_Handler(void) __attribute__((naked));\r
+static void BusFault_Handler(void) __attribute__((naked));\r
+static void UsageFault_Handler(void) __attribute__((naked));\r
+static void DebugMon_Handler(void);\r
+\r
+//*****************************************************************************\r
+//\r
+// Forward declaration of the specific IRQ handlers. These are aliased\r
+// to the IntDefaultHandler, which is a 'forever' loop. When the application\r
+// defines a handler (with the same name), this will automatically take \r
+// precedence over these weak definitions\r
+//\r
+//*****************************************************************************\r
+void WDT_IRQHandler(void) ALIAS(IntDefaultHandler);\r
+void TIMER0_IRQHandler(void) ALIAS(IntDefaultHandler);\r
+void TIMER1_IRQHandler(void) ALIAS(IntDefaultHandler);\r
+void TIMER2_IRQHandler(void) ALIAS(IntDefaultHandler);\r
+void TIMER3_IRQHandler(void) ALIAS(IntDefaultHandler);\r
+void UART0_IRQHandler(void) ALIAS(IntDefaultHandler);\r
+void UART1_IRQHandler(void) ALIAS(IntDefaultHandler);\r
+void UART2_IRQHandler(void) ALIAS(IntDefaultHandler);\r
+void UART3_IRQHandler(void) ALIAS(IntDefaultHandler);\r
+void PWM1_IRQHandler(void) ALIAS(IntDefaultHandler);\r
+void I2C0_IRQHandler(void) ALIAS(IntDefaultHandler);\r
+void I2C1_IRQHandler(void) ALIAS(IntDefaultHandler);\r
+void I2C2_IRQHandler(void) ALIAS(IntDefaultHandler);\r
+void SPI_IRQHandler(void) ALIAS(IntDefaultHandler);\r
+void SSP0_IRQHandler(void) ALIAS(IntDefaultHandler);\r
+void SSP1_IRQHandler(void) ALIAS(IntDefaultHandler);\r
+void PLL0_IRQHandler(void) ALIAS(IntDefaultHandler);\r
+void RTC_IRQHandler(void) ALIAS(IntDefaultHandler);\r
+void EINT0_IRQHandler(void) ALIAS(IntDefaultHandler);\r
+void EINT1_IRQHandler(void) ALIAS(IntDefaultHandler);\r
+void EINT2_IRQHandler(void) ALIAS(IntDefaultHandler);\r
+void EINT3_IRQHandler(void) ALIAS(IntDefaultHandler);\r
+void ADC_IRQHandler(void) ALIAS(IntDefaultHandler);\r
+void BOD_IRQHandler(void) ALIAS(IntDefaultHandler);\r
+void USB_IRQHandler(void) ALIAS(IntDefaultHandler);\r
+void CAN_IRQHandler(void) ALIAS(IntDefaultHandler);\r
+void DMA_IRQHandler(void) ALIAS(IntDefaultHandler);\r
+void I2S_IRQHandler(void) ALIAS(IntDefaultHandler);\r
+void ENET_IRQHandler(void) ALIAS(IntDefaultHandler);\r
+void RIT_IRQHandler(void) ALIAS(IntDefaultHandler);\r
+void MCPWM_IRQHandler(void) ALIAS(IntDefaultHandler);\r
+void QEI_IRQHandler(void) ALIAS(IntDefaultHandler);\r
+void PLL1_IRQHandler(void) ALIAS(IntDefaultHandler);\r
+\r
+extern void xPortSysTickHandler(void);\r
+extern void xPortPendSVHandler(void);\r
+extern void vPortSVCHandler( void );\r
+\r
+\r
+//*****************************************************************************\r
+//\r
+// The entry point for the C++ library startup\r
+//\r
+//*****************************************************************************\r
+extern WEAK void __libc_init_array(void);\r
+\r
+//*****************************************************************************\r
+//\r
+// The entry point for the application.\r
+// __main() is the entry point for redlib based applications\r
+// main() is the entry point for newlib based applications\r
+//\r
+//*****************************************************************************\r
+extern WEAK void __main(void);\r
+extern WEAK void main(void);\r
+//*****************************************************************************\r
+//\r
+// External declaration for the pointer to the stack top from the Linker Script\r
+//\r
+//*****************************************************************************\r
+extern void _vStackTop;\r
+\r
+//*****************************************************************************\r
+//\r
+// The vector table.\r
+// This relies on the linker script to place at correct location in memory.\r
+//\r
+//*****************************************************************************\r
+__attribute__ ((section(".isr_vector")))\r
+void (* const g_pfnVectors[])(void) =\r
+{\r
+ // Core Level - CM3\r
+ (void *)&_vStackTop, // The initial stack pointer\r
+ Reset_Handler, // The reset handler\r
+ NMI_Handler, // The NMI handler\r
+ HardFault_Handler, // The hard fault handler\r
+ MemManage_Handler, // The MPU fault handler\r
+ BusFault_Handler, // The bus fault handler\r
+ UsageFault_Handler, // The usage fault handler\r
+ 0, // Reserved\r
+ 0, // Reserved\r
+ 0, // Reserved\r
+ 0, // Reserved\r
+ vPortSVCHandler, // SVCall handler\r
+ DebugMon_Handler, // Debug monitor handler\r
+ 0, // Reserved\r
+ xPortPendSVHandler, // The PendSV handler\r
+ xPortSysTickHandler, // The SysTick handler\r
+\r
+ // Chip Level - LPC17\r
+ WDT_IRQHandler, // 16, 0x40 - WDT\r
+ TIMER0_IRQHandler, // 17, 0x44 - TIMER0\r
+ TIMER1_IRQHandler, // 18, 0x48 - TIMER1\r
+ TIMER2_IRQHandler, // 19, 0x4c - TIMER2\r
+ TIMER3_IRQHandler, // 20, 0x50 - TIMER3\r
+ UART0_IRQHandler, // 21, 0x54 - UART0\r
+ UART1_IRQHandler, // 22, 0x58 - UART1\r
+ UART2_IRQHandler, // 23, 0x5c - UART2\r
+ UART3_IRQHandler, // 24, 0x60 - UART3\r
+ PWM1_IRQHandler, // 25, 0x64 - PWM1\r
+ I2C0_IRQHandler, // 26, 0x68 - I2C0\r
+ I2C1_IRQHandler, // 27, 0x6c - I2C1\r
+ I2C2_IRQHandler, // 28, 0x70 - I2C2\r
+ SPI_IRQHandler, // 29, 0x74 - SPI\r
+ SSP0_IRQHandler, // 30, 0x78 - SSP0\r
+ SSP1_IRQHandler, // 31, 0x7c - SSP1\r
+ PLL0_IRQHandler, // 32, 0x80 - PLL0 (Main PLL)\r
+ RTC_IRQHandler, // 33, 0x84 - RTC\r
+ EINT0_IRQHandler, // 34, 0x88 - EINT0\r
+ EINT1_IRQHandler, // 35, 0x8c - EINT1\r
+ EINT2_IRQHandler, // 36, 0x90 - EINT2\r
+ EINT3_IRQHandler, // 37, 0x94 - EINT3\r
+ ADC_IRQHandler, // 38, 0x98 - ADC\r
+ BOD_IRQHandler, // 39, 0x9c - BOD\r
+ USB_IRQHandler, // 40, 0xA0 - USB\r
+ CAN_IRQHandler, // 41, 0xa4 - CAN\r
+ DMA_IRQHandler, // 42, 0xa8 - GP DMA\r
+ I2S_IRQHandler, // 43, 0xac - I2S\r
+ ENET_IRQHandler, // Ethernet.\r
+ RIT_IRQHandler, // 45, 0xb4 - RITINT\r
+ MCPWM_IRQHandler, // 46, 0xb8 - Motor Control PWM\r
+ QEI_IRQHandler, // 47, 0xbc - Quadrature Encoder\r
+ PLL1_IRQHandler, // 48, 0xc0 - PLL1 (USB PLL)\r
+};\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are constructs created by the linker, indicating where the\r
+// the "data" and "bss" segments reside in memory. The initializers for the\r
+// for the "data" segment resides immediately following the "text" segment.\r
+//\r
+//*****************************************************************************\r
+extern unsigned long _etext;\r
+extern unsigned long _data;\r
+extern unsigned long _edata;\r
+extern unsigned long _bss;\r
+extern unsigned long _ebss;\r
+\r
+//*****************************************************************************\r
+// Reset entry point for your code.\r
+// Sets up a simple runtime environment and initializes the C/C++\r
+// library.\r
+//\r
+//*****************************************************************************\r
+void Reset_Handler(void)\r
+{\r
+ unsigned long *pulSrc, *pulDest;\r
+\r
+ //\r
+ // Copy the data segment initializers from flash to SRAM.\r
+ //\r
+ pulSrc = &_etext;\r
+ for(pulDest = &_data; pulDest < &_edata; )\r
+ {\r
+ *pulDest++ = *pulSrc++;\r
+ }\r
+\r
+ //\r
+ // Zero fill the bss segment. This is done with inline assembly since this\r
+ // will clear the value of pulDest if it is not kept in a register.\r
+ //\r
+ __asm(" ldr r0, =_bss\n"\r
+ " ldr r1, =_ebss\n"\r
+ " mov r2, #0\n"\r
+ " .thumb_func\n"\r
+ "zero_loop:\n"\r
+ " cmp r0, r1\n"\r
+ " it lt\n"\r
+ " strlt r2, [r0], #4\n"\r
+ " blt zero_loop");\r
+\r
+ //\r
+ // Call C++ library initilisation, if present\r
+ //\r
+ if (__libc_init_array)\r
+ __libc_init_array() ;\r
+\r
+ //\r
+ // Call the application's entry point.\r
+ // __main() is the entry point for redlib based applications (which calls main())\r
+ // main() is the entry point for newlib based applications\r
+ //\r
+ if (__main)\r
+ __main() ;\r
+ else\r
+ main() ;\r
+\r
+ //\r
+ // main() shouldn't return, but if it does, we'll just enter an infinite loop \r
+ //\r
+ while (1) {\r
+ ;\r
+ }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+// This is the code that gets called when the processor receives a NMI. This\r
+// simply enters an infinite loop, preserving the system state for examination\r
+// by a debugger.\r
+//\r
+//*****************************************************************************\r
+static void NMI_Handler(void)\r
+{\r
+ while(1)\r
+ {\r
+ }\r
+}\r
+\r
+static void HardFault_Handler(void)\r
+{\r
+ for( ;; );\r
+}\r
+\r
+void pop_registers_from_fault_stack(unsigned int * hardfault_args)\r
+{\r
+unsigned int stacked_r0;\r
+unsigned int stacked_r1;\r
+unsigned int stacked_r2;\r
+unsigned int stacked_r3;\r
+unsigned int stacked_r12;\r
+unsigned int stacked_lr;\r
+unsigned int stacked_pc;\r
+unsigned int stacked_psr;\r
+\r
+ stacked_r0 = ((unsigned long) hardfault_args[0]);\r
+ stacked_r1 = ((unsigned long) hardfault_args[1]);\r
+ stacked_r2 = ((unsigned long) hardfault_args[2]);\r
+ stacked_r3 = ((unsigned long) hardfault_args[3]);\r
+\r
+ stacked_r12 = ((unsigned long) hardfault_args[4]);\r
+ stacked_lr = ((unsigned long) hardfault_args[5]);\r
+ stacked_pc = ((unsigned long) hardfault_args[6]);\r
+ stacked_psr = ((unsigned long) hardfault_args[7]);\r
+\r
+ /* Inspect stacked_pc to locate the offending instruction. */\r
+ for( ;; );\r
+}\r
+\r
+static void MemManage_Handler(void)\r
+{\r
+ __asm volatile\r
+ (\r
+ " tst lr, #4 \n"\r
+ " ite eq \n"\r
+ " mrseq r0, msp \n"\r
+ " mrsne r0, psp \n"\r
+ " ldr r1, [r0, #24] \n"\r
+ " ldr r2, handler2_address_const \n"\r
+ " bx r2 \n"\r
+ " handler2_address_const: .word pop_registers_from_fault_stack \n"\r
+ );\r
+}\r
+\r
+static void BusFault_Handler(void)\r
+{\r
+ __asm volatile\r
+ (\r
+ " tst lr, #4 \n"\r
+ " ite eq \n"\r
+ " mrseq r0, msp \n"\r
+ " mrsne r0, psp \n"\r
+ " ldr r1, [r0, #24] \n"\r
+ " ldr r2, handler3_address_const \n"\r
+ " bx r2 \n"\r
+ " handler3_address_const: .word pop_registers_from_fault_stack \n"\r
+ );\r
+}\r
+\r
+static void UsageFault_Handler(void)\r
+{\r
+ __asm volatile\r
+ (\r
+ " tst lr, #4 \n"\r
+ " ite eq \n"\r
+ " mrseq r0, msp \n"\r
+ " mrsne r0, psp \n"\r
+ " ldr r1, [r0, #24] \n"\r
+ " ldr r2, handler4_address_const \n"\r
+ " bx r2 \n"\r
+ " handler4_address_const: .word pop_registers_from_fault_stack \n"\r
+ );\r
+}\r
+\r
+static void DebugMon_Handler(void)\r
+{\r
+ while(1)\r
+ {\r
+ }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+// Processor ends up here if an unexpected interrupt occurs or a handler\r
+// is not present in the application code.\r
+//\r
+//*****************************************************************************\r
+static void IntDefaultHandler(void)\r
+{\r
+ //\r
+ // Go into an infinite loop.\r
+ //\r
+ while(1)\r
+ {\r
+ }\r
+}\r
--- /dev/null
+/*\r
+ FreeRTOS V5.4.2 - Copyright (C) 2009 Real Time Engineers Ltd.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under \r
+ the terms of the GNU General Public License (version 2) as published by the \r
+ Free Software Foundation and modified by the FreeRTOS exception.\r
+ **NOTE** The exception to the GPL is included to allow you to distribute a\r
+ combined work that includes FreeRTOS without being obliged to provide the \r
+ source code for proprietary components outside of the FreeRTOS kernel. \r
+ Alternative commercial license and support terms are also available upon \r
+ request. See the licensing section of http://www.FreeRTOS.org for full \r
+ license details.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT\r
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details.\r
+\r
+ You should have received a copy of the GNU General Public License along\r
+ with FreeRTOS; if not, write to the Free Software Foundation, Inc., 59\r
+ Temple Place, Suite 330, Boston, MA 02111-1307 USA.\r
+\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * Looking for a quick start? Then check out the FreeRTOS eBook! *\r
+ * See http://www.FreeRTOS.org/Documentation for details *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ Please ensure to read the configuration and relevant port sections of the\r
+ online documentation.\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+\r
+//#error The batch file Demo\CORTEX_LPC1768_GCC_RedSuite\CreateProjectDirectoryStructure.bat must be executed before the first build. After executing the batch file hit F5 to refrech the Eclipse project, then delete this line.\r
+\r
+/* Library includes. */\r
+#include <string.h>\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "queue.h"\r
+#include "semphr.h"\r
+\r
+/* Red Suite includes. */\r
+#include "lcd_driver.h"\r
+#include "lcd.h"\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * This file demonstrates the use of MPU using just three tasks - two 'reg test'\r
+ * tasks and one 'check' task. Read the comments above the\r
+ * function prototypes for more information.\r
+ */\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Misc constants. */\r
+#define mainDONT_BLOCK ( 0 )\r
+\r
+/* Definitions for the messages that can be sent to the check task. */\r
+#define mainREG_TEST_1_STILL_EXECUTING ( 0 )\r
+#define mainREG_TEST_2_STILL_EXECUTING ( 1 )\r
+#define mainPRINT_SYSTEM_STATUS ( 2 )\r
+\r
+/* GCC specifics. */\r
+#define mainALIGN_TO( x ) __attribute__((aligned(x)))\r
+\r
+/* Hardware specifics. The start and end address are chosen to ensure the\r
+required GPIO are covered while also ensuring the necessary alignment is\r
+achieved. */\r
+#define mainGPIO_START_ADDRESS ( 0x2009c000UL )\r
+#define mainGPIO_END_ADDRESS ( mainGPIO_START_ADDRESS + ( 64 * 1024 ) )\r
+/*-----------------------------------------------------------*/\r
+/* Prototypes for functions that implement tasks. -----------*/\r
+/*-----------------------------------------------------------*/\r
+\r
+/* \r
+ * Prototype for the reg test tasks. Amongst other things, these fill the CPU\r
+ * registers with known values before checking that the registers still contain\r
+ * the expected values. Each of the two tasks use different values so an error\r
+ * in the context switch mechanism can be caught. Both reg test tasks execute\r
+ * at the idle priority so will get preempted regularly.\r
+ */\r
+static void prvRegTest1Task( void *pvParameters );\r
+static void prvRegTest2Task( void *pvParameters );\r
+\r
+/*\r
+ * Prototype for the check task. The check task demonstrates various features\r
+ * of the MPU before entering a loop where it waits for commands to arrive on a\r
+ * queue.\r
+ *\r
+ * The check task will periodically be commanded to print out a status message.\r
+ * If both the reg tests tasks are executing as expected the check task will\r
+ * print "PASS" to the debug port, otherwise it will print 'FAIL'. Debug port\r
+ * messages can be viewed within the CrossWorks IDE.\r
+ */\r
+static void prvCheckTask( void *pvParameters );\r
+\r
+\r
+\r
+/*-----------------------------------------------------------*/\r
+/* Prototypes for other misc functions. --------------------*/\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Just configures any clocks and IO necessary.\r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+/*\r
+ * Simply deletes the calling task. The function is provided only because it\r
+ * is simpler to call from asm code than the normal vTaskDelete() API function.\r
+ * It has the noinline attribute because it is called from asm code.\r
+ */\r
+static void prvDeleteMe( void ) __attribute__((noinline));\r
+\r
+/*\r
+ * Used by both reg test tasks to send messages to the check task. The message\r
+ * just lets the check task know that the sending is still functioning correctly.\r
+ * If a reg test task detects an error it will delete itself, and in so doing\r
+ * prevent itself from sending any more 'I'm Alive' messages to the check task.\r
+ */\r
+static void prvSendImAlive( xQueueHandle xHandle, unsigned long ulTaskNumber );\r
+\r
+/*\r
+ * The check task is created with access to three memory regions (plus its\r
+ * stack). Each memory region is configured with different parameters and\r
+ * prvTestMemoryRegions() demonstrates what can and cannot be accessed for each\r
+ * region. prvTestMemoryRegions() also demonstrates a task that was created\r
+ * as a privileged task settings its own privilege level down to that of a user\r
+ * task.\r
+ */\r
+static void prvTestMemoryRegions( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The handle of the queue used to communicate between tasks and between tasks\r
+and interrupts. Note that this is a file scope variable that falls outside of\r
+any MPU region. As such other techniques have to be used to allow the tasks\r
+to gain access to the queue. See the comments in the tasks themselves for \r
+further information. */\r
+static xQueueHandle xFileScopeCheckQueue = NULL;\r
+\r
+\r
+\r
+/*-----------------------------------------------------------*/\r
+/* Data used by the 'check' task. ---------------------------*/\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Define the constants used to allocate the check task stack. Note that the\r
+stack size is defined in words, not bytes. */\r
+#define mainCHECK_TASK_STACK_SIZE_WORDS 128\r
+#define mainCHECK_TASK_STACK_ALIGNMENT ( mainCHECK_TASK_STACK_SIZE_WORDS * sizeof( portSTACK_TYPE ) )\r
+\r
+/* Declare the stack that will be used by the check task. The kernel will\r
+ automatically create an MPU region for the stack. The stack alignment must \r
+ match its size, so if 128 words are reserved for the stack then it must be \r
+ aligned to ( 128 * 4 ) bytes. */\r
+static portSTACK_TYPE xCheckTaskStack[ mainCHECK_TASK_STACK_SIZE_WORDS ] mainALIGN_TO( mainCHECK_TASK_STACK_ALIGNMENT );\r
+\r
+/* Declare three arrays - an MPU region will be created for each array\r
+ using the xTaskParameters structure below. Note that the arrays allocate \r
+slightly more RAM than is actually assigned to the MPU region. This is to \r
+permit writes off the end of the array to be detected even when the arrays are \r
+placed in adjacent memory locations (with no gaps between them). The align \r
+size must be a power of two. */\r
+#define mainREAD_WRITE_ARRAY_SIZE 130\r
+#define mainREAD_WRITE_ALIGN_SIZE 128\r
+char cReadWriteArray[ mainREAD_WRITE_ARRAY_SIZE ] mainALIGN_TO( mainREAD_WRITE_ALIGN_SIZE );\r
+\r
+#define mainREAD_ONLY_ARRAY_SIZE 260\r
+#define mainREAD_ONLY_ALIGN_SIZE 256\r
+char cReadOnlyArray[ mainREAD_ONLY_ARRAY_SIZE ] mainALIGN_TO( mainREAD_ONLY_ALIGN_SIZE );\r
+\r
+#define mainPRIVILEGED_ONLY_ACCESS_ARRAY_SIZE 130\r
+#define mainPRIVILEGED_ONLY_ACCESS_ALIGN_SIZE 128\r
+char cPrivilegedOnlyAccessArray[ mainPRIVILEGED_ONLY_ACCESS_ALIGN_SIZE ] mainALIGN_TO( mainPRIVILEGED_ONLY_ACCESS_ALIGN_SIZE );\r
+\r
+/* Fill in a xTaskParameters structure to define the check task. */\r
+static const xTaskParameters xCheckTaskParameters =\r
+{\r
+ prvCheckTask, /* pvTaskCode - the function that implements the task. */\r
+ ( signed char * ) "Check", /* pcName */\r
+ mainCHECK_TASK_STACK_SIZE_WORDS, /* usStackDepth - defined in words, not bytes. */\r
+ ( void * ) 0x12121212, /* pvParameters - this value is just to test that the parameter is being passed into the task correctly. */\r
+ ( tskIDLE_PRIORITY + 1 ) | portPRIVILEGE_BIT,/* uxPriority - this is the highest priority task in the system. The task is created in privileged mode to demonstrate accessing the privileged only data. */\r
+ xCheckTaskStack, /* puxStackBuffer - the array to use as the task stack, as declared above. */\r
+\r
+ /* xRegions - In this case the xRegions array is used to create MPU regions\r
+ for all three of the arrays declared directly above. Each MPU region is\r
+ created with different parameters. */\r
+ { \r
+ /* Base address Length Parameters */\r
+ { cReadWriteArray, mainREAD_WRITE_ALIGN_SIZE, portMPU_REGION_READ_WRITE },\r
+ { cReadOnlyArray, mainREAD_ONLY_ALIGN_SIZE, portMPU_REGION_READ_ONLY },\r
+ { cPrivilegedOnlyAccessArray, mainPRIVILEGED_ONLY_ACCESS_ALIGN_SIZE, portMPU_REGION_PRIVILEGED_READ_WRITE }\r
+ }\r
+};\r
+\r
+/* Three MPU regions are defined for use by the 'check' task when the task is \r
+created. These are only used to demonstrate the MPU features and are not\r
+actually necessary for the check task to fulfill its primary purpose. Instead\r
+the MPU regions are replaced with those defined by xAltRegions prior to the \r
+check task receiving any data on the queue or printing any messages to the\r
+debug console. The MPU region defined below covers the GPIO peripherals used\r
+to write to the LCD. */\r
+static const xMemoryRegion xAltRegions[ portNUM_CONFIGURABLE_REGIONS ] =\r
+{ \r
+ /* Base address Length Parameters */\r
+ { mainGPIO_START_ADDRESS, ( 64 * 1024 ), portMPU_REGION_READ_WRITE },\r
+ { 0, 0, 0 },\r
+ { 0, 0, 0 }\r
+};\r
+\r
+\r
+\r
+/*-----------------------------------------------------------*/\r
+/* Data used by the 'reg test' tasks. -----------------------*/\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Define the constants used to allocate the reg test task stacks. Note that\r
+that stack size is defined in words, not bytes. */\r
+#define mainREG_TEST_STACK_SIZE_WORDS 128\r
+#define mainREG_TEST_STACK_ALIGNMENT ( mainREG_TEST_STACK_SIZE_WORDS * sizeof( portSTACK_TYPE ) )\r
+\r
+/* Declare the stacks that will be used by the reg test tasks. The kernel will\r
+automatically create an MPU region for the stack. The stack alignment must \r
+match its size, so if 128 words are reserved for the stack then it must be \r
+aligned to ( 128 * 4 ) bytes. */\r
+static portSTACK_TYPE xRegTest1Stack[ mainREG_TEST_STACK_SIZE_WORDS ] mainALIGN_TO( mainREG_TEST_STACK_ALIGNMENT );\r
+static portSTACK_TYPE xRegTest2Stack[ mainREG_TEST_STACK_SIZE_WORDS ] mainALIGN_TO( mainREG_TEST_STACK_ALIGNMENT );\r
+\r
+/* Fill in a xTaskParameters structure per reg test task to define the tasks. */\r
+static const xTaskParameters xRegTest1Parameters =\r
+{\r
+ prvRegTest1Task, /* pvTaskCode - the function that implements the task. */\r
+ ( signed char * ) "RegTest1", /* pcName */\r
+ mainREG_TEST_STACK_SIZE_WORDS, /* usStackDepth */\r
+ ( void * ) 0x12345678, /* pvParameters - this value is just to test that the parameter is being passed into the task correctly. */\r
+ tskIDLE_PRIORITY | portPRIVILEGE_BIT, /* uxPriority - note that this task is created with privileges to demonstrate one method of passing a queue handle into the task. */\r
+ xRegTest1Stack, /* puxStackBuffer - the array to use as the task stack, as declared above. */\r
+ { /* xRegions - this task does not use any non-stack data. */\r
+ /* Base address Length Parameters */\r
+ { 0x00, 0x00, 0x00 },\r
+ { 0x00, 0x00, 0x00 },\r
+ { 0x00, 0x00, 0x00 }\r
+ }\r
+};\r
+/*-----------------------------------------------------------*/\r
+\r
+static xTaskParameters xRegTest2Parameters =\r
+{\r
+ prvRegTest2Task, /* pvTaskCode - the function that implements the task. */\r
+ ( signed char * ) "RegTest2", /* pcName */\r
+ mainREG_TEST_STACK_SIZE_WORDS, /* usStackDepth */\r
+ ( void * ) NULL, /* pvParameters - this task uses the parameter to pass in a queue handle, but the queue is not created yet. */\r
+ tskIDLE_PRIORITY, /* uxPriority */\r
+ xRegTest2Stack, /* puxStackBuffer - the array to use as the task stack, as declared above. */\r
+ { /* xRegions - this task does not use any non-stack data. */\r
+ /* Base address Length Parameters */\r
+ { 0x00, 0x00, 0x00 },\r
+ { 0x00, 0x00, 0x00 },\r
+ { 0x00, 0x00, 0x00 }\r
+ }\r
+};\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+int main( void )\r
+{\r
+ prvSetupHardware();\r
+\r
+ /* Create the queue used to pass "I'm alive" messages to the check task. */\r
+ xFileScopeCheckQueue = xQueueCreate( 1, sizeof( unsigned long ) );\r
+\r
+ /* One check task uses the task parameter to receive the queue handle.\r
+ This allows the file scope variable to be accessed from within the task.\r
+ The pvParameters member of xRegTest2Parameters can only be set after the\r
+ queue has been created. */\r
+ xRegTest2Parameters.pvParameters = xFileScopeCheckQueue;\r
+\r
+ /* Create the three test tasks. Handles to the created tasks are not\r
+ required, hence the second parameter is NULL. */\r
+ xTaskCreateRestricted( &xRegTest1Parameters, NULL );\r
+ xTaskCreateRestricted( &xRegTest2Parameters, NULL );\r
+ xTaskCreateRestricted( &xCheckTaskParameters, NULL );\r
+\r
+ /* Start the scheduler. */\r
+ vTaskStartScheduler();\r
+\r
+ /* Will only get here if there was insufficient memory to create the idle\r
+ task. */\r
+ for( ;; );\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvCheckTask( void *pvParameters )\r
+{\r
+/* This task is created in privileged mode so can access the file scope\r
+queue variable. Take a stack copy of this before the task is set into user\r
+mode. Once that task is in user mode the file scope queue variable will no\r
+longer be accessible but the stack copy will. */\r
+xQueueHandle xQueue = xFileScopeCheckQueue;\r
+long lMessage;\r
+unsigned long ulStillAliveCounts[ 2 ] = { 0 };\r
+char *pcStatusMessage = "PASS\r\n";\r
+unsigned char x = 5, y = 10;\r
+\r
+ /* Just to remove compiler warning. */\r
+ ( void ) pvParameters;\r
+\r
+ /* Demonstrate how the various memory regions can and can't be accessed. \r
+ The task privilege is set down to user mode within this function. */\r
+ prvTestMemoryRegions();\r
+\r
+ /* Change the memory regions allocated to this task to those initially\r
+ set up for demonstration purposes to those actually required by the task. */\r
+ vTaskAllocateMPURegions( NULL, xAltRegions );\r
+\r
+ /* This loop performs the main function of the task, which is blocking\r
+ on a message queue then processing each message as it arrives. */\r
+ for( ;; )\r
+ {\r
+ /* Wait for the next message to arrive. */\r
+ xQueueReceive( xQueue, &lMessage, portMAX_DELAY );\r
+ \r
+ switch( lMessage )\r
+ {\r
+ case mainREG_TEST_1_STILL_EXECUTING : \r
+ /* Message from task 1, so task 1 must still be executing. */\r
+ ( ulStillAliveCounts[ 0 ] )++;\r
+ break;\r
+\r
+ case mainREG_TEST_2_STILL_EXECUTING : \r
+ /* Message from task 2, so task 2 must still be executing. */\r
+ ( ulStillAliveCounts[ 1 ] )++;\r
+ break;\r
+\r
+ case mainPRINT_SYSTEM_STATUS : \r
+ /* Message from tick hook, time to print out the system\r
+ status. If messages has stopped arriving from either reg\r
+ test task then the status must be set to fail. */\r
+ if( ( ulStillAliveCounts[ 0 ] == 0 ) || ( ulStillAliveCounts[ 1 ] == 0 ) )\r
+ {\r
+ /* One or both of the test tasks are no longer sending \r
+ 'still alive' messages. */\r
+ pcStatusMessage = "FAIL\r\n";\r
+ }\r
+\r
+ /* Print a pass/fail message to the LCD - moving the\r
+ message each time to provide feedback that the output\r
+ is still being produced. LCD_PrintString() accesses const\r
+ data stored in flash, which all tasks are at liberty to do, \r
+ and GPIO for which an MPU region has been set up for it. */\r
+ LCD_ClearScreen();\r
+ LCD_PrintString( x>>1, y>>1, pcStatusMessage, 6, COLOR_RED );\r
+ x += 7;\r
+ y += 9;\r
+\r
+ /* Reset the count of 'still alive' messages. */\r
+ memset( ulStillAliveCounts, 0x00, sizeof( ulStillAliveCounts ) );\r
+ break;\r
+\r
+ default :\r
+ /* Something unexpected happened. Delete this task so the \r
+ error is apparent (no output will be displayed). */\r
+ prvDeleteMe();\r
+ break;\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvTestMemoryRegions( void )\r
+{\r
+long l;\r
+char cTemp;\r
+\r
+ /* The check task is created in the privileged mode. The privileged array \r
+ can be both read from and written to while this task is privileged. */\r
+ cPrivilegedOnlyAccessArray[ 0 ] = 'a';\r
+ if( cPrivilegedOnlyAccessArray[ 0 ] != 'a' )\r
+ {\r
+ /* Something unexpected happened. Delete this task so the error is\r
+ apparent (no output will be displayed). */\r
+ prvDeleteMe();\r
+ }\r
+\r
+ /* Writing off the end of the RAM allocated to this task will *NOT* cause a\r
+ protection fault because the task is still executing in a privileged mode. \r
+ Uncomment the following to test. */\r
+ /*cPrivilegedOnlyAccessArray[ mainPRIVILEGED_ONLY_ACCESS_ALIGN_SIZE ] = 'a';*/\r
+\r
+ /* Now set the task into user mode. */\r
+ portSWITCH_TO_USER_MODE();\r
+ \r
+ /* Accessing the privileged only array will now cause a fault. Uncomment \r
+ the following line to test. */ \r
+ /*cPrivilegedOnlyAccessArray[ 0 ] = 'a';*/\r
+\r
+ /* The read/write array can still be successfully read and written. */\r
+ for( l = 0; l < mainREAD_WRITE_ALIGN_SIZE; l++ )\r
+ {\r
+ cReadWriteArray[ l ] = 'a';\r
+ if( cReadWriteArray[ l ] != 'a' )\r
+ {\r
+ /* Something unexpected happened. Delete this task so the error is\r
+ apparent (no output will be displayed). */\r
+ prvDeleteMe();\r
+ }\r
+ }\r
+\r
+ /* But attempting to read or write off the end of the RAM allocated to this\r
+ task will cause a fault. Uncomment either of the following two lines to \r
+ test. */\r
+ /* cReadWriteArray[ 0 ] = cReadWriteArray[ -1 ]; */\r
+ /* cReadWriteArray[ mainREAD_WRITE_ALIGN_SIZE ] = 0x00; */\r
+\r
+ /* The read only array can be successfully read... */\r
+ for( l = 0; l < mainREAD_ONLY_ALIGN_SIZE; l++ )\r
+ {\r
+ cTemp = cReadOnlyArray[ l ];\r
+ }\r
+\r
+ /* ...but cannot be written. Uncomment the following line to test. */\r
+ /* cReadOnlyArray[ 0 ] = 'a'; */\r
+\r
+ /* Writing to the first and last locations in the stack array should not \r
+ cause a protection fault. Note that doing this will cause the kernel to\r
+ detect a stack overflow if configCHECK_FOR_STACK_OVERFLOW is greater than \r
+ 1. */\r
+ xCheckTaskStack[ 0 ] = 0;\r
+ xCheckTaskStack[ mainCHECK_TASK_STACK_SIZE_WORDS - 1 ] = 0;\r
+\r
+ /* Writing off either end of the stack array should cause a protection \r
+ fault, uncomment either of the following two lines to test. */\r
+ /* xCheckTaskStack[ -1 ] = 0; */\r
+ /* xCheckTaskStack[ mainCHECK_TASK_STACK_SIZE_WORDS ] = 0; */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvRegTest1Task( void *pvParameters )\r
+{\r
+/* This task is created in privileged mode so can access the file scope\r
+queue variable. Take a stack copy of this before the task is set into user\r
+mode. Once that task is in user mode the file scope queue variable will no\r
+longer be accessible but the stack copy will. */\r
+xQueueHandle xQueue = xFileScopeCheckQueue;\r
+\r
+ /* Now the queue handle has been obtained the task can switch to user \r
+ mode. This is just one method of passing a handle into a protected\r
+ task, the other reg test task uses the task parameter instead. */\r
+ portSWITCH_TO_USER_MODE();\r
+\r
+ /* First check that the parameter value is as expected. */\r
+ if( pvParameters != ( void * ) 0x12345678 )\r
+ {\r
+ /* Error detected. Delete the task so it stops communicating with\r
+ the check task. */\r
+ prvDeleteMe();\r
+ }\r
+\r
+\r
+ for( ;; )\r
+ { \r
+ /* This task tests the kernel context switch mechanism by reading and\r
+ writing directly to registers - which requires the test to be written\r
+ in assembly code. */\r
+ __asm volatile \r
+ ( \r
+ " MOV R4, #104 \n" /* Set registers to a known value. R0 to R1 are done in the loop below. */\r
+ " MOV R5, #105 \n"\r
+ " MOV R6, #106 \n"\r
+ " MOV R8, #108 \n"\r
+ " MOV R9, #109 \n"\r
+ " MOV R10, #110 \n"\r
+ " MOV R11, #111 \n"\r
+ "reg1loop: \n"\r
+ " MOV R0, #100 \n" /* Set the scratch registers to known values - done inside the loop as they get clobbered. */\r
+ " MOV R1, #101 \n"\r
+ " MOV R2, #102 \n"\r
+ " MOV R3, #103 \n"\r
+ " MOV R12, #112 \n"\r
+ " SVC #1 \n" /* Yield just to increase test coverage. */\r
+ " CMP R0, #100 \n" /* Check all the registers still contain their expected values. */\r
+ " BNE prvDeleteMe \n" /* Value was not as expected, delete the task so it stops communicating with the check task. */\r
+ " CMP R1, #101 \n"\r
+ " BNE prvDeleteMe \n"\r
+ " CMP R2, #102 \n"\r
+ " BNE prvDeleteMe \n"\r
+ " CMP R3, #103 \n"\r
+ " BNE prvDeleteMe \n"\r
+ " CMP R4, #104 \n" \r
+ " BNE prvDeleteMe \n" \r
+ " CMP R5, #105 \n"\r
+ " BNE prvDeleteMe \n"\r
+ " CMP R6, #106 \n"\r
+ " BNE prvDeleteMe \n"\r
+ " CMP R8, #108 \n"\r
+ " BNE prvDeleteMe \n"\r
+ " CMP R9, #109 \n"\r
+ " BNE prvDeleteMe \n"\r
+ " CMP R10, #110 \n"\r
+ " BNE prvDeleteMe \n"\r
+ " CMP R11, #111 \n"\r
+ " BNE prvDeleteMe \n"\r
+ " CMP R12, #112 \n"\r
+ " BNE prvDeleteMe \n"\r
+ );\r
+\r
+ /* Send mainREG_TEST_1_STILL_EXECUTING to the check task to indicate that this \r
+ task is still functioning. */\r
+ prvSendImAlive( xQueue, mainREG_TEST_1_STILL_EXECUTING );\r
+\r
+ /* Go back to check all the register values again. */\r
+ __asm volatile( " B reg1loop " );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvRegTest2Task( void *pvParameters )\r
+{\r
+/* The queue handle is passed in as the task parameter. This is one method of\r
+passing data into a protected task, the other check task uses a different \r
+method. */\r
+xQueueHandle xQueue = ( xQueueHandle ) pvParameters;\r
+\r
+ for( ;; )\r
+ {\r
+ /* This task tests the kernel context switch mechanism by reading and\r
+ writing directly to registers - which requires the test to be written\r
+ in assembly code. */\r
+ __asm volatile \r
+ ( \r
+ " MOV R4, #4 \n" /* Set registers to a known value. R0 to R1 are done in the loop below. */\r
+ " MOV R5, #5 \n"\r
+ " MOV R6, #6 \n"\r
+ " MOV R8, #8 \n" /* Frame pointer is omitted as it must not be changed. */\r
+ " MOV R9, #9 \n"\r
+ " MOV R10, 10 \n"\r
+ " MOV R11, #11 \n" \r
+ "reg2loop: \n"\r
+ " MOV R0, #13 \n" /* Set the scratch registers to known values - done inside the loop as they get clobbered. */\r
+ " MOV R1, #1 \n"\r
+ " MOV R2, #2 \n"\r
+ " MOV R3, #3 \n"\r
+ " MOV R12, #12 \n"\r
+ " CMP R0, #13 \n" /* Check all the registers still contain their expected values. */\r
+ " BNE prvDeleteMe \n" /* Value was not as expected, delete the task so it stops communicating with the check task */\r
+ " CMP R1, #1 \n"\r
+ " BNE prvDeleteMe \n"\r
+ " CMP R2, #2 \n"\r
+ " BNE prvDeleteMe \n"\r
+ " CMP R3, #3 \n"\r
+ " BNE prvDeleteMe \n"\r
+ " CMP R4, #4 \n"\r
+ " BNE prvDeleteMe \n"\r
+ " CMP R5, #5 \n"\r
+ " BNE prvDeleteMe \n"\r
+ " CMP R6, #6 \n"\r
+ " BNE prvDeleteMe \n"\r
+ " CMP R8, #8 \n"\r
+ " BNE prvDeleteMe \n"\r
+ " CMP R9, #9 \n"\r
+ " BNE prvDeleteMe \n"\r
+ " CMP R10, #10 \n"\r
+ " BNE prvDeleteMe \n"\r
+ " CMP R11, #11 \n"\r
+ " BNE prvDeleteMe \n"\r
+ " CMP R12, #12 \n"\r
+ " BNE prvDeleteMe \n"\r
+ );\r
+\r
+ /* Send mainREG_TEST_2_STILL_EXECUTING to the check task to indicate that this \r
+ task is still functioning. */\r
+ prvSendImAlive( xQueue, mainREG_TEST_2_STILL_EXECUTING );\r
+\r
+ /* Go back to check all the register values again. */\r
+ __asm volatile( " B reg2loop " );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvDeleteMe( void )\r
+{\r
+ vTaskDelete( NULL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSendImAlive( xQueueHandle xHandle, unsigned long ulTaskNumber )\r
+{\r
+ if( xHandle != NULL )\r
+ {\r
+ xQueueSend( xHandle, &ulTaskNumber, mainDONT_BLOCK );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void prvSetupHardware( void )\r
+{\r
+ /* Disable peripherals power. */\r
+ SC->PCONP = 0;\r
+\r
+ /* Enable GPIO power. */\r
+ SC->PCONP = PCONP_PCGPIO;\r
+\r
+ /* Disable TPIU. */\r
+ PINCON->PINSEL10 = 0;\r
+\r
+ if ( SC->PLL0STAT & ( 1 << 25 ) )\r
+ {\r
+ /* Enable PLL, disconnected. */\r
+ SC->PLL0CON = 1; \r
+ SC->PLL0FEED = PLLFEED_FEED1;\r
+ SC->PLL0FEED = PLLFEED_FEED2;\r
+ }\r
+ \r
+ /* Disable PLL, disconnected. */\r
+ SC->PLL0CON = 0; \r
+ SC->PLL0FEED = PLLFEED_FEED1;\r
+ SC->PLL0FEED = PLLFEED_FEED2;\r
+ \r
+ /* Enable main OSC. */\r
+ SC->SCS |= 0x20; \r
+ while( !( SC->SCS & 0x40 ) );\r
+ \r
+ /* select main OSC, 12MHz, as the PLL clock source. */\r
+ SC->CLKSRCSEL = 0x1; \r
+ \r
+ SC->PLL0CFG = 0x20031;\r
+ SC->PLL0FEED = PLLFEED_FEED1;\r
+ SC->PLL0FEED = PLLFEED_FEED2;\r
+ \r
+ /* Enable PLL, disconnected. */\r
+ SC->PLL0CON = 1; \r
+ SC->PLL0FEED = PLLFEED_FEED1;\r
+ SC->PLL0FEED = PLLFEED_FEED2;\r
+ \r
+ /* Set clock divider. */\r
+ SC->CCLKCFG = 0x03;\r
+ \r
+ /* Configure flash accelerator. */\r
+ SC->FLASHCFG = 0x403a;\r
+ \r
+ /* Check lock bit status. */\r
+ while( ( ( SC->PLL0STAT & ( 1 << 26 ) ) == 0 ) ); \r
+ \r
+ /* Enable and connect. */\r
+ SC->PLL0CON = 3; \r
+ SC->PLL0FEED = PLLFEED_FEED1;\r
+ SC->PLL0FEED = PLLFEED_FEED2;\r
+ while( ( ( SC->PLL0STAT & ( 1 << 25 ) ) == 0 ) ); \r
+\r
+ \r
+ \r
+ \r
+ /* Configure the clock for the USB. */\r
+ \r
+ if( SC->PLL1STAT & ( 1 << 9 ) )\r
+ {\r
+ /* Enable PLL, disconnected. */\r
+ SC->PLL1CON = 1; \r
+ SC->PLL1FEED = PLLFEED_FEED1;\r
+ SC->PLL1FEED = PLLFEED_FEED2;\r
+ }\r
+ \r
+ /* Disable PLL, disconnected. */\r
+ SC->PLL1CON = 0; \r
+ SC->PLL1FEED = PLLFEED_FEED1;\r
+ SC->PLL1FEED = PLLFEED_FEED2;\r
+ \r
+ SC->PLL1CFG = 0x23;\r
+ SC->PLL1FEED = PLLFEED_FEED1;\r
+ SC->PLL1FEED = PLLFEED_FEED2;\r
+ \r
+ /* Enable PLL, disconnected. */\r
+ SC->PLL1CON = 1; \r
+ SC->PLL1FEED = PLLFEED_FEED1;\r
+ SC->PLL1FEED = PLLFEED_FEED2;\r
+ while( ( ( SC->PLL1STAT & ( 1 << 10 ) ) == 0 ) );\r
+ \r
+ /* Enable and connect. */\r
+ SC->PLL1CON = 3; \r
+ SC->PLL1FEED = PLLFEED_FEED1;\r
+ SC->PLL1FEED = PLLFEED_FEED2;\r
+ while( ( ( SC->PLL1STAT & ( 1 << 9 ) ) == 0 ) );\r
+\r
+ /* Setup the peripheral bus to be the same as the PLL output (64 MHz). */\r
+ SC->PCLKSEL0 = 0x05555555;\r
+ \r
+ /* Prepare the LCD. */\r
+ LCDdriver_initialisation();\r
+ LCD_PrintString( 5, 10, "FreeRTOS.org", 14, COLOR_GREEN);\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationTickHook( void )\r
+{\r
+static unsigned long ulCallCount;\r
+const unsigned long ulCallsBetweenSends = 5000 / portTICK_RATE_MS;\r
+const unsigned long ulMessage = mainPRINT_SYSTEM_STATUS;\r
+portBASE_TYPE xDummy;\r
+\r
+ /* If configUSE_TICK_HOOK is set to 1 then this function will get called\r
+ from each RTOS tick. It is called from the tick interrupt and therefore\r
+ will be executing in the privileged state. */\r
+\r
+ ulCallCount++;\r
+\r
+ /* Is it time to print out the pass/fail message again? */\r
+ if( ulCallCount >= ulCallsBetweenSends )\r
+ {\r
+ ulCallCount = 0;\r
+\r
+ /* Send a message to the check task to command it to check that all\r
+ the tasks are still running then print out the status. \r
+ \r
+ This is running in an ISR so has to use the "FromISR" version of\r
+ xQueueSend(). Because it is in an ISR it is running with privileges\r
+ so can access xFileScopeCheckQueue directly. */\r
+ xQueueSendFromISR( xFileScopeCheckQueue, &ulMessage, &xDummy );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationStackOverflowHook( xTaskHandle *pxTask, signed portCHAR *pcTaskName )\r
+{\r
+ /* If configCHECK_FOR_STACK_OVERFLOW is set to either 1 or 2 then this \r
+ function will automatically get called if a task overflows its stack. */\r
+ ( void ) pxTask;\r
+ ( void ) pcTaskName;\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationMallocFailedHook( void )\r
+{\r
+ /* If configUSE_MALLOC_FAILED_HOOK is set to 1 then this function will\r
+ be called automatically if a call to pvPortMalloc() fails. pvPortMalloc()\r
+ is called automatically when a task, queue or semaphore is created. */\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
--- /dev/null
+/*\r
+ Copyright 2001, 2002 Georges Menie (www.menie.org)\r
+ stdarg version contributed by Christian Ettinger\r
+\r
+ This program is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU Lesser General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ This program is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU Lesser General Public License for more details.\r
+\r
+ You should have received a copy of the GNU Lesser General Public License\r
+ along with this program; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+*/\r
+\r
+/*\r
+ putchar is the only external dependency for this file,\r
+ if you have a working putchar, leave it commented out.\r
+ If not, uncomment the define below and\r
+ replace outbyte(c) by your own function call.\r
+\r
+*/\r
+\r
+#define putchar(c) c\r
+\r
+#include <stdarg.h>\r
+\r
+static void printchar(char **str, int c)\r
+{\r
+ //extern int putchar(int c);\r
+ \r
+ if (str) {\r
+ **str = (char)c;\r
+ ++(*str);\r
+ }\r
+ else\r
+ { \r
+ (void)putchar(c);\r
+ }\r
+}\r
+\r
+#define PAD_RIGHT 1\r
+#define PAD_ZERO 2\r
+\r
+static int prints(char **out, const char *string, int width, int pad)\r
+{\r
+ register int pc = 0, padchar = ' ';\r
+\r
+ if (width > 0) {\r
+ register int len = 0;\r
+ register const char *ptr;\r
+ for (ptr = string; *ptr; ++ptr) ++len;\r
+ if (len >= width) width = 0;\r
+ else width -= len;\r
+ if (pad & PAD_ZERO) padchar = '0';\r
+ }\r
+ if (!(pad & PAD_RIGHT)) {\r
+ for ( ; width > 0; --width) {\r
+ printchar (out, padchar);\r
+ ++pc;\r
+ }\r
+ }\r
+ for ( ; *string ; ++string) {\r
+ printchar (out, *string);\r
+ ++pc;\r
+ }\r
+ for ( ; width > 0; --width) {\r
+ printchar (out, padchar);\r
+ ++pc;\r
+ }\r
+\r
+ return pc;\r
+}\r
+\r
+/* the following should be enough for 32 bit int */\r
+#define PRINT_BUF_LEN 12\r
+\r
+static int printi(char **out, int i, int b, int sg, int width, int pad, int letbase)\r
+{\r
+ char print_buf[PRINT_BUF_LEN];\r
+ register char *s;\r
+ register int t, neg = 0, pc = 0;\r
+ register unsigned int u = (unsigned int)i;\r
+\r
+ if (i == 0) {\r
+ print_buf[0] = '0';\r
+ print_buf[1] = '\0';\r
+ return prints (out, print_buf, width, pad);\r
+ }\r
+\r
+ if (sg && b == 10 && i < 0) {\r
+ neg = 1;\r
+ u = (unsigned int)-i;\r
+ }\r
+\r
+ s = print_buf + PRINT_BUF_LEN-1;\r
+ *s = '\0';\r
+\r
+ while (u) {\r
+ t = (unsigned int)u % b;\r
+ if( t >= 10 )\r
+ t += letbase - '0' - 10;\r
+ *--s = (char)(t + '0');\r
+ u /= b;\r
+ }\r
+\r
+ if (neg) {\r
+ if( width && (pad & PAD_ZERO) ) {\r
+ printchar (out, '-');\r
+ ++pc;\r
+ --width;\r
+ }\r
+ else {\r
+ *--s = '-';\r
+ }\r
+ }\r
+\r
+ return pc + prints (out, s, width, pad);\r
+}\r
+\r
+static int print( char **out, const char *format, va_list args )\r
+{\r
+ register int width, pad;\r
+ register int pc = 0;\r
+ char scr[2];\r
+\r
+ for (; *format != 0; ++format) {\r
+ if (*format == '%') {\r
+ ++format;\r
+ width = pad = 0;\r
+ if (*format == '\0') break;\r
+ if (*format == '%') goto out;\r
+ if (*format == '-') {\r
+ ++format;\r
+ pad = PAD_RIGHT;\r
+ }\r
+ while (*format == '0') {\r
+ ++format;\r
+ pad |= PAD_ZERO;\r
+ }\r
+ for ( ; *format >= '0' && *format <= '9'; ++format) {\r
+ width *= 10;\r
+ width += *format - '0';\r
+ }\r
+ if( *format == 's' ) {\r
+ register char *s = (char *)va_arg( args, int );\r
+ pc += prints (out, s?s:"(null)", width, pad);\r
+ continue;\r
+ }\r
+ if( *format == 'd' ) {\r
+ pc += printi (out, va_arg( args, int ), 10, 1, width, pad, 'a');\r
+ continue;\r
+ }\r
+ if( *format == 'x' ) {\r
+ pc += printi (out, va_arg( args, int ), 16, 0, width, pad, 'a');\r
+ continue;\r
+ }\r
+ if( *format == 'X' ) {\r
+ pc += printi (out, va_arg( args, int ), 16, 0, width, pad, 'A');\r
+ continue;\r
+ }\r
+ if( *format == 'u' ) {\r
+ pc += printi (out, va_arg( args, int ), 10, 0, width, pad, 'a');\r
+ continue;\r
+ }\r
+ if( *format == 'c' ) {\r
+ /* char are converted to int then pushed on the stack */\r
+ scr[0] = (char)va_arg( args, int );\r
+ scr[1] = '\0';\r
+ pc += prints (out, scr, width, pad);\r
+ continue;\r
+ }\r
+ }\r
+ else {\r
+ out:\r
+ printchar (out, *format);\r
+ ++pc;\r
+ }\r
+ }\r
+ if (out) **out = '\0';\r
+ va_end( args );\r
+ return pc;\r
+}\r
+\r
+int printf(const char *format, ...)\r
+{\r
+ va_list args;\r
+ \r
+ va_start( args, format );\r
+ return print( 0, format, args );\r
+}\r
+\r
+int sprintf(char *out, const char *format, ...)\r
+{\r
+ va_list args;\r
+ \r
+ va_start( args, format );\r
+ return print( &out, format, args );\r
+}\r
+\r
+\r
+int snprintf( char *buf, unsigned int count, const char *format, ... )\r
+{\r
+ va_list args;\r
+ \r
+ ( void ) count;\r
+ \r
+ va_start( args, format );\r
+ return print( &buf, format, args );\r
+}\r
+\r
+\r
+#ifdef TEST_PRINTF\r
+int main(void)\r
+{\r
+ char *ptr = "Hello world!";\r
+ char *np = 0;\r
+ int i = 5;\r
+ unsigned int bs = sizeof(int)*8;\r
+ int mi;\r
+ char buf[80];\r
+\r
+ mi = (1 << (bs-1)) + 1;\r
+ printf("%s\n", ptr);\r
+ printf("printf test\n");\r
+ printf("%s is null pointer\n", np);\r
+ printf("%d = 5\n", i);\r
+ printf("%d = - max int\n", mi);\r
+ printf("char %c = 'a'\n", 'a');\r
+ printf("hex %x = ff\n", 0xff);\r
+ printf("hex %02x = 00\n", 0);\r
+ printf("signed %d = unsigned %u = hex %x\n", -3, -3, -3);\r
+ printf("%d %s(s)%", 0, "message");\r
+ printf("\n");\r
+ printf("%d %s(s) with %%\n", 0, "message");\r
+ sprintf(buf, "justif: \"%-10s\"\n", "left"); printf("%s", buf);\r
+ sprintf(buf, "justif: \"%10s\"\n", "right"); printf("%s", buf);\r
+ sprintf(buf, " 3: %04d zero padded\n", 3); printf("%s", buf);\r
+ sprintf(buf, " 3: %-4d left justif.\n", 3); printf("%s", buf);\r
+ sprintf(buf, " 3: %4d right justif.\n", 3); printf("%s", buf);\r
+ sprintf(buf, "-3: %04d zero padded\n", -3); printf("%s", buf);\r
+ sprintf(buf, "-3: %-4d left justif.\n", -3); printf("%s", buf);\r
+ sprintf(buf, "-3: %4d right justif.\n", -3); printf("%s", buf);\r
+\r
+ return 0;\r
+}\r
+\r
+/*\r
+ * if you compile this file with\r
+ * gcc -Wall $(YOUR_C_OPTIONS) -DTEST_PRINTF -c printf.c\r
+ * you will get a normal warning:\r
+ * printf.c:214: warning: spurious trailing `%' in format\r
+ * this line is testing an invalid % at the end of the format string.\r
+ *\r
+ * this should display (on 32bit int machine) :\r
+ *\r
+ * Hello world!\r
+ * printf test\r
+ * (null) is null pointer\r
+ * 5 = 5\r
+ * -2147483647 = - max int\r
+ * char a = 'a'\r
+ * hex ff = ff\r
+ * hex 00 = 00\r
+ * signed -3 = unsigned 4294967293 = hex fffffffd\r
+ * 0 message(s)\r
+ * 0 message(s) with %\r
+ * justif: "left "\r
+ * justif: " right"\r
+ * 3: 0003 zero padded\r
+ * 3: 3 left justif.\r
+ * 3: 3 right justif.\r
+ * -3: -003 zero padded\r
+ * -3: -3 left justif.\r
+ * -3: -3 right justif.\r
+ */\r
+\r
+#endif\r
+\r
+\r
+/* To keep linker happy. */\r
+int write( int i, char* c, int n)\r
+{\r
+ (void)i;\r
+ (void)n;\r
+ (void)c;\r
+ return 0;\r
+}\r
+\r
--- /dev/null
+/*\r
+ * GENERATED FILE - DO NOT EDIT\r
+ * (C) Code Red Technologies Ltd, 2008-9 \r
+ * Generated C linker script file for LPC1768 \r
+ * (created from nxp_lpc13_c.ld (v2.0.11 (200907061347)) on Thu Jul 09 12:44:31 BST 2009)\r
+*/\r
+\r
+GROUP(libgcc.a libc.a)
+\r
+MEMORY\r
+{\r
+ FLASH (rx) : ORIGIN = 0x0 LENGTH = 0x80000\r
+ SRAM (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000\r
+ AHBRAM0 : ORIGIN = 0x2007c000, LENGTH = 0x4000\r
+ AHBRAM1 : ORIGIN = 0x20080000, LENGTH = 0x4000\r
+}\r
+\r
+_vRamTop = 0x10000000 + 0x8000;\r
+\r
+ENTRY(ResetISR)\r
+\r
+SECTIONS\r
+{\r
+ __FLASH_segment_start__ = .;\r
+ \r
+ /* Privileged section at the start of the flash - vectors must be first\r
+ whatever. */\r
+ privileged_functions :\r
+ {\r
+ KEEP(*(.isr_vector))\r
+ *(privileged_functions)\r
+ __privileged_functions_end__ = .;\r
+ } > FLASH\r
+ \r
+ .text :\r
+ {\r
+ /* Non privileged code kept out of the first 16K or flash. */\r
+ . = 16K;\r
+ \r
+ *(.text*)\r
+ *(.rodata*)\r
+\r
+ } > FLASH\r
+\r
+\r
+ /* for exception handling/unwind - some Newlib functions (in common with C++ and STDC++) use this. */\r
+ \r
+ .ARM.extab : \r
+ {\r
+ *(.ARM.extab* .gnu.linkonce.armextab.*)\r
+ } > FLASH\r
+\r
+ __exidx_start = .;\r
+ .ARM.exidx :\r
+ {\r
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)\r
+ } > FLASH\r
+ __exidx_end = .;\r
+\r
+ _etext = .;\r
+ \r
+ __FLASH_segment_end__ = .; \r
+\r
+ /* zero initialized data */ \r
+ privileged_data :\r
+ {\r
+ _bss = .;\r
+ __privileged_data_start__ = .;\r
+ __SRAM_segment_start__ = .;\r
+ *(privileged_data)\r
+ __privileged_data_end__ = .;\r
+ } > SRAM \r
+\r
+ /* Non kernel data is kept out of the first 256 bytes of SRAM. */\r
+ . = 0x10000000 + 256;\r
+\r
+ .bss :\r
+ {\r
+ *(.bss*)\r
+ *(COMMON)\r
+ _ebss = .;\r
+ } > SRAM\r
+ \r
+ .data : AT (__exidx_end)\r
+ {\r
+ _data = .; \r
+ *(vtable)\r
+ *(.data*)\r
+ _edata = .;\r
+ } > SRAM\r
+\r
+\r
+ /* Where we put the heap with cr_clib */\r
+ .cr_heap :\r
+ {\r
+ end = .;\r
+ _pvHeapStart = .;\r
+ __SRAM_segment_end__ = .;\r
+ } > SRAM\r
+\r
+/*\r
+ Note: (ref: M0000066)\r
+ Moving the stack down by 16 is to work around a GDB bug.\r
+ This space can be reclaimed for Production Builds.\r
+*/ \r
+ _vStackTop = _vRamTop - 16;\r
+ \r
+ .ETHRAM :\r
+ {\r
+ } > AHBRAM0\r
+ \r
+ .USBRAM :\r
+ {\r
+ } > AHBRAM1\r
+}\r
--- /dev/null
+/* Don't need anything here. */
+
+#include <stdlib.h>
+#include <sys/stat.h>
+
+int _read_r (struct _reent *r, int file, char * ptr, int len)
+{
+ ( void ) r;
+ ( void ) file;
+ ( void ) ptr;
+ ( void ) len;
+ return -1;
+}
+
+/***************************************************************************/
+
+int _lseek_r (struct _reent *r, int file, int ptr, int dir)
+{
+ ( void ) r;
+ ( void ) file;
+ ( void ) ptr;
+ ( void ) dir;
+
+ return 0;
+}
+
+/***************************************************************************/
+
+int _write_r (struct _reent *r, int file, char * ptr, int len)
+{
+ ( void ) r;
+ ( void ) file;
+ ( void ) ptr;
+ ( void ) len;
+
+ return 0;
+}
+
+/***************************************************************************/
+
+int _close_r (struct _reent *r, int file)
+{
+ ( void ) r;
+ ( void ) file;
+
+ return 0;
+}
+
+/***************************************************************************/
+
+caddr_t _sbrk_r (struct _reent *r, int incr)
+{
+ ( void ) r;
+ ( void ) incr;
+
+ return 0;
+}
+
+/***************************************************************************/
+
+int _fstat_r (struct _reent *r, int file, struct stat * st)
+{
+ ( void ) r;
+ ( void ) file;
+ ( void ) st;
+
+ return 0;
+}
+
+/***************************************************************************/
+
+int _isatty_r(struct _reent *r, int fd)
+{
+ ( void ) r;
+ ( void ) fd;
+
+ return 0;
+}
+
+
+
+
--- /dev/null
+/******************************************************************************\r
+ * @file: system_LPC17xx.h\r
+ * @purpose: CMSIS Cortex-M3 Device Peripheral Access Layer Header File\r
+ * for the NXP LPC17xx Device Series \r
+ * @version: V1.0\r
+ * @date: 25. Nov. 2008\r
+ *----------------------------------------------------------------------------\r
+ *\r
+ * Copyright (C) 2008 ARM Limited. All rights reserved.\r
+ *\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M3 \r
+ * processor based microcontrollers. This file can be freely distributed \r
+ * within development tools that are supporting such ARM based processors. \r
+ *\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+\r
+\r
+#ifndef __SYSTEM_LPC17xx_H\r
+#define __SYSTEM_LPC17xx_H\r
+\r
+extern uint32_t SystemFrequency; /*!< System Clock Frequency (Core Clock) */\r
+\r
+\r
+/**\r
+ * Initialize the system\r
+ *\r
+ * @param none\r
+ * @return none\r
+ *\r
+ * @brief Setup the microcontroller system.\r
+ * Initialize the System and update the SystemFrequency variable.\r
+ */\r
+extern void SystemInit (void);\r
+#endif\r
projects / freertos / commitdiff