]> git.sur5r.net Git - freertos/commitdiff
Continue working on GCC/CA_9 port layer - tick interrupt now working but needs tidy up.
authorrtel <rtel@1d2547de-c912-0410-9cb9-b8ca96c0e9e2>
Thu, 23 Jan 2014 11:51:57 +0000 (11:51 +0000)
committerrtel <rtel@1d2547de-c912-0410-9cb9-b8ca96c0e9e2>
Thu, 23 Jan 2014 11:51:57 +0000 (11:51 +0000)
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2174 1d2547de-c912-0410-9cb9-b8ca96c0e9e2

FreeRTOS/Source/portable/GCC/ARM_CA9/port.c
FreeRTOS/Source/portable/GCC/ARM_CA9/portASM.S

index 84a6d1db9f872075dbe07525b5ee5f3e9576e734..b05eedecf8da40e0415ffea7690b1fa10f886800 100644 (file)
@@ -337,6 +337,7 @@ uint32_t ulAPSR;
                if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE )\r
                {\r
                        /* Start the timer that generates the tick ISR. */\r
+                       __asm volatile( "cpsid i" );\r
                        configSETUP_TICK_INTERRUPT();\r
 \r
 //                     __asm volatile( "cpsie i" );\r
index 072e45e5456b3ebc12983a1068c4e5bd88d550ef..eb8320a81ad6e6aafb887082d1f8f5de4fe48f74 100644 (file)
@@ -52,7 +52,6 @@
     licensing and training services.\r
 */\r
 \r
-\r
        .text\r
 \r
        .set SYS_MODE,  0x1f\r
@@ -241,6 +240,7 @@ FreeRTOS_IRQ_Handler:
        /* Read value from the interrupt acknowledge register, which is stored in r0\r
        for future parameter and interrupt clearing use. */\r
        LDR     r2, ulICCIARConst\r
+       LDR             r2, [r2]\r
        LDR             r0, [r2]\r
 \r
        /* Ensure bit 2 of the stack pointer is clear.  r2 holds the bit 2 value for\r
@@ -259,6 +259,7 @@ FreeRTOS_IRQ_Handler:
 \r
        /* Write the value read from ICCIAR to ICCEOIR. */\r
        LDR     r4, ulICCEOIRConst\r
+       LDR             r4, [r4]\r
        STR             r0, [r4]\r
 \r
        /* Restore the old nesting count. */\r