* @date 23 Feb 2012\r
*\r
Copyright (C) 2011-2012 Infineon Technologies AG. All rights reserved.\r
-* \r
+*\r
*\r
* @par\r
* Infineon Technologies AG (Infineon) is supplying this software for use with Infineon's\r
\r
#ifdef __cplusplus\r
extern "C" {\r
-#endif \r
+#endif\r
\r
\r
\r
#elif defined(__ICCARM__)\r
#pragma language=extended\r
#elif defined(__GNUC__)\r
- /* anonymous unions are enabled by default */ \r
+ /* anonymous unions are enabled by default */\r
#elif defined(__TMS470__)\r
-/* anonymous unions are enabled by default */ \r
+/* anonymous unions are enabled by default */\r
#elif defined(__TASKING__)\r
- #pragma warning 586 \r
+ #pragma warning 586\r
#else\r
#warning Not supported compiler type\r
#endif\r
USIC1_3_IRQn = 93, /*!< USIC1 SR3 Interrupt */\r
USIC1_4_IRQn = 94, /*!< USIC1 SR4 Interrupt */\r
USIC1_5_IRQn = 95, /*!< USIC1 SR5 Interrupt */\r
-USIC2_0_IRQn = 96, /*!< USIC2 SR0 Interrupt */ \r
+USIC2_0_IRQn = 96, /*!< USIC2 SR0 Interrupt */\r
USIC2_1_IRQn = 97, /*!< USIC2 SR1 Interrupt */\r
USIC2_2_IRQn = 98, /*!< USIC2 SR2 Interrupt */\r
USIC2_3_IRQn = 99, /*!< USIC2 SR3 Interrupt */\r
reg &= ~(mask);\\r
reg |= (val << pos) & mask;\\r
}\r
- \r
+\r
/** Macro to read the bits in register */\r
#define RD_REG(reg, mask, pos) (((reg)&mask) >> pos)\r
/** Macro to set the particular bit in register */\r
/* CAN */\r
/***************************************************************************/\r
\r
- /* \r
+ /*\r
*CAN GLOBAL registers\r
*/\r
typedef struct {\r
__O uint32_t MITR; /*!<Module Interrupt Trigger Register Offset 0x01CC*/\r
}CAN_GLOBAL_TypeDef;\r
\r
- /* \r
+ /*\r
*CAN NODE registers\r
*/\r
typedef struct {\r
__IO uint32_t NFCR; /*!<Node 0 Frame Counter Register Offset 0x0218*/\r
}CAN_NODE_TypeDef;\r
\r
- /* \r
+ /*\r
*CAN MO registers\r
*/\r
typedef struct {\r
/* CCU4x */\r
/***************************************************************************/\r
\r
- /* \r
+ /*\r
*CAPCOM4 Global Registers\r
*/\r
typedef struct {\r
__I uint32_t MIDR; /*!<Module Identification Offset 0x0080*/\r
}CCU4_GLOBAL_TypeDef;\r
\r
- /* \r
+ /*\r
*CC40 Registers\r
*/\r
typedef struct {\r
/* CCU8x */\r
/***************************************************************************/\r
\r
- /* \r
+ /*\r
*CAPCOM8 Global Registers\r
*/\r
typedef struct {\r
__I uint32_t MIDR; /*!<Module Identification Offset 0x0080*/\r
}CCU8_GLOBAL_TypeDef;\r
\r
- /* \r
+ /*\r
*CC8x Registers\r
*/\r
typedef struct {\r
/* DAC */\r
/***************************************************************************/\r
\r
- /* \r
+ /*\r
*DAC Kernel Registers\r
*/\r
typedef struct {\r
/* DLR */\r
/***************************************************************************/\r
\r
- /* \r
+ /*\r
*DLR registers\r
*/\r
typedef struct {\r
/* GPDMA1 */\r
/***************************************************************************/\r
\r
- /* \r
+ /*\r
*Channel Related registers\r
*/\r
typedef struct {\r
__IO uint32_t CFGH; /*!<Configuration Register for Channel 0 High Word Offset 0x0044*/\r
}GPDMA1_CH_TypeDef;\r
\r
- /* \r
+ /*\r
*GPDMA1 Global registers\r
*/\r
typedef struct {\r
/* GPDMA0 */\r
/***************************************************************************/\r
\r
- /* \r
+ /*\r
*Channel Related registers\r
*/\r
typedef struct {\r
__IO uint32_t DSR; /*!<Destination Scatter Register for Channel 0 Offset 0x0050*/\r
}GPDMA0_CH_TypeDef;\r
\r
- /* \r
+ /*\r
*GPDMA0 Global registers\r
*/\r
typedef struct {\r
/* DSD */\r
/***************************************************************************/\r
\r
- /* \r
+ /*\r
*DSD Global Registers\r
*/\r
typedef struct {\r
__O uint32_t EVFLAGCLR; /*!<Event Flag Clear Register Offset 0x00E4*/\r
}DSD_GLOBAL_TypeDef;\r
\r
- /* \r
+ /*\r
*DSD CHANNEL Registers\r
*/\r
typedef struct {\r
#define DSD_CH2 ((DSD_CH_TypeDef*)(DSD_BASE + DSD_CH2_BASE))\r
#define DSD_CH3 ((DSD_CH_TypeDef*)(DSD_BASE + DSD_CH3_BASE))\r
\r
-/***************************************************************************/\r
-/* DWT */\r
-/***************************************************************************/\r
-\r
- /* \r
- *Cortex M4 - Data Watchpoint and Trace\r
- */\r
-typedef struct { /*!< DWT Structure */\r
- __IO uint32_t DWT_CTRL; /*!< Use the DWT Control Register to enable the DWT unit. */\r
- __IO uint32_t DWT_CYCCNT; /*!< The DWT_CYCCNT register characteristics are:Purpose Shows or sets the value of the processor cycle counter, CYCCNT.Usage constraints The DWT unit suspends CYCCNT counting when the processor is in Debug state.Configurations Implemented only when DWT_CTRL.NOCYCCNT is RAZ, see Control register, DWT_CTRL on page C1-879.When DWT_CTRL.NOCYCCNT is RAO no cycle counter is implemented and this register is UNK/SBZP.For more information see CYCCNT cycle counter and related timers on page C1-871. */\r
- __IO uint32_t DWT_CPICNT; /*!< The DWT_CPICNT register characteristics are:Purpose Counts additional cycles required to execute multi-cycle instructions and instruction fetch stalls.Usage constraints The counter initializes to 0 when software enables its counter overflow event by setting the DWT_CTRL.CPIEVTENA bit to 1.Configurations Implemented only when DWT_CTRL.NOPRFCNT is RAZ, see Control register, DWT_CTRL on page C1-879.If DWT_CTRL.NOPRFCNT is RAO, indicating that the implementation does not include the profiling counters, this re */\r
- __IO uint32_t DWT_EXCCNT; /*!< The DWT_EXCCNT register characteristics are:Purpose Counts the total cycles spent in exception processingUsage constraints The counter initializes to 0 when software enables its counter overflow event by setting the DWT_CTRL.EXCEVTENA bit to 1.Configurations Implemented only when DWT_CTRL.NOPRFCNT is RAZ, see Control register, DWT_CTRL on page C1-879.If DWT_CTRL.NOPRFCNT is RAO, indicating that the implementation does not include the profiling counters, this register is UNK/SBZP.For more information see Pr */\r
- __IO uint32_t DWT_SLEEPCNT; /*!< The DWT_SLEEPCNT register characteristics are:Purpose Counts the total number of cycles that the processor is sleeping.Usage constraints The counter initializes to 0 when software enables its counter overflow event by setting the DWT_CTRL.SLEEPEVTENA bit to 1.Configurations Implemented only when DWT_CTRL.NOPRFCNT is RAZ, see Control register, DWT_CTRL on page C1-879.If DWT_CTRL.NOPRFCNT is RAO, indicating that the implementation does not include the profiling counters, this register is UNK/SBZP.ARM recomme */\r
- __IO uint32_t DWT_LSUCNT; /*!< The DWT_LSUCNT register characteristics are:Purpose Increments on the additional cycles required to execute all load or store instructionsUsage constraints The counter initializes to 0 when software enables its counter overflow event by setting the DWT_CTRL.LSUEVTENA bit to 1.Configurations Implemented only when DWT_CTRL.NOPRFCNT is RAZ, see Control register, DWT_CTRL on page C1-879.If DWT_CTRL.NOPRFCNT is RAO, indicating that the implementation does not include the profiling counters, this register is UNK */\r
- __IO uint32_t DWT_FOLDCNT; /*!< The DWT_FOLDCNT register characteristics are:Purpose Increments on each instruction that takes 0 cycles.Usage constraints The counter initializes to 0 when software enables its counter overflow event by setting the DWT_CTRL.FOLDEVTENA bit to 1. If an implementation includes profiling counters but does not support instruction folding, this counter can be RAZ/WI.Configurations Implemented only when DWT_CTRL.NOPRFCNT is RAZ, see Control register, DWT_CTRL on page C1-879.If DWT_CTRL.NOPRFCNT is RAO, indicating */\r
- __I uint32_t DWT_PCSR; /*!< The DWT_PCSR characteristics are:Purpose Samples the current value of the program counter.Usage constraints There are no usage constraints.NoteBit [0] of any sampled value is RAZ and does not reflect instruction set state as it does in a PC sample on the ARMv7-A and ARMv7-R architecture profiles.Configurations An optional feature. Register is RAZ/WI if not implemented.For more information see Program counter sampling support on page C1-877. */\r
- __IO uint32_t DWT_COMP0; /*!< The DWT_COMP0 register characteristics are:Purpose Provides a reference value for use by comparator 0.Usage constraints The operation of comparator 0 depends also on the registers DWT_MASK0 and DWT_FUNCTION0, see Comparator Mask registers, DWT_MASKn on page C1-892 and Comparator Function registers, DWT_FUNCTIONn on page C1-893.Configurations Implemented only when DWT_CTRL.NUMCOMP is nonzero, see Control register, DWT_CTRL on page C1-879.DWT_CTRL.NUMCOMP defines the number of implemented DWT_COMPn registers */\r
- __IO uint32_t DWT_MASK0; /*!< The DWT_MASK0 register characteristics are:Purpose Provides the size of the ignore mask applied to the access address for address range matching by comparator 0.Usage constraints The operation of comparator 0 depends also on the registers DWT_COMP0 and DWT_FUNCTION0, see Comparator registers, DWT_COMPn on page C1-891 and Comparator Function registers, DWT_FUNCTIONn on page C1-893.Configurations Implemented only when DWT_CTRL.NUMCOMP is nonzero, see Control register, DWT_CTRL on page C1-879.DWT_CTRL.NUMCOMP */\r
- __IO uint32_t DWT_FUNCTION0; /*!< The DWT_FUNCTION0 register characteristics are:Purpose Controls the operation of comparator 0.Usage constraints The operation of comparator 0 depends also on the registers DWT_COMP0 and DWT_MASK0, see Comparator registers, DWT_COMPn on page C1-891 and Comparator Mask registers, DWT_MASKn on page C1-892.Reading this register clears some fields to zero. See the field descriptions in Table C1-39 on page C1-894 for more information, and for the usage constraints of individual fields.Configurations Implemented */\r
- __I uint32_t RESERVED0;\r
- __IO uint32_t DWT_COMP1; /*!< The DWT_COMP1 register characteristics are:Purpose Provides a reference value for use by comparator n.Usage constraints The operation of comparator 1 depends also on the registers DWT_MASK1 and DWT_FUNCTION1, see Comparator Mask registers, DWT_MASKn on page C1-892 and Comparator Function registers, DWT_FUNCTIONn on page C1-893.Configurations Implemented only when DWT_CTRL.NUMCOMP is nonzero, see Control register, DWT_CTRL on page C1-879.DWT_CTRL.NUMCOMP defines the number of implemented DWT_COMPn registers */\r
- __IO uint32_t DWT_MASK1; /*!< The DWT_MASK1 register characteristics are:Purpose Provides the size of the ignore mask applied to the access address for address range matching by comparator 1.Usage constraints The operation of comparator 1 depends also on the registers DWT_COMP1 and DWT_FUNCTION1, see Comparator registers, DWT_COMPn on page C1-891 and Comparator Function registers, DWT_FUNCTIONn on page C1-893.Configurations Implemented only when DWT_CTRL.NUMCOMP is nonzero, see Control register, DWT_CTRL on page C1-879.DWT_CTRL.NUMCOMP */\r
- __IO uint32_t DWT_FUNCTION1; /*!< The DWT_FUNCTION1 register characteristics are:Purpose Controls the operation of comparator 1.Usage constraints The operation of comparator 1 depends also on the registers DWT_COMP1 and DWT_MASK1, see Comparator registers, DWT_COMPn on page C1-891 and Comparator Mask registers, DWT_MASKn on page C1-892.Reading this register clears some fields to zero. See the field descriptions in Table C1-39 on page C1-894 for more information, and for the usage constraints of individual fields.Configurations Implemented */\r
- __I uint32_t RESERVED1;\r
- __IO uint32_t DWT_COMP2; /*!< The DWT_COMP2 register characteristics are:Purpose Provides a reference value for use by comparator n.Usage constraints The operation of comparator n depends also on the registers DWT_MASK2 and DWT_FUNCTION2, see Comparator Mask registers, DWT_MASKn on page C1-892 and Comparator Function registers, DWT_FUNCTIONn on page C1-893.Configurations Implemented only when DWT_CTRL.NUMCOMP is nonzero, see Control register, DWT_CTRL on page C1-879.DWT_CTRL.NUMCOMP defines the number of implemented DWT_COMPn registers */\r
- __IO uint32_t DWT_MASK2; /*!< The DWT_MASK2 register characteristics are:Purpose Provides the size of the ignore mask applied to the access address for address range matching by comparator 2.Usage constraints The operation of comparator 2 depends also on the registers DWT_COMP2 and DWT_FUNCTION2, see Comparator registers, DWT_COMPn on page C1-891 and Comparator Function registers, DWT_FUNCTIONn on page C1-893.Configurations Implemented only when DWT_CTRL.NUMCOMP is nonzero, see Control register, DWT_CTRL on page C1-879.DWT_CTRL.NUMCOMP */\r
- __IO uint32_t DWT_FUNCTION2; /*!< The DWT_FUNCTION2 register characteristics are:Purpose Controls the operation of comparator 2.Usage constraints The operation of comparator 2 depends also on the registers DWT_COMP2 and DWT_MASK2, see Comparator registers, DWT_COMPn on page C1-891 and Comparator Mask registers, DWT_MASKn on page C1-892.Reading this register clears some fields to zero. See the field descriptions in Table C1-39 on page C1-894 for more information, and for the usage constraints of individual fields.Configurations Implemented */\r
- __I uint32_t RESERVED2;\r
- __IO uint32_t DWT_COMP3; /*!< The DWT_COMP3 register characteristics are:Purpose Provides a reference value for use by comparator n.Usage constraints The operation of comparator 3 depends also on the registers DWT_MASK3 and DWT_FUNCTION3, see Comparator Mask registers, DWT_MASKn on page C1-892 and Comparator Function registers, DWT_FUNCTIONn on page C1-893.Configurations Implemented only when DWT_CTRL.NUMCOMP is nonzero, see Control register, DWT_CTRL on page C1-879.DWT_CTRL.NUMCOMP defines the number of implemented DWT_COMPn registers */\r
- __IO uint32_t DWT_MASK3; /*!< The DWT_MASK3 register characteristics are:Purpose Provides the size of the ignore mask applied to the access address for address range matching by comparator 3.Usage constraints The operation of comparator 3 depends also on the registers DWT_COMP3 and DWT_FUNCTION3, see Comparator registers, DWT_COMPn on page C1-891 and Comparator Function registers, DWT_FUNCTIONn on page C1-893.Configurations Implemented only when DWT_CTRL.NUMCOMP is nonzero, see Control register, DWT_CTRL on page C1-879.DWT_CTRL.NUMCOMP */\r
- __IO uint32_t DWT_FUNCTION3; /*!< The DWT_FUNCTION3 register characteristics are:Purpose Controls the operation of comparator 3.Usage constraints The operation of comparator 3 depends also on the registers DWT_COMP3 and DWT_MASK3, see Comparator registers, DWT_COMPn on page C1-891 and Comparator Mask registers, DWT_MASKn on page C1-892.Reading this register clears some fields to zero. See the field descriptions in Table C1-39 on page C1-894 for more information, and for the usage constraints of individual fields.Configurations Implemented */\r
- __I uint32_t RESERVED3[989];\r
- __I uint32_t DWTPID4; /*!< Peripheral identification register4 */\r
- __I uint32_t DWTPID5; /*!< Peripheral identification register5 */\r
- __I uint32_t DWTPID6; /*!< Peripheral identification register6 */\r
- __I uint32_t DWTPID7; /*!< Peripheral identification register7 */\r
- __I uint32_t DWTPID0; /*!< Peripheral identification register0 */\r
- __I uint32_t DWTPID1; /*!< Peripheral identification register1 */\r
- __I uint32_t DWTPID2; /*!< Peripheral identification register2 */\r
- __I uint32_t DWTPID3; /*!< Peripheral identification register3 */\r
- __I uint32_t DWTCID0; /*!< Component identification register0 */\r
- __I uint32_t DWTCID1; /*!< Component identification register1 */\r
- __I uint32_t DWTCID2; /*!< Component identification register2 */\r
- __I uint32_t DWTCID3; /*!< Component identification register3 */\r
-} DWT_Type;\r
-\r
-#define DWT_BASE ((uint32_t)0xE0001000U)\r
-#define DWT_GLOBAL_BASE (0x0000U)\r
-/***************************************************************************/\r
-/* Peripheral Declaration */\r
-/***************************************************************************/\r
-#define DWT ((DWT_Type *)(DWT_BASE + DWT_GLOBAL_BASE))\r
-\r
/***************************************************************************/\r
/* EBU */\r
/***************************************************************************/\r
\r
- /* \r
+ /*\r
*EBU GLOBAL registers\r
*/\r
typedef struct {\r
__IO uint32_t USERCON; /*!<EBU Test/Control Configuration Register Offset 0x000C*/\r
}EBU_GLOBAL_TypeDef;\r
\r
- /* \r
+ /*\r
*EBU chipselect registers\r
*/\r
typedef struct {\r
__I uint32_t RESERVED1[6];\r
__IO uint32_t BUSRCON; /*!<EBU Bus Configuration Register Offset 0x0038*/\r
__IO uint32_t BUSRAP; /*!<EBU Bus Read Access Parameter Register Offset*/\r
-__IO uint32_t BUSWCON; /*!<EBU Bus Write Configuration Register Offset*/ \r
-__IO uint32_t BUSWAP; /*!<EBU Bus Write Access Parameter Register Offset*/ \r
+__IO uint32_t BUSWCON; /*!<EBU Bus Write Configuration Register Offset*/\r
+__IO uint32_t BUSWAP; /*!<EBU Bus Write Access Parameter Register Offset*/\r
}EBU_CS1_TypeDef;\r
\r
typedef struct {\r
__IO uint32_t ADDRSEL; /*!<EBU Address Select Register 0 Offset 0x0020*/\r
__I uint32_t RESERVED1[9];\r
__IO uint32_t BUSRCON; /*!<EBU Bus Configuration Register Offset 0x0048*/\r
-__IO uint32_t BUSRAP; /*!<EBU Bus Read Access Parameter Register Offset*/ \r
-__IO uint32_t BUSWCON; /*!<EBU Bus Write Configuration Register Offset*/ \r
-__IO uint32_t BUSWAP; /*!<EBU Bus Write Access Parameter Register Offset*/ \r
+__IO uint32_t BUSRAP; /*!<EBU Bus Read Access Parameter Register Offset*/\r
+__IO uint32_t BUSWCON; /*!<EBU Bus Write Configuration Register Offset*/\r
+__IO uint32_t BUSWAP; /*!<EBU Bus Write Access Parameter Register Offset*/\r
}EBU_CS2_TypeDef;\r
\r
typedef struct {\r
__IO uint32_t ADDRSEL; /*!<EBU Address Select Register 0 Offset 0x0024*/\r
__I uint32_t RESERVED1[12];\r
__IO uint32_t BUSRCON; /*!<EBU Bus Configuration Register Offset 0x0058*/\r
-__IO uint32_t BUSRAP; /*!<EBU Bus Read Access Parameter Register Offset*/ \r
-__IO uint32_t BUSWCON; /*!<EBU Bus Write Configuration Register Offset*/ \r
-__IO uint32_t BUSWAP; /*!<EBU Bus Write Access Parameter Register Offset*/ \r
+__IO uint32_t BUSRAP; /*!<EBU Bus Read Access Parameter Register Offset*/\r
+__IO uint32_t BUSWCON; /*!<EBU Bus Write Configuration Register Offset*/\r
+__IO uint32_t BUSWAP; /*!<EBU Bus Write Access Parameter Register Offset*/\r
}EBU_CS3_TypeDef;\r
\r
- /* \r
+ /*\r
*EBU SDRAM registers\r
*/\r
typedef struct {\r
/* ERUx */\r
/***************************************************************************/\r
\r
- /* \r
+ /*\r
*ERU Registers\r
*/\r
typedef struct {\r
/* ETHx */\r
/***************************************************************************/\r
\r
- /* \r
+ /*\r
*Ethernet Unit\r
*/\r
typedef struct {\r
/* ETH0_CON */\r
/***************************************************************************/\r
\r
- /* \r
+ /*\r
*Ethernet I/O Control Register\r
*/\r
typedef struct {\r
/* ETM */\r
/***************************************************************************/\r
\r
- /* \r
+ /*\r
*Cortex M4 - Embedded Trace Macrocell\r
*/\r
typedef struct { /*!< ETM Structure */\r
/* FCE */\r
/***************************************************************************/\r
\r
- /* \r
+ /*\r
*Global registers\r
*/\r
typedef struct {\r
__I uint32_t ID; /*!<Module Identification Register Offset 0x0008*/\r
}FCE_GLOBAL_TypeDef;\r
\r
- /* \r
+ /*\r
*Generic CRC Engine registers\r
*/\r
typedef struct {\r
/* FLASH0 */\r
/***************************************************************************/\r
\r
- /* \r
+ /*\r
*FLASH0 GLOBAL registers\r
*/\r
typedef struct {\r
/* FPB */\r
/***************************************************************************/\r
\r
- /* \r
+ /*\r
*Cortex M4 - Flash Patch and Breakpoint\r
*/\r
typedef struct { /*!< FPB Structure */\r
/* LEDTS0 */\r
/***************************************************************************/\r
\r
- /* \r
+ /*\r
*LEDTS0 KERNEL registers\r
*/\r
typedef struct {\r
/* PBAx */\r
/***************************************************************************/\r
\r
- /* \r
+ /*\r
*Peripheral Bridge Status and Write Error Address registers\r
*/\r
typedef struct {\r
/* PMU0 */\r
/***************************************************************************/\r
\r
- /* \r
+ /*\r
*PMU0 ID register\r
*/\r
typedef struct {\r
/* POSIFx */\r
/***************************************************************************/\r
\r
- /* \r
+ /*\r
*Position Interface\r
*/\r
typedef struct {\r
/* PREF */\r
/***************************************************************************/\r
\r
- /* \r
+ /*\r
*Prefetch\r
*/\r
typedef struct {\r
/* RTC */\r
/***************************************************************************/\r
\r
- /* \r
+ /*\r
*RTC Kernel registers\r
*/\r
typedef struct {\r
/* SCU */\r
/***************************************************************************/\r
\r
- /* \r
+ /*\r
*SCU CCU PLL registers\r
*/\r
typedef struct {\r
__I uint32_t CLKMXSTAT; /*!<Clock Multiplexing Status Register Offset 0x0738*/\r
}SCU_PLL_TypeDef;\r
\r
- /* \r
+ /*\r
*SCU CCU OSC registers\r
*/\r
typedef struct {\r
__IO uint32_t OSCHPCTRL; /*!<OSC_HP Control Register Offset 0x0704*/\r
}SCU_OSC_TypeDef;\r
\r
- /* \r
+ /*\r
*SCU CCU Clock Control registers\r
*/\r
typedef struct {\r
/* SCU */\r
/***************************************************************************/\r
\r
- /* \r
+ /*\r
*SCU GCU CONTROL registers\r
*/\r
typedef struct {\r
__IO uint32_t RMDATA; /*!<Retention Memory Access Data Register Offset 0x00CC*/\r
}SCU_GENERAL_TypeDef;\r
\r
- /* \r
+ /*\r
*SCU GCU PARITY registers\r
*/\r
typedef struct {\r
__IO uint32_t PMTSR; /*!<Parity Memory Test Select Register Offset 0x0158*/\r
}SCU_PARITY_TypeDef;\r
\r
- /* \r
+ /*\r
*SCU GCU INTERRUPT registers\r
*/\r
typedef struct {\r
__IO uint32_t NMIREQEN; /*!<SCU Service Request Mask Offset 0x0088*/\r
}SCU_INTERRUPT_TypeDef;\r
\r
- /* \r
+ /*\r
*SCU TRAP registers\r
*/\r
typedef struct {\r
/* SCU */\r
/***************************************************************************/\r
\r
- /* \r
+ /*\r
*SCU HIBERNATE registers\r
*/\r
typedef struct {\r
/* SCU */\r
/***************************************************************************/\r
\r
- /* \r
+ /*\r
*SCU PWRCTRL registers\r
*/\r
typedef struct {\r
/* SCU */\r
/***************************************************************************/\r
\r
- /* \r
+ /*\r
*SCU RESET CONTROL registers\r
*/\r
typedef struct {\r
/* SDMMC */\r
/***************************************************************************/\r
\r
- /* \r
+ /*\r
*SDMMC registers\r
*/\r
typedef struct {\r
/* TPIU */\r
/***************************************************************************/\r
\r
- /* \r
+ /*\r
*Cortex M4 - Trace Port Interface Unit\r
*/\r
typedef struct { /*!< TPIU Structure */\r
/* USB0 */\r
/***************************************************************************/\r
\r
- /* \r
+ /*\r
*CONTROL registers\r
*/\r
typedef struct {\r
__IO uint32_t PCGCCTL; /*!<Power and Clock Gating Control Register Offset 0x0E00*/\r
}USB0_GLOBAL_TypeDef;\r
\r
- /* \r
+ /*\r
*ENDPOINT-0 registers\r
*/\r
typedef struct {\r
__I uint32_t DOEPDMAB0; /*!<Device Endpoint-0 DMA Buffer Address Register Offset 0x0B1C*/\r
}USB0_EP0_TypeDef;\r
\r
- /* \r
+ /*\r
*ENDPOINTx registers\r
*/\r
typedef struct {\r
__I uint32_t DOEPDMAB; /*!<Device Endpoint-1 DMA Buffer Address Register Offset 0x0B3C*/\r
}USB0_EP_TypeDef;\r
\r
- /* \r
+ /*\r
*CHANNEL registers\r
*/\r
typedef struct {\r
/* USICx */\r
/***************************************************************************/\r
\r
- /* \r
+ /*\r
*Module wide registers\r
*/\r
typedef struct {\r
__I uint32_t ID; /*!<Module Identification Register Offset 0x0008*/\r
}USIC_GLOBAL_TypeDef;\r
\r
- /* \r
+ /*\r
*Channel Related registers\r
*/\r
typedef struct {\r
/* VADC */\r
/***************************************************************************/\r
\r
- /* \r
+ /*\r
*ADC Group registers\r
*/\r
typedef struct {\r
__I uint32_t RESD[16]; /*!<Group 0 Result Reg. 0, Debug Offset 0x0780*/\r
}VADC_G_TypeDef;\r
\r
- /* \r
+ /*\r
*ADC global registers\r
*/\r
typedef struct {\r
/* WDT */\r
/***************************************************************************/\r
\r
- /* \r
+ /*\r
*WDT Kernel registers\r
*/\r
typedef struct {\r
#elif defined(__ICCARM__)\r
/* leave anonymous unions enabled */\r
#elif defined(__GNUC__)\r
- /* anonymous unions are enabled by default */ \r
+ /* anonymous unions are enabled by default */\r
#elif defined(__TMS470__)\r
- /* anonymous unions are enabled by default */ \r
+ /* anonymous unions are enabled by default */\r
#elif defined(__TASKING__)\r
- #pragma warning restore \r
+ #pragma warning restore\r
#else\r
#warning Not supported compiler type\r
#endif\r
\r
#ifdef __cplusplus\r
}\r
-#endif \r
+#endif\r
\r
#endif // ifndef __XMC4500_H__\r
projects / freertos / commitdiff