#define portNVIC_PENDSV_PRI ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\r
#define portNVIC_SYSTICK_PRI ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\r
\r
-/* Constants required to check the validity of an interrupt prority. */\r
+/* Constants required to check the validity of an interrupt priority. */\r
#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )\r
#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )\r
#define portAIRCR_REG ( * ( ( volatile unsigned long * ) 0xE000ED0C ) )\r
+#define portMAX_8_BIT_VALUE ( ( unsigned char ) 0xff )\r
+#define portTOP_BIT_OF_BYTE ( ( unsigned char ) 0x80 )\r
+#define portMAX_PRIGROUP_BITS ( ( unsigned char ) 7 )\r
#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )\r
+#define portPRIGROUP_SHIFT ( 8UL )\r
\r
/* Constants required to set up the initial stack. */\r
-#define portINITIAL_XPSR ( 0x01000000 )\r
+#define portINITIAL_XPSR ( 0x01000000UL )\r
\r
/* The systick is a 24-bit counter. */\r
#define portMAX_24_BIT_NUMBER ( 0xffffffUL )\r
#endif /* configUSE_TICKLESS_IDLE */\r
\r
/*\r
- * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure \r
+ * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure\r
* FreeRTOS API functions are not called from interrupts that have been assigned\r
* a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
*/\r
#if ( configASSERT_DEFINED == 1 )\r
static unsigned char ucMaxSysCallPriority = 0;\r
+ static unsigned long ulMaxPRIGROUPValue = 0;\r
static const volatile unsigned char * const pcInterruptPriorityRegisters = ( const volatile unsigned char * const ) portNVIC_IP_REGISTERS_OFFSET_16;\r
#endif /* configASSERT_DEFINED */\r
\r
{\r
volatile unsigned long ulOriginalPriority;\r
volatile char * const pcFirstUserPriorityRegister = ( volatile char * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );\r
+ volatile unsigned char ucMaxPriorityValue;\r
\r
/* Determine the maximum priority from which ISR safe FreeRTOS API\r
functions can be called. ISR safe functions are those that end in\r
Save the interrupt priority value that is about to be clobbered. */\r
ulOriginalPriority = *pcFirstUserPriorityRegister;\r
\r
- /* Write the configMAX_SYSCALL_INTERRUPT_PRIORITY value to an interrupt\r
- priority register. */\r
- *pcFirstUserPriorityRegister = configMAX_SYSCALL_INTERRUPT_PRIORITY;\r
+ /* Determine the number of priority bits available. First write to all\r
+ possible bits. */\r
+ *pcFirstUserPriorityRegister = portMAX_8_BIT_VALUE;\r
\r
- /* Read back the written priority to obtain its value as seen by the\r
- hardware, which will only implement a subset of the priority bits. */\r
- ucMaxSysCallPriority = *pcFirstUserPriorityRegister;\r
+ /* Read the value back to see how many bits stuck. */\r
+ ucMaxPriorityValue = *pcFirstUserPriorityRegister;\r
+\r
+ /* Use the same mask on the maximum system call priority. */\r
+ ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;\r
+\r
+ /* Calculate the maximum acceptable priority group value for the number\r
+ of bits read back. */\r
+ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;\r
+ while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )\r
+ {\r
+ ulMaxPRIGROUPValue--;\r
+ ucMaxPriorityValue <<= ( unsigned char ) 0x01;\r
+ }\r
+\r
+ /* Shift the priority group value back to its position within the AIRCR\r
+ register. */\r
+ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;\r
+ ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;\r
\r
/* Restore the clobbered interrupt priority register to its original\r
value. */\r
/* Look up the interrupt's priority. */\r
ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];\r
\r
- /* The following assertion will fail if a service routine (ISR) for \r
+ /* The following assertion will fail if a service routine (ISR) for\r
an interrupt that has been assigned a priority above\r
configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API\r
- function. ISR safe FreeRTOS API functions must *only* be called \r
+ function. ISR safe FreeRTOS API functions must *only* be called\r
from interrupts that have been assigned a priority at or below\r
configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
- \r
+\r
Numerically low interrupt priority numbers represent logically high\r
- interrupt priorities, therefore the priority of the interrupt must \r
- be set to a value equal to or numerically *higher* than \r
+ interrupt priorities, therefore the priority of the interrupt must\r
+ be set to a value equal to or numerically *higher* than\r
configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
- \r
+\r
Interrupts that use the FreeRTOS API must not be left at their\r
default priority of zero as that is the highest possible priority,\r
- which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, \r
- and therefore also guaranteed to be invalid. \r
- \r
- FreeRTOS maintains separate thread and ISR API functions to ensure \r
+ which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,\r
+ and therefore also guaranteed to be invalid.\r
+\r
+ FreeRTOS maintains separate thread and ISR API functions to ensure\r
interrupt entry is as fast and simple as possible.\r
- \r
+\r
The following links provide detailed information:\r
http://www.freertos.org/RTOS-Cortex-M3-M4.html\r
http://www.freertos.org/FAQHelp.html */\r
configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );\r
}\r
\r
- /* Priority grouping: The interrupt controller (NVIC) allows the bits \r
- that define each interrupt's priority to be split between bits that \r
+ /* Priority grouping: The interrupt controller (NVIC) allows the bits\r
+ that define each interrupt's priority to be split between bits that\r
define the interrupt's pre-emption priority bits and bits that define\r
- the interrupt's sub-priority. For simplicity all bits must be defined \r
+ the interrupt's sub-priority. For simplicity all bits must be defined\r
to be pre-emption priority bits. The following assertion will fail if\r
- this is not the case (if some bits represent a sub-priority). \r
- \r
- If CMSIS libraries are being used then the correct setting can be \r
- achieved by calling NVIC_SetPriorityGrouping( 0 ); before starting the \r
- scheduler. */\r
- configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) == 0 );\r
+ this is not the case (if some bits represent a sub-priority).\r
+\r
+ If the application only uses CMSIS libraries for interrupt\r
+ configuration then the correct setting can be achieved on all Cortex-M\r
+ devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the\r
+ scheduler. Note however that some vendor specific peripheral libraries\r
+ assume a non-zero priority group setting, in which cases using a value\r
+ of zero will result in unpredicable behaviour. */\r
+ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );\r
}\r
\r
#endif /* configASSERT_DEFINED */\r
#define portNVIC_PENDSV_PRI ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\r
#define portNVIC_SYSTICK_PRI ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\r
\r
-/* Constants required to check the validity of an interrupt prority. */\r
+/* Constants required to check the validity of an interrupt priority. */\r
#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )\r
#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )\r
#define portAIRCR_REG ( * ( ( volatile unsigned long * ) 0xE000ED0C ) )\r
+#define portMAX_8_BIT_VALUE ( ( unsigned char ) 0xff )\r
+#define portTOP_BIT_OF_BYTE ( ( unsigned char ) 0x80 )\r
+#define portMAX_PRIGROUP_BITS ( ( unsigned char ) 7 )\r
#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )\r
+#define portPRIGROUP_SHIFT ( 8UL )\r
\r
/* Constants required to manipulate the VFP. */\r
#define portFPCCR ( ( volatile unsigned long * ) 0xe000ef34 ) /* Floating point context control register. */\r
*/\r
#if ( configASSERT_DEFINED == 1 )\r
static unsigned char ucMaxSysCallPriority = 0;\r
+ static unsigned long ulMaxPRIGROUPValue = 0;\r
static const volatile unsigned char * const pcInterruptPriorityRegisters = ( const volatile unsigned char * const ) portNVIC_IP_REGISTERS_OFFSET_16;\r
#endif /* configASSERT_DEFINED */\r
\r
{\r
volatile unsigned long ulOriginalPriority;\r
volatile char * const pcFirstUserPriorityRegister = ( volatile char * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );\r
+ volatile unsigned char ucMaxPriorityValue;\r
\r
/* Determine the maximum priority from which ISR safe FreeRTOS API\r
functions can be called. ISR safe functions are those that end in\r
Save the interrupt priority value that is about to be clobbered. */\r
ulOriginalPriority = *pcFirstUserPriorityRegister;\r
\r
- /* Write the configMAX_SYSCALL_INTERRUPT_PRIORITY value to an interrupt\r
- priority register. */\r
- *pcFirstUserPriorityRegister = configMAX_SYSCALL_INTERRUPT_PRIORITY;\r
+ /* Determine the number of priority bits available. First write to all\r
+ possible bits. */\r
+ *pcFirstUserPriorityRegister = portMAX_8_BIT_VALUE;\r
\r
- /* Read back the written priority to obtain its value as seen by the\r
- hardware, which will only implement a subset of the priority bits. */\r
- ucMaxSysCallPriority = *pcFirstUserPriorityRegister;\r
+ /* Read the value back to see how many bits stuck. */\r
+ ucMaxPriorityValue = *pcFirstUserPriorityRegister;\r
+\r
+ /* Use the same mask on the maximum system call priority. */\r
+ ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;\r
+\r
+ /* Calculate the maximum acceptable priority group value for the number\r
+ of bits read back. */\r
+ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;\r
+ while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )\r
+ {\r
+ ulMaxPRIGROUPValue--;\r
+ ucMaxPriorityValue <<= ( unsigned char ) 0x01;\r
+ }\r
+\r
+ /* Shift the priority group value back to its position within the AIRCR\r
+ register. */\r
+ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;\r
+ ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;\r
\r
/* Restore the clobbered interrupt priority register to its original\r
value. */\r
/* Look up the interrupt's priority. */\r
ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];\r
\r
- /* The following assertion will fail if a service routine (ISR) for \r
+ /* The following assertion will fail if a service routine (ISR) for\r
an interrupt that has been assigned a priority above\r
configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API\r
- function. ISR safe FreeRTOS API functions must *only* be called \r
+ function. ISR safe FreeRTOS API functions must *only* be called\r
from interrupts that have been assigned a priority at or below\r
configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
- \r
+\r
Numerically low interrupt priority numbers represent logically high\r
- interrupt priorities, therefore the priority of the interrupt must \r
- be set to a value equal to or numerically *higher* than \r
+ interrupt priorities, therefore the priority of the interrupt must\r
+ be set to a value equal to or numerically *higher* than\r
configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
- \r
+\r
Interrupts that use the FreeRTOS API must not be left at their\r
default priority of zero as that is the highest possible priority,\r
- which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, \r
- and therefore also guaranteed to be invalid. \r
- \r
- FreeRTOS maintains separate thread and ISR API functions to ensure \r
+ which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,\r
+ and therefore also guaranteed to be invalid.\r
+\r
+ FreeRTOS maintains separate thread and ISR API functions to ensure\r
interrupt entry is as fast and simple as possible.\r
- \r
+\r
The following links provide detailed information:\r
http://www.freertos.org/RTOS-Cortex-M3-M4.html\r
http://www.freertos.org/FAQHelp.html */\r
configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );\r
}\r
\r
- /* Priority grouping: The interrupt controller (NVIC) allows the bits \r
- that define each interrupt's priority to be split between bits that \r
+ /* Priority grouping: The interrupt controller (NVIC) allows the bits\r
+ that define each interrupt's priority to be split between bits that\r
define the interrupt's pre-emption priority bits and bits that define\r
- the interrupt's sub-priority. For simplicity all bits must be defined \r
+ the interrupt's sub-priority. For simplicity all bits must be defined\r
to be pre-emption priority bits. The following assertion will fail if\r
- this is not the case (if some bits represent a sub-priority). \r
- \r
- If CMSIS libraries are being used then the correct setting can be \r
- achieved by calling NVIC_SetPriorityGrouping( 0 ); before starting the \r
- scheduler. */\r
- configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) == 0 );\r
+ this is not the case (if some bits represent a sub-priority).\r
+\r
+ If the application only uses CMSIS libraries for interrupt\r
+ configuration then the correct setting can be achieved on all Cortex-M\r
+ devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the\r
+ scheduler. Note however that some vendor specific peripheral libraries\r
+ assume a non-zero priority group setting, in which cases using a value\r
+ of zero will result in unpredicable behaviour. */\r
+ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );\r
}\r
\r
#endif /* configASSERT_DEFINED */\r
#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )\r
#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )\r
#define portAIRCR_REG ( * ( ( volatile unsigned long * ) 0xE000ED0C ) )\r
+#define portMAX_8_BIT_VALUE ( ( unsigned char ) 0xff )\r
+#define portTOP_BIT_OF_BYTE ( ( unsigned char ) 0x80 )\r
+#define portMAX_PRIGROUP_BITS ( ( unsigned char ) 7 )\r
#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )\r
+#define portPRIGROUP_SHIFT ( 8UL )\r
\r
/* Constants required to set up the initial stack. */\r
#define portINITIAL_XPSR ( 0x01000000 )\r
*/\r
#if ( configASSERT_DEFINED == 1 )\r
static unsigned char ucMaxSysCallPriority = 0;\r
+ static unsigned long ulMaxPRIGROUPValue = 0;\r
static const volatile unsigned char * const pcInterruptPriorityRegisters = ( const volatile unsigned char * const ) portNVIC_IP_REGISTERS_OFFSET_16;\r
#endif /* configASSERT_DEFINED */\r
\r
{\r
volatile unsigned long ulOriginalPriority;\r
volatile char * const pcFirstUserPriorityRegister = ( volatile char * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );\r
+ volatile unsigned char ucMaxPriorityValue;\r
\r
/* Determine the maximum priority from which ISR safe FreeRTOS API\r
functions can be called. ISR safe functions are those that end in\r
Save the interrupt priority value that is about to be clobbered. */\r
ulOriginalPriority = *pcFirstUserPriorityRegister;\r
\r
- /* Write the configMAX_SYSCALL_INTERRUPT_PRIORITY value to an interrupt\r
- priority register. */\r
- *pcFirstUserPriorityRegister = configMAX_SYSCALL_INTERRUPT_PRIORITY;\r
+ /* Determine the number of priority bits available. First write to all\r
+ possible bits. */\r
+ *pcFirstUserPriorityRegister = portMAX_8_BIT_VALUE;\r
\r
- /* Read back the written priority to obtain its value as seen by the\r
- hardware, which will only implement a subset of the priority bits. */\r
- ucMaxSysCallPriority = *pcFirstUserPriorityRegister;\r
+ /* Read the value back to see how many bits stuck. */\r
+ ucMaxPriorityValue = *pcFirstUserPriorityRegister;\r
+\r
+ /* Use the same mask on the maximum system call priority. */\r
+ ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;\r
+\r
+ /* Calculate the maximum acceptable priority group value for the number\r
+ of bits read back. */\r
+ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;\r
+ while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )\r
+ {\r
+ ulMaxPRIGROUPValue--;\r
+ ucMaxPriorityValue <<= ( unsigned char ) 0x01;\r
+ }\r
+\r
+ /* Shift the priority group value back to its position within the AIRCR\r
+ register. */\r
+ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;\r
+ ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;\r
\r
/* Restore the clobbered interrupt priority register to its original\r
value. */\r
/* Look up the interrupt's priority. */\r
ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];\r
\r
- /* The following assertion will fail if a service routine (ISR) for \r
+ /* The following assertion will fail if a service routine (ISR) for\r
an interrupt that has been assigned a priority above\r
configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API\r
- function. ISR safe FreeRTOS API functions must *only* be called \r
+ function. ISR safe FreeRTOS API functions must *only* be called\r
from interrupts that have been assigned a priority at or below\r
configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
- \r
+\r
Numerically low interrupt priority numbers represent logically high\r
- interrupt priorities, therefore the priority of the interrupt must \r
- be set to a value equal to or numerically *higher* than \r
+ interrupt priorities, therefore the priority of the interrupt must\r
+ be set to a value equal to or numerically *higher* than\r
configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
- \r
+\r
Interrupts that use the FreeRTOS API must not be left at their\r
default priority of zero as that is the highest possible priority,\r
- which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, \r
- and therefore also guaranteed to be invalid. \r
- \r
- FreeRTOS maintains separate thread and ISR API functions to ensure \r
+ which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,\r
+ and therefore also guaranteed to be invalid.\r
+\r
+ FreeRTOS maintains separate thread and ISR API functions to ensure\r
interrupt entry is as fast and simple as possible.\r
- \r
+\r
The following links provide detailed information:\r
http://www.freertos.org/RTOS-Cortex-M3-M4.html\r
http://www.freertos.org/FAQHelp.html */\r
configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );\r
}\r
\r
- /* Priority grouping: The interrupt controller (NVIC) allows the bits \r
- that define each interrupt's priority to be split between bits that \r
+ /* Priority grouping: The interrupt controller (NVIC) allows the bits\r
+ that define each interrupt's priority to be split between bits that\r
define the interrupt's pre-emption priority bits and bits that define\r
- the interrupt's sub-priority. For simplicity all bits must be defined \r
+ the interrupt's sub-priority. For simplicity all bits must be defined\r
to be pre-emption priority bits. The following assertion will fail if\r
- this is not the case (if some bits represent a sub-priority). \r
- \r
- If CMSIS libraries are being used then the correct setting can be \r
- achieved by calling NVIC_SetPriorityGrouping( 0 ); before starting the \r
- scheduler. */\r
- configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) == 0 );\r
+ this is not the case (if some bits represent a sub-priority).\r
+\r
+ If the application only uses CMSIS libraries for interrupt\r
+ configuration then the correct setting can be achieved on all Cortex-M\r
+ devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the\r
+ scheduler. Note however that some vendor specific peripheral libraries\r
+ assume a non-zero priority group setting, in which cases using a value\r
+ of zero will result in unpredicable behaviour. */\r
+ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );\r
}\r
\r
#endif /* configASSERT_DEFINED */\r
#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )\r
#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )\r
#define portAIRCR_REG ( * ( ( volatile unsigned long * ) 0xE000ED0C ) )\r
+#define portMAX_8_BIT_VALUE ( ( unsigned char ) 0xff )\r
+#define portTOP_BIT_OF_BYTE ( ( unsigned char ) 0x80 )\r
+#define portMAX_PRIGROUP_BITS ( ( unsigned char ) 7 )\r
#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )\r
+#define portPRIGROUP_SHIFT ( 8UL )\r
\r
/* Constants required to manipulate the VFP. */\r
#define portFPCCR ( ( volatile unsigned long * ) 0xe000ef34 ) /* Floating point context control register. */\r
*/\r
#if ( configASSERT_DEFINED == 1 )\r
static unsigned char ucMaxSysCallPriority = 0;\r
+ static unsigned long ulMaxPRIGROUPValue = 0;\r
static const volatile unsigned char * const pcInterruptPriorityRegisters = ( const volatile unsigned char * const ) portNVIC_IP_REGISTERS_OFFSET_16;\r
#endif /* configASSERT_DEFINED */\r
\r
{\r
volatile unsigned long ulOriginalPriority;\r
volatile char * const pcFirstUserPriorityRegister = ( volatile char * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );\r
+ volatile unsigned char ucMaxPriorityValue;\r
\r
/* Determine the maximum priority from which ISR safe FreeRTOS API\r
functions can be called. ISR safe functions are those that end in\r
Save the interrupt priority value that is about to be clobbered. */\r
ulOriginalPriority = *pcFirstUserPriorityRegister;\r
\r
- /* Write the configMAX_SYSCALL_INTERRUPT_PRIORITY value to an interrupt\r
- priority register. */\r
- *pcFirstUserPriorityRegister = configMAX_SYSCALL_INTERRUPT_PRIORITY;\r
+ /* Determine the number of priority bits available. First write to all\r
+ possible bits. */\r
+ *pcFirstUserPriorityRegister = portMAX_8_BIT_VALUE;\r
\r
- /* Read back the written priority to obtain its value as seen by the\r
- hardware, which will only implement a subset of the priority bits. */\r
- ucMaxSysCallPriority = *pcFirstUserPriorityRegister;\r
+ /* Read the value back to see how many bits stuck. */\r
+ ucMaxPriorityValue = *pcFirstUserPriorityRegister;\r
+\r
+ /* Use the same mask on the maximum system call priority. */\r
+ ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;\r
+\r
+ /* Calculate the maximum acceptable priority group value for the number\r
+ of bits read back. */\r
+ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;\r
+ while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )\r
+ {\r
+ ulMaxPRIGROUPValue--;\r
+ ucMaxPriorityValue <<= ( unsigned char ) 0x01;\r
+ }\r
+\r
+ /* Shift the priority group value back to its position within the AIRCR\r
+ register. */\r
+ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;\r
+ ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;\r
\r
/* Restore the clobbered interrupt priority register to its original\r
value. */\r
/* Look up the interrupt's priority. */\r
ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];\r
\r
- /* The following assertion will fail if a service routine (ISR) for \r
+ /* The following assertion will fail if a service routine (ISR) for\r
an interrupt that has been assigned a priority above\r
configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API\r
- function. ISR safe FreeRTOS API functions must *only* be called \r
+ function. ISR safe FreeRTOS API functions must *only* be called\r
from interrupts that have been assigned a priority at or below\r
configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
- \r
+\r
Numerically low interrupt priority numbers represent logically high\r
- interrupt priorities, therefore the priority of the interrupt must \r
- be set to a value equal to or numerically *higher* than \r
+ interrupt priorities, therefore the priority of the interrupt must\r
+ be set to a value equal to or numerically *higher* than\r
configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
- \r
+\r
Interrupts that use the FreeRTOS API must not be left at their\r
default priority of zero as that is the highest possible priority,\r
- which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, \r
- and therefore also guaranteed to be invalid. \r
- \r
- FreeRTOS maintains separate thread and ISR API functions to ensure \r
+ which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,\r
+ and therefore also guaranteed to be invalid.\r
+\r
+ FreeRTOS maintains separate thread and ISR API functions to ensure\r
interrupt entry is as fast and simple as possible.\r
- \r
+\r
The following links provide detailed information:\r
http://www.freertos.org/RTOS-Cortex-M3-M4.html\r
http://www.freertos.org/FAQHelp.html */\r
configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );\r
}\r
\r
- /* Priority grouping: The interrupt controller (NVIC) allows the bits \r
- that define each interrupt's priority to be split between bits that \r
+ /* Priority grouping: The interrupt controller (NVIC) allows the bits\r
+ that define each interrupt's priority to be split between bits that\r
define the interrupt's pre-emption priority bits and bits that define\r
- the interrupt's sub-priority. For simplicity all bits must be defined \r
+ the interrupt's sub-priority. For simplicity all bits must be defined\r
to be pre-emption priority bits. The following assertion will fail if\r
- this is not the case (if some bits represent a sub-priority). \r
- \r
- If CMSIS libraries are being used then the correct setting can be \r
- achieved by calling NVIC_SetPriorityGrouping( 0 ); before starting the \r
- scheduler. */\r
- configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) == 0 );\r
+ this is not the case (if some bits represent a sub-priority).\r
+\r
+ If the application only uses CMSIS libraries for interrupt\r
+ configuration then the correct setting can be achieved on all Cortex-M\r
+ devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the\r
+ scheduler. Note however that some vendor specific peripheral libraries\r
+ assume a non-zero priority group setting, in which cases using a value\r
+ of zero will result in unpredicable behaviour. */\r
+ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );\r
}\r
\r
#endif /* configASSERT_DEFINED */\r
#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )\r
#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )\r
#define portAIRCR_REG ( * ( ( volatile unsigned long * ) 0xE000ED0C ) )\r
+#define portMAX_8_BIT_VALUE ( ( unsigned char ) 0xff )\r
+#define portTOP_BIT_OF_BYTE ( ( unsigned char ) 0x80 )\r
+#define portMAX_PRIGROUP_BITS ( ( unsigned char ) 7 )\r
#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )\r
+#define portPRIGROUP_SHIFT ( 8UL )\r
\r
/* Constants required to set up the initial stack. */\r
#define portINITIAL_XPSR ( 0x01000000 )\r
*/\r
#if ( configASSERT_DEFINED == 1 )\r
static unsigned char ucMaxSysCallPriority = 0;\r
+ static unsigned long ulMaxPRIGROUPValue = 0;\r
static const volatile unsigned char * const pcInterruptPriorityRegisters = ( unsigned char * ) portNVIC_IP_REGISTERS_OFFSET_16;\r
#endif /* configASSERT_DEFINED */\r
\r
{\r
volatile unsigned long ulOriginalPriority;\r
volatile char * const pcFirstUserPriorityRegister = ( char * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );\r
+ volatile unsigned char ucMaxPriorityValue;\r
\r
/* Determine the maximum priority from which ISR safe FreeRTOS API\r
functions can be called. ISR safe functions are those that end in\r
Save the interrupt priority value that is about to be clobbered. */\r
ulOriginalPriority = *pcFirstUserPriorityRegister;\r
\r
- /* Write the configMAX_SYSCALL_INTERRUPT_PRIORITY value to an interrupt\r
- priority register. */\r
- *pcFirstUserPriorityRegister = configMAX_SYSCALL_INTERRUPT_PRIORITY;\r
+ /* Determine the number of priority bits available. First write to all\r
+ possible bits. */\r
+ *pcFirstUserPriorityRegister = portMAX_8_BIT_VALUE;\r
\r
- /* Read back the written priority to obtain its value as seen by the\r
- hardware, which will only implement a subset of the priority bits. */\r
- ucMaxSysCallPriority = *pcFirstUserPriorityRegister;\r
+ /* Read the value back to see how many bits stuck. */\r
+ ucMaxPriorityValue = *pcFirstUserPriorityRegister;\r
+\r
+ /* Use the same mask on the maximum system call priority. */\r
+ ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;\r
+\r
+ /* Calculate the maximum acceptable priority group value for the number\r
+ of bits read back. */\r
+ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;\r
+ while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )\r
+ {\r
+ ulMaxPRIGROUPValue--;\r
+ ucMaxPriorityValue <<= ( unsigned char ) 0x01;\r
+ }\r
+\r
+ /* Shift the priority group value back to its position within the AIRCR\r
+ register. */\r
+ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;\r
+ ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;\r
\r
/* Restore the clobbered interrupt priority register to its original\r
value. */\r
/* Look up the interrupt's priority. */\r
ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];\r
\r
- /* The following assertion will fail if a service routine (ISR) for \r
+ /* The following assertion will fail if a service routine (ISR) for\r
an interrupt that has been assigned a priority above\r
configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API\r
- function. ISR safe FreeRTOS API functions must *only* be called \r
+ function. ISR safe FreeRTOS API functions must *only* be called\r
from interrupts that have been assigned a priority at or below\r
configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
- \r
+\r
Numerically low interrupt priority numbers represent logically high\r
- interrupt priorities, therefore the priority of the interrupt must \r
- be set to a value equal to or numerically *higher* than \r
+ interrupt priorities, therefore the priority of the interrupt must\r
+ be set to a value equal to or numerically *higher* than\r
configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
- \r
+\r
Interrupts that use the FreeRTOS API must not be left at their\r
default priority of zero as that is the highest possible priority,\r
- which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, \r
- and therefore also guaranteed to be invalid. \r
- \r
- FreeRTOS maintains separate thread and ISR API functions to ensure \r
+ which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,\r
+ and therefore also guaranteed to be invalid.\r
+\r
+ FreeRTOS maintains separate thread and ISR API functions to ensure\r
interrupt entry is as fast and simple as possible.\r
- \r
+\r
The following links provide detailed information:\r
http://www.freertos.org/RTOS-Cortex-M3-M4.html\r
http://www.freertos.org/FAQHelp.html */\r
configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );\r
}\r
\r
- /* Priority grouping: The interrupt controller (NVIC) allows the bits \r
- that define each interrupt's priority to be split between bits that \r
+ /* Priority grouping: The interrupt controller (NVIC) allows the bits\r
+ that define each interrupt's priority to be split between bits that\r
define the interrupt's pre-emption priority bits and bits that define\r
- the interrupt's sub-priority. For simplicity all bits must be defined \r
+ the interrupt's sub-priority. For simplicity all bits must be defined\r
to be pre-emption priority bits. The following assertion will fail if\r
- this is not the case (if some bits represent a sub-priority). \r
- \r
- If CMSIS libraries are being used then the correct setting can be \r
- achieved by calling NVIC_SetPriorityGrouping( 0 ); before starting the \r
- scheduler. */\r
- configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) == 0 );\r
+ this is not the case (if some bits represent a sub-priority).\r
+\r
+ If the application only uses CMSIS libraries for interrupt\r
+ configuration then the correct setting can be achieved on all Cortex-M\r
+ devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the\r
+ scheduler. Note however that some vendor specific peripheral libraries\r
+ assume a non-zero priority group setting, in which cases using a value\r
+ of zero will result in unpredicable behaviour. */\r
+ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );\r
}\r
\r
#endif /* configASSERT_DEFINED */\r
#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )\r
#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )\r
#define portAIRCR_REG ( * ( ( volatile unsigned long * ) 0xE000ED0C ) )\r
+#define portMAX_8_BIT_VALUE ( ( unsigned char ) 0xff )\r
+#define portTOP_BIT_OF_BYTE ( ( unsigned char ) 0x80 )\r
+#define portMAX_PRIGROUP_BITS ( ( unsigned char ) 7 )\r
#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )\r
+#define portPRIGROUP_SHIFT ( 8UL )\r
\r
/* Constants required to manipulate the VFP. */\r
#define portFPCCR ( ( volatile unsigned long * ) 0xe000ef34 ) /* Floating point context control register. */\r
*/\r
#if ( configASSERT_DEFINED == 1 )\r
static unsigned char ucMaxSysCallPriority = 0;\r
+ static unsigned long ulMaxPRIGROUPValue = 0;\r
static const volatile unsigned char * const pcInterruptPriorityRegisters = ( unsigned char * ) portNVIC_IP_REGISTERS_OFFSET_16;\r
#endif /* configASSERT_DEFINED */\r
\r
{\r
volatile unsigned long ulOriginalPriority;\r
volatile char * const pcFirstUserPriorityRegister = ( char * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );\r
+ volatile unsigned char ucMaxPriorityValue;\r
\r
/* Determine the maximum priority from which ISR safe FreeRTOS API\r
functions can be called. ISR safe functions are those that end in\r
Save the interrupt priority value that is about to be clobbered. */\r
ulOriginalPriority = *pcFirstUserPriorityRegister;\r
\r
- /* Write the configMAX_SYSCALL_INTERRUPT_PRIORITY value to an interrupt\r
- priority register. */\r
- *pcFirstUserPriorityRegister = configMAX_SYSCALL_INTERRUPT_PRIORITY;\r
+ /* Determine the number of priority bits available. First write to all\r
+ possible bits. */\r
+ *pcFirstUserPriorityRegister = portMAX_8_BIT_VALUE;\r
\r
- /* Read back the written priority to obtain its value as seen by the\r
- hardware, which will only implement a subset of the priority bits. */\r
- ucMaxSysCallPriority = *pcFirstUserPriorityRegister;\r
+ /* Read the value back to see how many bits stuck. */\r
+ ucMaxPriorityValue = *pcFirstUserPriorityRegister;\r
+\r
+ /* Use the same mask on the maximum system call priority. */\r
+ ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;\r
+\r
+ /* Calculate the maximum acceptable priority group value for the number\r
+ of bits read back. */\r
+ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;\r
+ while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )\r
+ {\r
+ ulMaxPRIGROUPValue--;\r
+ ucMaxPriorityValue <<= ( unsigned char ) 0x01;\r
+ }\r
+\r
+ /* Shift the priority group value back to its position within the AIRCR\r
+ register. */\r
+ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;\r
+ ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;\r
\r
/* Restore the clobbered interrupt priority register to its original\r
value. */\r
/* Look up the interrupt's priority. */\r
ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];\r
\r
- /* The following assertion will fail if a service routine (ISR) for \r
+ /* The following assertion will fail if a service routine (ISR) for\r
an interrupt that has been assigned a priority above\r
configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API\r
- function. ISR safe FreeRTOS API functions must *only* be called \r
+ function. ISR safe FreeRTOS API functions must *only* be called\r
from interrupts that have been assigned a priority at or below\r
configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
- \r
+\r
Numerically low interrupt priority numbers represent logically high\r
- interrupt priorities, therefore the priority of the interrupt must \r
- be set to a value equal to or numerically *higher* than \r
+ interrupt priorities, therefore the priority of the interrupt must\r
+ be set to a value equal to or numerically *higher* than\r
configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
- \r
+\r
Interrupts that use the FreeRTOS API must not be left at their\r
default priority of zero as that is the highest possible priority,\r
- which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, \r
- and therefore also guaranteed to be invalid. \r
- \r
- FreeRTOS maintains separate thread and ISR API functions to ensure \r
+ which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,\r
+ and therefore also guaranteed to be invalid.\r
+\r
+ FreeRTOS maintains separate thread and ISR API functions to ensure\r
interrupt entry is as fast and simple as possible.\r
- \r
+\r
The following links provide detailed information:\r
http://www.freertos.org/RTOS-Cortex-M3-M4.html\r
http://www.freertos.org/FAQHelp.html */\r
configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );\r
}\r
\r
- /* Priority grouping: The interrupt controller (NVIC) allows the bits \r
- that define each interrupt's priority to be split between bits that \r
+ /* Priority grouping: The interrupt controller (NVIC) allows the bits\r
+ that define each interrupt's priority to be split between bits that\r
define the interrupt's pre-emption priority bits and bits that define\r
- the interrupt's sub-priority. For simplicity all bits must be defined \r
+ the interrupt's sub-priority. For simplicity all bits must be defined\r
to be pre-emption priority bits. The following assertion will fail if\r
- this is not the case (if some bits represent a sub-priority). \r
- \r
- If CMSIS libraries are being used then the correct setting can be \r
- achieved by calling NVIC_SetPriorityGrouping( 0 ); before starting the \r
- scheduler. */\r
- configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) == 0 );\r
+ this is not the case (if some bits represent a sub-priority).\r
+\r
+ If the application only uses CMSIS libraries for interrupt\r
+ configuration then the correct setting can be achieved on all Cortex-M\r
+ devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the\r
+ scheduler. Note however that some vendor specific peripheral libraries\r
+ assume a non-zero priority group setting, in which cases using a value\r
+ of zero will result in unpredicable behaviour. */\r
+ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );\r
}\r
- \r
+\r
#endif /* configASSERT_DEFINED */\r
\r
\r
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