]> git.sur5r.net Git - openocd/commitdiff
s3c24xx_nand_controller_t -> struct s3c24xx_nand_controller
authorZachary T Welch <zw@superlucidity.net>
Fri, 13 Nov 2009 15:38:52 +0000 (07:38 -0800)
committerZachary T Welch <zw@superlucidity.net>
Fri, 13 Nov 2009 19:58:07 +0000 (11:58 -0800)
Remove misleading typedef and redundant suffix from struct s3c24xx_nand_controller.

src/flash/s3c2410_nand.c
src/flash/s3c2412_nand.c
src/flash/s3c2440_nand.c
src/flash/s3c2443_nand.c
src/flash/s3c24xx_nand.c
src/flash/s3c24xx_nand.h

index c57fe9369ed073381e5731a9a928dc6195ed1011..4d084403bf3d4606139fffc332ee49a15135bb90 100644 (file)
@@ -32,7 +32,7 @@
 
 NAND_DEVICE_COMMAND_HANDLER(s3c2410_nand_device_command)
 {
-       s3c24xx_nand_controller_t *info;
+       struct s3c24xx_nand_controller *info;
        CALL_S3C24XX_DEVICE_COMMAND(nand, &info);
 
        /* fill in the address fields for the core device */
@@ -46,7 +46,7 @@ NAND_DEVICE_COMMAND_HANDLER(s3c2410_nand_device_command)
 
 static int s3c2410_init(struct nand_device_s *nand)
 {
-       s3c24xx_nand_controller_t *s3c24xx_info = nand->controller_priv;
+       struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
        target_t *target = s3c24xx_info->target;
 
        target_write_u32(target, S3C2410_NFCONF,
@@ -58,7 +58,7 @@ static int s3c2410_init(struct nand_device_s *nand)
 
 static int s3c2410_write_data(struct nand_device_s *nand, uint16_t data)
 {
-       s3c24xx_nand_controller_t *s3c24xx_info = nand->controller_priv;
+       struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
        target_t *target = s3c24xx_info->target;
 
        if (target->state != TARGET_HALTED) {
@@ -72,7 +72,7 @@ static int s3c2410_write_data(struct nand_device_s *nand, uint16_t data)
 
 static int s3c2410_read_data(struct nand_device_s *nand, void *data)
 {
-       s3c24xx_nand_controller_t *s3c24xx_info = nand->controller_priv;
+       struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
        target_t *target = s3c24xx_info->target;
 
        if (target->state != TARGET_HALTED) {
@@ -86,7 +86,7 @@ static int s3c2410_read_data(struct nand_device_s *nand, void *data)
 
 static int s3c2410_nand_ready(struct nand_device_s *nand, int timeout)
 {
-       s3c24xx_nand_controller_t *s3c24xx_info = nand->controller_priv;
+       struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
        target_t *target = s3c24xx_info->target;
        uint8_t status;
 
index b41705dc44f579e3afb65ba063930a751c859e01..9f456fe5607776f319e932d873154a77f0173186 100644 (file)
@@ -32,7 +32,7 @@
 
 NAND_DEVICE_COMMAND_HANDLER(s3c2412_nand_device_command)
 {
-       s3c24xx_nand_controller_t *info;
+       struct s3c24xx_nand_controller *info;
        CALL_S3C24XX_DEVICE_COMMAND(nand, &info);
 
        /* fill in the address fields for the core device */
@@ -46,7 +46,7 @@ NAND_DEVICE_COMMAND_HANDLER(s3c2412_nand_device_command)
 
 static int s3c2412_init(struct nand_device_s *nand)
 {
-       s3c24xx_nand_controller_t *s3c24xx_info = nand->controller_priv;
+       struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
        target_t *target = s3c24xx_info->target;
 
        target_write_u32(target, S3C2410_NFCONF,
index 8c056878080844ee295816d30d95f0b699407c38..40037c7f262c09da77ed4be81cbaf4fc1bb0a308 100644 (file)
@@ -33,7 +33,7 @@
 
 NAND_DEVICE_COMMAND_HANDLER(s3c2440_nand_device_command)
 {
-       s3c24xx_nand_controller_t *info;
+       struct s3c24xx_nand_controller *info;
        CALL_S3C24XX_DEVICE_COMMAND(nand, &info);
 
        /* fill in the address fields for the core device */
@@ -47,7 +47,7 @@ NAND_DEVICE_COMMAND_HANDLER(s3c2440_nand_device_command)
 
 static int s3c2440_init(struct nand_device_s *nand)
 {
-       s3c24xx_nand_controller_t *s3c24xx_info = nand->controller_priv;
+       struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
        target_t *target = s3c24xx_info->target;
 
        target_write_u32(target, S3C2410_NFCONF,
@@ -63,7 +63,7 @@ static int s3c2440_init(struct nand_device_s *nand)
 
 int s3c2440_nand_ready(struct nand_device_s *nand, int timeout)
 {
-       s3c24xx_nand_controller_t *s3c24xx_info = nand->controller_priv;
+       struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
        target_t *target = s3c24xx_info->target;
        uint8_t status;
 
@@ -89,7 +89,7 @@ int s3c2440_nand_ready(struct nand_device_s *nand, int timeout)
 
 int s3c2440_read_block_data(struct nand_device_s *nand, uint8_t *data, int data_size)
 {
-       s3c24xx_nand_controller_t *s3c24xx_info = nand->controller_priv;
+       struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
        target_t *target = s3c24xx_info->target;
        uint32_t nfdata = s3c24xx_info->data;
        uint32_t tmp;
@@ -125,7 +125,7 @@ int s3c2440_read_block_data(struct nand_device_s *nand, uint8_t *data, int data_
 
 int s3c2440_write_block_data(struct nand_device_s *nand, uint8_t *data, int data_size)
 {
-       s3c24xx_nand_controller_t *s3c24xx_info = nand->controller_priv;
+       struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
        target_t *target = s3c24xx_info->target;
        uint32_t nfdata = s3c24xx_info->data;
        uint32_t tmp;
index 30549f6b7d414d4e8e3facda792d0d1abf69084e..0f086441200fe0842e86d7b9b8a1526d1820012f 100644 (file)
@@ -33,7 +33,7 @@
 
 NAND_DEVICE_COMMAND_HANDLER(s3c2443_nand_device_command)
 {
-       s3c24xx_nand_controller_t *info;
+       struct s3c24xx_nand_controller *info;
        CALL_S3C24XX_DEVICE_COMMAND(nand, &info);
 
        /* fill in the address fields for the core device */
@@ -47,7 +47,7 @@ NAND_DEVICE_COMMAND_HANDLER(s3c2443_nand_device_command)
 
 static int s3c2443_init(struct nand_device_s *nand)
 {
-       s3c24xx_nand_controller_t *s3c24xx_info = nand->controller_priv;
+       struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
        target_t *target = s3c24xx_info->target;
 
        target_write_u32(target, S3C2410_NFCONF,
index e2bc00532071e900c37b5a6abf4e77dc4ff2c9ca..17de5d414be4bc348f4e1d3befc98cd6aa0e5a1e 100644 (file)
@@ -33,9 +33,9 @@
 
 S3C24XX_DEVICE_COMMAND()
 {
-       s3c24xx_nand_controller_t *s3c24xx_info;
+       struct s3c24xx_nand_controller *s3c24xx_info;
 
-       s3c24xx_info = malloc(sizeof(s3c24xx_nand_controller_t));
+       s3c24xx_info = malloc(sizeof(struct s3c24xx_nand_controller));
        if (s3c24xx_info == NULL) {
                LOG_ERROR("no memory for nand controller\n");
                return -ENOMEM;
@@ -59,7 +59,7 @@ int s3c24xx_register_commands(struct command_context_s *cmd_ctx)
 
 int s3c24xx_reset(struct nand_device_s *nand)
 {
-       s3c24xx_nand_controller_t *s3c24xx_info = nand->controller_priv;
+       struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
        target_t *target = s3c24xx_info->target;
 
        if (target->state != TARGET_HALTED) {
@@ -74,7 +74,7 @@ int s3c24xx_reset(struct nand_device_s *nand)
 
 int s3c24xx_command(struct nand_device_s *nand, uint8_t command)
 {
-       s3c24xx_nand_controller_t *s3c24xx_info = nand->controller_priv;
+       struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
        target_t *target = s3c24xx_info->target;
 
        if (target->state != TARGET_HALTED) {
@@ -89,7 +89,7 @@ int s3c24xx_command(struct nand_device_s *nand, uint8_t command)
 
 int s3c24xx_address(struct nand_device_s *nand, uint8_t address)
 {
-       s3c24xx_nand_controller_t *s3c24xx_info = nand->controller_priv;
+       struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
        target_t *target = s3c24xx_info->target;
 
        if (target->state != TARGET_HALTED) {
@@ -103,7 +103,7 @@ int s3c24xx_address(struct nand_device_s *nand, uint8_t address)
 
 int s3c24xx_write_data(struct nand_device_s *nand, uint16_t data)
 {
-       s3c24xx_nand_controller_t *s3c24xx_info = nand->controller_priv;
+       struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
        target_t *target = s3c24xx_info->target;
 
        if (target->state != TARGET_HALTED) {
@@ -117,7 +117,7 @@ int s3c24xx_write_data(struct nand_device_s *nand, uint16_t data)
 
 int s3c24xx_read_data(struct nand_device_s *nand, void *data)
 {
-       s3c24xx_nand_controller_t *s3c24xx_info = nand->controller_priv;
+       struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
        target_t *target = s3c24xx_info->target;
 
        if (target->state != TARGET_HALTED) {
index 3f304a98ea807cba4fc472324e6b83ce79cb559f..6cfad3d311f2e6b54fd1a54ce8b2883b63d43eac 100644 (file)
@@ -30,7 +30,7 @@
 #include "nand.h"
 #include "s3c24xx_regs_nand.h"
 
-typedef struct s3c24xx_nand_controller_s
+struct s3c24xx_nand_controller
 {
        struct target_s *target;
 
@@ -39,7 +39,7 @@ typedef struct s3c24xx_nand_controller_s
        uint32_t                 addr;
        uint32_t                 data;
        uint32_t                 nfstat;
-} s3c24xx_nand_controller_t;
+};
 
 /* Default to using the un-translated NAND register based address */
 #undef S3C2410_NFREG
@@ -48,7 +48,7 @@ typedef struct s3c24xx_nand_controller_s
 #define S3C24XX_DEVICE_COMMAND() \
                COMMAND_HELPER(s3c24xx_nand_device_command, \
                                struct nand_device_s *nand, \
-                               s3c24xx_nand_controller_t **info)
+                               struct s3c24xx_nand_controller **info)
 
 S3C24XX_DEVICE_COMMAND();