--- /dev/null
+PACKAGE install\r
+{\r
+ version = "4.01:213";\r
+ COMPONENT altera_nios2\r
+ {\r
+ VERSION 7.080902\r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/nios2_ip/altera_nios2";\r
+ }\r
+ }\r
+ COMPONENT altera_nios_custom_instruction\r
+ {\r
+ VERSION 7.080902\r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/nios2_ip/altera_nios_custom_instruction";\r
+ }\r
+ }\r
+ COMPONENT altera_nios_custom_instr_bitswap\r
+ {\r
+ VERSION 7.080902\r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/nios2_ip/altera_nios_custom_instr_bitswap";\r
+ }\r
+ }\r
+ COMPONENT altera_nios_custom_instr_endian_converter\r
+ {\r
+ VERSION 7.080902\r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/nios2_ip/altera_nios_custom_instr_endian_converter";\r
+ }\r
+ }\r
+ COMPONENT altera_nios_custom_instr_floating_point\r
+ {\r
+ VERSION 7.080902\r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/nios2_ip/altera_nios_custom_instr_floating_point";\r
+ }\r
+ }\r
+ COMPONENT altera_nios_custom_instr_interrupt_vector\r
+ {\r
+ VERSION 7.080902\r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/nios2_ip/altera_nios_custom_instr_interrupt_vector";\r
+ }\r
+ }\r
+ COMPONENT altera_nios_dev_board_cyclone_1c20\r
+ {\r
+ VERSION 7.080902\r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/nios2_ip/altera_nios_dev_board_cyclone_1c20";\r
+ }\r
+ }\r
+ COMPONENT altera_nios_dev_board_cyclone_2c35\r
+ {\r
+ VERSION 7.080902\r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/nios2_ip/altera_nios_dev_board_cyclone_2c35";\r
+ }\r
+ }\r
+ COMPONENT altera_nios_dev_board_stratix_1s10\r
+ {\r
+ VERSION 7.080902\r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/nios2_ip/altera_nios_dev_board_stratix_1s10";\r
+ }\r
+ }\r
+ COMPONENT altera_nios_dev_board_stratix_1s10_es\r
+ {\r
+ VERSION 7.080902\r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/nios2_ip/altera_nios_dev_board_stratix_1s10_es";\r
+ }\r
+ }\r
+ COMPONENT altera_nios_dev_board_stratix_1s40\r
+ {\r
+ VERSION 7.080902\r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/nios2_ip/altera_nios_dev_board_stratix_1s40";\r
+ }\r
+ }\r
+ COMPONENT altera_nios_dev_board_stratix_2s60\r
+ {\r
+ VERSION 7.080902\r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/nios2_ip/altera_nios_dev_board_stratix_2s60";\r
+ }\r
+ }\r
+ COMPONENT altera_nios_dev_board_stratix_2s60_es\r
+ {\r
+ VERSION 7.080902\r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/nios2_ip/altera_nios_dev_board_stratix_2s60_es";\r
+ }\r
+ }\r
+ COMPONENT altera_nios_dev_board_stratix_2s60_rohs\r
+ {\r
+ VERSION 7.080902\r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/nios2_ip/altera_nios_dev_board_stratix_2s60_rohs";\r
+ }\r
+ }\r
+ COMPONENT altera_nios_dev_kit_stratix_edition_sram\r
+ {\r
+ VERSION 7.080902\r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/nios2_ip/altera_nios_dev_kit_stratix_edition_sram";\r
+ }\r
+ }\r
+ COMPONENT altera_nios_dev_kit_stratix_edition_sram2\r
+ {\r
+ VERSION 7.080902\r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/nios2_ip/altera_nios_dev_kit_stratix_edition_sram2";\r
+ }\r
+ }\r
+ COMPONENT altera_nios_multiply\r
+ {\r
+ VERSION 7.080902\r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/nios2_ip/altera_nios_multiply";\r
+ }\r
+ }\r
+ COMPONENT altera_avalon_adapter_downstream_pipeline\r
+ {\r
+ VERSION 7.080902\r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_adapter_downstream_pipeline";\r
+ }\r
+ }\r
+ COMPONENT altera_avalon_adapter_master_y\r
+ {\r
+ VERSION 7.080902\r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_adapter_master_y";\r
+ }\r
+ }\r
+ COMPONENT altera_avalon_adapter_slave_y\r
+ {\r
+ VERSION 7.080902\r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_adapter_slave_y";\r
+ }\r
+ }\r
+ COMPONENT altera_avalon_adapter_upstream_pipeline\r
+ {\r
+ VERSION 7.080902\r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_adapter_upstream_pipeline";\r
+ }\r
+ }\r
+ COMPONENT altera_avalon_adapter_waitrequest_pipeline\r
+ {\r
+ VERSION 7.080902\r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_adapter_waitrequest_pipeline";\r
+ }\r
+ }\r
+ COMPONENT altera_avalon_asmi\r
+ {\r
+ VERSION 7.080902\r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_asmi";\r
+ }\r
+ }\r
+ COMPONENT altera_avalon_burst_adapter\r
+ {\r
+ VERSION 7.080902\r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_burst_adapter";\r
+ }\r
+ }\r
+ COMPONENT altera_avalon_cf\r
+ {\r
+ VERSION 7.080902\r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_cf";\r
+ }\r
+ }\r
+ COMPONENT altera_avalon_cfi_flash\r
+ {\r
+ VERSION 7.080902\r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_cfi_flash";\r
+ }\r
+ }\r
+ COMPONENT altera_avalon_clock_adapter\r
+ {\r
+ VERSION 7.080902\r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_clock_adapter";\r
+ }\r
+ }\r
+ COMPONENT altera_avalon_clock_crossing\r
+ {\r
+ VERSION 7.080902\r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_clock_crossing";\r
+ }\r
+ }\r
+ COMPONENT altera_avalon_cs8900\r
+ {\r
+ VERSION 7.080902\r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_cs8900";\r
+ }\r
+ }\r
+ COMPONENT altera_avalon_cy7c1380_ssram\r
+ {\r
+ VERSION 7.080902\r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_cy7c1380_ssram";\r
+ }\r
+ }\r
+ COMPONENT altera_avalon_dma\r
+ {\r
+ VERSION 7.080902\r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_dma";\r
+ }\r
+ }\r
+ COMPONENT altera_avalon_endian_adapter\r
+ {\r
+ VERSION 7.080902\r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_endian_adapter";\r
+ }\r
+ }\r
+ COMPONENT altera_avalon_epcs_flash_controller\r
+ {\r
+ VERSION 7.080902\r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_epcs_flash_controller";\r
+ }\r
+ }\r
+ COMPONENT altera_avalon_fifo\r
+ {\r
+ VERSION 7.080902\r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_fifo";\r
+ }\r
+ }\r
+ COMPONENT altera_avalon_jtag_uart\r
+ {\r
+ VERSION 7.080902\r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_jtag_uart";\r
+ }\r
+ }\r
+ COMPONENT altera_avalon_lan91c111\r
+ {\r
+ VERSION 7.080902\r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_lan91c111";\r
+ }\r
+ }\r
+ COMPONENT altera_avalon_lcd_16207\r
+ {\r
+ VERSION 7.080902\r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_lcd_16207";\r
+ }\r
+ }\r
+ COMPONENT altera_avalon_mailbox\r
+ {\r
+ VERSION 7.080902\r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_mailbox";\r
+ }\r
+ }\r
+ COMPONENT altera_avalon_mutex\r
+ {\r
+ VERSION 7.080902\r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_mutex";\r
+ }\r
+ }\r
+ COMPONENT altera_avalon_new_sdram_controller\r
+ {\r
+ VERSION 7.080902\r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_new_sdram_controller";\r
+ }\r
+ }\r
+ COMPONENT altera_avalon_onchip_memory\r
+ {\r
+ VERSION 7.080902\r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_onchip_memory";\r
+ }\r
+ }\r
+ COMPONENT altera_avalon_onchip_memory2\r
+ {\r
+ VERSION 7.080902\r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2";\r
+ }\r
+ }\r
+ COMPONENT altera_avalon_performance_counter\r
+ {\r
+ VERSION 7.080902\r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_performance_counter";\r
+ }\r
+ }\r
+ COMPONENT altera_avalon_pio\r
+ {\r
+ VERSION 7.080902\r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_pio";\r
+ }\r
+ }\r
+ COMPONENT altera_avalon_pipeline_bridge\r
+ {\r
+ VERSION 7.080902\r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_pipeline_bridge";\r
+ }\r
+ }\r
+ COMPONENT altera_avalon_pll\r
+ {\r
+ VERSION 7.080902\r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_pll";\r
+ }\r
+ }\r
+ COMPONENT altera_avalon_sgdma\r
+ {\r
+ VERSION 7.080902\r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_sgdma";\r
+ }\r
+ }\r
+ COMPONENT altera_avalon_spi\r
+ {\r
+ VERSION 7.080902\r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_spi";\r
+ }\r
+ }\r
+ COMPONENT altera_avalon_sysid\r
+ {\r
+ VERSION 7.080902\r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_sysid";\r
+ }\r
+ }\r
+ COMPONENT altera_avalon_timer\r
+ {\r
+ VERSION 7.080902\r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_timer";\r
+ }\r
+ }\r
+ COMPONENT altera_avalon_tri_state_bridge\r
+ {\r
+ VERSION 7.080902\r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_tri_state_bridge";\r
+ }\r
+ }\r
+ COMPONENT altera_avalon_uart\r
+ {\r
+ VERSION 7.080902\r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_uart";\r
+ }\r
+ }\r
+ COMPONENT altera_avalon_user_defined_interface\r
+ {\r
+ VERSION 7.080902\r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_user_defined_interface";\r
+ }\r
+ }\r
+ COMPONENT altera_sopc_builder\r
+ {\r
+ VERSION 7.080902\r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_sopc_builder";\r
+ }\r
+ }\r
+ COMPONENT amd_avalon_am29lv065d_flash\r
+ {\r
+ VERSION 7.080902\r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/amd_avalon_am29lv065d_flash";\r
+ }\r
+ }\r
+ COMPONENT amd_avalon_am29lv128m_flash\r
+ {\r
+ VERSION 7.080902\r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/amd_avalon_am29lv128m_flash";\r
+ }\r
+ }\r
+ COMPONENT no_legacy_module\r
+ {\r
+ VERSION 7.080902\r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/no_legacy_module";\r
+ }\r
+ }\r
+ COMPONENT triple_speed_ethernet\r
+ {\r
+ VERSION 9.0\r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/triple_speed_ethernet/lib/sopc_builder/altera_triple_speed_ethernet";\r
+ }\r
+ }\r
+ COMPONENT ddr2_sdram_component\r
+ {\r
+ VERSION 9.0\r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/ddr_ddr2_sdram/lib/sopc_builder/ddr2_sdram_component";\r
+ }\r
+ }\r
+ COMPONENT ddr_sdram_component\r
+ {\r
+ VERSION 9.0\r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/ddr_ddr2_sdram/lib/sopc_builder/ddr_sdram_component";\r
+ }\r
+ }\r
+ COMPONENT ddr3_high_perf\r
+ {\r
+ VERSION 8.1\r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/ddr3_high_perf/lib/sopc_builder/ddr3_high_perf";\r
+ }\r
+ }\r
+ COMPONENT ddr2_high_perf\r
+ {\r
+ VERSION 8.1\r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/ddr2_high_perf/lib/sopc_builder/ddr2_high_perf";\r
+ }\r
+ }\r
+ COMPONENT ddr_high_perf\r
+ {\r
+ VERSION 8.1\r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/ddr_high_perf/lib/sopc_builder/ddr_high_perf";\r
+ }\r
+ }\r
+ COMPONENT altera_avalon_pcie_compiler\r
+ {\r
+ VERSION 9.0\r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/pci_express_compiler/lib/sopc_builder/altera_avalon_pcie_compiler";\r
+ }\r
+ }\r
+ COMPONENT altera_avalon_pcie_compiler_adapter\r
+ {\r
+ VERSION 9.0\r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/pci_express_compiler/lib/sopc_builder/altera_avalon_pcie_compiler_adapter";\r
+ }\r
+ }\r
+ COMPONENT altera_avalon_pci_compiler\r
+ {\r
+ VERSION 9.0\r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/pci_compiler/lib/sopc_builder/altera_avalon_pci_compiler";\r
+ }\r
+ }\r
+ COMPONENT altera_avalon_pci_compiler_adapter\r
+ {\r
+ VERSION 9.0\r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/pci_compiler/lib/sopc_builder/altera_avalon_pci_compiler_adapter";\r
+ }\r
+ }\r
+}\r
--- /dev/null
+PACKAGE install2 \r
+{\r
+ # This file informs the Nios II IDE of non-legacy component paths.\r
+ # Generated 2009.08.05.16:22:08\r
+ COMPONENT alt_vip_clip \r
+ {\r
+ VERSION 9.0 \r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/clipper/lib";\r
+ }\r
+ }\r
+ COMPONENT alt_vip_cpr \r
+ {\r
+ VERSION 9.0 \r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/color_plane_sequencer/lib";\r
+ }\r
+ }\r
+ COMPONENT alt_vip_crs \r
+ {\r
+ VERSION 9.0 \r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/chroma_resampler/lib";\r
+ }\r
+ }\r
+ COMPONENT alt_vip_csc \r
+ {\r
+ VERSION 9.0 \r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/csc/lib";\r
+ }\r
+ }\r
+ COMPONENT alt_vip_dil \r
+ {\r
+ VERSION 9.0 \r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/deinterlacer/lib";\r
+ }\r
+ }\r
+ COMPONENT alt_vip_fir \r
+ {\r
+ VERSION 9.0 \r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/fir_filter_2d/lib";\r
+ }\r
+ }\r
+ COMPONENT alt_vip_gam \r
+ {\r
+ VERSION 9.0 \r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/gamma_corrector/lib";\r
+ }\r
+ }\r
+ COMPONENT alt_vip_lbc \r
+ {\r
+ VERSION 9.0 \r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/line_buffer_compiler/lib";\r
+ }\r
+ }\r
+ COMPONENT alt_vip_med \r
+ {\r
+ VERSION 9.0 \r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/median_filter_2d/lib";\r
+ }\r
+ }\r
+ COMPONENT alt_vip_mix \r
+ {\r
+ VERSION 9.0 \r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/alpha_blending_mixer/lib";\r
+ }\r
+ }\r
+ COMPONENT alt_vip_scl \r
+ {\r
+ VERSION 9.0 \r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/scaler/lib";\r
+ }\r
+ }\r
+ COMPONENT alt_vip_tpg \r
+ {\r
+ VERSION 9.0 \r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/test_pattern_generator/lib";\r
+ }\r
+ }\r
+ COMPONENT alt_vip_vfb \r
+ {\r
+ VERSION 9.0 \r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/frame_buffer/lib";\r
+ }\r
+ }\r
+ COMPONENT altera_avalon_dc_fifo \r
+ {\r
+ VERSION 9.0 \r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_dc_fifo";\r
+ }\r
+ }\r
+ COMPONENT altera_avalon_half_rate_bridge \r
+ {\r
+ VERSION 9.0 \r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_half_rate_bridge";\r
+ }\r
+ }\r
+ COMPONENT altera_avalon_multi_channel_shared_fifo \r
+ {\r
+ VERSION 9.0 \r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_multi_channel_shared_fifo";\r
+ }\r
+ }\r
+ COMPONENT altera_avalon_packets_to_master \r
+ {\r
+ VERSION 9.0 \r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_packets_to_master";\r
+ }\r
+ }\r
+ COMPONENT altera_avalon_pixel_converter \r
+ {\r
+ VERSION 9.0 \r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_pixel_converter";\r
+ }\r
+ }\r
+ COMPONENT altera_avalon_remote_update_cycloneiii \r
+ {\r
+ VERSION 9.0 \r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_remote_update_cycloneiii";\r
+ }\r
+ }\r
+ COMPONENT altera_avalon_round_robin_scheduler \r
+ {\r
+ VERSION 9.0 \r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_round_robin_scheduler";\r
+ }\r
+ }\r
+ COMPONENT altera_avalon_sc_fifo \r
+ {\r
+ VERSION 9.0 \r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_sc_fifo";\r
+ }\r
+ }\r
+ COMPONENT altera_avalon_st_bytes_to_packets \r
+ {\r
+ VERSION 9.0 \r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_st_bytes_to_packets";\r
+ }\r
+ }\r
+ COMPONENT altera_avalon_st_idle_inserter \r
+ {\r
+ VERSION 9.0 \r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_st_idle_inserter";\r
+ }\r
+ }\r
+ COMPONENT altera_avalon_st_idle_remover \r
+ {\r
+ VERSION 9.0 \r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_st_idle_remover";\r
+ }\r
+ }\r
+ COMPONENT altera_avalon_st_packets_to_bytes \r
+ {\r
+ VERSION 9.0 \r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_st_packets_to_bytes";\r
+ }\r
+ }\r
+ COMPONENT altera_avalon_video_sync_generator \r
+ {\r
+ VERSION 9.0 \r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_video_sync_generator";\r
+ }\r
+ }\r
+ COMPONENT altera_jtag_avalon_master \r
+ {\r
+ VERSION 9.0 \r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_jtag_avalon_master";\r
+ }\r
+ }\r
+ COMPONENT altera_jtag_dc_streaming \r
+ {\r
+ VERSION 9.0 \r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_jtag_phy";\r
+ }\r
+ }\r
+ COMPONENT altpll \r
+ {\r
+ VERSION 9.0 \r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_altpll";\r
+ }\r
+ }\r
+ COMPONENT avalon_mm_master_bfm \r
+ {\r
+ VERSION 9.0 \r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/verification/avalon_mm_bfm/avalon_mm_master_bfm";\r
+ }\r
+ }\r
+ COMPONENT avalon_mm_slave_bfm \r
+ {\r
+ VERSION 9.0 \r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/verification/avalon_mm_bfm/avalon_mm_slave_bfm";\r
+ }\r
+ }\r
+ COMPONENT pci_lite \r
+ {\r
+ VERSION 9.0 \r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_pci_lite";\r
+ }\r
+ }\r
+ COMPONENT sls_avalon_usb20hr \r
+ {\r
+ VERSION 2.2 \r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/sls/usb20hr_ocp_eval_pack/hardware/component";\r
+ }\r
+ }\r
+ COMPONENT spi_slave_to_avalon_mm_master_bridge \r
+ {\r
+ VERSION 9.0 \r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_spislave_to_avalonmm_bridge";\r
+ }\r
+ }\r
+ COMPONENT spislave \r
+ {\r
+ VERSION 9.0 \r
+ {\r
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_spi_phy_slave";\r
+ }\r
+ }\r
+}\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>\r
+<?fileVersion 3.1.0?>\r
+\r
+<ManagedProjectBuildInfo>\r
+<project id="RTOSDemo.nios2.exec.1581235184" name="Nios II Executable" projectType="nios2.exec">\r
+<configuration artifactExtension="elf" artifactName="RTOSDemo" cleanCommand="rm -rf" description="" errorParsers="org.eclipse.cdt.core.MakeErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GASErrorParser" id="nios2.exec.debug.1446010332" name="Debug" parent="nios2.exec.debug">\r
+<toolChain id="com.altera.nj.ui.exe.Debug.241068812" name="com.altera.nj.ui.exe.Debug" superClass="com.altera.nj.ui.exe.Debug">\r
+<tool id="com.altera.nj.ui.tool.compiler.exe.debug.238740427" name="Nios II Compiler" superClass="com.altera.nj.ui.tool.compiler.exe.debug">\r
+<option id="nios2.compiler.general.include.paths.1954487624" superClass="nios2.compiler.general.include.paths" valueType="includePath">\r
+<listOptionValue builtIn="false" value=""${workspace_loc:/RTOSDemo/FreeRTOS/portable/GCC/Nios2}""/>\r
+<listOptionValue builtIn="false" value=""${workspace_loc:/RTOSDemo/Common_Demo_Tasks/include}""/>\r
+<listOptionValue builtIn="false" value=""${workspace_loc:/RTOSDemo/FreeRTOS/include}""/>\r
+<listOptionValue builtIn="false" value=""${workspace_loc:/RTOSDemo}""/>\r
+</option>\r
+</tool>\r
+<tool id="com.altera.nj.ui.tool.linker.exe.debug.2054232498" name="Linker" superClass="com.altera.nj.ui.tool.linker.exe.debug"/>\r
+<macros expandEnvironmentMacros="true"/>\r
+</toolChain>\r
+</configuration>\r
+<configuration artifactExtension="elf" artifactName="RTOSDemo" cleanCommand="rm -rf" description="" errorParsers="org.eclipse.cdt.core.MakeErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GASErrorParser" id="nios2.exec.release.654306637" name="Release" parent="nios2.exec.release">\r
+<toolChain id="com.altera.nj.ui.exe.Release.506996366" name="com.altera.nj.ui.exe.Release" superClass="com.altera.nj.ui.exe.Release">\r
+<tool id="com.altera.nj.ui.tool.compiler.exe.release.1487128363" name="Nios II Compiler" superClass="com.altera.nj.ui.tool.compiler.exe.release"/>\r
+<tool id="com.altera.nj.ui.tool.linker.exe.release.733767895" name="Linker" superClass="com.altera.nj.ui.tool.linker.exe.release"/>\r
+</toolChain>\r
+</configuration>\r
+<macros/>\r
+</project>\r
+</ManagedProjectBuildInfo>\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>\r
+<?eclipse-cdt version="2.0"?>\r
+\r
+<cdtproject id="org.eclipse.cdt.managedbuilder.core.managedMake">\r
+<extension id="org.eclipse.cdt.managedbuilder.core.ManagedBuildManager" point="org.eclipse.cdt.core.ScannerInfoProvider"/>\r
+<extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser">\r
+<attribute key="addr2line" value="addr2line"/>\r
+<attribute key="c++filt" value="c++filt"/>\r
+</extension>\r
+<extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser">\r
+<attribute key="addr2line" value="addr2line"/>\r
+<attribute key="c++filt" value="c++filt"/>\r
+</extension>\r
+<data>\r
+<item id="org.eclipse.cdt.core.pathentry">\r
+<pathentry kind="src" path=""/>\r
+<pathentry kind="out" path=""/>\r
+<pathentry kind="con" path="org.eclipse.cdt.managedbuilder.MANAGED_CONTAINER"/>\r
+<pathentry kind="con" path="org.eclipse.cdt.make.core.DISCOVERED_SCANNER_INFO"/>\r
+</item>\r
+<item id="scannerConfiguration">\r
+<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile"/>\r
+<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">\r
+<buildOutputProvider>\r
+<openAction enabled="true" filePath=""/>\r
+<parser enabled="true"/>\r
+</buildOutputProvider>\r
+<scannerInfoProvider id="specsFile">\r
+<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>\r
+<parser enabled="true"/>\r
+</scannerInfoProvider>\r
+</profile>\r
+<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">\r
+<buildOutputProvider>\r
+<openAction enabled="false" filePath=""/>\r
+<parser enabled="true"/>\r
+</buildOutputProvider>\r
+<scannerInfoProvider id="makefileGenerator">\r
+<runAction arguments="-f ${project_name}_scd.mk" command="make" useDefault="true"/>\r
+<parser enabled="false"/>\r
+</scannerInfoProvider>\r
+</profile>\r
+<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">\r
+<buildOutputProvider>\r
+<openAction enabled="false" filePath=""/>\r
+<parser enabled="true"/>\r
+</buildOutputProvider>\r
+<scannerInfoProvider id="specsFile">\r
+<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>\r
+<parser enabled="false"/>\r
+</scannerInfoProvider>\r
+</profile>\r
+<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">\r
+<buildOutputProvider>\r
+<openAction enabled="false" filePath=""/>\r
+<parser enabled="true"/>\r
+</buildOutputProvider>\r
+<scannerInfoProvider id="specsFile">\r
+<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>\r
+<parser enabled="false"/>\r
+</scannerInfoProvider>\r
+</profile>\r
+</item>\r
+</data>\r
+</cdtproject>\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
+<projectDescription>\r
+ <name>RTOSDemo</name>\r
+ <comment></comment>\r
+ <projects>\r
+ <project>RTOSDemo_syslib</project>\r
+ </projects>\r
+ <buildSpec>\r
+ <buildCommand>\r
+ <name>org.eclipse.cdt.make.core.makeBuilder</name>\r
+ <triggers>clean,full,incremental,</triggers>\r
+ <arguments>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.enableCleanBuild</key>\r
+ <value>false</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.append_environment</key>\r
+ <value>true</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.stopOnError</key>\r
+ <value>false</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.enabledIncrementalBuild</key>\r
+ <value>false</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.build.command</key>\r
+ <value>make</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.build.target.inc</key>\r
+ <value>all</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.build.arguments</key>\r
+ <value></value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>\r
+ <value>true</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.environment</key>\r
+ <value></value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.enableFullBuild</key>\r
+ <value>false</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.build.target.auto</key>\r
+ <value>all</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.enableAutoBuild</key>\r
+ <value>false</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.build.target.clean</key>\r
+ <value>clean</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.core.errorOutputParser</key>\r
+ <value>org.eclipse.cdt.core.MakeErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GASErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.VCErrorParser;</value>\r
+ </dictionary>\r
+ </arguments>\r
+ </buildCommand>\r
+ <buildCommand>\r
+ <name>com.altera.ide.core.alterabuilder</name>\r
+ <arguments>\r
+ </arguments>\r
+ </buildCommand>\r
+ <buildCommand>\r
+ <name>org.eclipse.cdt.make.core.ScannerConfigBuilder</name>\r
+ <arguments>\r
+ </arguments>\r
+ </buildCommand>\r
+ </buildSpec>\r
+ <natures>\r
+ <nature>org.eclipse.cdt.core.cnature</nature>\r
+ <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>\r
+ <nature>com.altera.ide.core.AlteraNios2Nature</nature>\r
+ <nature>com.altera.ide.core.AlteraApplicationNature</nature>\r
+ <nature>org.eclipse.cdt.make.core.makeNature</nature>\r
+ <nature>org.eclipse.cdt.make.core.ScannerConfigNature</nature>\r
+ </natures>\r
+</projectDescription>\r
--- /dev/null
+#Tue Aug 04 21:28:00 BST 2009\r
+eclipse.preferences.version=1\r
+indexerId=org.eclipse.cdt.core.fastIndexer\r
--- /dev/null
+#Tue Aug 04 21:27:58 BST 2009\r
+eclipse.preferences.version=1\r
+nios2.exec.debug.746546544/internalBuilder/enabled=false\r
+nios2.exec.debug.746546544/internalBuilder/ignoreErr=true\r
+nios2.exec.release.1419815778/internalBuilder/enabled=false\r
+nios2.exec.release.1419815778/internalBuilder/ignoreErr=true\r
--- /dev/null
+#Tue Aug 04 21:40:26 BST 2009\r
+eclipse.preferences.version=1\r
+org.eclipse.ltk.core.refactoring.enable.project.refactoring.history=false\r
--- /dev/null
+/*\r
+ FreeRTOS V5.4.1 - Copyright (C) 2009 Real Time Engineers Ltd.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under \r
+ the terms of the GNU General Public License (version 2) as published by the \r
+ Free Software Foundation and modified by the FreeRTOS exception.\r
+ **NOTE** The exception to the GPL is included to allow you to distribute a\r
+ combined work that includes FreeRTOS without being obliged to provide the \r
+ source code for proprietary components outside of the FreeRTOS kernel. \r
+ Alternative commercial license and support terms are also available upon \r
+ request. See the licensing section of http://www.FreeRTOS.org for full \r
+ license details.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT\r
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details.\r
+\r
+ You should have received a copy of the GNU General Public License along\r
+ with FreeRTOS; if not, write to the Free Software Foundation, Inc., 59\r
+ Temple Place, Suite 330, Boston, MA 02111-1307 USA.\r
+\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * Looking for a quick start? Then check out the FreeRTOS eBook! *\r
+ * See http://www.FreeRTOS.org/Documentation for details *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ Please ensure to read the configuration and relevant port sections of the\r
+ online documentation.\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+#include "system.h"\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. \r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 0\r
+#define configUSE_TICK_HOOK 0\r
+#define configTICK_RATE_HZ ( ( portTickType ) 1000 )\r
+#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) SYS_CLK_FREQ ) \r
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )\r
+#define configMINIMAL_STACK_SIZE ( 1024 )\r
+#define configISR_STACK_SIZE configMINIMAL_STACK_SIZE\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) 8388608 )\r
+#define configMAX_TASK_NAME_LEN ( 8 )\r
+#define configUSE_TRACE_FACILITY 0\r
+#define configUSE_16_BIT_TICKS 0\r
+#define configIDLE_SHOULD_YIELD 0\r
+#define configUSE_MUTEXES 1\r
+#define configUSE_RECURSIVE_MUTEXES 1\r
+#define configUSE_COUNTING_SEMAPHORES 1\r
+#define configCHECK_FOR_STACK_OVERFLOW 2\r
+#define configQUEUE_REGISTRY_SIZE 0\r
+\r
+/* Co-routine definitions. */\r
+#define configUSE_CO_ROUTINES 0\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 1\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskCleanUpResources 0\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+#define INCLUDE_uxTaskGetStackHighWaterMark 1\r
+\r
+/* The priority at which the tick interrupt runs. This should probably be\r
+kept at 1. */\r
+#define configKERNEL_INTERRUPT_PRIORITY 0x01\r
+\r
+/* The maximum interrupt priority from which FreeRTOS.org API functions can\r
+be called. Only API functions that end in ...FromISR() can be used within\r
+interrupts. */\r
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 0x03\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
--- /dev/null
+/*\r
+ FreeRTOS V5.4.1 - Copyright (C) 2009 Real Time Engineers Ltd.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under \r
+ the terms of the GNU General Public License (version 2) as published by the \r
+ Free Software Foundation and modified by the FreeRTOS exception.\r
+ **NOTE** The exception to the GPL is included to allow you to distribute a\r
+ combined work that includes FreeRTOS without being obliged to provide the \r
+ source code for proprietary components outside of the FreeRTOS kernel. \r
+ Alternative commercial license and support terms are also available upon \r
+ request. See the licensing section of http://www.FreeRTOS.org for full \r
+ license details.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT\r
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details.\r
+\r
+ You should have received a copy of the GNU General Public License along\r
+ with FreeRTOS; if not, write to the Free Software Foundation, Inc., 59\r
+ Temple Place, Suite 330, Boston, MA 02111-1307 USA.\r
+\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * Looking for a quick start? Then check out the FreeRTOS eBook! *\r
+ * See http://www.FreeRTOS.org/Documentation for details *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ Please ensure to read the configuration and relevant port sections of the\r
+ online documentation.\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+/*-----------------------------------------------------------\r
+ * Simple parallel port IO routines.\r
+ *-----------------------------------------------------------*/\r
+\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+\r
+/* Demo app includes. */\r
+#include "system.h"\r
+#include "altera_avalon_pio_regs.h"\r
+#include "partest.h"\r
+\r
+/*---------------------------------------------------------------------------*/\r
+\r
+#define partstNUM_LEDS ( 8 )\r
+\r
+/*---------------------------------------------------------------------------*/\r
+\r
+static unsigned portLONG ulLedStates;\r
+\r
+/*---------------------------------------------------------------------------*/\r
+\r
+void vParTestInitialise( void )\r
+{\r
+ IOWR_ALTERA_AVALON_PIO_DIRECTION( LED_PIO_BASE, ALTERA_AVALON_PIO_DIRECTION_OUTPUT );\r
+ ulLedStates = 0; \r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )\r
+{\r
+ if( uxLED < partstNUM_LEDS )\r
+ {\r
+ taskENTER_CRITICAL();\r
+ {\r
+ if ( xValue > 0 )\r
+ {\r
+ ulLedStates |= 1 << uxLED;\r
+ }\r
+ else\r
+ {\r
+ ulLedStates &= ~( 1 << uxLED );\r
+ }\r
+ IOWR_ALTERA_AVALON_PIO_DATA( LED_PIO_BASE, ulLedStates );\r
+ }\r
+ taskEXIT_CRITICAL();\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestToggleLED( unsigned portBASE_TYPE uxLED )\r
+{\r
+ if( uxLED < partstNUM_LEDS )\r
+ {\r
+ taskENTER_CRITICAL();\r
+ {\r
+ vParTestSetLED( uxLED, !( ulLedStates & ( 1 << uxLED ) ) );\r
+ } \r
+ taskEXIT_CRITICAL();\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>\r
+<stf>\r
+ <project sdk="RTOSDemo_syslib" target="Nios II Application">\r
+ </project>\r
+</stf>\r
--- /dev/null
+/*\r
+ FreeRTOS V5.4.1 - Copyright (C) 2009 Real Time Engineers Ltd.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under \r
+ the terms of the GNU General Public License (version 2) as published by the \r
+ Free Software Foundation and modified by the FreeRTOS exception.\r
+ **NOTE** The exception to the GPL is included to allow you to distribute a\r
+ combined work that includes FreeRTOS without being obliged to provide the \r
+ source code for proprietary components outside of the FreeRTOS kernel. \r
+ Alternative commercial license and support terms are also available upon \r
+ request. See the licensing section of http://www.FreeRTOS.org for full \r
+ license details.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT\r
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details.\r
+\r
+ You should have received a copy of the GNU General Public License along\r
+ with FreeRTOS; if not, write to the Free Software Foundation, Inc., 59\r
+ Temple Place, Suite 330, Boston, MA 02111-1307 USA.\r
+\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * Looking for a quick start? Then check out the FreeRTOS eBook! *\r
+ * See http://www.FreeRTOS.org/Documentation for details *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ Please ensure to read the configuration and relevant port sections of the\r
+ online documentation.\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+/*\r
+ * Creates all the demo application tasks, then starts the scheduler.\r
+ * In addition to the standard demo tasks, the following tasks and tests are\r
+ * defined and/or created within this file:\r
+ *\r
+ * "Check" task - This only executes every five seconds but has the highest\r
+ * priority so is guaranteed to get processor time. Its main function is to \r
+ * check that all the standard demo tasks are still operational. The check\r
+ * task will write an error message to the console should an error be detected\r
+ * within any of the demo tasks. The check task also toggles the LED defined\r
+ * by mainCHECK_LED every 5 seconds while the system is error free, with the\r
+ * toggle rate increasing to every 500ms should an error occur.\r
+ * \r
+ * "Reg test" tasks - These fill the registers with known values, then check\r
+ * that each register still contains its expected value. Each task uses\r
+ * different values. The tasks run with very low priority so get preempted very\r
+ * frequently. A register containing an unexpected value is indicative of an\r
+ * error in the context switching mechanism.\r
+ *\r
+ * See the online documentation for this demo for more information on interrupt\r
+ * usage.\r
+ */\r
+\r
+/* Standard includes. */\r
+#include <stddef.h>\r
+#include <stdio.h>\r
+#include <string.h>\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "queue.h"\r
+\r
+/* Demo application includes. */\r
+#include "partest.h"\r
+#include "flash.h"\r
+#include "blocktim.h"\r
+#include "semtest.h"\r
+#include "serial.h"\r
+#include "comtest.h"\r
+#include "GenQTest.h"\r
+#include "QPeek.h"\r
+#include "integer.h"\r
+#include "PollQ.h"\r
+#include "BlockQ.h"\r
+#include "dynamic.h"\r
+#include "countsem.h"\r
+#include "recmutex.h"\r
+#include "death.h"\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The rate at which the LED controlled by the 'check' task will toggle when no\r
+errors have been detected. */\r
+#define mainNO_ERROR_PERIOD ( 5000 )\r
+\r
+/* The rate at which the LED controlled by the 'check' task will toggle when an\r
+error has been detected. */\r
+#define mainERROR_PERIOD ( 500 )\r
+\r
+/* The LED toggled by the Check task. */\r
+#define mainCHECK_LED ( 7 )\r
+\r
+/* The first LED used by the ComTest tasks. One LED toggles each time a \r
+character is transmitted, and one each time a character is received and\r
+verified as being the expected character. */\r
+#define mainCOMTEST_LED ( 4 )\r
+\r
+/* Priority definitions for the tasks in the demo application. */\r
+#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )\r
+#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 )\r
+#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainQUEUE_BLOCK_PRIORITY ( tskIDLE_PRIORITY + 3 )\r
+#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainSEMAPHORE_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+#define mainGENERIC_QUEUE_PRIORITY ( tskIDLE_PRIORITY )\r
+#define mainREG_TEST_PRIORITY ( tskIDLE_PRIORITY )\r
+\r
+/* Misc. */\r
+#define mainDONT_WAIT ( 0 )\r
+\r
+/* The parameters passed to the reg test tasks. This is just done to check\r
+the parameter passing mechanism is working correctly. */\r
+#define mainREG_TEST_1_PARAMETER ( ( void * ) 0x12345678 )\r
+#define mainREG_TEST_2_PARAMETER ( ( void * ) 0x87654321 )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Setup the processor ready for the demo.\r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+/*\r
+ * Execute all of the check functions to ensure the tests haven't failed.\r
+ */ \r
+static void prvCheckTask( void *pvParameters );\r
+\r
+/*\r
+ * The register test (or RegTest) tasks as described at the top of this file.\r
+ */\r
+static void prvFirstRegTestTask( void *pvParameters );\r
+static void prvSecondRegTestTask( void *pvParameters );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Counters that are incremented on each iteration of the RegTest tasks\r
+so long as no errors have been detected. */\r
+volatile unsigned long ulRegTest1Counter = 0UL, ulRegTest2Counter = 0UL;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Create the demo tasks then start the scheduler.\r
+ */\r
+int main( void )\r
+{\r
+ /* Configure any hardware required for this demo. */\r
+ prvSetupHardware();\r
+ \r
+ /* Create all the other standard demo tasks. These serve no purpose other\r
+ than to test the port and demonstrate the use of the FreeRTOS API. */\r
+ vStartLEDFlashTasks( tskIDLE_PRIORITY );\r
+ vStartIntegerMathTasks( mainGENERIC_QUEUE_PRIORITY );\r
+ vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );\r
+ vStartBlockingQueueTasks( mainQUEUE_BLOCK_PRIORITY );\r
+ vCreateBlockTimeTasks();\r
+ vStartSemaphoreTasks( mainSEMAPHORE_TASK_PRIORITY );\r
+ vStartDynamicPriorityTasks();\r
+ vStartQueuePeekTasks();\r
+ vStartGenericQueueTasks( mainGENERIC_QUEUE_PRIORITY );\r
+ vStartCountingSemaphoreTasks();\r
+ vStartRecursiveMutexTasks();\r
+ vAltStartComTestTasks( mainCOM_TEST_PRIORITY, 0, mainCOMTEST_LED );\r
+ \r
+ /* prvCheckTask uses sprintf so requires more stack. */\r
+ xTaskCreate( prvCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );\r
+ \r
+ /* The RegTest tasks as described at the top of this file. */\r
+ xTaskCreate( prvFirstRegTestTask, "Rreg1", configMINIMAL_STACK_SIZE, mainREG_TEST_1_PARAMETER, mainREG_TEST_PRIORITY, NULL );\r
+ xTaskCreate( prvSecondRegTestTask, "Rreg2", configMINIMAL_STACK_SIZE, mainREG_TEST_2_PARAMETER, mainREG_TEST_PRIORITY, NULL );\r
+\r
+ /* This task has to be created last as it keeps account of the number of tasks\r
+ it expects to see running. */\r
+ vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );\r
+\r
+ /* Finally start the scheduler. */\r
+ vTaskStartScheduler();\r
+ \r
+ /* Will only reach here if there is insufficient heap available to start\r
+ the scheduler. */\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupHardware( void )\r
+{\r
+ /* Setup the digital IO for the LED's. */\r
+ vParTestInitialise();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationStackOverflowHook( void )\r
+{\r
+ /* Look at pxCurrentTCB to see which task overflowed its stack. */\r
+ for( ;; )\r
+ {\r
+ asm( "break" );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void _general_exception_handler( unsigned portLONG ulCause, unsigned portLONG ulStatus )\r
+{\r
+ /* This overrides the definition provided by the kernel. Other exceptions \r
+ should be handled here. */\r
+ for( ;; )\r
+ {\r
+ asm( "break" );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvCheckTask( void *pvParameters )\r
+{\r
+portTickType xLastExecutionTime, ulTicksToWait = mainNO_ERROR_PERIOD;\r
+unsigned long ulLastRegTest1 = 0UL, ulLastRegTest2 = 0UL;\r
+const portCHAR * pcMessage;\r
+\r
+ /* Initialise the variable used to control our iteration rate prior to\r
+ its first use. */\r
+ xLastExecutionTime = xTaskGetTickCount();\r
+\r
+ for( ;; )\r
+ {\r
+ /* Wait until it is time to run the tests again. */\r
+ vTaskDelayUntil( &xLastExecutionTime, ulTicksToWait );\r
+ \r
+ /* Have any of the standard demo tasks detected an error in their \r
+ operation? */\r
+ if( xAreIntegerMathsTaskStillRunning() != pdTRUE )\r
+ {\r
+ ulTicksToWait = mainERROR_PERIOD;\r
+ pcMessage = "Error: Integer Maths.\n";\r
+ }\r
+ else if( xAreGenericQueueTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulTicksToWait = mainERROR_PERIOD;\r
+ pcMessage = "Error: GenQ.\n";\r
+ }\r
+ else if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ ulTicksToWait = mainERROR_PERIOD;\r
+ pcMessage = "Error: BlockQ.\n";\r
+ }\r
+ else if( xArePollingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ ulTicksToWait = mainERROR_PERIOD;\r
+ pcMessage = "Error: PollQ.\n";\r
+ }\r
+ else if( xAreQueuePeekTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulTicksToWait = mainERROR_PERIOD;\r
+ pcMessage = "Error: PeekQ.\n";\r
+ }\r
+ else if( xAreBlockTimeTestTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulTicksToWait = mainERROR_PERIOD;\r
+ pcMessage = "Error: Block Time.\n";\r
+ }\r
+ else if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulTicksToWait = mainERROR_PERIOD;\r
+ pcMessage = "Error: Semaphore Test.\n";\r
+ }\r
+ else if( xAreComTestTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulTicksToWait = mainERROR_PERIOD;\r
+ pcMessage = "Error: Comm Test.\n";\r
+ }\r
+ else if( xIsCreateTaskStillRunning() != pdTRUE )\r
+ {\r
+ ulTicksToWait = mainERROR_PERIOD;\r
+ pcMessage = "Error: Suicidal Tasks.\n";\r
+ }\r
+ else if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulTicksToWait = mainERROR_PERIOD;\r
+ pcMessage = "Error: Dynamic Priority.\n";\r
+ }\r
+ else if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulTicksToWait = mainERROR_PERIOD;\r
+ pcMessage = "Error: Count Semaphore.\n";\r
+ }\r
+ else if( xAreRecursiveMutexTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulTicksToWait = mainERROR_PERIOD;\r
+ pcMessage = "Error: Recursive Mutex.\n";\r
+ }\r
+ else if( ulLastRegTest1 == ulRegTest1Counter )\r
+ {\r
+ /* ulRegTest1Counter is no longer being incremented, indicating\r
+ that an error has been discovered in prvFirstRegTestTask(). */\r
+ ulTicksToWait = mainERROR_PERIOD;\r
+ pcMessage = "Error: Reg Test1.\n";\r
+ }\r
+ else if( ulLastRegTest2 == ulRegTest2Counter )\r
+ {\r
+ /* ulRegTest2Counter is no longer being incremented, indicating\r
+ that an error has been discovered in prvSecondRegTestTask(). */ \r
+ ulTicksToWait = mainERROR_PERIOD;\r
+ pcMessage = "Error: Reg Test2.\n";\r
+ }\r
+ else\r
+ {\r
+ pcMessage = NULL;\r
+ }\r
+ \r
+ /* Remember the counter values this time around so a counter failing\r
+ to be incremented correctly can be spotted. */\r
+ ulLastRegTest1 = ulRegTest1Counter;\r
+ ulLastRegTest2 = ulRegTest2Counter;\r
+ \r
+ /* Print out an error message if there is one. Mutual exclusion is \r
+ not used as this is the only task accessing stdout. */\r
+ if( pcMessage != NULL )\r
+ {\r
+ printf( pcMessage );\r
+ }\r
+ \r
+ /* Provide visual feedback of the system status. If the LED is toggled\r
+ every 5 seconds then no errors have been found. If the LED is toggled\r
+ every 500ms then at least one error has been found. */\r
+ vParTestToggleLED( mainCHECK_LED );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvFirstRegTestTask( void *pvParameters )\r
+{\r
+ /* Check the parameters are passed in as expected. */\r
+ if( pvParameters != mainREG_TEST_1_PARAMETER )\r
+ {\r
+ /* Don't execute any further so an error is recognised by the check \r
+ task. */\r
+ vTaskDelete( NULL );\r
+ }\r
+ \r
+ /* Fill registers with known values, then check that each register still\r
+ contains its expected value. An incorrect value is indicative of an error\r
+ in the context switching process. \r
+ \r
+ If no errors are found ulRegTest1Counter is incremented. The check task\r
+ will recognise an error if ulRegTest1Counter stops being incremented. \r
+ This task also performs a manual yield in the middle of its execution, just\r
+ to increase the test coverage. */\r
+ asm volatile (\r
+ " .extern ulRegTest1Counter \n" \\r
+ " \n" \\r
+ " addi r3, r0, 3 \n" \\r
+ " addi r4, r0, 4 \n" \\r
+ " addi r5, r0, 5 \n" \\r
+ " addi r6, r0, 6 \n" \\r
+ " addi r7, r0, 7 \n" \\r
+ " addi r8, r0, 8 \n" \\r
+ " addi r9, r0, 9 \n" \\r
+ " addi r10, r0, 10 \n" \\r
+ " addi r11, r0, 11 \n" \\r
+ " addi r12, r0, 12 \n" \\r
+ " addi r13, r0, 13 \n" \\r
+ " addi r14, r0, 14 \n" \\r
+ " addi r15, r0, 15 \n" \\r
+ " addi r16, r0, 16 \n" \\r
+ " addi r17, r0, 17 \n" \\r
+ " addi r18, r0, 18 \n" \\r
+ " addi r19, r0, 19 \n" \\r
+ " addi r20, r0, 20 \n" \\r
+ " addi r21, r0, 21 \n" \\r
+ " addi r22, r0, 22 \n" \\r
+ " addi r23, r0, 23 \n" \\r
+ " addi r28, r0, 28 \n" \\r
+ " addi r31, r0, 31 \n" \\r
+ "RegTest1: \n" \\r
+ " addi r2, r0, 0 \n" \\r
+ " trap \n" \\r
+ " bne r2, r0, RegTest1Error \n" \\r
+ " addi r2, r0, 3 \n" \\r
+ " bne r2, r3, RegTest1Error \n" \\r
+ " addi r2, r0, 4 \n" \\r
+ " bne r2, r4, RegTest1Error \n" \\r
+ " addi r2, r0, 5 \n" \\r
+ " bne r2, r5, RegTest1Error \n" \\r
+ " addi r2, r0, 6 \n" \\r
+ " bne r2, r6, RegTest1Error \n" \\r
+ " addi r2, r0, 7 \n" \\r
+ " bne r2, r7, RegTest1Error \n" \\r
+ " addi r2, r0, 8 \n" \\r
+ " bne r2, r8, RegTest1Error \n" \\r
+ " addi r2, r0, 9 \n" \\r
+ " bne r2, r9, RegTest1Error \n" \\r
+ " addi r2, r0, 10 \n" \\r
+ " bne r2, r10, RegTest1Error \n" \\r
+ " addi r2, r0, 11 \n" \\r
+ " bne r2, r11, RegTest1Error \n" \\r
+ " addi r2, r0, 12 \n" \\r
+ " bne r2, r12, RegTest1Error \n" \\r
+ " addi r2, r0, 13 \n" \\r
+ " bne r2, r13, RegTest1Error \n" \\r
+ " addi r2, r0, 14 \n" \\r
+ " bne r2, r14, RegTest1Error \n" \\r
+ " addi r2, r0, 15 \n" \\r
+ " bne r2, r15, RegTest1Error \n" \\r
+ " addi r2, r0, 16 \n" \\r
+ " bne r2, r16, RegTest1Error \n" \\r
+ " addi r2, r0, 17 \n" \\r
+ " bne r2, r17, RegTest1Error \n" \\r
+ " addi r2, r0, 18 \n" \\r
+ " bne r2, r18, RegTest1Error \n" \\r
+ " addi r2, r0, 19 \n" \\r
+ " bne r2, r19, RegTest1Error \n" \\r
+ " addi r2, r0, 20 \n" \\r
+ " bne r2, r20, RegTest1Error \n" \\r
+ " addi r2, r0, 21 \n" \\r
+ " bne r2, r21, RegTest1Error \n" \\r
+ " addi r2, r0, 22 \n" \\r
+ " bne r2, r22, RegTest1Error \n" \\r
+ " addi r2, r0, 23 \n" \\r
+ " bne r2, r23, RegTest1Error \n" \\r
+ " addi r2, r0, 28 \n" \\r
+ " bne r2, r28, RegTest1Error \n" \\r
+ " addi r2, r0, 31 \n" \\r
+ " bne r2, r31, RegTest1Error \n" \\r
+ " ldw r2, %gprel(ulRegTest1Counter)(gp) \n" \\r
+ " addi r2, r2, 1 \n" \\r
+ " stw r2, %gprel(ulRegTest1Counter)(gp) \n" \\r
+ " br RegTest1 \n" \\r
+ "RegTest1Error: \n" \\r
+ " br RegTest1Error \n"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSecondRegTestTask( void *pvParameters )\r
+{\r
+ /* Check the parameters are passed in as expected. */\r
+ if( pvParameters != mainREG_TEST_2_PARAMETER )\r
+ {\r
+ /* Don't execute any further so an error is recognised by the check \r
+ task. */\r
+ vTaskDelete( NULL );\r
+ }\r
+ \r
+ /* Fill registers with known values, then check that each register still\r
+ contains its expected value. An incorrect value is indicative of an error\r
+ in the context switching process. \r
+ \r
+ If no errors are found ulRegTest2Counter is incremented. The check task\r
+ will recognise an error if ulRegTest2Counter stops being incremented. */\r
+ asm volatile (\r
+ " .extern ulRegTest2Counter \n" \\r
+ " \n" \\r
+ " addi r3, r0, 3 \n" \\r
+ " addi r4, r0, 4 \n" \\r
+ " addi r5, r0, 5 \n" \\r
+ " addi r6, r0, 6 \n" \\r
+ " addi r7, r0, 7 \n" \\r
+ " addi r8, r0, 8 \n" \\r
+ " addi r9, r0, 9 \n" \\r
+ " addi r10, r0, 10 \n" \\r
+ " addi r11, r0, 11 \n" \\r
+ " addi r12, r0, 12 \n" \\r
+ " addi r13, r0, 13 \n" \\r
+ " addi r14, r0, 14 \n" \\r
+ " addi r15, r0, 15 \n" \\r
+ " addi r16, r0, 16 \n" \\r
+ " addi r17, r0, 17 \n" \\r
+ " addi r18, r0, 18 \n" \\r
+ " addi r19, r0, 19 \n" \\r
+ " addi r20, r0, 20 \n" \\r
+ " addi r21, r0, 21 \n" \\r
+ " addi r22, r0, 22 \n" \\r
+ " addi r23, r0, 23 \n" \\r
+ " addi r28, r0, 28 \n" \\r
+ " addi r31, r0, 31 \n" \\r
+ "RegTest2: \n" \\r
+ " addi r2, r0, 0 \n" \\r
+ " bne r2, r0, RegTest2Error \n" \\r
+ " addi r2, r0, 3 \n" \\r
+ " bne r2, r3, RegTest2Error \n" \\r
+ " addi r2, r0, 4 \n" \\r
+ " bne r2, r4, RegTest2Error \n" \\r
+ " addi r2, r0, 5 \n" \\r
+ " bne r2, r5, RegTest2Error \n" \\r
+ " addi r2, r0, 6 \n" \\r
+ " bne r2, r6, RegTest2Error \n" \\r
+ " addi r2, r0, 7 \n" \\r
+ " bne r2, r7, RegTest2Error \n" \\r
+ " addi r2, r0, 8 \n" \\r
+ " bne r2, r8, RegTest2Error \n" \\r
+ " addi r2, r0, 9 \n" \\r
+ " bne r2, r9, RegTest2Error \n" \\r
+ " addi r2, r0, 10 \n" \\r
+ " bne r2, r10, RegTest2Error \n" \\r
+ " addi r2, r0, 11 \n" \\r
+ " bne r2, r11, RegTest2Error \n" \\r
+ " addi r2, r0, 12 \n" \\r
+ " bne r2, r12, RegTest2Error \n" \\r
+ " addi r2, r0, 13 \n" \\r
+ " bne r2, r13, RegTest2Error \n" \\r
+ " addi r2, r0, 14 \n" \\r
+ " bne r2, r14, RegTest2Error \n" \\r
+ " addi r2, r0, 15 \n" \\r
+ " bne r2, r15, RegTest2Error \n" \\r
+ " addi r2, r0, 16 \n" \\r
+ " bne r2, r16, RegTest2Error \n" \\r
+ " addi r2, r0, 17 \n" \\r
+ " bne r2, r17, RegTest2Error \n" \\r
+ " addi r2, r0, 18 \n" \\r
+ " bne r2, r18, RegTest2Error \n" \\r
+ " addi r2, r0, 19 \n" \\r
+ " bne r2, r19, RegTest2Error \n" \\r
+ " addi r2, r0, 20 \n" \\r
+ " bne r2, r20, RegTest2Error \n" \\r
+ " addi r2, r0, 21 \n" \\r
+ " bne r2, r21, RegTest2Error \n" \\r
+ " addi r2, r0, 22 \n" \\r
+ " bne r2, r22, RegTest2Error \n" \\r
+ " addi r2, r0, 23 \n" \\r
+ " bne r2, r23, RegTest2Error \n" \\r
+ " addi r2, r0, 28 \n" \\r
+ " bne r2, r28, RegTest2Error \n" \\r
+ " addi r2, r0, 31 \n" \\r
+ " bne r2, r31, RegTest2Error \n" \\r
+ " ldw r2, %gprel(ulRegTest2Counter)(gp) \n" \\r
+ " addi r2, r2, 1 \n" \\r
+ " stw r2, %gprel(ulRegTest2Counter)(gp) \n" \\r
+ " br RegTest2 \n" \\r
+ "RegTest2Error: \n" \\r
+ " br RegTest2Error \n"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V5.4.1 - Copyright (C) 2009 Real Time Engineers Ltd.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under \r
+ the terms of the GNU General Public License (version 2) as published by the \r
+ Free Software Foundation and modified by the FreeRTOS exception.\r
+ **NOTE** The exception to the GPL is included to allow you to distribute a\r
+ combined work that includes FreeRTOS without being obliged to provide the \r
+ source code for proprietary components outside of the FreeRTOS kernel. \r
+ Alternative commercial license and support terms are also available upon \r
+ request. See the licensing section of http://www.FreeRTOS.org for full \r
+ license details.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT\r
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details.\r
+\r
+ You should have received a copy of the GNU General Public License along\r
+ with FreeRTOS; if not, write to the Free Software Foundation, Inc., 59\r
+ Temple Place, Suite 330, Boston, MA 02111-1307 USA.\r
+\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * Looking for a quick start? Then check out the FreeRTOS eBook! *\r
+ * See http://www.FreeRTOS.org/Documentation for details *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ Please ensure to read the configuration and relevant port sections of the\r
+ online documentation.\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+/* NOTE: This is just a test file and not intended to be a generic \r
+COM driver. */\r
+\r
+#include "altera_avalon_uart.h"\r
+#include "altera_avalon_uart_regs.h"\r
+#include "sys/alt_irq.h"\r
+\r
+#include "FreeRTOS.h"\r
+#include "queue.h"\r
+#include "system.h"\r
+#include "Serial.h"\r
+/*---------------------------------------------------------------------------*/\r
+\r
+#define serINVALID_QUEUE ( ( xQueueHandle ) 0 )\r
+#define serNO_BLOCK ( ( portTickType ) 0 )\r
+/*---------------------------------------------------------------------------*/\r
+\r
+static xQueueHandle xRxedChars; \r
+static xQueueHandle xCharsForTx; \r
+\r
+alt_u32 uartControl;\r
+/*---------------------------------------------------------------------------*/\r
+\r
+static void vUARTInterruptHandler( void* context, alt_u32 id );\r
+static void vUARTReceiveHandler( alt_u32 status );\r
+static void vUARTTransmitHandler( alt_u32 status );\r
+/*---------------------------------------------------------------------------*/\r
+\r
+xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )\r
+{\r
+ /* Create the queues used to hold Rx and Tx characters. */\r
+ xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );\r
+ xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );\r
+\r
+ /* If the queues were created correctly then setup the serial port hardware. */\r
+ if( ( xRxedChars != serINVALID_QUEUE ) && ( xCharsForTx != serINVALID_QUEUE ) )\r
+ {\r
+ portENTER_CRITICAL();\r
+ {\r
+ uartControl = ALTERA_AVALON_UART_CONTROL_RTS_MSK | ALTERA_AVALON_UART_CONTROL_RRDY_MSK | ALTERA_AVALON_UART_CONTROL_DCTS_MSK;\r
+ IOWR_ALTERA_AVALON_UART_CONTROL( UART_BASE, uartControl ); \r
+ \r
+ /* register the interrupt handler */\r
+ alt_irq_register ( UART_IRQ, NULL, vUARTInterruptHandler );\r
+ }\r
+ portEXIT_CRITICAL();\r
+ }\r
+ else\r
+ {\r
+ return ( xComPortHandle ) 0;\r
+ }\r
+ return ( xComPortHandle ) 1;\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+\r
+void vSerialClose( xComPortHandle xPort )\r
+{\r
+ /* Never used. */\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime )\r
+{\r
+ /* The port handle is not required as this driver only supports one port. */\r
+ ( void ) pxPort;\r
+\r
+\r
+ /* Get the next character from the buffer. Return false if no characters\r
+ are available, or arrive before xBlockTime expires. */\r
+ if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )\r
+ {\r
+ return pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ uartControl |= ALTERA_AVALON_UART_CONTROL_RRDY_MSK;\r
+ IOWR_ALTERA_AVALON_UART_CONTROL( UART_BASE, uartControl );\r
+ return pdFALSE;\r
+ }\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime )\r
+{\r
+signed portBASE_TYPE lReturn = pdPASS;\r
+\r
+ /* Place the character in the queue of characters to be transmitted. */\r
+ if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) == pdPASS )\r
+ {\r
+ /*Triggers an interrupt on every character or (down) when queue is full. */\r
+ uartControl |= ALTERA_AVALON_UART_CONTROL_TRDY_MSK; \r
+ IOWR_ALTERA_AVALON_UART_CONTROL( UART_BASE, uartControl );\r
+ lReturn = pdPASS;\r
+ }\r
+ else\r
+ { \r
+ lReturn = pdFAIL;\r
+ }\r
+ return lReturn;\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+\r
+void vSerialPutString( xComPortHandle pxPort, const signed portCHAR * const pcString, unsigned portSHORT usStringLength )\r
+{\r
+signed portCHAR *pxNext;\r
+\r
+ /* A couple of parameters that this port does not use. */\r
+ ( void ) usStringLength;\r
+ ( void ) pxPort;\r
+\r
+ /* NOTE: This implementation does not handle the queue being full as no block time is used! */\r
+\r
+ /* The port handle is not required as this driver only supports UART0. */\r
+ ( void ) pxPort;\r
+\r
+ /* Send each character in the string, one at a time. */\r
+ pxNext = ( signed portCHAR * ) pcString;\r
+ while( *pxNext )\r
+ {\r
+ xSerialPutChar( pxPort, *pxNext, serNO_BLOCK );\r
+ pxNext++;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vUARTInterruptHandler( void* context, alt_u32 id )\r
+{\r
+ alt_u32 status;\r
+\r
+ /* Read the status register in order to determine the cause of the \r
+ interrupt. */\r
+ status = IORD_ALTERA_AVALON_UART_STATUS( UART_BASE );\r
+ \r
+ /* Clear any error flags set at the device */\r
+ IOWR_ALTERA_AVALON_UART_STATUS( UART_BASE, 0 );\r
+ \r
+ /* process a read irq */\r
+ if ( status & ALTERA_AVALON_UART_STATUS_RRDY_MSK )\r
+ {\r
+ vUARTReceiveHandler( status );\r
+ }\r
+ \r
+ /* process a write irq */\r
+ if ( status & ( ALTERA_AVALON_UART_STATUS_TRDY_MSK ) )\r
+ {\r
+ vUARTTransmitHandler( status );\r
+ }\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+\r
+static void vUARTReceiveHandler( alt_u32 status )\r
+{\r
+signed portCHAR cChar;\r
+portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;\r
+\r
+ /* If there was an error, discard the data */\r
+ if ( status & ( ALTERA_AVALON_UART_STATUS_PE_MSK | ALTERA_AVALON_UART_STATUS_FE_MSK ) )\r
+ {\r
+ asm("break");\r
+ return;\r
+ }\r
+\r
+ /* Transfer data from the device to the circular buffer */\r
+ cChar = IORD_ALTERA_AVALON_UART_RXDATA( UART_BASE );\r
+ if ( pdTRUE != xQueueSendFromISR( xRxedChars, &cChar, &xHigherPriorityTaskWoken ) )\r
+ {\r
+ /* If the circular buffer was full, disable interrupts. Interrupts will \r
+ be re-enabled when data is removed from the buffer. */\r
+ uartControl &= ~ALTERA_AVALON_UART_CONTROL_RRDY_MSK;\r
+ IOWR_ALTERA_AVALON_UART_CONTROL( UART_BASE, uartControl );\r
+ }\r
+ \r
+ portEND_SWITCHING_ISR( xHigherPriorityTaskWoken );\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+\r
+static void vUARTTransmitHandler( alt_u32 status )\r
+{\r
+signed portCHAR cChar;\r
+portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;\r
+ /* Transfer data if there is some ready to be transferred */\r
+ if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xHigherPriorityTaskWoken ) == pdTRUE )\r
+ {\r
+ IOWR_ALTERA_AVALON_UART_TXDATA( UART_BASE, cChar );\r
+ }\r
+ else\r
+ {\r
+ uartControl &= ~ALTERA_AVALON_UART_CONTROL_TRDY_MSK;\r
+ }\r
+ \r
+ IOWR_ALTERA_AVALON_UART_CONTROL( UART_BASE, uartControl );\r
+ portEND_SWITCHING_ISR( xHigherPriorityTaskWoken ); \r
+} \r
+/*---------------------------------------------------------------------------*/\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>\r
+<?fileVersion 3.1.0?>\r
+\r
+<ManagedProjectBuildInfo>\r
+<project id="RTOSDemo_syslib.nios2.lib.1122692399" name="Nios II Library" projectType="nios2.lib">\r
+<configuration artifactExtension="a" artifactName="RTOSDemo_syslib" cleanCommand="rm -rf" description="" errorParsers="org.eclipse.cdt.core.MakeErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GASErrorParser" id="nios2.lib.debug.1710955039" name="Debug" parent="nios2.lib.debug">\r
+<toolChain id="com.altera.nj.ui.lib.Debug.629598059" name="com.altera.nj.ui.lib.Debug" superClass="com.altera.nj.ui.lib.Debug">\r
+<tool id="com.altera.nj.ui.tool.compiler.lib.debug.2113232429" name="Nios II Compiler" superClass="com.altera.nj.ui.tool.compiler.lib.debug"/>\r
+<tool id="com.altera.nj.ui.tool.archiver.lib.debug.346993942" name="Archiver" superClass="com.altera.nj.ui.tool.archiver.lib.debug"/>\r
+</toolChain>\r
+</configuration>\r
+<configuration artifactExtension="a" artifactName="RTOSDemo_syslib" cleanCommand="rm -rf" description="" errorParsers="org.eclipse.cdt.core.MakeErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GASErrorParser" id="nios2.lib.release.872414519" name="Release" parent="nios2.lib.release">\r
+<toolChain id="com.altera.nj.ui.lib.Release.1045176498" name="com.altera.nj.ui.lib.Release" superClass="com.altera.nj.ui.lib.Release">\r
+<tool id="com.altera.nj.ui.tool.compiler.lib.release.1684787927" name="Nios II Compiler" superClass="com.altera.nj.ui.tool.compiler.lib.release"/>\r
+<tool id="com.altera.nj.ui.tool.archiver.lib.release.2019566308" name="Archiver" superClass="com.altera.nj.ui.tool.archiver.lib.release"/>\r
+</toolChain>\r
+</configuration>\r
+</project>\r
+</ManagedProjectBuildInfo>\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>\r
+<?eclipse-cdt version="2.0"?>\r
+\r
+<cdtproject id="org.eclipse.cdt.managedbuilder.core.managedMake">\r
+<extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>\r
+<extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>\r
+<extension id="org.eclipse.cdt.managedbuilder.core.ManagedBuildManager" point="org.eclipse.cdt.core.ScannerInfoProvider"/>\r
+<data>\r
+<item id="scannerConfiguration">\r
+<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile"/>\r
+<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">\r
+<buildOutputProvider>\r
+<openAction enabled="true" filePath=""/>\r
+<parser enabled="true"/>\r
+</buildOutputProvider>\r
+<scannerInfoProvider id="specsFile">\r
+<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>\r
+<parser enabled="true"/>\r
+</scannerInfoProvider>\r
+</profile>\r
+<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">\r
+<buildOutputProvider>\r
+<openAction enabled="false" filePath=""/>\r
+<parser enabled="true"/>\r
+</buildOutputProvider>\r
+<scannerInfoProvider id="makefileGenerator">\r
+<runAction arguments="-f ${project_name}_scd.mk" command="make" useDefault="true"/>\r
+<parser enabled="false"/>\r
+</scannerInfoProvider>\r
+</profile>\r
+<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">\r
+<buildOutputProvider>\r
+<openAction enabled="false" filePath=""/>\r
+<parser enabled="true"/>\r
+</buildOutputProvider>\r
+<scannerInfoProvider id="specsFile">\r
+<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>\r
+<parser enabled="false"/>\r
+</scannerInfoProvider>\r
+</profile>\r
+<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">\r
+<buildOutputProvider>\r
+<openAction enabled="false" filePath=""/>\r
+<parser enabled="true"/>\r
+</buildOutputProvider>\r
+<scannerInfoProvider id="specsFile">\r
+<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>\r
+<parser enabled="false"/>\r
+</scannerInfoProvider>\r
+</profile>\r
+</item>\r
+<item id="org.eclipse.cdt.core.pathentry">\r
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+<pathentry kind="out" path=""/>\r
+<pathentry kind="con" path="org.eclipse.cdt.make.core.DISCOVERED_SCANNER_INFO"/>\r
+<pathentry kind="con" path="org.eclipse.cdt.managedbuilder.MANAGED_CONTAINER"/>\r
+</item>\r
+</data>\r
+</cdtproject>\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
+<projectDescription>\r
+ <name>RTOSDemo_syslib</name>\r
+ <comment></comment>\r
+ <projects>\r
+ </projects>\r
+ <buildSpec>\r
+ <buildCommand>\r
+ <name>org.eclipse.cdt.make.core.makeBuilder</name>\r
+ <triggers>clean,full,incremental,</triggers>\r
+ <arguments>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.enableCleanBuild</key>\r
+ <value>false</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.append_environment</key>\r
+ <value>true</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.stopOnError</key>\r
+ <value>false</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.enabledIncrementalBuild</key>\r
+ <value>false</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.build.command</key>\r
+ <value>make</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.build.target.inc</key>\r
+ <value>all</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.build.arguments</key>\r
+ <value></value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>\r
+ <value>true</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.environment</key>\r
+ <value></value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.enableFullBuild</key>\r
+ <value>false</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.build.target.auto</key>\r
+ <value>all</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.enableAutoBuild</key>\r
+ <value>false</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.build.target.clean</key>\r
+ <value>clean</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.core.errorOutputParser</key>\r
+ <value>org.eclipse.cdt.core.MakeErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GASErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.VCErrorParser;</value>\r
+ </dictionary>\r
+ </arguments>\r
+ </buildCommand>\r
+ <buildCommand>\r
+ <name>com.altera.ide.core.alterabuilder</name>\r
+ <arguments>\r
+ </arguments>\r
+ </buildCommand>\r
+ <buildCommand>\r
+ <name>org.eclipse.cdt.make.core.ScannerConfigBuilder</name>\r
+ <arguments>\r
+ </arguments>\r
+ </buildCommand>\r
+ </buildSpec>\r
+ <natures>\r
+ <nature>org.eclipse.cdt.core.cnature</nature>\r
+ <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>\r
+ <nature>com.altera.ide.core.AlteraNios2Nature</nature>\r
+ <nature>com.altera.ide.core.AlteraSDKNature</nature>\r
+ <nature>org.eclipse.cdt.make.core.makeNature</nature>\r
+ <nature>org.eclipse.cdt.make.core.ScannerConfigNature</nature>\r
+ </natures>\r
+</projectDescription>\r
--- /dev/null
+#Tue Aug 04 21:28:00 BST 2009\r
+eclipse.preferences.version=1\r
+indexerId=org.eclipse.cdt.core.fastIndexer\r
--- /dev/null
+#Tue Aug 04 21:27:57 BST 2009\r
+eclipse.preferences.version=1\r
+nios2.lib.debug.1710955039/internalBuilder/enabled=false\r
+nios2.lib.debug.1710955039/internalBuilder/ignoreErr=true\r
+nios2.lib.release.872414519/internalBuilder/enabled=false\r
+nios2.lib.release.872414519/internalBuilder/ignoreErr=true\r
--- /dev/null
+/*******************************************************************************\r
+* \r
+* System Library Project \r
+* ====================== \r
+* \r
+* This is the library project custom created for your hardware system. \r
+* It is built up from auto-generated files and component source files. \r
+* \r
+* The auto-generated system source files can be found in: \r
+* <configuration_folder>/system_description \r
+* e.g. Release/system_description/system.h *\r
+* \r
+* The component source files from the relevant sopc component folders \r
+* e.g. <sopc_kit_nios2>/components/altera_nios2 \r
+* \r
+* To change the system library build properties, right click on the project \r
+* and select properties. This allows you to set options like timers, \r
+* memory sections and build options. \r
+* *\r
+*******************************************************************************/\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>\r
+<stf>\r
+ <project ptf="C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\NiosII_CycloneIII_DBC3C40_GCC\cpu.ptf" target="Nios II System Library">\r
+ </project>\r
+ <cpu name="cpu_0">\r
+ </cpu>\r
+ <os_spec clean_exit="yes" direct_drivers="no" exception_stack="no" instruction_emulation="no" name="none (single-threaded)" no_c_plus_plus="no" no_exit="no" profiling="no" small_footprint="no" sopc_component_dir="altera_hal" stack_checking="no" stderr="jtag_uart_0" stdin="jtag_uart_0" stdout="jtag_uart_0">\r
+ <sys_defines>\r
+<define name="alt_max_fd" quote="no" value="32"/>\r
+<define name="alt_sys_clk" quote="no" value="SYS_CLK"/>\r
+<define name="alt_timestamp_clk" quote="no" value="none"/>\r
+</sys_defines>\r
+<make_macros>\r
+<macro name="alt_sim_optimize" quote="no" value="0"/>\r
+</make_macros>\r
+</os_spec>\r
+ <link_spec auto_gen_script="yes">\r
+ <script name="none">\r
+ <section memory="sdram" name=".text"/>\r
+<section memory="sdram" name=".rodata"/>\r
+<section memory="sdram" name=".rwdata"/>\r
+<section memory="sdram" name=".stack"/>\r
+<section memory="sdram" name=".heap"/>\r
+<section memory="sdram" name=".exceptionstack" size="0x400"/>\r
+</script>\r
+ </link_spec>\r
+</stf>\r
--- /dev/null
+SYSTEM cpu\r
+{\r
+ System_Wizard_Version = "8.00";\r
+ System_Wizard_Build = "215";\r
+ Builder_Application = "sopc_builder_ca";\r
+ WIZARD_SCRIPT_ARGUMENTS \r
+ {\r
+ hdl_language = "vhdl";\r
+ device_family = "CYCLONEIII";\r
+ device_family_id = "CYCLONEIII";\r
+ generate_sdk = "0";\r
+ do_build_sim = "0";\r
+ hardcopy_compatible = "0";\r
+ CLOCKS \r
+ {\r
+ CLOCK clk\r
+ {\r
+ frequency = "75000000";\r
+ source = "External";\r
+ Is_Clock_Source = "0";\r
+ display_name = "clk";\r
+ pipeline = "0";\r
+ clock_module_connection_point_for_c2h = "clk.clk";\r
+ }\r
+ }\r
+ clock_freq = "75000000";\r
+ clock_freq = "75000000";\r
+ board_class = "";\r
+ view_master_columns = "1";\r
+ view_master_priorities = "0";\r
+ generate_hdl = "";\r
+ bustype_column_width = "0";\r
+ clock_column_width = "80";\r
+ name_column_width = "75";\r
+ desc_column_width = "75";\r
+ base_column_width = "75";\r
+ end_column_width = "75";\r
+ BOARD_INFO \r
+ {\r
+ altera_avalon_epcs_flash_controller \r
+ {\r
+ reference_designators = "";\r
+ }\r
+ altera_avalon_cfi_flash \r
+ {\r
+ reference_designators = "";\r
+ }\r
+ }\r
+ do_log_history = "0";\r
+ }\r
+ MODULE cpu_0\r
+ {\r
+ MASTER instruction_master\r
+ {\r
+ PORT_WIRING \r
+ {\r
+ PORT clk\r
+ {\r
+ type = "clk";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT reset_n\r
+ {\r
+ type = "reset_n";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "0";\r
+ }\r
+ PORT i_address\r
+ {\r
+ type = "address";\r
+ width = "25";\r
+ direction = "output";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT i_read\r
+ {\r
+ type = "read";\r
+ width = "1";\r
+ direction = "output";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT i_readdata\r
+ {\r
+ type = "readdata";\r
+ width = "32";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT i_readdatavalid\r
+ {\r
+ type = "readdatavalid";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT i_waitrequest\r
+ {\r
+ type = "waitrequest";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ }\r
+ SYSTEM_BUILDER_INFO \r
+ {\r
+ Bus_Type = "avalon";\r
+ Is_Asynchronous = "0";\r
+ DBS_Big_Endian = "0";\r
+ Adapts_To = "";\r
+ Do_Stream_Reads = "0";\r
+ Do_Stream_Writes = "0";\r
+ Max_Address_Width = "32";\r
+ Data_Width = "32";\r
+ Address_Width = "25";\r
+ Maximum_Burst_Size = "1";\r
+ Register_Incoming_Signals = "0";\r
+ Register_Outgoing_Signals = "0";\r
+ Interleave_Bursts = "";\r
+ Linewrap_Bursts = "";\r
+ Burst_On_Burst_Boundaries_Only = "";\r
+ Always_Burst_Max_Burst = "";\r
+ Is_Big_Endian = "0";\r
+ Is_Enabled = "1";\r
+ Is_Instruction_Master = "1";\r
+ Is_Readable = "1";\r
+ Is_Writeable = "0";\r
+ Address_Group = "0";\r
+ Has_IRQ = "0";\r
+ Irq_Scheme = "individual_requests";\r
+ Interrupt_Range = "0-0";\r
+ }\r
+ MEMORY_MAP \r
+ {\r
+ Entry cpu_0/jtag_debug_module\r
+ {\r
+ address = "0x00901800";\r
+ span = "0x00000800";\r
+ is_bridge = "0";\r
+ }\r
+ Entry onchip_memory/s1\r
+ {\r
+ address = "0x00904000";\r
+ span = "0x00002000";\r
+ is_bridge = "0";\r
+ }\r
+ Entry sdram/s1\r
+ {\r
+ address = "0x01000000";\r
+ span = "0x01000000";\r
+ is_bridge = "0";\r
+ }\r
+ Entry epcs_controller/epcs_control_port\r
+ {\r
+ address = "0x00906000";\r
+ span = "0x00000800";\r
+ is_bridge = "0";\r
+ }\r
+ Entry cfi_flash/s1\r
+ {\r
+ address = "0x00000000";\r
+ span = "0x00800000";\r
+ is_bridge = "0";\r
+ }\r
+ Entry DBC3C40_SRAM_inst/avalon_tristate_slave\r
+ {\r
+ address = "0x00800000";\r
+ span = "0x00100000";\r
+ is_bridge = "0";\r
+ }\r
+ }\r
+ }\r
+ MASTER custom_instruction_master\r
+ {\r
+ SYSTEM_BUILDER_INFO \r
+ {\r
+ Bus_Type = "nios_custom_instruction";\r
+ Data_Width = "32";\r
+ Address_Width = "8";\r
+ Is_Custom_Instruction = "1";\r
+ Is_Enabled = "0";\r
+ Max_Address_Width = "8";\r
+ Base_Address = "N/A";\r
+ Is_Visible = "0";\r
+ }\r
+ PORT_WIRING \r
+ {\r
+ PORT dataa\r
+ {\r
+ type = "dataa";\r
+ width = "32";\r
+ direction = "output";\r
+ }\r
+ PORT datab\r
+ {\r
+ type = "datab";\r
+ width = "32";\r
+ direction = "output";\r
+ }\r
+ PORT result\r
+ {\r
+ type = "result";\r
+ width = "32";\r
+ direction = "input";\r
+ }\r
+ PORT clk_en\r
+ {\r
+ type = "clk_en";\r
+ width = "1";\r
+ direction = "output";\r
+ }\r
+ PORT reset\r
+ {\r
+ type = "reset";\r
+ width = "1";\r
+ direction = "output";\r
+ }\r
+ PORT start\r
+ {\r
+ type = "start";\r
+ width = "1";\r
+ direction = "output";\r
+ }\r
+ PORT done\r
+ {\r
+ type = "done";\r
+ width = "1";\r
+ direction = "input";\r
+ }\r
+ PORT n\r
+ {\r
+ type = "n";\r
+ width = "8";\r
+ direction = "output";\r
+ }\r
+ PORT a\r
+ {\r
+ type = "a";\r
+ width = "5";\r
+ direction = "output";\r
+ }\r
+ PORT b\r
+ {\r
+ type = "b";\r
+ width = "5";\r
+ direction = "output";\r
+ }\r
+ PORT c\r
+ {\r
+ type = "c";\r
+ width = "5";\r
+ direction = "output";\r
+ }\r
+ PORT readra\r
+ {\r
+ type = "readra";\r
+ width = "1";\r
+ direction = "output";\r
+ }\r
+ PORT readrb\r
+ {\r
+ type = "readrb";\r
+ width = "1";\r
+ direction = "output";\r
+ }\r
+ PORT writerc\r
+ {\r
+ type = "writerc";\r
+ width = "1";\r
+ direction = "output";\r
+ }\r
+ }\r
+ }\r
+ SLAVE jtag_debug_module\r
+ {\r
+ SYSTEM_BUILDER_INFO \r
+ {\r
+ Bus_Type = "avalon";\r
+ Write_Wait_States = "0cycles";\r
+ Read_Wait_States = "1cycles";\r
+ Hold_Time = "0cycles";\r
+ Setup_Time = "0cycles";\r
+ Is_Printable_Device = "0";\r
+ Address_Alignment = "dynamic";\r
+ Well_Behaved_Waitrequest = "0";\r
+ Is_Nonvolatile_Storage = "0";\r
+ Address_Span = "2048";\r
+ Read_Latency = "0";\r
+ Is_Memory_Device = "1";\r
+ Maximum_Pending_Read_Transactions = "0";\r
+ Minimum_Uninterrupted_Run_Length = "1";\r
+ Accepts_Internal_Connections = "1";\r
+ Write_Latency = "0";\r
+ Is_Flash = "0";\r
+ Data_Width = "32";\r
+ Address_Width = "9";\r
+ Maximum_Burst_Size = "1";\r
+ Register_Incoming_Signals = "0";\r
+ Register_Outgoing_Signals = "0";\r
+ Interleave_Bursts = "0";\r
+ Linewrap_Bursts = "0";\r
+ Burst_On_Burst_Boundaries_Only = "0";\r
+ Always_Burst_Max_Burst = "0";\r
+ Is_Big_Endian = "0";\r
+ Is_Enabled = "1";\r
+ Accepts_External_Connections = "1";\r
+ Requires_Internal_Connections = "";\r
+ MASTERED_BY cpu_0/instruction_master\r
+ {\r
+ priority = "1";\r
+ Offset_Address = "0x00901800";\r
+ }\r
+ MASTERED_BY cpu_0/data_master\r
+ {\r
+ priority = "1";\r
+ Offset_Address = "0x00901800";\r
+ }\r
+ Base_Address = "0x00901800";\r
+ Is_Readable = "1";\r
+ Is_Writeable = "1";\r
+ Uses_Tri_State_Data_Bus = "0";\r
+ Has_IRQ = "0";\r
+ JTAG_Hub_Base_Id = "1118278";\r
+ JTAG_Hub_Instance_Id = "0";\r
+ Address_Group = "0";\r
+ IRQ_MASTER cpu_0/data_master\r
+ {\r
+ IRQ_Number = "NC";\r
+ }\r
+ }\r
+ PORT_WIRING \r
+ {\r
+ PORT jtag_debug_module_address\r
+ {\r
+ type = "address";\r
+ width = "9";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT jtag_debug_module_begintransfer\r
+ {\r
+ type = "begintransfer";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT jtag_debug_module_byteenable\r
+ {\r
+ type = "byteenable";\r
+ width = "4";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT jtag_debug_module_clk\r
+ {\r
+ type = "clk";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT jtag_debug_module_debugaccess\r
+ {\r
+ type = "debugaccess";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT jtag_debug_module_readdata\r
+ {\r
+ type = "readdata";\r
+ width = "32";\r
+ direction = "output";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT jtag_debug_module_reset\r
+ {\r
+ type = "reset";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT jtag_debug_module_resetrequest\r
+ {\r
+ type = "resetrequest";\r
+ width = "1";\r
+ direction = "output";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT jtag_debug_module_select\r
+ {\r
+ type = "chipselect";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT jtag_debug_module_write\r
+ {\r
+ type = "write";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT jtag_debug_module_writedata\r
+ {\r
+ type = "writedata";\r
+ width = "32";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT reset_n\r
+ {\r
+ Is_Enabled = "1";\r
+ direction = "input";\r
+ type = "reset_n";\r
+ width = "1";\r
+ }\r
+ }\r
+ }\r
+ MASTER data_master\r
+ {\r
+ SYSTEM_BUILDER_INFO \r
+ {\r
+ Has_IRQ = "1";\r
+ Irq_Scheme = "individual_requests";\r
+ Bus_Type = "avalon";\r
+ Is_Asynchronous = "0";\r
+ DBS_Big_Endian = "0";\r
+ Adapts_To = "";\r
+ Do_Stream_Reads = "0";\r
+ Do_Stream_Writes = "0";\r
+ Max_Address_Width = "32";\r
+ Data_Width = "32";\r
+ Address_Width = "25";\r
+ Maximum_Burst_Size = "1";\r
+ Register_Incoming_Signals = "1";\r
+ Register_Outgoing_Signals = "0";\r
+ Interleave_Bursts = "0";\r
+ Linewrap_Bursts = "0";\r
+ Burst_On_Burst_Boundaries_Only = "";\r
+ Always_Burst_Max_Burst = "0";\r
+ Is_Big_Endian = "0";\r
+ Is_Enabled = "1";\r
+ Is_Data_Master = "1";\r
+ Address_Group = "0";\r
+ Is_Readable = "1";\r
+ Is_Writeable = "1";\r
+ Interrupt_Range = "0-31";\r
+ }\r
+ PORT_WIRING \r
+ {\r
+ PORT d_irq\r
+ {\r
+ type = "irq";\r
+ width = "32";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT d_address\r
+ {\r
+ type = "address";\r
+ width = "25";\r
+ direction = "output";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT d_byteenable\r
+ {\r
+ type = "byteenable";\r
+ width = "4";\r
+ direction = "output";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT d_read\r
+ {\r
+ type = "read";\r
+ width = "1";\r
+ direction = "output";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT d_readdata\r
+ {\r
+ type = "readdata";\r
+ width = "32";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT d_readdatavalid\r
+ {\r
+ type = "readdatavalid";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "0";\r
+ }\r
+ PORT d_waitrequest\r
+ {\r
+ type = "waitrequest";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT d_write\r
+ {\r
+ type = "write";\r
+ width = "1";\r
+ direction = "output";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT d_writedata\r
+ {\r
+ type = "writedata";\r
+ width = "32";\r
+ direction = "output";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT jtag_debug_module_debugaccess_to_roms\r
+ {\r
+ type = "debugaccess";\r
+ width = "1";\r
+ direction = "output";\r
+ Is_Enabled = "1";\r
+ }\r
+ }\r
+ MEMORY_MAP \r
+ {\r
+ Entry cpu_0/jtag_debug_module\r
+ {\r
+ address = "0x00901800";\r
+ span = "0x00000800";\r
+ is_bridge = "0";\r
+ }\r
+ Entry onchip_memory/s1\r
+ {\r
+ address = "0x00904000";\r
+ span = "0x00002000";\r
+ is_bridge = "0";\r
+ }\r
+ Entry jtag_uart_0/avalon_jtag_slave\r
+ {\r
+ address = "0x009000d0";\r
+ span = "0x00000008";\r
+ is_bridge = "0";\r
+ }\r
+ Entry sdram/s1\r
+ {\r
+ address = "0x01000000";\r
+ span = "0x01000000";\r
+ is_bridge = "0";\r
+ }\r
+ Entry sysid/control_slave\r
+ {\r
+ address = "0x009000d8";\r
+ span = "0x00000008";\r
+ is_bridge = "0";\r
+ }\r
+ Entry LED_Pio/s1\r
+ {\r
+ address = "0x00900080";\r
+ span = "0x00000010";\r
+ is_bridge = "0";\r
+ }\r
+ Entry SG_Pio/s1\r
+ {\r
+ address = "0x00900090";\r
+ span = "0x00000010";\r
+ is_bridge = "0";\r
+ }\r
+ Entry IO_Pio/s1\r
+ {\r
+ address = "0x009000a0";\r
+ span = "0x00000010";\r
+ is_bridge = "0";\r
+ }\r
+ Entry Button_Pio/s1\r
+ {\r
+ address = "0x009000b0";\r
+ span = "0x00000010";\r
+ is_bridge = "0";\r
+ }\r
+ Entry uart/s1\r
+ {\r
+ address = "0x00900040";\r
+ span = "0x00000020";\r
+ is_bridge = "0";\r
+ }\r
+ Entry LM74_Pio/s1\r
+ {\r
+ address = "0x009000c0";\r
+ span = "0x00000010";\r
+ is_bridge = "0";\r
+ }\r
+ Entry epcs_controller/epcs_control_port\r
+ {\r
+ address = "0x00906000";\r
+ span = "0x00000800";\r
+ is_bridge = "0";\r
+ }\r
+ Entry cfi_flash/s1\r
+ {\r
+ address = "0x00000000";\r
+ span = "0x00800000";\r
+ is_bridge = "0";\r
+ }\r
+ Entry DBC3C40_SRAM_inst/avalon_tristate_slave\r
+ {\r
+ address = "0x00800000";\r
+ span = "0x00100000";\r
+ is_bridge = "0";\r
+ }\r
+ Entry sys_clk/s1\r
+ {\r
+ address = "0x00900060";\r
+ span = "0x00000020";\r
+ is_bridge = "0";\r
+ }\r
+ Entry nios_vga_inst/vga_regs\r
+ {\r
+ address = "0x00900000";\r
+ span = "0x00000040";\r
+ is_bridge = "0";\r
+ }\r
+ }\r
+ }\r
+ WIZARD_SCRIPT_ARGUMENTS \r
+ {\r
+ cache_has_dcache = "0";\r
+ cache_dcache_size = "0";\r
+ cache_dcache_line_size = "0";\r
+ cache_dcache_bursts = "0";\r
+ cache_dcache_ram_block_type = "AUTO";\r
+ num_tightly_coupled_data_masters = "0";\r
+ gui_num_tightly_coupled_data_masters = "0";\r
+ gui_include_tightly_coupled_data_masters = "0";\r
+ gui_omit_avalon_data_master = "0";\r
+ cache_has_icache = "1";\r
+ cache_icache_size = "16384";\r
+ cache_icache_line_size = "32";\r
+ cache_icache_ram_block_type = "AUTO";\r
+ cache_icache_bursts = "0";\r
+ num_tightly_coupled_instruction_masters = "0";\r
+ gui_num_tightly_coupled_instruction_masters = "0";\r
+ gui_include_tightly_coupled_instruction_masters = "0";\r
+ debug_level = "3";\r
+ include_oci = "1";\r
+ oci_sbi_enabled = "1";\r
+ oci_num_xbrk = "2";\r
+ oci_num_dbrk = "2";\r
+ oci_dbrk_trace = "0";\r
+ oci_dbrk_pairs = "1";\r
+ oci_onchip_trace = "0";\r
+ oci_offchip_trace = "0";\r
+ oci_data_trace = "0";\r
+ include_third_party_debug_port = "0";\r
+ oci_trace_addr_width = "7";\r
+ oci_trigger_arming = "1";\r
+ oci_debugreq_signals = "0";\r
+ oci_embedded_pll = "0";\r
+ oci_num_pm = "0";\r
+ oci_pm_width = "32";\r
+ performance_counters_present = "0";\r
+ performance_counters_width = "32";\r
+ always_encrypt = "1";\r
+ debug_simgen = "0";\r
+ activate_model_checker = "0";\r
+ activate_test_end_checker = "0";\r
+ activate_trace = "1";\r
+ activate_monitors = "1";\r
+ clear_x_bits_ld_non_bypass = "1";\r
+ bit_31_bypass_dcache = "1";\r
+ hdl_sim_caches_cleared = "1";\r
+ hbreak_test = "0";\r
+ allow_full_address_range = "0";\r
+ extra_exc_info = "0";\r
+ branch_prediction_type = "Static";\r
+ bht_ptr_sz = "8";\r
+ bht_index_pc_only = "0";\r
+ gui_branch_prediction_type = "Static";\r
+ full_waveform_signals = "0";\r
+ export_pcb = "0";\r
+ avalon_debug_port_present = "0";\r
+ illegal_instructions_trap = "0";\r
+ illegal_memory_access_detection = "0";\r
+ illegal_mem_exc = "0";\r
+ slave_access_error_exc = "0";\r
+ division_error_exc = "0";\r
+ advanced_exc = "0";\r
+ gui_mmu_present = "0";\r
+ mmu_present = "0";\r
+ process_id_num_bits = "8";\r
+ tlb_ptr_sz = "7";\r
+ tlb_num_ways = "16";\r
+ udtlb_num_entries = "6";\r
+ uitlb_num_entries = "4";\r
+ fast_tlb_miss_exc_slave = "";\r
+ fast_tlb_miss_exc_offset = "0x00000000";\r
+ mpu_present = "0";\r
+ mpu_num_data_regions = "8";\r
+ mpu_num_inst_regions = "8";\r
+ mpu_min_data_region_size_log2 = "12";\r
+ mpu_min_inst_region_size_log2 = "12";\r
+ mpu_use_limit = "0";\r
+ hardware_divide_present = "0";\r
+ gui_hardware_divide_setting = "0";\r
+ hardware_multiply_present = "1";\r
+ hardware_multiply_impl = "embedded_mul";\r
+ shift_rot_impl = "fast_le_shift";\r
+ gui_hardware_multiply_setting = "embedded_mul_fast_le_shift";\r
+ reset_slave = "cfi_flash/s1";\r
+ break_slave = "cpu_0/jtag_debug_module";\r
+ exc_slave = "sdram/s1";\r
+ reset_offset = "0x00000000";\r
+ break_offset = "0x00000020";\r
+ exc_offset = "0x00000020";\r
+ cpu_reset = "0";\r
+ CPU_Implementation = "small";\r
+ cpu_selection = "s";\r
+ device_family_id = "CYCLONEIII";\r
+ address_stall_present = "1";\r
+ dsp_block_supports_shift = "0";\r
+ mrams_present = "0";\r
+ do_generate = "1";\r
+ cpuid_value = "0";\r
+ cpuid_sz = "1";\r
+ dont_overwrite_cpuid = "1";\r
+ allow_legacy_sdk = "1";\r
+ legacy_sdk_support = "1";\r
+ inst_addr_width = "25";\r
+ data_addr_width = "25";\r
+ asp_debug = "0";\r
+ asp_core_debug = "0";\r
+ CPU_Architecture = "nios2";\r
+ cache_icache_burst_type = "none";\r
+ include_debug = "0";\r
+ include_trace = "0";\r
+ hardware_multiply_uses_les = "0";\r
+ hardware_multiply_omits_msw = "1";\r
+ big_endian = "0";\r
+ break_slave_override = "";\r
+ break_offset_override = "0x20";\r
+ altera_show_unreleased_features = "0";\r
+ altera_show_unpublished_features = "0";\r
+ altera_internal_test = "0";\r
+ alt_log_port_base = "";\r
+ alt_log_port_type = "";\r
+ gui_illegal_instructions_trap = "0";\r
+ atomic_mem_present = "0";\r
+ nmi_present = "0";\r
+ fast_intr_present = "0";\r
+ num_shadow_regs = "0";\r
+ gui_illegal_memory_access_detection = "0";\r
+ cache_omit_dcache = "0";\r
+ cache_omit_icache = "0";\r
+ omit_instruction_master = "0";\r
+ omit_data_master = "0";\r
+ ras_ptr_sz = "4";\r
+ jtb_ptr_sz = "5";\r
+ ibuf_ptr_sz = "4";\r
+ always_bypass_dcache = "0";\r
+ iss_trace_on = "0";\r
+ iss_trace_warning = "1";\r
+ iss_trace_info = "1";\r
+ iss_trace_disassembly = "0";\r
+ iss_trace_registers = "0";\r
+ iss_trace_instr_count = "0";\r
+ iss_software_debug = "0";\r
+ iss_software_debug_port = "9996";\r
+ iss_memory_dump_start = "";\r
+ iss_memory_dump_end = "";\r
+ Boot_Copier = "boot_loader_cfi.srec";\r
+ Boot_Copier_EPCS = "boot_loader_epcs.srec";\r
+ Boot_Copier_EPCS_SII_SIII_CIII = "boot_loader_epcs_sii_siii_ciii.srec";\r
+ Boot_Copier_BE = "boot_loader_cfi_be.srec";\r
+ Boot_Copier_EPCS_BE = "boot_loader_epcs_be.srec";\r
+ Boot_Copier_EPCS_SII_SIII_CIII_BE = "boot_loader_epcs_sii_siii_ciii_be.srec";\r
+ CONSTANTS \r
+ {\r
+ CONSTANT __nios_catch_irqs__\r
+ {\r
+ value = "1";\r
+ comment = "Include panic handler for all irqs (needs uart)";\r
+ }\r
+ CONSTANT __nios_use_constructors__\r
+ {\r
+ value = "1";\r
+ comment = "Call c++ static constructors";\r
+ }\r
+ CONSTANT __nios_use_small_printf__\r
+ {\r
+ value = "1";\r
+ comment = "Smaller non-ANSI printf, with no floating point";\r
+ }\r
+ CONSTANT nasys_has_icache\r
+ {\r
+ value = "1";\r
+ comment = "True if instruction cache present";\r
+ }\r
+ CONSTANT nasys_icache_size\r
+ {\r
+ value = "16384";\r
+ comment = "Size in bytes of instruction cache";\r
+ }\r
+ CONSTANT nasys_icache_line_size\r
+ {\r
+ value = "32";\r
+ comment = "Size in bytes of each icache line";\r
+ }\r
+ CONSTANT nasys_icache_line_size_log2\r
+ {\r
+ value = "5";\r
+ comment = "Log2 size in bytes of each icache line";\r
+ }\r
+ CONSTANT nasys_has_dcache\r
+ {\r
+ value = "0";\r
+ comment = "True if instruction cache present";\r
+ }\r
+ CONSTANT nasys_dcache_size\r
+ {\r
+ value = "0";\r
+ comment = "Size in bytes of data cache";\r
+ }\r
+ CONSTANT nasys_dcache_line_size\r
+ {\r
+ value = "0";\r
+ comment = "Size in bytes of each dcache line";\r
+ }\r
+ CONSTANT nasys_dcache_line_size_log2\r
+ {\r
+ value = "-Infinity";\r
+ comment = "Log2 size in bytes of each dcache line";\r
+ }\r
+ }\r
+ license_status = "encrypted";\r
+ mainmem_slave = "DBC3C40_SRAM_inst/avalon_tristate_slave";\r
+ datamem_slave = "DBC3C40_SRAM_inst/avalon_tristate_slave";\r
+ maincomm_slave = "uart/s1";\r
+ germs_monitor_id = "";\r
+ }\r
+ class = "altera_nios2";\r
+ class_version = "7.08";\r
+ SYSTEM_BUILDER_INFO \r
+ {\r
+ Is_Enabled = "1";\r
+ Clock_Source = "clk";\r
+ Has_Clock = "1";\r
+ Parameters_Signature = "";\r
+ Is_CPU = "1";\r
+ Instantiate_In_System_Module = "1";\r
+ Required_Device_Family = "STRATIX,STRATIXGX,STRATIXII,STRATIXIIGX,STRATIXIIGXLITE,STRATIXIII,STRATIXIV,CYCLONE,CYCLONEII,CYCLONEIII";\r
+ Default_Module_Name = "cpu";\r
+ Top_Level_Ports_Are_Enumerated = "1";\r
+ View \r
+ {\r
+ Settings_Summary = "Nios II/s
+ <br> 16-Kbyte Instruction Cache
+
+ <br> JTAG Debug Module
+ ";\r
+ MESSAGES \r
+ {\r
+ }\r
+ }\r
+ }\r
+ iss_model_name = "altera_nios2";\r
+ HDL_INFO \r
+ {\r
+ PLI_Files = "";\r
+ Precompiled_Simulation_Library_Files = "";\r
+ Simulation_HDL_Files = "";\r
+ Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/cpu_0_test_bench.vhd, __PROJECT_DIRECTORY__/cpu_0_mult_cell.vhd, __PROJECT_DIRECTORY__/cpu_0_jtag_debug_module_tck.vhd, __PROJECT_DIRECTORY__/cpu_0_jtag_debug_module_sysclk.vhd, __PROJECT_DIRECTORY__/cpu_0_jtag_debug_module_wrapper.vhd, __PROJECT_DIRECTORY__/cpu_0.vhd";\r
+ Synthesis_Only_Files = "";\r
+ }\r
+ MASTER tightly_coupled_instruction_master_0\r
+ {\r
+ PORT_WIRING \r
+ {\r
+ }\r
+ SYSTEM_BUILDER_INFO \r
+ {\r
+ Register_Incoming_Signals = "0";\r
+ Bus_Type = "avalon";\r
+ Data_Width = "32";\r
+ Max_Address_Width = "31";\r
+ Address_Width = "8";\r
+ Is_Instruction_Master = "1";\r
+ Has_IRQ = "0";\r
+ Is_Enabled = "0";\r
+ Is_Big_Endian = "0";\r
+ Connection_Limit = "1";\r
+ Is_Channel = "1";\r
+ }\r
+ }\r
+ MASTER tightly_coupled_instruction_master_1\r
+ {\r
+ PORT_WIRING \r
+ {\r
+ }\r
+ SYSTEM_BUILDER_INFO \r
+ {\r
+ Register_Incoming_Signals = "0";\r
+ Bus_Type = "avalon";\r
+ Data_Width = "32";\r
+ Max_Address_Width = "31";\r
+ Address_Width = "8";\r
+ Address_Group = "0";\r
+ Is_Instruction_Master = "1";\r
+ Is_Readable = "1";\r
+ Is_Writeable = "0";\r
+ Has_IRQ = "0";\r
+ Is_Enabled = "0";\r
+ Is_Big_Endian = "0";\r
+ Connection_Limit = "1";\r
+ Is_Channel = "1";\r
+ }\r
+ }\r
+ MASTER tightly_coupled_instruction_master_2\r
+ {\r
+ PORT_WIRING \r
+ {\r
+ }\r
+ SYSTEM_BUILDER_INFO \r
+ {\r
+ Register_Incoming_Signals = "0";\r
+ Bus_Type = "avalon";\r
+ Data_Width = "32";\r
+ Max_Address_Width = "31";\r
+ Address_Width = "8";\r
+ Address_Group = "0";\r
+ Is_Instruction_Master = "1";\r
+ Is_Readable = "1";\r
+ Is_Writeable = "0";\r
+ Has_IRQ = "0";\r
+ Is_Enabled = "0";\r
+ Is_Big_Endian = "0";\r
+ Connection_Limit = "1";\r
+ Is_Channel = "1";\r
+ }\r
+ }\r
+ MASTER tightly_coupled_instruction_master_3\r
+ {\r
+ PORT_WIRING \r
+ {\r
+ }\r
+ SYSTEM_BUILDER_INFO \r
+ {\r
+ Register_Incoming_Signals = "0";\r
+ Bus_Type = "avalon";\r
+ Data_Width = "32";\r
+ Max_Address_Width = "31";\r
+ Address_Width = "8";\r
+ Address_Group = "0";\r
+ Is_Instruction_Master = "1";\r
+ Is_Readable = "1";\r
+ Is_Writeable = "0";\r
+ Has_IRQ = "0";\r
+ Is_Enabled = "0";\r
+ Is_Big_Endian = "0";\r
+ Connection_Limit = "1";\r
+ Is_Channel = "1";\r
+ }\r
+ }\r
+ MASTER data_master2\r
+ {\r
+ PORT_WIRING \r
+ {\r
+ }\r
+ SYSTEM_BUILDER_INFO \r
+ {\r
+ Register_Incoming_Signals = "1";\r
+ Bus_Type = "avalon";\r
+ Data_Width = "32";\r
+ Max_Address_Width = "31";\r
+ Address_Width = "8";\r
+ Address_Group = "0";\r
+ Is_Data_Master = "1";\r
+ Is_Readable = "1";\r
+ Is_Writeable = "1";\r
+ Has_IRQ = "0";\r
+ Is_Enabled = "0";\r
+ Is_Big_Endian = "0";\r
+ }\r
+ }\r
+ MASTER tightly_coupled_data_master_0\r
+ {\r
+ PORT_WIRING \r
+ {\r
+ }\r
+ SYSTEM_BUILDER_INFO \r
+ {\r
+ Register_Incoming_Signals = "0";\r
+ Bus_Type = "avalon";\r
+ Data_Width = "32";\r
+ Max_Address_Width = "31";\r
+ Address_Width = "8";\r
+ Address_Group = "0";\r
+ Is_Data_Master = "1";\r
+ Is_Readable = "1";\r
+ Is_Writeable = "1";\r
+ Has_IRQ = "0";\r
+ Is_Enabled = "0";\r
+ Is_Big_Endian = "0";\r
+ Connection_Limit = "1";\r
+ Is_Channel = "1";\r
+ }\r
+ }\r
+ MASTER tightly_coupled_data_master_1\r
+ {\r
+ PORT_WIRING \r
+ {\r
+ }\r
+ SYSTEM_BUILDER_INFO \r
+ {\r
+ Register_Incoming_Signals = "0";\r
+ Bus_Type = "avalon";\r
+ Data_Width = "32";\r
+ Max_Address_Width = "31";\r
+ Address_Width = "8";\r
+ Address_Group = "0";\r
+ Is_Data_Master = "1";\r
+ Is_Readable = "1";\r
+ Is_Writeable = "1";\r
+ Has_IRQ = "0";\r
+ Is_Enabled = "0";\r
+ Is_Big_Endian = "0";\r
+ Connection_Limit = "1";\r
+ Is_Channel = "1";\r
+ }\r
+ }\r
+ MASTER tightly_coupled_data_master_2\r
+ {\r
+ PORT_WIRING \r
+ {\r
+ }\r
+ SYSTEM_BUILDER_INFO \r
+ {\r
+ Register_Incoming_Signals = "0";\r
+ Bus_Type = "avalon";\r
+ Data_Width = "32";\r
+ Max_Address_Width = "31";\r
+ Address_Width = "8";\r
+ Address_Group = "0";\r
+ Is_Data_Master = "1";\r
+ Is_Readable = "1";\r
+ Is_Writeable = "1";\r
+ Has_IRQ = "0";\r
+ Is_Enabled = "0";\r
+ Is_Big_Endian = "0";\r
+ Connection_Limit = "1";\r
+ Is_Channel = "1";\r
+ }\r
+ }\r
+ MASTER tightly_coupled_data_master_3\r
+ {\r
+ PORT_WIRING \r
+ {\r
+ }\r
+ SYSTEM_BUILDER_INFO \r
+ {\r
+ Register_Incoming_Signals = "0";\r
+ Bus_Type = "avalon";\r
+ Data_Width = "32";\r
+ Max_Address_Width = "31";\r
+ Address_Width = "8";\r
+ Address_Group = "0";\r
+ Is_Data_Master = "1";\r
+ Is_Readable = "1";\r
+ Is_Writeable = "1";\r
+ Has_IRQ = "0";\r
+ Is_Enabled = "0";\r
+ Is_Big_Endian = "0";\r
+ Connection_Limit = "1";\r
+ Is_Channel = "1";\r
+ }\r
+ }\r
+ PORT_WIRING \r
+ {\r
+ PORT jtag_debug_trigout\r
+ {\r
+ width = "1";\r
+ direction = "output";\r
+ Is_Enabled = "0";\r
+ }\r
+ PORT jtag_debug_offchip_trace_clk\r
+ {\r
+ width = "1";\r
+ direction = "output";\r
+ Is_Enabled = "0";\r
+ }\r
+ PORT jtag_debug_offchip_trace_data\r
+ {\r
+ width = "18";\r
+ direction = "output";\r
+ Is_Enabled = "0";\r
+ }\r
+ PORT clkx2\r
+ {\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "0";\r
+ visible = "0";\r
+ }\r
+ }\r
+ SIMULATION \r
+ {\r
+ DISPLAY \r
+ {\r
+ SIGNAL aaa\r
+ {\r
+ format = "Logic";\r
+ name = "i_readdata";\r
+ radix = "hexadecimal";\r
+ }\r
+ SIGNAL aab\r
+ {\r
+ format = "Logic";\r
+ name = "i_readdatavalid";\r
+ radix = "hexadecimal";\r
+ }\r
+ SIGNAL aac\r
+ {\r
+ format = "Logic";\r
+ name = "i_waitrequest";\r
+ radix = "hexadecimal";\r
+ }\r
+ SIGNAL aad\r
+ {\r
+ format = "Logic";\r
+ name = "i_address";\r
+ radix = "hexadecimal";\r
+ }\r
+ SIGNAL aae\r
+ {\r
+ format = "Logic";\r
+ name = "i_read";\r
+ radix = "hexadecimal";\r
+ }\r
+ SIGNAL aaf\r
+ {\r
+ format = "Logic";\r
+ name = "clk";\r
+ radix = "hexadecimal";\r
+ }\r
+ SIGNAL aag\r
+ {\r
+ format = "Logic";\r
+ name = "reset_n";\r
+ radix = "hexadecimal";\r
+ }\r
+ SIGNAL aah\r
+ {\r
+ format = "Logic";\r
+ name = "d_readdata";\r
+ radix = "hexadecimal";\r
+ }\r
+ SIGNAL aai\r
+ {\r
+ format = "Logic";\r
+ name = "d_waitrequest";\r
+ radix = "hexadecimal";\r
+ }\r
+ SIGNAL aaj\r
+ {\r
+ format = "Logic";\r
+ name = "d_irq";\r
+ radix = "hexadecimal";\r
+ }\r
+ SIGNAL aak\r
+ {\r
+ format = "Logic";\r
+ name = "d_address";\r
+ radix = "hexadecimal";\r
+ }\r
+ SIGNAL aal\r
+ {\r
+ format = "Logic";\r
+ name = "d_byteenable";\r
+ radix = "hexadecimal";\r
+ }\r
+ SIGNAL aam\r
+ {\r
+ format = "Logic";\r
+ name = "d_read";\r
+ radix = "hexadecimal";\r
+ }\r
+ SIGNAL aan\r
+ {\r
+ format = "Logic";\r
+ name = "d_write";\r
+ radix = "hexadecimal";\r
+ }\r
+ SIGNAL aao\r
+ {\r
+ format = "Logic";\r
+ name = "d_writedata";\r
+ radix = "hexadecimal";\r
+ }\r
+ SIGNAL aap\r
+ {\r
+ format = "Divider";\r
+ name = "base pipeline";\r
+ radix = "";\r
+ }\r
+ SIGNAL aaq\r
+ {\r
+ format = "Logic";\r
+ name = "clk";\r
+ radix = "hexadecimal";\r
+ }\r
+ SIGNAL aar\r
+ {\r
+ format = "Logic";\r
+ name = "reset_n";\r
+ radix = "hexadecimal";\r
+ }\r
+ SIGNAL aas\r
+ {\r
+ format = "Logic";\r
+ name = "M_stall";\r
+ radix = "hexadecimal";\r
+ }\r
+ SIGNAL aat\r
+ {\r
+ format = "Logic";\r
+ name = "F_pcb_nxt";\r
+ radix = "hexadecimal";\r
+ }\r
+ SIGNAL aau\r
+ {\r
+ format = "Logic";\r
+ name = "F_pcb";\r
+ radix = "hexadecimal";\r
+ }\r
+ SIGNAL aav\r
+ {\r
+ format = "Logic";\r
+ name = "D_pcb";\r
+ radix = "hexadecimal";\r
+ }\r
+ SIGNAL aaw\r
+ {\r
+ format = "Logic";\r
+ name = "E_pcb";\r
+ radix = "hexadecimal";\r
+ }\r
+ SIGNAL aax\r
+ {\r
+ format = "Logic";\r
+ name = "M_pcb";\r
+ radix = "hexadecimal";\r
+ }\r
+ SIGNAL aay\r
+ {\r
+ format = "Logic";\r
+ name = "W_pcb";\r
+ radix = "hexadecimal";\r
+ }\r
+ SIGNAL aaz\r
+ {\r
+ format = "Logic";\r
+ name = "F_vinst";\r
+ radix = "ascii";\r
+ }\r
+ SIGNAL aba\r
+ {\r
+ format = "Logic";\r
+ name = "D_vinst";\r
+ radix = "ascii";\r
+ }\r
+ SIGNAL abb\r
+ {\r
+ format = "Logic";\r
+ name = "E_vinst";\r
+ radix = "ascii";\r
+ }\r
+ SIGNAL abc\r
+ {\r
+ format = "Logic";\r
+ name = "M_vinst";\r
+ radix = "ascii";\r
+ }\r
+ SIGNAL abd\r
+ {\r
+ format = "Logic";\r
+ name = "W_vinst";\r
+ radix = "ascii";\r
+ }\r
+ SIGNAL abe\r
+ {\r
+ format = "Logic";\r
+ name = "F_inst_ram_hit";\r
+ radix = "hexadecimal";\r
+ }\r
+ SIGNAL abf\r
+ {\r
+ format = "Logic";\r
+ name = "F_issue";\r
+ radix = "hexadecimal";\r
+ }\r
+ SIGNAL abg\r
+ {\r
+ format = "Logic";\r
+ name = "F_kill";\r
+ radix = "hexadecimal";\r
+ }\r
+ SIGNAL abh\r
+ {\r
+ format = "Logic";\r
+ name = "D_kill";\r
+ radix = "hexadecimal";\r
+ }\r
+ SIGNAL abi\r
+ {\r
+ format = "Logic";\r
+ name = "D_refetch";\r
+ radix = "hexadecimal";\r
+ }\r
+ SIGNAL abj\r
+ {\r
+ format = "Logic";\r
+ name = "D_issue";\r
+ radix = "hexadecimal";\r
+ }\r
+ SIGNAL abk\r
+ {\r
+ format = "Logic";\r
+ name = "D_valid";\r
+ radix = "hexadecimal";\r
+ }\r
+ SIGNAL abl\r
+ {\r
+ format = "Logic";\r
+ name = "E_valid";\r
+ radix = "hexadecimal";\r
+ }\r
+ SIGNAL abm\r
+ {\r
+ format = "Logic";\r
+ name = "M_valid";\r
+ radix = "hexadecimal";\r
+ }\r
+ SIGNAL abn\r
+ {\r
+ format = "Logic";\r
+ name = "W_valid";\r
+ radix = "hexadecimal";\r
+ }\r
+ SIGNAL abo\r
+ {\r
+ format = "Logic";\r
+ name = "W_wr_dst_reg";\r
+ radix = "hexadecimal";\r
+ }\r
+ SIGNAL abp\r
+ {\r
+ format = "Logic";\r
+ name = "W_dst_regnum";\r
+ radix = "hexadecimal";\r
+ }\r
+ SIGNAL abq\r
+ {\r
+ format = "Logic";\r
+ name = "W_wr_data";\r
+ radix = "hexadecimal";\r
+ }\r
+ SIGNAL abr\r
+ {\r
+ format = "Logic";\r
+ name = "F_en";\r
+ radix = "hexadecimal";\r
+ }\r
+ SIGNAL abs\r
+ {\r
+ format = "Logic";\r
+ name = "D_en";\r
+ radix = "hexadecimal";\r
+ }\r
+ SIGNAL abt\r
+ {\r
+ format = "Logic";\r
+ name = "E_en";\r
+ radix = "hexadecimal";\r
+ }\r
+ SIGNAL abu\r
+ {\r
+ format = "Logic";\r
+ name = "M_en";\r
+ radix = "hexadecimal";\r
+ }\r
+ SIGNAL abv\r
+ {\r
+ format = "Logic";\r
+ name = "F_iw";\r
+ radix = "hexadecimal";\r
+ }\r
+ SIGNAL abw\r
+ {\r
+ format = "Logic";\r
+ name = "D_iw";\r
+ radix = "hexadecimal";\r
+ }\r
+ SIGNAL abx\r
+ {\r
+ format = "Logic";\r
+ name = "E_iw";\r
+ radix = "hexadecimal";\r
+ }\r
+ SIGNAL aby\r
+ {\r
+ format = "Logic";\r
+ name = "E_valid_prior_to_hbreak";\r
+ radix = "hexadecimal";\r
+ }\r
+ SIGNAL abz\r
+ {\r
+ format = "Logic";\r
+ name = "M_pipe_flush_nxt";\r
+ radix = "hexadecimal";\r
+ }\r
+ SIGNAL aca\r
+ {\r
+ format = "Logic";\r
+ name = "M_pipe_flush_baddr_nxt";\r
+ radix = "hexadecimal";\r
+ }\r
+ SIGNAL acb\r
+ {\r
+ format = "Logic";\r
+ name = "M_status_reg_pie";\r
+ radix = "hexadecimal";\r
+ }\r
+ SIGNAL acc\r
+ {\r
+ format = "Logic";\r
+ name = "M_ienable_reg";\r
+ radix = "hexadecimal";\r
+ }\r
+ SIGNAL acd\r
+ {\r
+ format = "Logic";\r
+ name = "intr_req";\r
+ radix = "hexadecimal";\r
+ }\r
+ }\r
+ }\r
+ }\r
+ MODULE onchip_memory\r
+ {\r
+ SLAVE s1\r
+ {\r
+ PORT_WIRING \r
+ {\r
+ PORT clk\r
+ {\r
+ type = "clk";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT reset_n\r
+ {\r
+ type = "reset_n";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "0";\r
+ }\r
+ PORT address\r
+ {\r
+ type = "address";\r
+ width = "11";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT chipselect\r
+ {\r
+ type = "chipselect";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT clken\r
+ {\r
+ type = "clken";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ default_value = "1'b1";\r
+ }\r
+ PORT read\r
+ {\r
+ type = "read";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "0";\r
+ }\r
+ PORT readdata\r
+ {\r
+ type = "readdata";\r
+ width = "32";\r
+ direction = "output";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT write\r
+ {\r
+ type = "write";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT writedata\r
+ {\r
+ type = "writedata";\r
+ width = "32";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT debugaccess\r
+ {\r
+ type = "debugaccess";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "0";\r
+ }\r
+ PORT byteenable\r
+ {\r
+ type = "byteenable";\r
+ width = "4";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ }\r
+ SYSTEM_BUILDER_INFO \r
+ {\r
+ Bus_Type = "avalon";\r
+ Write_Wait_States = "0cycles";\r
+ Read_Wait_States = "0cycles";\r
+ Hold_Time = "0cycles";\r
+ Setup_Time = "0cycles";\r
+ Is_Printable_Device = "0";\r
+ Address_Alignment = "dynamic";\r
+ Well_Behaved_Waitrequest = "0";\r
+ Is_Nonvolatile_Storage = "0";\r
+ Address_Span = "8192";\r
+ Read_Latency = "1";\r
+ Is_Memory_Device = "1";\r
+ Maximum_Pending_Read_Transactions = "0";\r
+ Minimum_Uninterrupted_Run_Length = "1";\r
+ Accepts_Internal_Connections = "1";\r
+ Write_Latency = "0";\r
+ Is_Flash = "0";\r
+ Data_Width = "32";\r
+ Address_Width = "11";\r
+ Maximum_Burst_Size = "1";\r
+ Register_Incoming_Signals = "0";\r
+ Register_Outgoing_Signals = "0";\r
+ Interleave_Bursts = "0";\r
+ Linewrap_Bursts = "0";\r
+ Burst_On_Burst_Boundaries_Only = "0";\r
+ Always_Burst_Max_Burst = "0";\r
+ Is_Big_Endian = "0";\r
+ Is_Enabled = "1";\r
+ MASTERED_BY cpu_0/instruction_master\r
+ {\r
+ priority = "1";\r
+ Offset_Address = "0x00904000";\r
+ }\r
+ MASTERED_BY cpu_0/data_master\r
+ {\r
+ priority = "1";\r
+ Offset_Address = "0x00904000";\r
+ }\r
+ Base_Address = "0x00904000";\r
+ Address_Group = "0";\r
+ Has_IRQ = "0";\r
+ Is_Channel = "1";\r
+ Is_Writable = "1";\r
+ IRQ_MASTER cpu_0/data_master\r
+ {\r
+ IRQ_Number = "NC";\r
+ }\r
+ }\r
+ }\r
+ iss_model_name = "altera_memory";\r
+ WIZARD_SCRIPT_ARGUMENTS \r
+ {\r
+ allow_mram_sim_contents_only_file = "0";\r
+ ram_block_type = "AUTO";\r
+ init_contents_file = "onchip_memory";\r
+ non_default_init_file_enabled = "0";\r
+ gui_ram_block_type = "Automatic";\r
+ Writeable = "1";\r
+ dual_port = "0";\r
+ Size_Value = "8192";\r
+ Size_Multiple = "1";\r
+ use_shallow_mem_blocks = "0";\r
+ init_mem_content = "1";\r
+ allow_in_system_memory_content_editor = "0";\r
+ instance_id = "NONE";\r
+ read_during_write_mode = "DONT_CARE";\r
+ ignore_auto_block_type_assignment = "1";\r
+ MAKE \r
+ {\r
+ TARGET delete_placeholder_warning\r
+ {\r
+ onchip_memory \r
+ {\r
+ Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt";\r
+ Is_Phony = "1";\r
+ Target_File = "do_delete_placeholder_warning";\r
+ }\r
+ }\r
+ TARGET hex\r
+ {\r
+ onchip_memory \r
+ {\r
+ Command1 = "@echo Post-processing to create $(notdir $@)";\r
+ Command2 = "elf2hex $(ELF) 0x00904000 0x905FFF --width=32 $(QUARTUS_PROJECT_DIR)/onchip_memory.hex --create-lanes=0 ";\r
+ Dependency = "$(ELF)";\r
+ Target_File = "$(QUARTUS_PROJECT_DIR)/onchip_memory.hex";\r
+ }\r
+ }\r
+ TARGET sim\r
+ {\r
+ onchip_memory \r
+ {\r
+ Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";\r
+ Command2 = "@echo Hardware simulation is not enabled for the target SOPC Builder system. Skipping creation of hardware simulation model contents and simulation symbol files. \\(Note: This does not affect the instruction set simulator.\\)";\r
+ Command3 = "touch $(SIMDIR)/dummy_file";\r
+ Dependency = "$(ELF)";\r
+ Target_File = "$(SIMDIR)/dummy_file";\r
+ }\r
+ }\r
+ }\r
+ contents_info = "";\r
+ }\r
+ SIMULATION \r
+ {\r
+ DISPLAY \r
+ {\r
+ SIGNAL a\r
+ {\r
+ name = "chipselect";\r
+ conditional = "1";\r
+ }\r
+ SIGNAL c\r
+ {\r
+ name = "address";\r
+ radix = "hexadecimal";\r
+ }\r
+ SIGNAL d\r
+ {\r
+ name = "byteenable";\r
+ radix = "binary";\r
+ conditional = "1";\r
+ }\r
+ SIGNAL e\r
+ {\r
+ name = "readdata";\r
+ radix = "hexadecimal";\r
+ }\r
+ SIGNAL b\r
+ {\r
+ name = "write";\r
+ conditional = "1";\r
+ }\r
+ SIGNAL f\r
+ {\r
+ name = "writedata";\r
+ radix = "hexadecimal";\r
+ conditional = "1";\r
+ }\r
+ }\r
+ }\r
+ SYSTEM_BUILDER_INFO \r
+ {\r
+ Prohibited_Device_Family = "MERCURY, APEX20K, APEX20KE, APEX20KC, APEXII, ACEX1K, FLEX10KE, EXCALIBUR_ARM, MAXII";\r
+ Instantiate_In_System_Module = "1";\r
+ Is_Enabled = "1";\r
+ Default_Module_Name = "onchip_memory";\r
+ Top_Level_Ports_Are_Enumerated = "1";\r
+ Clock_Source = "clk";\r
+ Has_Clock = "1";\r
+ View \r
+ {\r
+ MESSAGES \r
+ {\r
+ }\r
+ }\r
+ }\r
+ class = "altera_avalon_onchip_memory2";\r
+ class_version = "7.08";\r
+ HDL_INFO \r
+ {\r
+ Precompiled_Simulation_Library_Files = "";\r
+ Simulation_HDL_Files = "";\r
+ Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/onchip_memory.vhd";\r
+ Synthesis_Only_Files = "";\r
+ }\r
+ SLAVE s2\r
+ {\r
+ PORT_WIRING \r
+ {\r
+ }\r
+ SYSTEM_BUILDER_INFO \r
+ {\r
+ Bus_Type = "avalon";\r
+ Is_Memory_Device = "1";\r
+ Address_Group = "0";\r
+ Address_Alignment = "dynamic";\r
+ Address_Width = "11";\r
+ Data_Width = "32";\r
+ Has_IRQ = "0";\r
+ Read_Wait_States = "0";\r
+ Write_Wait_States = "0";\r
+ Address_Span = "8192";\r
+ Read_Latency = "1";\r
+ Is_Channel = "1";\r
+ Is_Enabled = "0";\r
+ Is_Writable = "1";\r
+ }\r
+ }\r
+ PORT_WIRING \r
+ {\r
+ }\r
+ }\r
+ MODULE jtag_uart_0\r
+ {\r
+ SLAVE avalon_jtag_slave\r
+ {\r
+ PORT_WIRING \r
+ {\r
+ PORT clk\r
+ {\r
+ type = "clk";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT reset_n\r
+ {\r
+ type = "reset_n";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "0";\r
+ }\r
+ PORT av_irq\r
+ {\r
+ type = "irq";\r
+ width = "1";\r
+ direction = "output";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT av_chipselect\r
+ {\r
+ type = "chipselect";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT av_address\r
+ {\r
+ type = "address";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT av_read_n\r
+ {\r
+ type = "read_n";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT av_readdata\r
+ {\r
+ type = "readdata";\r
+ width = "32";\r
+ direction = "output";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT av_write_n\r
+ {\r
+ type = "write_n";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT av_writedata\r
+ {\r
+ type = "writedata";\r
+ width = "32";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT av_waitrequest\r
+ {\r
+ type = "waitrequest";\r
+ width = "1";\r
+ direction = "output";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT dataavailable\r
+ {\r
+ type = "dataavailable";\r
+ width = "1";\r
+ direction = "output";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT readyfordata\r
+ {\r
+ type = "readyfordata";\r
+ width = "1";\r
+ direction = "output";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT rst_n\r
+ {\r
+ type = "reset_n";\r
+ direction = "input";\r
+ width = "1";\r
+ Is_Enabled = "1";\r
+ }\r
+ }\r
+ SYSTEM_BUILDER_INFO \r
+ {\r
+ Has_IRQ = "1";\r
+ Bus_Type = "avalon";\r
+ Read_Wait_States = "peripheral_controlled";\r
+ Write_Wait_States = "peripheral_controlled";\r
+ Hold_Time = "0cycles";\r
+ Setup_Time = "0cycles";\r
+ Is_Printable_Device = "1";\r
+ Address_Alignment = "native";\r
+ Well_Behaved_Waitrequest = "0";\r
+ Is_Nonvolatile_Storage = "0";\r
+ Read_Latency = "0";\r
+ Is_Memory_Device = "0";\r
+ Maximum_Pending_Read_Transactions = "0";\r
+ Minimum_Uninterrupted_Run_Length = "1";\r
+ Accepts_Internal_Connections = "1";\r
+ Write_Latency = "0";\r
+ Is_Flash = "0";\r
+ Data_Width = "32";\r
+ Address_Width = "1";\r
+ Maximum_Burst_Size = "1";\r
+ Register_Incoming_Signals = "0";\r
+ Register_Outgoing_Signals = "0";\r
+ Interleave_Bursts = "0";\r
+ Linewrap_Bursts = "0";\r
+ Burst_On_Burst_Boundaries_Only = "0";\r
+ Always_Burst_Max_Burst = "0";\r
+ Is_Big_Endian = "0";\r
+ Is_Enabled = "1";\r
+ JTAG_Hub_Base_Id = "262254";\r
+ JTAG_Hub_Instance_Id = "0";\r
+ Connection_Limit = "1";\r
+ MASTERED_BY cpu_0/data_master\r
+ {\r
+ priority = "1";\r
+ Offset_Address = "0x009000d0";\r
+ }\r
+ IRQ_MASTER cpu_0/data_master\r
+ {\r
+ IRQ_Number = "1";\r
+ }\r
+ Base_Address = "0x009000d0";\r
+ Address_Group = "0";\r
+ }\r
+ }\r
+ class = "altera_avalon_jtag_uart";\r
+ class_version = "7.08";\r
+ iss_model_name = "altera_avalon_jtag_uart";\r
+ WIZARD_SCRIPT_ARGUMENTS \r
+ {\r
+ write_depth = "64";\r
+ read_depth = "64";\r
+ write_threshold = "8";\r
+ read_threshold = "8";\r
+ read_char_stream = "";\r
+ showascii = "1";\r
+ read_le = "0";\r
+ write_le = "0";\r
+ altera_show_unreleased_jtag_uart_features = "0";\r
+ }\r
+ SIMULATION \r
+ {\r
+ DISPLAY \r
+ {\r
+ SIGNAL av_chipselect\r
+ {\r
+ name = "av_chipselect";\r
+ }\r
+ SIGNAL av_address\r
+ {\r
+ name = "av_address";\r
+ radix = "hexadecimal";\r
+ }\r
+ SIGNAL av_read_n\r
+ {\r
+ name = "av_read_n";\r
+ }\r
+ SIGNAL av_readdata\r
+ {\r
+ name = "av_readdata";\r
+ radix = "hexadecimal";\r
+ }\r
+ SIGNAL av_write_n\r
+ {\r
+ name = "av_write_n";\r
+ }\r
+ SIGNAL av_writedata\r
+ {\r
+ name = "av_writedata";\r
+ radix = "hexadecimal";\r
+ }\r
+ SIGNAL av_waitrequest\r
+ {\r
+ name = "av_waitrequest";\r
+ }\r
+ SIGNAL dataavailable\r
+ {\r
+ name = "dataavailable";\r
+ }\r
+ SIGNAL readyfordata\r
+ {\r
+ name = "readyfordata";\r
+ }\r
+ SIGNAL av_irq\r
+ {\r
+ name = "av_irq";\r
+ }\r
+ }\r
+ INTERACTIVE_IN drive\r
+ {\r
+ enable = "0";\r
+ file = "_input_data_stream.dat";\r
+ mutex = "_input_data_mutex.dat";\r
+ log = "_in.log";\r
+ rate = "100";\r
+ signals = "temp,list";\r
+ exe = "nios2-terminal";\r
+ }\r
+ INTERACTIVE_OUT log\r
+ {\r
+ enable = "1";\r
+ exe = "perl -- atail-f.pl";\r
+ file = "_output_stream.dat";\r
+ radix = "ascii";\r
+ signals = "temp,list";\r
+ }\r
+ Fix_Me_Up = "";\r
+ }\r
+ SYSTEM_BUILDER_INFO \r
+ {\r
+ Is_Enabled = "1";\r
+ Clock_Source = "clk";\r
+ Has_Clock = "1";\r
+ Instantiate_In_System_Module = "1";\r
+ Iss_Launch_Telnet = "0";\r
+ Top_Level_Ports_Are_Enumerated = "1";\r
+ View \r
+ {\r
+ MESSAGES \r
+ {\r
+ }\r
+ Settings_Summary = "<br>Write Depth: 64; Write IRQ Threshold: 8
+ <br>Read Depth: 64; Read IRQ Threshold: 8";\r
+ }\r
+ }\r
+ HDL_INFO \r
+ {\r
+ Precompiled_Simulation_Library_Files = "";\r
+ Simulation_HDL_Files = "";\r
+ Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/jtag_uart_0.vhd";\r
+ Synthesis_Only_Files = "";\r
+ }\r
+ PORT_WIRING \r
+ {\r
+ }\r
+ }\r
+ MODULE sdram\r
+ {\r
+ SLAVE s1\r
+ {\r
+ PORT_WIRING \r
+ {\r
+ PORT clk\r
+ {\r
+ type = "clk";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT reset_n\r
+ {\r
+ type = "reset_n";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT az_addr\r
+ {\r
+ type = "address";\r
+ width = "22";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT az_be_n\r
+ {\r
+ type = "byteenable_n";\r
+ width = "4";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT az_cs\r
+ {\r
+ type = "chipselect";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT az_data\r
+ {\r
+ type = "writedata";\r
+ width = "32";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT az_rd_n\r
+ {\r
+ type = "read_n";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT az_wr_n\r
+ {\r
+ type = "write_n";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT za_data\r
+ {\r
+ type = "readdata";\r
+ width = "32";\r
+ direction = "output";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT za_valid\r
+ {\r
+ type = "readdatavalid";\r
+ width = "1";\r
+ direction = "output";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT za_waitrequest\r
+ {\r
+ type = "waitrequest";\r
+ width = "1";\r
+ direction = "output";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT zs_addr\r
+ {\r
+ direction = "output";\r
+ width = "12";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT zs_ba\r
+ {\r
+ direction = "output";\r
+ width = "2";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT zs_cas_n\r
+ {\r
+ direction = "output";\r
+ width = "1";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT zs_cke\r
+ {\r
+ direction = "output";\r
+ width = "1";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT zs_cs_n\r
+ {\r
+ direction = "output";\r
+ width = "1";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT zs_dq\r
+ {\r
+ direction = "inout";\r
+ width = "32";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT zs_dqm\r
+ {\r
+ direction = "output";\r
+ width = "4";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT zs_ras_n\r
+ {\r
+ direction = "output";\r
+ width = "1";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT zs_we_n\r
+ {\r
+ direction = "output";\r
+ width = "1";\r
+ Is_Enabled = "1";\r
+ }\r
+ }\r
+ SYSTEM_BUILDER_INFO \r
+ {\r
+ Bus_Type = "avalon";\r
+ Read_Wait_States = "peripheral_controlled";\r
+ Write_Wait_States = "peripheral_controlled";\r
+ Hold_Time = "0cycles";\r
+ Setup_Time = "0cycles";\r
+ Is_Printable_Device = "0";\r
+ Address_Alignment = "dynamic";\r
+ Well_Behaved_Waitrequest = "0";\r
+ Is_Nonvolatile_Storage = "0";\r
+ Address_Span = "16777216";\r
+ Read_Latency = "0";\r
+ Is_Memory_Device = "1";\r
+ Maximum_Pending_Read_Transactions = "6";\r
+ Minimum_Uninterrupted_Run_Length = "1";\r
+ Accepts_Internal_Connections = "1";\r
+ Write_Latency = "0";\r
+ Is_Flash = "0";\r
+ Data_Width = "32";\r
+ Address_Width = "22";\r
+ Maximum_Burst_Size = "1";\r
+ Register_Incoming_Signals = "0";\r
+ Register_Outgoing_Signals = "0";\r
+ Interleave_Bursts = "0";\r
+ Linewrap_Bursts = "0";\r
+ Burst_On_Burst_Boundaries_Only = "0";\r
+ Always_Burst_Max_Burst = "0";\r
+ Is_Big_Endian = "0";\r
+ Is_Enabled = "1";\r
+ MASTERED_BY cpu_0/instruction_master\r
+ {\r
+ priority = "1";\r
+ Offset_Address = "0x01000000";\r
+ }\r
+ MASTERED_BY cpu_0/data_master\r
+ {\r
+ priority = "1";\r
+ Offset_Address = "0x01000000";\r
+ }\r
+ Base_Address = "0x01000000";\r
+ Has_IRQ = "0";\r
+ Simulation_Num_Lanes = "1";\r
+ Address_Group = "0";\r
+ IRQ_MASTER cpu_0/data_master\r
+ {\r
+ IRQ_Number = "NC";\r
+ }\r
+ }\r
+ }\r
+ PORT_WIRING \r
+ {\r
+ PORT zs_addr\r
+ {\r
+ type = "export";\r
+ width = "12";\r
+ direction = "output";\r
+ Is_Enabled = "0";\r
+ }\r
+ PORT zs_ba\r
+ {\r
+ type = "export";\r
+ width = "2";\r
+ direction = "output";\r
+ Is_Enabled = "0";\r
+ }\r
+ PORT zs_cas_n\r
+ {\r
+ type = "export";\r
+ width = "1";\r
+ direction = "output";\r
+ Is_Enabled = "0";\r
+ }\r
+ PORT zs_cke\r
+ {\r
+ type = "export";\r
+ width = "1";\r
+ direction = "output";\r
+ Is_Enabled = "0";\r
+ }\r
+ PORT zs_cs_n\r
+ {\r
+ type = "export";\r
+ width = "1";\r
+ direction = "output";\r
+ Is_Enabled = "0";\r
+ }\r
+ PORT zs_dq\r
+ {\r
+ type = "export";\r
+ width = "32";\r
+ direction = "output";\r
+ Is_Enabled = "0";\r
+ }\r
+ PORT zs_dqm\r
+ {\r
+ type = "export";\r
+ width = "4";\r
+ direction = "output";\r
+ Is_Enabled = "0";\r
+ }\r
+ PORT zs_ras_n\r
+ {\r
+ type = "export";\r
+ width = "1";\r
+ direction = "output";\r
+ Is_Enabled = "0";\r
+ }\r
+ PORT zs_we_n\r
+ {\r
+ type = "export";\r
+ width = "1";\r
+ direction = "output";\r
+ Is_Enabled = "0";\r
+ }\r
+ }\r
+ iss_model_name = "altera_memory";\r
+ WIZARD_SCRIPT_ARGUMENTS \r
+ {\r
+ register_data_in = "1";\r
+ sim_model_base = "0";\r
+ sdram_data_width = "32";\r
+ sdram_addr_width = "12";\r
+ sdram_row_width = "12";\r
+ sdram_col_width = "8";\r
+ sdram_num_chipselects = "1";\r
+ sdram_num_banks = "4";\r
+ refresh_period = "15.625";\r
+ powerup_delay = "100.0";\r
+ cas_latency = "2";\r
+ t_rfc = "70.0";\r
+ t_rp = "15.0";\r
+ t_mrd = "3";\r
+ t_rcd = "15.0";\r
+ t_ac = "6.0";\r
+ t_wr = "14.0";\r
+ init_refresh_commands = "2";\r
+ init_nop_delay = "0.0";\r
+ shared_data = "0";\r
+ sdram_bank_width = "2";\r
+ tristate_bridge_slave = "";\r
+ starvation_indicator = "0";\r
+ is_initialized = "1";\r
+ }\r
+ SIMULATION \r
+ {\r
+ DISPLAY \r
+ {\r
+ SIGNAL a\r
+ {\r
+ name = "az_addr";\r
+ radix = "hexadecimal";\r
+ }\r
+ SIGNAL b\r
+ {\r
+ name = "az_be_n";\r
+ radix = "hexadecimal";\r
+ }\r
+ SIGNAL c\r
+ {\r
+ name = "az_cs";\r
+ }\r
+ SIGNAL d\r
+ {\r
+ name = "az_data";\r
+ radix = "hexadecimal";\r
+ }\r
+ SIGNAL e\r
+ {\r
+ name = "az_rd_n";\r
+ }\r
+ SIGNAL f\r
+ {\r
+ name = "az_wr_n";\r
+ }\r
+ SIGNAL h\r
+ {\r
+ name = "za_data";\r
+ radix = "hexadecimal";\r
+ }\r
+ SIGNAL i\r
+ {\r
+ name = "za_valid";\r
+ }\r
+ SIGNAL j\r
+ {\r
+ name = "za_waitrequest";\r
+ }\r
+ SIGNAL l\r
+ {\r
+ name = "CODE";\r
+ radix = "ascii";\r
+ }\r
+ SIGNAL g\r
+ {\r
+ name = "clk";\r
+ }\r
+ SIGNAL k\r
+ {\r
+ name = "za_cannotrefresh";\r
+ suppress = "1";\r
+ }\r
+ SIGNAL m\r
+ {\r
+ name = "zs_addr";\r
+ radix = "hexadecimal";\r
+ suppress = "0";\r
+ }\r
+ SIGNAL n\r
+ {\r
+ name = "zs_ba";\r
+ radix = "hexadecimal";\r
+ suppress = "0";\r
+ }\r
+ SIGNAL o\r
+ {\r
+ name = "zs_cs_n";\r
+ radix = "hexadecimal";\r
+ suppress = "0";\r
+ }\r
+ SIGNAL p\r
+ {\r
+ name = "zs_ras_n";\r
+ suppress = "0";\r
+ }\r
+ SIGNAL q\r
+ {\r
+ name = "zs_cas_n";\r
+ suppress = "0";\r
+ }\r
+ SIGNAL r\r
+ {\r
+ name = "zs_we_n";\r
+ suppress = "0";\r
+ }\r
+ SIGNAL s\r
+ {\r
+ name = "zs_dq";\r
+ radix = "hexadecimal";\r
+ suppress = "0";\r
+ }\r
+ SIGNAL t\r
+ {\r
+ name = "zs_dqm";\r
+ radix = "hexadecimal";\r
+ suppress = "0";\r
+ }\r
+ SIGNAL u\r
+ {\r
+ name = "zt_addr";\r
+ radix = "hexadecimal";\r
+ suppress = "1";\r
+ }\r
+ SIGNAL v\r
+ {\r
+ name = "zt_ba";\r
+ radix = "hexadecimal";\r
+ suppress = "1";\r
+ }\r
+ SIGNAL w\r
+ {\r
+ name = "zt_oe";\r
+ suppress = "1";\r
+ }\r
+ SIGNAL x\r
+ {\r
+ name = "zt_cke";\r
+ suppress = "1";\r
+ }\r
+ SIGNAL y\r
+ {\r
+ name = "zt_chipselect";\r
+ suppress = "1";\r
+ }\r
+ SIGNAL z0\r
+ {\r
+ name = "zt_lock_n";\r
+ suppress = "1";\r
+ }\r
+ SIGNAL z1\r
+ {\r
+ name = "zt_ras_n";\r
+ suppress = "1";\r
+ }\r
+ SIGNAL z2\r
+ {\r
+ name = "zt_cas_n";\r
+ suppress = "1";\r
+ }\r
+ SIGNAL z3\r
+ {\r
+ name = "zt_we_n";\r
+ suppress = "1";\r
+ }\r
+ SIGNAL z4\r
+ {\r
+ name = "zt_cs_n";\r
+ radix = "hexadecimal";\r
+ suppress = "1";\r
+ }\r
+ SIGNAL z5\r
+ {\r
+ name = "zt_dqm";\r
+ radix = "hexadecimal";\r
+ suppress = "1";\r
+ }\r
+ SIGNAL z6\r
+ {\r
+ name = "zt_data";\r
+ radix = "hexadecimal";\r
+ suppress = "1";\r
+ }\r
+ SIGNAL z7\r
+ {\r
+ name = "tz_data";\r
+ radix = "hexadecimal";\r
+ suppress = "1";\r
+ }\r
+ SIGNAL z8\r
+ {\r
+ name = "tz_waitrequest";\r
+ suppress = "1";\r
+ }\r
+ }\r
+ Fix_Me_Up = "";\r
+ }\r
+ SYSTEM_BUILDER_INFO \r
+ {\r
+ Instantiate_In_System_Module = "1";\r
+ Is_Enabled = "1";\r
+ Default_Module_Name = "sdram";\r
+ Top_Level_Ports_Are_Enumerated = "1";\r
+ Clock_Source = "clk";\r
+ Has_Clock = "1";\r
+ Disable_Simulation_Port_Wiring = "0";\r
+ View \r
+ {\r
+ MESSAGES \r
+ {\r
+ }\r
+ Settings_Summary = "4194304 x 32<br>
+ Memory size: 16 MBytes<br>
+ 128 MBits
+ ";\r
+ }\r
+ }\r
+ class = "altera_avalon_new_sdram_controller";\r
+ class_version = "7.08";\r
+ HDL_INFO \r
+ {\r
+ Precompiled_Simulation_Library_Files = "";\r
+ Simulation_HDL_Files = "";\r
+ Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/sdram.vhd";\r
+ Synthesis_Only_Files = "";\r
+ }\r
+ }\r
+ MODULE sysid\r
+ {\r
+ SLAVE control_slave\r
+ {\r
+ PORT_WIRING \r
+ {\r
+ PORT clock\r
+ {\r
+ type = "clk";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "0";\r
+ }\r
+ PORT reset_n\r
+ {\r
+ type = "reset_n";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "0";\r
+ }\r
+ PORT address\r
+ {\r
+ type = "address";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT readdata\r
+ {\r
+ type = "readdata";\r
+ width = "32";\r
+ direction = "output";\r
+ Is_Enabled = "1";\r
+ }\r
+ }\r
+ SYSTEM_BUILDER_INFO \r
+ {\r
+ Bus_Type = "avalon";\r
+ Write_Wait_States = "0cycles";\r
+ Read_Wait_States = "1cycles";\r
+ Hold_Time = "0cycles";\r
+ Setup_Time = "0cycles";\r
+ Is_Printable_Device = "0";\r
+ Address_Alignment = "native";\r
+ Well_Behaved_Waitrequest = "0";\r
+ Is_Nonvolatile_Storage = "0";\r
+ Read_Latency = "0";\r
+ Is_Memory_Device = "0";\r
+ Maximum_Pending_Read_Transactions = "0";\r
+ Minimum_Uninterrupted_Run_Length = "1";\r
+ Accepts_Internal_Connections = "1";\r
+ Write_Latency = "0";\r
+ Is_Flash = "0";\r
+ Data_Width = "32";\r
+ Address_Width = "1";\r
+ Maximum_Burst_Size = "1";\r
+ Register_Incoming_Signals = "0";\r
+ Register_Outgoing_Signals = "0";\r
+ Interleave_Bursts = "0";\r
+ Linewrap_Bursts = "0";\r
+ Burst_On_Burst_Boundaries_Only = "0";\r
+ Always_Burst_Max_Burst = "0";\r
+ Is_Big_Endian = "0";\r
+ Is_Enabled = "1";\r
+ MASTERED_BY cpu_0/data_master\r
+ {\r
+ priority = "1";\r
+ Offset_Address = "0x009000d8";\r
+ }\r
+ Base_Address = "0x009000d8";\r
+ Has_IRQ = "0";\r
+ Address_Group = "0";\r
+ IRQ_MASTER cpu_0/data_master\r
+ {\r
+ IRQ_Number = "NC";\r
+ }\r
+ }\r
+ }\r
+ class = "altera_avalon_sysid";\r
+ class_version = "7.08";\r
+ SYSTEM_BUILDER_INFO \r
+ {\r
+ Date_Modified = "";\r
+ Is_Enabled = "1";\r
+ Instantiate_In_System_Module = "1";\r
+ Fixed_Module_Name = "sysid";\r
+ Top_Level_Ports_Are_Enumerated = "1";\r
+ Clock_Source = "clk";\r
+ Has_Clock = "1";\r
+ View \r
+ {\r
+ Settings_Summary = "System ID (at last Generate):<br> <b>2A1C5786</b> (unique ID tag) <br> <b>485BC1C0</b> (timestamp: Fri Jun 20, 2008 @4:42 PM)";\r
+ MESSAGES \r
+ {\r
+ }\r
+ }\r
+ }\r
+ WIZARD_SCRIPT_ARGUMENTS \r
+ {\r
+ id = "706500486u";\r
+ timestamp = "1213972928u";\r
+ regenerate_values = "0";\r
+ MAKE \r
+ {\r
+ TARGET verifysysid\r
+ {\r
+ verifysysid \r
+ {\r
+ All_Depends_On = "0";\r
+ Command = "nios2-download $(JTAG_CABLE) --sidp=0x009000d8 --id=706500486 --timestamp=1213972928";\r
+ Is_Phony = "1";\r
+ Target_File = "dummy_verifysysid_file";\r
+ }\r
+ }\r
+ }\r
+ }\r
+ HDL_INFO \r
+ {\r
+ Precompiled_Simulation_Library_Files = "";\r
+ Simulation_HDL_Files = "";\r
+ Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/sysid.vhd";\r
+ Synthesis_Only_Files = "";\r
+ }\r
+ PORT_WIRING \r
+ {\r
+ }\r
+ }\r
+ MODULE LED_Pio\r
+ {\r
+ SLAVE s1\r
+ {\r
+ PORT_WIRING \r
+ {\r
+ PORT clk\r
+ {\r
+ type = "clk";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT reset_n\r
+ {\r
+ type = "reset_n";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT address\r
+ {\r
+ type = "address";\r
+ width = "2";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT write_n\r
+ {\r
+ type = "write_n";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT writedata\r
+ {\r
+ type = "writedata";\r
+ width = "8";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT chipselect\r
+ {\r
+ type = "chipselect";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ }\r
+ SYSTEM_BUILDER_INFO \r
+ {\r
+ Bus_Type = "avalon";\r
+ Write_Wait_States = "0cycles";\r
+ Read_Wait_States = "1cycles";\r
+ Hold_Time = "0cycles";\r
+ Setup_Time = "0cycles";\r
+ Is_Printable_Device = "0";\r
+ Address_Alignment = "native";\r
+ Well_Behaved_Waitrequest = "0";\r
+ Is_Nonvolatile_Storage = "0";\r
+ Read_Latency = "0";\r
+ Is_Memory_Device = "0";\r
+ Maximum_Pending_Read_Transactions = "0";\r
+ Minimum_Uninterrupted_Run_Length = "1";\r
+ Accepts_Internal_Connections = "1";\r
+ Write_Latency = "0";\r
+ Is_Flash = "0";\r
+ Data_Width = "8";\r
+ Address_Width = "2";\r
+ Maximum_Burst_Size = "1";\r
+ Register_Incoming_Signals = "0";\r
+ Register_Outgoing_Signals = "0";\r
+ Interleave_Bursts = "0";\r
+ Linewrap_Bursts = "0";\r
+ Burst_On_Burst_Boundaries_Only = "0";\r
+ Always_Burst_Max_Burst = "0";\r
+ Is_Big_Endian = "0";\r
+ Is_Enabled = "1";\r
+ MASTERED_BY cpu_0/data_master\r
+ {\r
+ priority = "1";\r
+ Offset_Address = "0x00900080";\r
+ }\r
+ Base_Address = "0x00900080";\r
+ Has_IRQ = "0";\r
+ Address_Group = "0";\r
+ IRQ_MASTER cpu_0/data_master\r
+ {\r
+ IRQ_Number = "NC";\r
+ }\r
+ Is_Readable = "0";\r
+ Is_Writable = "1";\r
+ }\r
+ }\r
+ PORT_WIRING \r
+ {\r
+ PORT out_port\r
+ {\r
+ type = "export";\r
+ width = "8";\r
+ direction = "output";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT in_port\r
+ {\r
+ direction = "input";\r
+ Is_Enabled = "0";\r
+ width = "8";\r
+ }\r
+ PORT bidir_port\r
+ {\r
+ direction = "inout";\r
+ Is_Enabled = "0";\r
+ width = "8";\r
+ }\r
+ }\r
+ class = "altera_avalon_pio";\r
+ class_version = "7.08";\r
+ SYSTEM_BUILDER_INFO \r
+ {\r
+ Is_Enabled = "1";\r
+ Instantiate_In_System_Module = "1";\r
+ Wire_Test_Bench_Values = "1";\r
+ Top_Level_Ports_Are_Enumerated = "1";\r
+ Clock_Source = "clk";\r
+ Has_Clock = "1";\r
+ Date_Modified = "";\r
+ View \r
+ {\r
+ MESSAGES \r
+ {\r
+ }\r
+ Settings_Summary = " 8-bit PIO using <br>
+
+
+ output pins";\r
+ }\r
+ }\r
+ WIZARD_SCRIPT_ARGUMENTS \r
+ {\r
+ Do_Test_Bench_Wiring = "0";\r
+ Driven_Sim_Value = "0";\r
+ has_tri = "0";\r
+ has_out = "1";\r
+ has_in = "0";\r
+ capture = "0";\r
+ Data_Width = "8";\r
+ reset_value = "0";\r
+ edge_type = "NONE";\r
+ irq_type = "NONE";\r
+ bit_clearing_edge_register = "0";\r
+ }\r
+ HDL_INFO \r
+ {\r
+ Precompiled_Simulation_Library_Files = "";\r
+ Simulation_HDL_Files = "";\r
+ Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/LED_Pio.vhd";\r
+ Synthesis_Only_Files = "";\r
+ }\r
+ }\r
+ MODULE SG_Pio\r
+ {\r
+ SLAVE s1\r
+ {\r
+ PORT_WIRING \r
+ {\r
+ PORT clk\r
+ {\r
+ type = "clk";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT reset_n\r
+ {\r
+ type = "reset_n";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT address\r
+ {\r
+ type = "address";\r
+ width = "2";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT write_n\r
+ {\r
+ type = "write_n";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT writedata\r
+ {\r
+ type = "writedata";\r
+ width = "14";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT chipselect\r
+ {\r
+ type = "chipselect";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ }\r
+ SYSTEM_BUILDER_INFO \r
+ {\r
+ Bus_Type = "avalon";\r
+ Write_Wait_States = "0cycles";\r
+ Read_Wait_States = "1cycles";\r
+ Hold_Time = "0cycles";\r
+ Setup_Time = "0cycles";\r
+ Is_Printable_Device = "0";\r
+ Address_Alignment = "native";\r
+ Well_Behaved_Waitrequest = "0";\r
+ Is_Nonvolatile_Storage = "0";\r
+ Read_Latency = "0";\r
+ Is_Memory_Device = "0";\r
+ Maximum_Pending_Read_Transactions = "0";\r
+ Minimum_Uninterrupted_Run_Length = "1";\r
+ Accepts_Internal_Connections = "1";\r
+ Write_Latency = "0";\r
+ Is_Flash = "0";\r
+ Data_Width = "14";\r
+ Address_Width = "2";\r
+ Maximum_Burst_Size = "1";\r
+ Register_Incoming_Signals = "0";\r
+ Register_Outgoing_Signals = "0";\r
+ Interleave_Bursts = "0";\r
+ Linewrap_Bursts = "0";\r
+ Burst_On_Burst_Boundaries_Only = "0";\r
+ Always_Burst_Max_Burst = "0";\r
+ Is_Big_Endian = "0";\r
+ Is_Enabled = "1";\r
+ MASTERED_BY cpu_0/data_master\r
+ {\r
+ priority = "1";\r
+ Offset_Address = "0x00900090";\r
+ }\r
+ Base_Address = "0x00900090";\r
+ Has_IRQ = "0";\r
+ Address_Group = "0";\r
+ IRQ_MASTER cpu_0/data_master\r
+ {\r
+ IRQ_Number = "NC";\r
+ }\r
+ Is_Readable = "0";\r
+ Is_Writable = "1";\r
+ }\r
+ }\r
+ PORT_WIRING \r
+ {\r
+ PORT out_port\r
+ {\r
+ type = "export";\r
+ width = "14";\r
+ direction = "output";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT in_port\r
+ {\r
+ direction = "input";\r
+ Is_Enabled = "0";\r
+ width = "14";\r
+ }\r
+ PORT bidir_port\r
+ {\r
+ direction = "inout";\r
+ Is_Enabled = "0";\r
+ width = "14";\r
+ }\r
+ }\r
+ class = "altera_avalon_pio";\r
+ class_version = "7.08";\r
+ SYSTEM_BUILDER_INFO \r
+ {\r
+ Is_Enabled = "1";\r
+ Instantiate_In_System_Module = "1";\r
+ Wire_Test_Bench_Values = "1";\r
+ Top_Level_Ports_Are_Enumerated = "1";\r
+ Clock_Source = "clk";\r
+ Has_Clock = "1";\r
+ Date_Modified = "";\r
+ View \r
+ {\r
+ MESSAGES \r
+ {\r
+ }\r
+ Settings_Summary = " 14-bit PIO using <br>
+
+
+ output pins";\r
+ }\r
+ }\r
+ WIZARD_SCRIPT_ARGUMENTS \r
+ {\r
+ Do_Test_Bench_Wiring = "0";\r
+ Driven_Sim_Value = "0";\r
+ has_tri = "0";\r
+ has_out = "1";\r
+ has_in = "0";\r
+ capture = "0";\r
+ Data_Width = "14";\r
+ reset_value = "0";\r
+ edge_type = "NONE";\r
+ irq_type = "NONE";\r
+ bit_clearing_edge_register = "0";\r
+ }\r
+ HDL_INFO \r
+ {\r
+ Precompiled_Simulation_Library_Files = "";\r
+ Simulation_HDL_Files = "";\r
+ Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/SG_Pio.vhd";\r
+ Synthesis_Only_Files = "";\r
+ }\r
+ }\r
+ MODULE IO_Pio\r
+ {\r
+ SLAVE s1\r
+ {\r
+ PORT_WIRING \r
+ {\r
+ PORT clk\r
+ {\r
+ type = "clk";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT reset_n\r
+ {\r
+ type = "reset_n";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT address\r
+ {\r
+ type = "address";\r
+ width = "2";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT write_n\r
+ {\r
+ type = "write_n";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT writedata\r
+ {\r
+ type = "writedata";\r
+ width = "32";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT chipselect\r
+ {\r
+ type = "chipselect";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT readdata\r
+ {\r
+ type = "readdata";\r
+ width = "32";\r
+ direction = "output";\r
+ Is_Enabled = "1";\r
+ }\r
+ }\r
+ SYSTEM_BUILDER_INFO \r
+ {\r
+ Bus_Type = "avalon";\r
+ Write_Wait_States = "0cycles";\r
+ Read_Wait_States = "1cycles";\r
+ Hold_Time = "0cycles";\r
+ Setup_Time = "0cycles";\r
+ Is_Printable_Device = "0";\r
+ Address_Alignment = "native";\r
+ Well_Behaved_Waitrequest = "0";\r
+ Is_Nonvolatile_Storage = "0";\r
+ Read_Latency = "0";\r
+ Is_Memory_Device = "0";\r
+ Maximum_Pending_Read_Transactions = "0";\r
+ Minimum_Uninterrupted_Run_Length = "1";\r
+ Accepts_Internal_Connections = "1";\r
+ Write_Latency = "0";\r
+ Is_Flash = "0";\r
+ Data_Width = "32";\r
+ Address_Width = "2";\r
+ Maximum_Burst_Size = "1";\r
+ Register_Incoming_Signals = "0";\r
+ Register_Outgoing_Signals = "0";\r
+ Interleave_Bursts = "0";\r
+ Linewrap_Bursts = "0";\r
+ Burst_On_Burst_Boundaries_Only = "0";\r
+ Always_Burst_Max_Burst = "0";\r
+ Is_Big_Endian = "0";\r
+ Is_Enabled = "1";\r
+ MASTERED_BY cpu_0/data_master\r
+ {\r
+ priority = "1";\r
+ Offset_Address = "0x009000a0";\r
+ }\r
+ Base_Address = "0x009000a0";\r
+ Has_IRQ = "0";\r
+ Address_Group = "0";\r
+ IRQ_MASTER cpu_0/data_master\r
+ {\r
+ IRQ_Number = "NC";\r
+ }\r
+ Is_Readable = "1";\r
+ Is_Writable = "1";\r
+ }\r
+ }\r
+ PORT_WIRING \r
+ {\r
+ PORT bidir_port\r
+ {\r
+ type = "export";\r
+ width = "32";\r
+ direction = "inout";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT in_port\r
+ {\r
+ direction = "input";\r
+ Is_Enabled = "0";\r
+ width = "32";\r
+ }\r
+ PORT out_port\r
+ {\r
+ direction = "output";\r
+ Is_Enabled = "0";\r
+ width = "32";\r
+ }\r
+ }\r
+ class = "altera_avalon_pio";\r
+ class_version = "7.08";\r
+ SYSTEM_BUILDER_INFO \r
+ {\r
+ Is_Enabled = "1";\r
+ Instantiate_In_System_Module = "1";\r
+ Wire_Test_Bench_Values = "1";\r
+ Top_Level_Ports_Are_Enumerated = "1";\r
+ Clock_Source = "clk";\r
+ Has_Clock = "1";\r
+ Date_Modified = "";\r
+ View \r
+ {\r
+ MESSAGES \r
+ {\r
+ }\r
+ Settings_Summary = " 32-bit PIO using <br>
+ tri-state pins with edge type NONE and interrupt source NONE
+
+ ";\r
+ }\r
+ }\r
+ WIZARD_SCRIPT_ARGUMENTS \r
+ {\r
+ Do_Test_Bench_Wiring = "0";\r
+ Driven_Sim_Value = "0";\r
+ has_tri = "1";\r
+ has_out = "0";\r
+ has_in = "0";\r
+ capture = "0";\r
+ Data_Width = "32";\r
+ reset_value = "0";\r
+ edge_type = "NONE";\r
+ irq_type = "NONE";\r
+ bit_clearing_edge_register = "0";\r
+ }\r
+ HDL_INFO \r
+ {\r
+ Precompiled_Simulation_Library_Files = "";\r
+ Simulation_HDL_Files = "";\r
+ Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/IO_Pio.vhd";\r
+ Synthesis_Only_Files = "";\r
+ }\r
+ }\r
+ MODULE Button_Pio\r
+ {\r
+ SLAVE s1\r
+ {\r
+ PORT_WIRING \r
+ {\r
+ PORT clk\r
+ {\r
+ type = "clk";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT reset_n\r
+ {\r
+ type = "reset_n";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT address\r
+ {\r
+ type = "address";\r
+ width = "2";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT readdata\r
+ {\r
+ type = "readdata";\r
+ width = "9";\r
+ direction = "output";\r
+ Is_Enabled = "1";\r
+ }\r
+ }\r
+ SYSTEM_BUILDER_INFO \r
+ {\r
+ Bus_Type = "avalon";\r
+ Write_Wait_States = "0cycles";\r
+ Read_Wait_States = "1cycles";\r
+ Hold_Time = "0cycles";\r
+ Setup_Time = "0cycles";\r
+ Is_Printable_Device = "0";\r
+ Address_Alignment = "native";\r
+ Well_Behaved_Waitrequest = "0";\r
+ Is_Nonvolatile_Storage = "0";\r
+ Read_Latency = "0";\r
+ Is_Memory_Device = "0";\r
+ Maximum_Pending_Read_Transactions = "0";\r
+ Minimum_Uninterrupted_Run_Length = "1";\r
+ Accepts_Internal_Connections = "1";\r
+ Write_Latency = "0";\r
+ Is_Flash = "0";\r
+ Data_Width = "9";\r
+ Address_Width = "2";\r
+ Maximum_Burst_Size = "1";\r
+ Register_Incoming_Signals = "0";\r
+ Register_Outgoing_Signals = "0";\r
+ Interleave_Bursts = "0";\r
+ Linewrap_Bursts = "0";\r
+ Burst_On_Burst_Boundaries_Only = "0";\r
+ Always_Burst_Max_Burst = "0";\r
+ Is_Big_Endian = "0";\r
+ Is_Enabled = "1";\r
+ MASTERED_BY cpu_0/data_master\r
+ {\r
+ priority = "1";\r
+ Offset_Address = "0x009000b0";\r
+ }\r
+ Base_Address = "0x009000b0";\r
+ Has_IRQ = "0";\r
+ Address_Group = "0";\r
+ IRQ_MASTER cpu_0/data_master\r
+ {\r
+ IRQ_Number = "NC";\r
+ }\r
+ Is_Readable = "1";\r
+ Is_Writable = "0";\r
+ }\r
+ }\r
+ PORT_WIRING \r
+ {\r
+ PORT in_port\r
+ {\r
+ type = "export";\r
+ width = "9";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT out_port\r
+ {\r
+ direction = "output";\r
+ Is_Enabled = "0";\r
+ width = "9";\r
+ }\r
+ PORT bidir_port\r
+ {\r
+ direction = "inout";\r
+ Is_Enabled = "0";\r
+ width = "9";\r
+ }\r
+ }\r
+ class = "altera_avalon_pio";\r
+ class_version = "7.08";\r
+ SYSTEM_BUILDER_INFO \r
+ {\r
+ Is_Enabled = "1";\r
+ Instantiate_In_System_Module = "1";\r
+ Wire_Test_Bench_Values = "1";\r
+ Top_Level_Ports_Are_Enumerated = "1";\r
+ Clock_Source = "clk";\r
+ Has_Clock = "1";\r
+ Date_Modified = "";\r
+ View \r
+ {\r
+ MESSAGES \r
+ {\r
+ }\r
+ Settings_Summary = " 9-bit PIO using <br>
+
+ input pins with edge type NONE and interrupt source NONE
+ ";\r
+ }\r
+ }\r
+ WIZARD_SCRIPT_ARGUMENTS \r
+ {\r
+ Do_Test_Bench_Wiring = "0";\r
+ Driven_Sim_Value = "0";\r
+ has_tri = "0";\r
+ has_out = "0";\r
+ has_in = "1";\r
+ capture = "0";\r
+ Data_Width = "9";\r
+ reset_value = "0";\r
+ edge_type = "NONE";\r
+ irq_type = "NONE";\r
+ bit_clearing_edge_register = "0";\r
+ }\r
+ HDL_INFO \r
+ {\r
+ Precompiled_Simulation_Library_Files = "";\r
+ Simulation_HDL_Files = "";\r
+ Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/Button_Pio.vhd";\r
+ Synthesis_Only_Files = "";\r
+ }\r
+ }\r
+ MODULE uart\r
+ {\r
+ SLAVE s1\r
+ {\r
+ PORT_WIRING \r
+ {\r
+ PORT clk\r
+ {\r
+ type = "clk";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT reset_n\r
+ {\r
+ type = "reset_n";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT irq\r
+ {\r
+ type = "irq";\r
+ width = "1";\r
+ direction = "output";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT address\r
+ {\r
+ type = "address";\r
+ width = "3";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT begintransfer\r
+ {\r
+ type = "begintransfer";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT chipselect\r
+ {\r
+ type = "chipselect";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT read_n\r
+ {\r
+ type = "read_n";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT write_n\r
+ {\r
+ type = "write_n";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT writedata\r
+ {\r
+ type = "writedata";\r
+ width = "16";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT readdata\r
+ {\r
+ type = "readdata";\r
+ width = "16";\r
+ direction = "output";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT dataavailable\r
+ {\r
+ type = "dataavailable";\r
+ width = "1";\r
+ direction = "output";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT readyfordata\r
+ {\r
+ type = "readyfordata";\r
+ width = "1";\r
+ direction = "output";\r
+ Is_Enabled = "1";\r
+ }\r
+ }\r
+ SYSTEM_BUILDER_INFO \r
+ {\r
+ Has_IRQ = "1";\r
+ Bus_Type = "avalon";\r
+ Write_Wait_States = "1cycles";\r
+ Read_Wait_States = "1cycles";\r
+ Hold_Time = "0cycles";\r
+ Setup_Time = "0cycles";\r
+ Is_Printable_Device = "1";\r
+ Address_Alignment = "native";\r
+ Well_Behaved_Waitrequest = "0";\r
+ Is_Nonvolatile_Storage = "0";\r
+ Read_Latency = "0";\r
+ Is_Memory_Device = "0";\r
+ Maximum_Pending_Read_Transactions = "0";\r
+ Minimum_Uninterrupted_Run_Length = "1";\r
+ Accepts_Internal_Connections = "1";\r
+ Write_Latency = "0";\r
+ Is_Flash = "0";\r
+ Data_Width = "16";\r
+ Address_Width = "3";\r
+ Maximum_Burst_Size = "1";\r
+ Register_Incoming_Signals = "0";\r
+ Register_Outgoing_Signals = "0";\r
+ Interleave_Bursts = "0";\r
+ Linewrap_Bursts = "0";\r
+ Burst_On_Burst_Boundaries_Only = "0";\r
+ Always_Burst_Max_Burst = "0";\r
+ Is_Big_Endian = "0";\r
+ Is_Enabled = "1";\r
+ MASTERED_BY cpu_0/data_master\r
+ {\r
+ priority = "1";\r
+ Offset_Address = "0x00900040";\r
+ }\r
+ IRQ_MASTER cpu_0/data_master\r
+ {\r
+ IRQ_Number = "0";\r
+ }\r
+ Base_Address = "0x00900040";\r
+ Address_Group = "0";\r
+ }\r
+ }\r
+ PORT_WIRING \r
+ {\r
+ PORT rxd\r
+ {\r
+ type = "export";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT txd\r
+ {\r
+ type = "export";\r
+ width = "1";\r
+ direction = "output";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT cts_n\r
+ {\r
+ direction = "input";\r
+ width = "1";\r
+ Is_Enabled = "0";\r
+ }\r
+ PORT rts_n\r
+ {\r
+ direction = "output";\r
+ width = "1";\r
+ Is_Enabled = "0";\r
+ }\r
+ }\r
+ class = "altera_avalon_uart";\r
+ class_version = "7.08";\r
+ iss_model_name = "altera_avalon_uart";\r
+ SYSTEM_BUILDER_INFO \r
+ {\r
+ Instantiate_In_System_Module = "1";\r
+ Is_Enabled = "1";\r
+ Iss_Launch_Telnet = "0";\r
+ Top_Level_Ports_Are_Enumerated = "1";\r
+ View \r
+ {\r
+ Settings_Summary = "8-bit UART with 115200 baud, <br>
+ 1 stop bits and N parity";\r
+ Is_Collapsed = "1";\r
+ MESSAGES \r
+ {\r
+ }\r
+ }\r
+ Clock_Source = "clk";\r
+ Has_Clock = "1";\r
+ }\r
+ SIMULATION \r
+ {\r
+ DISPLAY \r
+ {\r
+ SIGNAL a\r
+ {\r
+ name = " Bus Interface";\r
+ format = "Divider";\r
+ }\r
+ SIGNAL b\r
+ {\r
+ name = "chipselect";\r
+ }\r
+ SIGNAL c\r
+ {\r
+ name = "address";\r
+ radix = "hexadecimal";\r
+ }\r
+ SIGNAL d\r
+ {\r
+ name = "writedata";\r
+ radix = "hexadecimal";\r
+ }\r
+ SIGNAL e\r
+ {\r
+ name = "readdata";\r
+ radix = "hexadecimal";\r
+ }\r
+ SIGNAL f\r
+ {\r
+ name = " Internals";\r
+ format = "Divider";\r
+ }\r
+ SIGNAL g\r
+ {\r
+ name = "tx_ready";\r
+ }\r
+ SIGNAL h\r
+ {\r
+ name = "tx_data";\r
+ radix = "ascii";\r
+ }\r
+ SIGNAL i\r
+ {\r
+ name = "rx_char_ready";\r
+ }\r
+ SIGNAL j\r
+ {\r
+ name = "rx_data";\r
+ radix = "ascii";\r
+ }\r
+ }\r
+ INTERACTIVE_OUT log\r
+ {\r
+ enable = "0";\r
+ file = "_log_module.txt";\r
+ radix = "ascii";\r
+ signals = "temp,list";\r
+ exe = "perl -- tail-f.pl";\r
+ }\r
+ INTERACTIVE_IN drive\r
+ {\r
+ enable = "0";\r
+ file = "_input_data_stream.dat";\r
+ mutex = "_input_data_mutex.dat";\r
+ log = "_in.log";\r
+ rate = "100";\r
+ signals = "temp,list";\r
+ exe = "perl -- uart.pl";\r
+ }\r
+ }\r
+ WIZARD_SCRIPT_ARGUMENTS \r
+ {\r
+ baud = "115200";\r
+ data_bits = "8";\r
+ fixed_baud = "1";\r
+ parity = "N";\r
+ stop_bits = "1";\r
+ use_cts_rts = "0";\r
+ use_eop_register = "0";\r
+ sim_true_baud = "0";\r
+ sim_char_stream = "";\r
+ }\r
+ HDL_INFO \r
+ {\r
+ Precompiled_Simulation_Library_Files = "";\r
+ Simulation_HDL_Files = "";\r
+ Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/uart.vhd";\r
+ Synthesis_Only_Files = "";\r
+ }\r
+ }\r
+ MODULE LM74_Pio\r
+ {\r
+ SLAVE s1\r
+ {\r
+ PORT_WIRING \r
+ {\r
+ PORT clk\r
+ {\r
+ type = "clk";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT reset_n\r
+ {\r
+ type = "reset_n";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT address\r
+ {\r
+ type = "address";\r
+ width = "2";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT write_n\r
+ {\r
+ type = "write_n";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT writedata\r
+ {\r
+ type = "writedata";\r
+ width = "3";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT chipselect\r
+ {\r
+ type = "chipselect";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT readdata\r
+ {\r
+ type = "readdata";\r
+ width = "3";\r
+ direction = "output";\r
+ Is_Enabled = "1";\r
+ }\r
+ }\r
+ SYSTEM_BUILDER_INFO \r
+ {\r
+ Bus_Type = "avalon";\r
+ Write_Wait_States = "0cycles";\r
+ Read_Wait_States = "1cycles";\r
+ Hold_Time = "0cycles";\r
+ Setup_Time = "0cycles";\r
+ Is_Printable_Device = "0";\r
+ Address_Alignment = "native";\r
+ Well_Behaved_Waitrequest = "0";\r
+ Is_Nonvolatile_Storage = "0";\r
+ Read_Latency = "0";\r
+ Is_Memory_Device = "0";\r
+ Maximum_Pending_Read_Transactions = "0";\r
+ Minimum_Uninterrupted_Run_Length = "1";\r
+ Accepts_Internal_Connections = "1";\r
+ Write_Latency = "0";\r
+ Is_Flash = "0";\r
+ Data_Width = "3";\r
+ Address_Width = "2";\r
+ Maximum_Burst_Size = "1";\r
+ Register_Incoming_Signals = "0";\r
+ Register_Outgoing_Signals = "0";\r
+ Interleave_Bursts = "0";\r
+ Linewrap_Bursts = "0";\r
+ Burst_On_Burst_Boundaries_Only = "0";\r
+ Always_Burst_Max_Burst = "0";\r
+ Is_Big_Endian = "0";\r
+ Is_Enabled = "1";\r
+ MASTERED_BY cpu_0/data_master\r
+ {\r
+ priority = "1";\r
+ Offset_Address = "0x009000c0";\r
+ }\r
+ Base_Address = "0x009000c0";\r
+ Has_IRQ = "0";\r
+ Address_Group = "0";\r
+ IRQ_MASTER cpu_0/data_master\r
+ {\r
+ IRQ_Number = "NC";\r
+ }\r
+ Is_Readable = "1";\r
+ Is_Writable = "1";\r
+ }\r
+ }\r
+ PORT_WIRING \r
+ {\r
+ PORT bidir_port\r
+ {\r
+ type = "export";\r
+ width = "3";\r
+ direction = "inout";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT in_port\r
+ {\r
+ direction = "input";\r
+ Is_Enabled = "0";\r
+ width = "3";\r
+ }\r
+ PORT out_port\r
+ {\r
+ direction = "output";\r
+ Is_Enabled = "0";\r
+ width = "3";\r
+ }\r
+ }\r
+ class = "altera_avalon_pio";\r
+ class_version = "7.08";\r
+ SYSTEM_BUILDER_INFO \r
+ {\r
+ Is_Enabled = "1";\r
+ Instantiate_In_System_Module = "1";\r
+ Wire_Test_Bench_Values = "1";\r
+ Top_Level_Ports_Are_Enumerated = "1";\r
+ Clock_Source = "clk";\r
+ Has_Clock = "1";\r
+ Date_Modified = "";\r
+ View \r
+ {\r
+ MESSAGES \r
+ {\r
+ }\r
+ Settings_Summary = " 3-bit PIO using <br>
+ tri-state pins with edge type NONE and interrupt source NONE
+
+ ";\r
+ }\r
+ }\r
+ WIZARD_SCRIPT_ARGUMENTS \r
+ {\r
+ Do_Test_Bench_Wiring = "0";\r
+ Driven_Sim_Value = "0";\r
+ has_tri = "1";\r
+ has_out = "0";\r
+ has_in = "0";\r
+ capture = "0";\r
+ Data_Width = "3";\r
+ reset_value = "0";\r
+ edge_type = "NONE";\r
+ irq_type = "NONE";\r
+ bit_clearing_edge_register = "0";\r
+ }\r
+ HDL_INFO \r
+ {\r
+ Precompiled_Simulation_Library_Files = "";\r
+ Simulation_HDL_Files = "";\r
+ Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/LM74_Pio.vhd";\r
+ Synthesis_Only_Files = "";\r
+ }\r
+ }\r
+ MODULE epcs_controller\r
+ {\r
+ SLAVE epcs_control_port\r
+ {\r
+ PORT_WIRING \r
+ {\r
+ PORT clk\r
+ {\r
+ type = "clk";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT reset_n\r
+ {\r
+ type = "reset_n";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT irq\r
+ {\r
+ type = "irq";\r
+ width = "1";\r
+ direction = "output";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT address\r
+ {\r
+ type = "address";\r
+ width = "9";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT chipselect\r
+ {\r
+ type = "chipselect";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT dataavailable\r
+ {\r
+ type = "dataavailable";\r
+ width = "1";\r
+ direction = "output";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT endofpacket\r
+ {\r
+ type = "endofpacket";\r
+ width = "1";\r
+ direction = "output";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT read_n\r
+ {\r
+ type = "read_n";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT readdata\r
+ {\r
+ type = "readdata";\r
+ width = "32";\r
+ direction = "output";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT readyfordata\r
+ {\r
+ type = "readyfordata";\r
+ width = "1";\r
+ direction = "output";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT write_n\r
+ {\r
+ type = "write_n";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT writedata\r
+ {\r
+ type = "writedata";\r
+ width = "32";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT data_from_cpu\r
+ {\r
+ Is_Enabled = "0";\r
+ direction = "input";\r
+ type = "writedata";\r
+ width = "16";\r
+ }\r
+ PORT data_to_cpu\r
+ {\r
+ Is_Enabled = "0";\r
+ direction = "output";\r
+ type = "readdata";\r
+ width = "16";\r
+ }\r
+ PORT epcs_select\r
+ {\r
+ Is_Enabled = "0";\r
+ direction = "input";\r
+ type = "chipselect";\r
+ width = "1";\r
+ }\r
+ PORT mem_addr\r
+ {\r
+ Is_Enabled = "0";\r
+ direction = "input";\r
+ type = "address";\r
+ width = "3";\r
+ }\r
+ }\r
+ SYSTEM_BUILDER_INFO \r
+ {\r
+ Has_IRQ = "1";\r
+ Bus_Type = "avalon";\r
+ Write_Wait_States = "1cycles";\r
+ Read_Wait_States = "1cycles";\r
+ Hold_Time = "0cycles";\r
+ Setup_Time = "0cycles";\r
+ Is_Printable_Device = "0";\r
+ Address_Alignment = "dynamic";\r
+ Well_Behaved_Waitrequest = "0";\r
+ Is_Nonvolatile_Storage = "1";\r
+ Address_Span = "2048";\r
+ Read_Latency = "0";\r
+ Is_Memory_Device = "1";\r
+ Maximum_Pending_Read_Transactions = "0";\r
+ Minimum_Uninterrupted_Run_Length = "1";\r
+ Accepts_Internal_Connections = "1";\r
+ Write_Latency = "0";\r
+ Is_Flash = "1";\r
+ Data_Width = "32";\r
+ Address_Width = "9";\r
+ Maximum_Burst_Size = "1";\r
+ Register_Incoming_Signals = "0";\r
+ Register_Outgoing_Signals = "0";\r
+ Interleave_Bursts = "0";\r
+ Linewrap_Bursts = "0";\r
+ Burst_On_Burst_Boundaries_Only = "0";\r
+ Always_Burst_Max_Burst = "0";\r
+ Is_Big_Endian = "0";\r
+ Is_Enabled = "1";\r
+ MASTERED_BY cpu_0/instruction_master\r
+ {\r
+ priority = "1";\r
+ Offset_Address = "0x00906000";\r
+ }\r
+ MASTERED_BY cpu_0/data_master\r
+ {\r
+ priority = "1";\r
+ Offset_Address = "0x00906000";\r
+ }\r
+ IRQ_MASTER cpu_0/data_master\r
+ {\r
+ IRQ_Number = "2";\r
+ }\r
+ Base_Address = "0x00906000";\r
+ Address_Group = "0";\r
+ }\r
+ WIZARD_SCRIPT_ARGUMENTS \r
+ {\r
+ class = "altera_avalon_epcs_flash_controller";\r
+ flash_reference_designator = "";\r
+ }\r
+ }\r
+ PORT_WIRING \r
+ {\r
+ PORT dclk\r
+ {\r
+ type = "export";\r
+ width = "1";\r
+ direction = "output";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT sce\r
+ {\r
+ type = "export";\r
+ width = "1";\r
+ direction = "output";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT sdo\r
+ {\r
+ type = "export";\r
+ width = "1";\r
+ direction = "output";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT data0\r
+ {\r
+ type = "export";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ }\r
+ WIZARD_SCRIPT_ARGUMENTS \r
+ {\r
+ databits = "8";\r
+ targetclock = "20";\r
+ clockunits = "MHz";\r
+ clockmult = "1000000";\r
+ numslaves = "1";\r
+ ismaster = "1";\r
+ clockpolarity = "0";\r
+ clockphase = "0";\r
+ lsbfirst = "0";\r
+ extradelay = "0";\r
+ targetssdelay = "100";\r
+ delayunits = "us";\r
+ delaymult = "1e-006";\r
+ prefix = "epcs_";\r
+ register_offset = "0x400";\r
+ use_asmi_atom = "0";\r
+ MAKE \r
+ {\r
+ MACRO \r
+ {\r
+ EPCS_CONTROLLER_BOOT_ROM_FLASHTARGET_ALT_SIM_PREFIX = "$(EPCS_CONTROLLER_BOOT_ROM_FLASHTARGET_TMP1:0=)";\r
+ EPCS_CONTROLLER_BOOT_ROM_FLASHTARGET_TMP1 = "$(ALT_SIM_OPTIMIZE:1=RUN_ON_HDL_SIMULATOR_ONLY_)";\r
+ }\r
+ MASTER cpu_0\r
+ {\r
+ MACRO \r
+ {\r
+ BOOTS_FROM_EPCS = "0";\r
+ BOOT_COPIER_EPCS = "boot_loader_epcs.srec";\r
+ CPU_CLASS = "altera_nios2";\r
+ CPU_RESET_ADDRESS = "0x0";\r
+ }\r
+ }\r
+ TARGET delete_placeholder_warning\r
+ {\r
+ epcs_controller \r
+ {\r
+ Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt";\r
+ Is_Phony = "1";\r
+ Target_File = "do_delete_placeholder_warning";\r
+ }\r
+ }\r
+ TARGET flashfiles\r
+ {\r
+ epcs_controller \r
+ {\r
+ Command1 = "@if [ $(BOOTS_FROM_EPCS) -eq 1 ]; then echo Post-processing to create $(notdir $@) ; elf2flash --input=$(ELF) --flash= --boot=$(DBL_QUOTE)$(shell $(DBL_QUOTE)$(QUARTUS_ROOTDIR)/sopc_builder/bin/find_sopc_component_dir$(DBL_QUOTE) $(CPU_CLASS) $(QUARTUS_PROJECT_DIR))/$(BOOT_COPIER_EPCS)$(DBL_QUOTE) --outfile=$(EPCS_CONTROLLER_BOOT_ROM_FLASHTARGET_ALT_SIM_PREFIX)epcs_controller_boot_rom.flash --sim_optimize=$(ALT_SIM_OPTIMIZE) --epcs --base=0x0 --end=0x7FFFFFFF ; fi";\r
+ Dependency = "$(ELF)";\r
+ Target_File = "$(EPCS_CONTROLLER_BOOT_ROM_FLASHTARGET_ALT_SIM_PREFIX)epcs_controller_boot_rom.flash";\r
+ }\r
+ }\r
+ TARGET sim\r
+ {\r
+ epcs_controller \r
+ {\r
+ Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";\r
+ Command2 = "@echo Hardware simulation is not enabled for the target SOPC Builder system. Skipping creation of hardware simulation model contents and simulation symbol files. \\(Note: This does not affect the instruction set simulator.\\)";\r
+ Command3 = "touch $(SIMDIR)/dummy_file";\r
+ Dependency = "$(ELF)";\r
+ Target_File = "$(SIMDIR)/dummy_file";\r
+ }\r
+ }\r
+ }\r
+ clockunit = "kHz";\r
+ delayunit = "us";\r
+ }\r
+ class = "altera_avalon_epcs_flash_controller";\r
+ class_version = "7.08";\r
+ SYSTEM_BUILDER_INFO \r
+ {\r
+ Is_Enabled = "1";\r
+ Clock_Source = "clk";\r
+ Has_Clock = "1";\r
+ Instantiate_In_System_Module = "1";\r
+ Required_Device_Family = "STRATIX,CYCLONE,CYCLONEII,CYCLONEIII,STRATIXIII,STRATIXII,STRATIXIIGX,ARRIAGX,STRATIXIIGXLITE";\r
+ Fixed_Module_Name = "epcs_controller";\r
+ Top_Level_Ports_Are_Enumerated = "1";\r
+ View \r
+ {\r
+ MESSAGES \r
+ {\r
+ }\r
+ }\r
+ }\r
+ HDL_INFO \r
+ {\r
+ Precompiled_Simulation_Library_Files = "";\r
+ Simulation_HDL_Files = "";\r
+ Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/epcs_controller.vhd";\r
+ Synthesis_Only_Files = "";\r
+ }\r
+ }\r
+ MODULE tri_state_bridge_0\r
+ {\r
+ SLAVE avalon_slave\r
+ {\r
+ PORT_WIRING \r
+ {\r
+ }\r
+ SYSTEM_BUILDER_INFO \r
+ {\r
+ Bus_Type = "avalon";\r
+ Write_Wait_States = "0cycles";\r
+ Read_Wait_States = "1cycles";\r
+ Hold_Time = "0cycles";\r
+ Setup_Time = "0cycles";\r
+ Is_Printable_Device = "0";\r
+ Address_Alignment = "dynamic";\r
+ Well_Behaved_Waitrequest = "0";\r
+ Is_Nonvolatile_Storage = "0";\r
+ Address_Span = "1";\r
+ Read_Latency = "0";\r
+ Is_Memory_Device = "0";\r
+ Maximum_Pending_Read_Transactions = "0";\r
+ Minimum_Uninterrupted_Run_Length = "1";\r
+ Accepts_Internal_Connections = "1";\r
+ Write_Latency = "0";\r
+ Is_Flash = "0";\r
+ Maximum_Burst_Size = "1";\r
+ Register_Incoming_Signals = "1";\r
+ Register_Outgoing_Signals = "1";\r
+ Interleave_Bursts = "0";\r
+ Linewrap_Bursts = "0";\r
+ Burst_On_Burst_Boundaries_Only = "0";\r
+ Always_Burst_Max_Burst = "0";\r
+ Is_Big_Endian = "0";\r
+ Is_Enabled = "1";\r
+ MASTERED_BY cpu_0/data_master\r
+ {\r
+ priority = "1";\r
+ Offset_Address = "0x00000000";\r
+ }\r
+ MASTERED_BY cpu_0/instruction_master\r
+ {\r
+ priority = "1";\r
+ Offset_Address = "0x00000000";\r
+ }\r
+ MASTERED_BY nios_vga_inst/vga_dma\r
+ {\r
+ priority = "1";\r
+ Offset_Address = "0x00000000";\r
+ }\r
+ Bridges_To = "tristate_master";\r
+ Base_Address = "N/A";\r
+ Has_IRQ = "0";\r
+ IRQ = "N/A";\r
+ Address_Group = "0";\r
+ IRQ_MASTER cpu_0/data_master\r
+ {\r
+ IRQ_Number = "NC";\r
+ }\r
+ }\r
+ }\r
+ MASTER tristate_master\r
+ {\r
+ SYSTEM_BUILDER_INFO \r
+ {\r
+ Bus_Type = "avalon_tristate";\r
+ Is_Asynchronous = "0";\r
+ DBS_Big_Endian = "0";\r
+ Adapts_To = "";\r
+ Maximum_Burst_Size = "1";\r
+ Register_Incoming_Signals = "0";\r
+ Register_Outgoing_Signals = "0";\r
+ Interleave_Bursts = "0";\r
+ Linewrap_Bursts = "0";\r
+ Burst_On_Burst_Boundaries_Only = "0";\r
+ Always_Burst_Max_Burst = "0";\r
+ Is_Big_Endian = "0";\r
+ Is_Enabled = "1";\r
+ Bridges_To = "avalon_slave";\r
+ }\r
+ PORT_WIRING \r
+ {\r
+ }\r
+ MEMORY_MAP \r
+ {\r
+ Entry cfi_flash/s1\r
+ {\r
+ address = "0x00000000";\r
+ span = "0x00800000";\r
+ is_bridge = "0";\r
+ }\r
+ Entry DBC3C40_SRAM_inst/avalon_tristate_slave\r
+ {\r
+ address = "0x00800000";\r
+ span = "0x00100000";\r
+ is_bridge = "0";\r
+ }\r
+ }\r
+ }\r
+ WIZARD_SCRIPT_ARGUMENTS \r
+ {\r
+ }\r
+ class = "altera_avalon_tri_state_bridge";\r
+ class_version = "7.08";\r
+ SYSTEM_BUILDER_INFO \r
+ {\r
+ Is_Enabled = "1";\r
+ Clock_Source = "clk";\r
+ Has_Clock = "1";\r
+ Instantiate_In_System_Module = "1";\r
+ Is_Bridge = "1";\r
+ Top_Level_Ports_Are_Enumerated = "1";\r
+ View \r
+ {\r
+ MESSAGES \r
+ {\r
+ }\r
+ }\r
+ }\r
+ }\r
+ MODULE sys_clk\r
+ {\r
+ SLAVE s1\r
+ {\r
+ PORT_WIRING \r
+ {\r
+ PORT clk\r
+ {\r
+ type = "clk";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT reset_n\r
+ {\r
+ type = "reset_n";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT irq\r
+ {\r
+ type = "irq";\r
+ width = "1";\r
+ direction = "output";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT address\r
+ {\r
+ type = "address";\r
+ width = "3";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT writedata\r
+ {\r
+ type = "writedata";\r
+ width = "16";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT readdata\r
+ {\r
+ type = "readdata";\r
+ width = "16";\r
+ direction = "output";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT chipselect\r
+ {\r
+ type = "chipselect";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT write_n\r
+ {\r
+ type = "write_n";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ }\r
+ SYSTEM_BUILDER_INFO \r
+ {\r
+ Has_IRQ = "1";\r
+ Bus_Type = "avalon";\r
+ Write_Wait_States = "0cycles";\r
+ Read_Wait_States = "1cycles";\r
+ Hold_Time = "0cycles";\r
+ Setup_Time = "0cycles";\r
+ Is_Printable_Device = "0";\r
+ Address_Alignment = "native";\r
+ Well_Behaved_Waitrequest = "0";\r
+ Is_Nonvolatile_Storage = "0";\r
+ Read_Latency = "0";\r
+ Is_Memory_Device = "0";\r
+ Maximum_Pending_Read_Transactions = "0";\r
+ Minimum_Uninterrupted_Run_Length = "1";\r
+ Accepts_Internal_Connections = "1";\r
+ Write_Latency = "0";\r
+ Is_Flash = "0";\r
+ Data_Width = "16";\r
+ Address_Width = "3";\r
+ Maximum_Burst_Size = "1";\r
+ Register_Incoming_Signals = "0";\r
+ Register_Outgoing_Signals = "0";\r
+ Interleave_Bursts = "0";\r
+ Linewrap_Bursts = "0";\r
+ Burst_On_Burst_Boundaries_Only = "0";\r
+ Always_Burst_Max_Burst = "0";\r
+ Is_Big_Endian = "0";\r
+ Is_Enabled = "1";\r
+ MASTERED_BY cpu_0/data_master\r
+ {\r
+ priority = "1";\r
+ Offset_Address = "0x00900060";\r
+ }\r
+ IRQ_MASTER cpu_0/data_master\r
+ {\r
+ IRQ_Number = "3";\r
+ }\r
+ Base_Address = "0x00900060";\r
+ Address_Group = "0";\r
+ }\r
+ }\r
+ class = "altera_avalon_timer";\r
+ class_version = "7.08";\r
+ iss_model_name = "altera_avalon_timer";\r
+ SYSTEM_BUILDER_INFO \r
+ {\r
+ Instantiate_In_System_Module = "1";\r
+ Is_Enabled = "1";\r
+ Top_Level_Ports_Are_Enumerated = "1";\r
+ View \r
+ {\r
+ Settings_Summary = "Timer with 1 ms timeout period.";\r
+ Is_Collapsed = "1";\r
+ MESSAGES \r
+ {\r
+ }\r
+ }\r
+ Clock_Source = "clk";\r
+ Has_Clock = "1";\r
+ }\r
+ WIZARD_SCRIPT_ARGUMENTS \r
+ {\r
+ always_run = "0";\r
+ fixed_period = "0";\r
+ snapshot = "1";\r
+ period = "1.0";\r
+ period_units = "ms";\r
+ reset_output = "0";\r
+ timeout_pulse_output = "0";\r
+ load_value = "74999";\r
+ counter_size = "32";\r
+ mult = "0.0010";\r
+ ticks_per_sec = "1000";\r
+ }\r
+ HDL_INFO \r
+ {\r
+ Precompiled_Simulation_Library_Files = "";\r
+ Simulation_HDL_Files = "";\r
+ Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/sys_clk.vhd";\r
+ Synthesis_Only_Files = "";\r
+ }\r
+ PORT_WIRING \r
+ {\r
+ }\r
+ }\r
+ MODULE cfi_flash\r
+ {\r
+ SLAVE s1\r
+ {\r
+ PORT_WIRING \r
+ {\r
+ PORT data\r
+ {\r
+ type = "data";\r
+ width = "16";\r
+ direction = "inout";\r
+ Is_Enabled = "1";\r
+ is_shared = "1";\r
+ }\r
+ PORT address\r
+ {\r
+ type = "address";\r
+ width = "22";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ is_shared = "1";\r
+ }\r
+ PORT read_n\r
+ {\r
+ type = "read_n";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ is_shared = "1";\r
+ }\r
+ PORT write_n\r
+ {\r
+ type = "write_n";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ is_shared = "1";\r
+ }\r
+ PORT select_n\r
+ {\r
+ type = "chipselect_n";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ is_shared = "0";\r
+ }\r
+ }\r
+ SYSTEM_BUILDER_INFO \r
+ {\r
+ Bus_Type = "avalon_tristate";\r
+ Write_Wait_States = "100ns";\r
+ Read_Wait_States = "100ns";\r
+ Hold_Time = "20ns";\r
+ Setup_Time = "20ns";\r
+ Is_Printable_Device = "0";\r
+ Address_Alignment = "dynamic";\r
+ Well_Behaved_Waitrequest = "0";\r
+ Is_Nonvolatile_Storage = "1";\r
+ Address_Span = "8388608";\r
+ Read_Latency = "0";\r
+ Is_Memory_Device = "1";\r
+ Maximum_Pending_Read_Transactions = "0";\r
+ Minimum_Uninterrupted_Run_Length = "1";\r
+ Accepts_Internal_Connections = "1";\r
+ Write_Latency = "0";\r
+ Is_Flash = "1";\r
+ Active_CS_Through_Read_Latency = "0";\r
+ Data_Width = "16";\r
+ Address_Width = "22";\r
+ Maximum_Burst_Size = "1";\r
+ Register_Incoming_Signals = "0";\r
+ Register_Outgoing_Signals = "0";\r
+ Interleave_Bursts = "0";\r
+ Linewrap_Bursts = "0";\r
+ Burst_On_Burst_Boundaries_Only = "0";\r
+ Always_Burst_Max_Burst = "0";\r
+ Is_Big_Endian = "0";\r
+ Is_Enabled = "1";\r
+ MASTERED_BY tri_state_bridge_0/tristate_master\r
+ {\r
+ priority = "1";\r
+ Offset_Address = "0x00000000";\r
+ }\r
+ Base_Address = "0x00000000";\r
+ Has_IRQ = "0";\r
+ Simulation_Num_Lanes = "1";\r
+ Convert_Xs_To_0 = "1";\r
+ Address_Group = "0";\r
+ IRQ_MASTER cpu_0/data_master\r
+ {\r
+ IRQ_Number = "NC";\r
+ }\r
+ }\r
+ WIZARD_SCRIPT_ARGUMENTS \r
+ {\r
+ class = "altera_avalon_cfi_flash";\r
+ Supports_Flash_File_System = "1";\r
+ flash_reference_designator = "";\r
+ }\r
+ }\r
+ WIZARD_SCRIPT_ARGUMENTS \r
+ {\r
+ Setup_Value = "20";\r
+ Wait_Value = "100";\r
+ Hold_Value = "20";\r
+ Timing_Units = "ns";\r
+ Unit_Multiplier = "1";\r
+ Size = "8388608";\r
+ MAKE \r
+ {\r
+ MACRO \r
+ {\r
+ CFI_FLASH_FLASHTARGET_ALT_SIM_PREFIX = "$(CFI_FLASH_FLASHTARGET_TMP1:0=)";\r
+ CFI_FLASH_FLASHTARGET_TMP1 = "$(ALT_SIM_OPTIMIZE:1=RUN_ON_HDL_SIMULATOR_ONLY_)";\r
+ }\r
+ MASTER cpu_0\r
+ {\r
+ MACRO \r
+ {\r
+ BOOT_COPIER = "boot_loader_cfi.srec";\r
+ CPU_CLASS = "altera_nios2";\r
+ CPU_RESET_ADDRESS = "0x0";\r
+ }\r
+ }\r
+ TARGET delete_placeholder_warning\r
+ {\r
+ cfi_flash \r
+ {\r
+ Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt";\r
+ Is_Phony = "1";\r
+ Target_File = "do_delete_placeholder_warning";\r
+ }\r
+ }\r
+ TARGET flashfiles\r
+ {\r
+ cfi_flash \r
+ {\r
+ Command1 = "@echo Post-processing to create $(notdir $@)";\r
+ Command2 = "elf2flash --input=$(ELF) --flash= --boot=$(DBL_QUOTE)$(shell $(DBL_QUOTE)$(QUARTUS_ROOTDIR)/sopc_builder/bin/find_sopc_component_dir$(DBL_QUOTE) $(CPU_CLASS) $(QUARTUS_PROJECT_DIR))/$(BOOT_COPIER)$(DBL_QUOTE) --outfile=$(CFI_FLASH_FLASHTARGET_ALT_SIM_PREFIX)cfi_flash.flash --sim_optimize=$(ALT_SIM_OPTIMIZE) --base=0x0 --end=0x7FFFFF --reset=$(CPU_RESET_ADDRESS) ";\r
+ Dependency = "$(ELF)";\r
+ Target_File = "$(CFI_FLASH_FLASHTARGET_ALT_SIM_PREFIX)cfi_flash.flash";\r
+ }\r
+ }\r
+ TARGET sim\r
+ {\r
+ cfi_flash \r
+ {\r
+ Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";\r
+ Command2 = "@echo Hardware simulation is not enabled for the target SOPC Builder system. Skipping creation of hardware simulation model contents and simulation symbol files. \\(Note: This does not affect the instruction set simulator.\\)";\r
+ Command3 = "touch $(SIMDIR)/dummy_file";\r
+ Dependency = "$(ELF)";\r
+ Target_File = "$(SIMDIR)/dummy_file";\r
+ }\r
+ }\r
+ }\r
+ }\r
+ SYSTEM_BUILDER_INFO \r
+ {\r
+ Simulation_Num_Lanes = "2";\r
+ Is_Enabled = "1";\r
+ Clock_Source = "clk";\r
+ Has_Clock = "1";\r
+ Make_Memory_Model = "1";\r
+ Instantiate_In_System_Module = "0";\r
+ Top_Level_Ports_Are_Enumerated = "1";\r
+ View \r
+ {\r
+ MESSAGES \r
+ {\r
+ }\r
+ }\r
+ }\r
+ class = "altera_avalon_cfi_flash";\r
+ class_version = "7.08";\r
+ iss_model_name = "altera_avalon_flash";\r
+ HDL_INFO \r
+ {\r
+ }\r
+ }\r
+ MODULE nios_vga_inst\r
+ {\r
+ MASTER vga_dma\r
+ {\r
+ PORT_WIRING \r
+ {\r
+ PORT cpu_clk\r
+ {\r
+ type = "clk";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT rst_n\r
+ {\r
+ type = "reset_n";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT ram_in\r
+ {\r
+ type = "readdata";\r
+ width = "32";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT wait_st\r
+ {\r
+ type = "waitrequest";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT ram_cs\r
+ {\r
+ type = "chipselect";\r
+ width = "1";\r
+ direction = "output";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT ram_wr\r
+ {\r
+ type = "write";\r
+ width = "1";\r
+ direction = "output";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT ram_rd\r
+ {\r
+ type = "read";\r
+ width = "1";\r
+ direction = "output";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT ram_addr\r
+ {\r
+ type = "address";\r
+ width = "26";\r
+ direction = "output";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT ram_out\r
+ {\r
+ type = "writedata";\r
+ width = "32";\r
+ direction = "output";\r
+ Is_Enabled = "1";\r
+ }\r
+ }\r
+ SYSTEM_BUILDER_INFO \r
+ {\r
+ Bus_Type = "avalon";\r
+ Is_Asynchronous = "0";\r
+ DBS_Big_Endian = "0";\r
+ Adapts_To = "";\r
+ Do_Stream_Reads = "0";\r
+ Do_Stream_Writes = "0";\r
+ Max_Address_Width = "32";\r
+ Data_Width = "32";\r
+ Address_Width = "26";\r
+ Maximum_Burst_Size = "1";\r
+ Register_Incoming_Signals = "0";\r
+ Register_Outgoing_Signals = "0";\r
+ Interleave_Bursts = "0";\r
+ Linewrap_Bursts = "0";\r
+ Burst_On_Burst_Boundaries_Only = "0";\r
+ Always_Burst_Max_Burst = "0";\r
+ Is_Big_Endian = "0";\r
+ Is_Enabled = "1";\r
+ }\r
+ MEMORY_MAP \r
+ {\r
+ Entry cfi_flash/s1\r
+ {\r
+ address = "0x00000000";\r
+ span = "0x00800000";\r
+ is_bridge = "0";\r
+ }\r
+ Entry DBC3C40_SRAM_inst/avalon_tristate_slave\r
+ {\r
+ address = "0x00800000";\r
+ span = "0x00100000";\r
+ is_bridge = "0";\r
+ }\r
+ }\r
+ }\r
+ SLAVE vga_regs\r
+ {\r
+ SYSTEM_BUILDER_INFO \r
+ {\r
+ Bus_Type = "avalon";\r
+ Write_Wait_States = "1cycles";\r
+ Read_Wait_States = "1cycles";\r
+ Hold_Time = "0cycles";\r
+ Setup_Time = "0cycles";\r
+ Is_Printable_Device = "0";\r
+ Address_Alignment = "native";\r
+ Well_Behaved_Waitrequest = "0";\r
+ Is_Nonvolatile_Storage = "0";\r
+ Read_Latency = "0";\r
+ Is_Memory_Device = "0";\r
+ Maximum_Pending_Read_Transactions = "0";\r
+ Minimum_Uninterrupted_Run_Length = "1";\r
+ Accepts_Internal_Connections = "1";\r
+ Write_Latency = "0";\r
+ Is_Flash = "0";\r
+ Data_Width = "32";\r
+ Address_Width = "4";\r
+ Maximum_Burst_Size = "1";\r
+ Register_Incoming_Signals = "0";\r
+ Register_Outgoing_Signals = "0";\r
+ Interleave_Bursts = "0";\r
+ Linewrap_Bursts = "0";\r
+ Burst_On_Burst_Boundaries_Only = "0";\r
+ Always_Burst_Max_Burst = "0";\r
+ Is_Big_Endian = "0";\r
+ Is_Enabled = "1";\r
+ MASTERED_BY cpu_0/data_master\r
+ {\r
+ priority = "1";\r
+ Offset_Address = "0x00900000";\r
+ }\r
+ Base_Address = "0x00900000";\r
+ Address_Group = "0";\r
+ IRQ_MASTER cpu_0/data_master\r
+ {\r
+ IRQ_Number = "NC";\r
+ }\r
+ }\r
+ PORT_WIRING \r
+ {\r
+ PORT cpu_cs\r
+ {\r
+ type = "chipselect";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT cpu_wr\r
+ {\r
+ type = "write";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT cpu_addr\r
+ {\r
+ type = "address";\r
+ width = "4";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT cpu_in\r
+ {\r
+ type = "writedata";\r
+ width = "32";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT cpu_out\r
+ {\r
+ type = "readdata";\r
+ width = "32";\r
+ direction = "output";\r
+ Is_Enabled = "1";\r
+ }\r
+ }\r
+ }\r
+ PORT_WIRING \r
+ {\r
+ PORT r\r
+ {\r
+ type = "export";\r
+ width = "8";\r
+ direction = "output";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT g\r
+ {\r
+ type = "export";\r
+ width = "8";\r
+ direction = "output";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT b\r
+ {\r
+ type = "export";\r
+ width = "8";\r
+ direction = "output";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT hs\r
+ {\r
+ type = "export";\r
+ width = "1";\r
+ direction = "output";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT vs\r
+ {\r
+ type = "export";\r
+ width = "1";\r
+ direction = "output";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT m1\r
+ {\r
+ type = "export";\r
+ width = "1";\r
+ direction = "output";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT m2\r
+ {\r
+ type = "export";\r
+ width = "1";\r
+ direction = "output";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT blank_n\r
+ {\r
+ type = "export";\r
+ width = "1";\r
+ direction = "output";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT sync_n\r
+ {\r
+ type = "export";\r
+ width = "1";\r
+ direction = "output";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT sync_t\r
+ {\r
+ type = "export";\r
+ width = "1";\r
+ direction = "output";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT lcd_reg\r
+ {\r
+ type = "export";\r
+ width = "3";\r
+ direction = "output";\r
+ Is_Enabled = "1";\r
+ }\r
+ PORT video_clk\r
+ {\r
+ type = "export";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ }\r
+ }\r
+ class = "no_legacy_module";\r
+ class_version = "7.08";\r
+ gtf_class_name = "nios_vga";\r
+ gtf_class_version = "1.0.1";\r
+ SYSTEM_BUILDER_INFO \r
+ {\r
+ Do_Not_Generate = "1";\r
+ Instantiate_In_System_Module = "1";\r
+ Is_Enabled = "1";\r
+ Clock_Source = "clk";\r
+ Has_Clock = "1";\r
+ View \r
+ {\r
+ MESSAGES \r
+ {\r
+ }\r
+ }\r
+ }\r
+ HDL_INFO \r
+ {\r
+ Simulation_HDL_Files = "__PROJECT_DIRECTORY__/nios_vga_inst.vhd";\r
+ }\r
+ WIZARD_SCRIPT_ARGUMENTS \r
+ {\r
+ terminated_ports \r
+ {\r
+ }\r
+ }\r
+ }\r
+ MODULE DBC3C40_SRAM_inst\r
+ {\r
+ SLAVE avalon_tristate_slave\r
+ {\r
+ SYSTEM_BUILDER_INFO \r
+ {\r
+ Bus_Type = "avalon_tristate";\r
+ Write_Wait_States = "1cycles";\r
+ Read_Wait_States = "1cycles";\r
+ Hold_Time = "1cycles";\r
+ Setup_Time = "0cycles";\r
+ Is_Printable_Device = "0";\r
+ Address_Alignment = "dynamic";\r
+ Well_Behaved_Waitrequest = "0";\r
+ Is_Nonvolatile_Storage = "0";\r
+ Address_Span = "1048576";\r
+ Read_Latency = "0";\r
+ Is_Memory_Device = "1";\r
+ Maximum_Pending_Read_Transactions = "0";\r
+ Minimum_Uninterrupted_Run_Length = "1";\r
+ Accepts_Internal_Connections = "1";\r
+ Write_Latency = "0";\r
+ Is_Flash = "0";\r
+ Active_CS_Through_Read_Latency = "0";\r
+ Data_Width = "16";\r
+ Address_Width = "19";\r
+ Maximum_Burst_Size = "1";\r
+ Register_Incoming_Signals = "0";\r
+ Register_Outgoing_Signals = "0";\r
+ Interleave_Bursts = "0";\r
+ Linewrap_Bursts = "0";\r
+ Burst_On_Burst_Boundaries_Only = "0";\r
+ Always_Burst_Max_Burst = "0";\r
+ Is_Big_Endian = "0";\r
+ Is_Enabled = "1";\r
+ MASTERED_BY tri_state_bridge_0/tristate_master\r
+ {\r
+ priority = "1";\r
+ Offset_Address = "0x00800000";\r
+ }\r
+ Base_Address = "0x00800000";\r
+ Address_Group = "0";\r
+ IRQ_MASTER cpu_0/data_master\r
+ {\r
+ IRQ_Number = "NC";\r
+ }\r
+ }\r
+ PORT_WIRING \r
+ {\r
+ PORT addr\r
+ {\r
+ type = "address";\r
+ width = "19";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ is_shared = "1";\r
+ }\r
+ PORT data\r
+ {\r
+ type = "data";\r
+ width = "16";\r
+ direction = "inout";\r
+ Is_Enabled = "1";\r
+ is_shared = "1";\r
+ }\r
+ PORT ncs\r
+ {\r
+ type = "chipselect_n";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ is_shared = "0";\r
+ }\r
+ PORT wrn\r
+ {\r
+ type = "write_n";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ is_shared = "1";\r
+ }\r
+ PORT rdn\r
+ {\r
+ type = "read_n";\r
+ width = "1";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ is_shared = "1";\r
+ }\r
+ PORT ben\r
+ {\r
+ type = "byteenable_n";\r
+ width = "2";\r
+ direction = "input";\r
+ Is_Enabled = "1";\r
+ is_shared = "1";\r
+ }\r
+ }\r
+ }\r
+ class = "no_legacy_module";\r
+ class_version = "7.08";\r
+ gtf_class_name = "DBC3C40_SRAM";\r
+ gtf_class_version = "1.0";\r
+ SYSTEM_BUILDER_INFO \r
+ {\r
+ Do_Not_Generate = "1";\r
+ Instantiate_In_System_Module = "0";\r
+ Is_Enabled = "1";\r
+ Clock_Source = "clk";\r
+ View \r
+ {\r
+ MESSAGES \r
+ {\r
+ }\r
+ }\r
+ }\r
+ HDL_INFO \r
+ {\r
+ Simulation_HDL_Files = "";\r
+ }\r
+ WIZARD_SCRIPT_ARGUMENTS \r
+ {\r
+ terminated_ports \r
+ {\r
+ }\r
+ }\r
+ }\r
+}\r
--- /dev/null
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--- /dev/null
+"c:/devtools/altera/90sp2/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/devtools/altera/90sp2/quartus/sopc_builder/bin/sopc_builder.jar;c:/devtools/altera/90sp2/quartus/sopc_builder/bin/PinAssigner.jar;c:/devtools/altera/90sp2/quartus/sopc_builder/bin/sopc_wizard.jar;c:/devtools/altera/90sp2/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/devtools/altera/90sp2/quartus/sopc_builder" -notalkback=1 -projectname -projectpathC:/E/Dev/FreeRTOS/WorkingCopy3/Demo/NiosII_CycloneIII_DBC3C40_GCC --no_splash --update_classes_and_exit --quartus_dir="c:/devtools/altera/90sp2/quartus" --sopc_perl="c:/devtools/altera/90sp2/quartus/bin/perl" --sopc_lib_path="c:\E\Dev\FreeRTOS\WorkingCopy3\Demo\NiosII_CycloneIII_DBC3C40_GCC+C:\devtools\altera\90\nios2eds\bin;+C:\devtools\altera\90sp2\ip\altera\asi\lib\ip_toolbench+C:\devtools\altera\90sp2\quartus\common\librarian\factories+Q:\quartus\cusp\bin+Q:\quartus\dsp_builder\bin+Q:\quartus\dsp_builder\bin\extlibs+C:\devtools\altera\90sp2\ip\altera\clipper\lib+C:\tools\altera\9.0\132\linux32\quartus\cusp\include+C:\tools\altera\9.0\132\linux32\quartus\cusp\include\cusp+C:\tools\altera\9.0\132\linux32\quartus\cusp\include\cusp\fuLib+C:\tools\altera\9.0\132\linux32\quartus\cusp\include\cusp\simlib+C:\tools\altera\9.0\132\linux32\quartus\cusp\synthinclude+C:\tools\altera\9.0\132\linux32\quartus\cusp\synthinclude\stlport+C:\tools\altera\9.0\132\linux32\quartus\cusp\synthinclude\stlport\config+C:\tools\altera\9.0\132\linux32\quartus\cusp\synthinclude\stlport\stl+C:\tools\altera\9.0\132\linux32\quartus\cusp\synthinclude\stlport\using+C:\tools\altera\9.0\132\linux32\quartus\cusp\synthinclude\stlport\wrap_std+C:\tools\altera\9.0\132\linux32\quartus\cusp\systemc\include\sysc\communication+C:\tools\altera\9.0\132\linux32\quartus\cusp\systemc\include\sysc\datatypes\bit+C:\tools\altera\9.0\132\linux32\quartus\cusp\systemc\include\sysc\datatypes\fx+C:\tools\altera\9.0\132\linux32\quartus\cusp\systemc\include\sysc\datatypes\int+C:\tools\altera\9.0\132\linux32\quartus\cusp\systemc\include\sysc\datatypes\misc+C:\tools\altera\9.0\132\linux32\quartus\cusp\systemc\include\sysc\kernel+C:\tools\altera\9.0\132\linux32\quartus\cusp\systemc\include\sysc\tracing+C:\tools\altera\9.0\132\linux32\quartus\cusp\systemc\include\sysc\utils+C:\tools\altera\9.0\132\linux32\quartus\cusp\systemc\include+C:\devtools\altera\90sp2\ip\altera\clipper\lib\ip_toolbench+C:\devtools\altera\90sp2\ip\altera\color_plane_sequencer\lib+C:\devtools\altera\90sp2\ip\altera\color_plane_sequencer\lib\ip_toolbench+C:\devtools\altera\90sp2\ip\altera\chroma_resampler\lib+C:\devtools\altera\90sp2\ip\altera\chroma_resampler\lib\ip_toolbench+C:\devtools\altera\90sp2\ip\altera\csc\lib+C:\devtools\altera\90sp2\ip\altera\csc\lib\ip_toolbench+C:\devtools\altera\90sp2\ip\altera\clocked_video_input\lib\ip_toolbench+C:\devtools\altera\90sp2\ip\altera\deinterlacer\lib+C:\devtools\altera\90sp2\ip\altera\deinterlacer\lib\ip_toolbench+C:\devtools\altera\90sp2\ip\altera\fir_filter_2d\lib+C:\devtools\altera\90sp2\ip\altera\fir_filter_2d\lib\ip_toolbench+C:\devtools\altera\90sp2\ip\altera\gamma_corrector\lib+C:\devtools\altera\90sp2\ip\altera\gamma_corrector\lib\ip_toolbench+C:\devtools\altera\90sp2\ip\altera\clocked_video_output\lib\ip_toolbench+C:\devtools\altera\90sp2\ip\altera\line_buffer_compiler\lib+C:\devtools\altera\90sp2\ip\altera\line_buffer_compiler\lib\ip_toolbench+C:\devtools\altera\90sp2\ip\altera\median_filter_2d\lib+C:\devtools\altera\90sp2\ip\altera\median_filter_2d\lib\ip_toolbench+C:\devtools\altera\90sp2\ip\altera\alpha_blending_mixer\lib+C:\devtools\altera\90sp2\ip\altera\alpha_blending_mixer\lib\ip_toolbench+C:\devtools\altera\90sp2\ip\altera\scaler\lib+C:\devtools\altera\90sp2\ip\altera\scaler\lib\ip_toolbench+C:\devtools\altera\90sp2\ip\altera\test_pattern_generator\lib+C:\devtools\altera\90sp2\ip\altera\test_pattern_generator\lib\ip_toolbench+C:\devtools\altera\90sp2\ip\altera\frame_buffer\lib+C:\devtools\altera\90sp2\ip\altera\frame_buffer\lib\ip_toolbench+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip+C:\devtools\altera\90sp2\quartus\sopc_builder\model\lib+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_cf+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_cfi_flash+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_dc_fifo+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_dma+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_epcs_flash_controller+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_fifo+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_half_rate_bridge+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_jtag_uart+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_lan91c111+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_lcd_16207+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_mailbox+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_multi_channel_shared_fifo+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_mutex+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_packets_to_master+C:\devtools\altera\90sp2\ip\altera\pci_compiler\lib\ip_toolbench+C:\devtools\altera\90sp2\ip\altera\pci_compiler\lib\sopc_builder+C:\devtools\altera\90sp2\ip\altera\pci_express_compiler\lib\ip_toolbench+C:\devtools\altera\90sp2\ip\altera\pci_express_compiler\lib\sopc_builder+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_performance_counter+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_pio+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_pixel_converter+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_remote_update_cycloneiii+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_round_robin_scheduler+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_sc_fifo+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_sgdma+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_spi+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_st_bytes_to_packets+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_st_idle_inserter+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_st_idle_remover+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_st_packets_to_bytes+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_sysid+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_timer+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_uart+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_video_sync_generator+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_jtag_avalon_master+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_jtag_phy+C:\devtools\altera\90sp2\ip\altera\nios2_ip\altera_nios2+C:\devtools\altera\90sp2\ip\altera\nios2_ip+C:\devtools\altera\90sp2\ip\altera\ddr_high_perf\lib\ip_toolbench+C:\devtools\altera\90sp2\ip\altera\ddr_high_perf\lib\sopc_builder+C:\devtools\altera\90sp2\ip\altera\ddr2_high_perf\lib\ip_toolbench+C:\devtools\altera\90sp2\ip\altera\ddr2_high_perf\lib\sopc_builder+C:\devtools\altera\90sp2\ip\altera\ddr3_high_perf\lib\ip_toolbench+C:\devtools\altera\90sp2\ip\altera\ddr3_high_perf\lib\sopc_builder+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_altpll+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\verification\avalon_mm_bfm\avalon_mm_master_bfm+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\verification\avalon_mm_bfm\avalon_mm_slave_bfm+C:\devtools\altera\90sp2\ip\altera\crc_compiler\lib\ip_toolbench+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_data_sink+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_data_source+C:\devtools\altera\90sp2\ip\altera\ddr_ddr2_sdram\lib\sopc_builder+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_pci_lite+C:\devtools\altera\90sp2\ip\altera\rapidio\lib\ip_toolbench+C:\devtools\altera\90sp2\ip\altera\sdi\lib\ip_toolbench+C:\devtools\altera\90sp2\ip\sls\usb20hr_ocp_eval_pack\hardware\component+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_spislave_to_avalonmm_bridge+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_spi_phy_slave+C:\devtools\altera\90sp2\ip\altera\triple_speed_ethernet\lib\ip_toolbench+C:\devtools\altera\90sp2\ip\altera\triple_speed_ethernet\lib\sopc_builder+C:\devtools\altera\90sp2\ip\altera\triple_speed_ethernet\lib\sopc_builder\altera_triple_speed_ethernet++c:/devtools/altera/90sp2/quartus/../ip/altera/sopc_builder_ip+c:/devtools/altera/90sp2/quartus/../ip/altera/nios2_ip"\r
projects / freertos / commitdiff