--- /dev/null
+#Script for AT91EB40a\r
+\r
+#Atmel ties SRST & TRST together, at which point it makes\r
+#no sense to use TRST, but use TMS instead.\r
+#\r
+#The annoying thing with tying SRST & TRST together is that\r
+#there is no way to halt the CPU *before and during* the\r
+#SRST reset, which means that the CPU will run a number\r
+#of cycles before it can be halted(as much as milliseconds).\r
+openocd {reset_config srst_only srst_pulls_trst}\r
+ \r
+#jtag scan chain\r
+#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)\r
+openocd {jtag_device 4 0x1 0xf 0xe}\r
+\r
+#target configuration\r
+openocd {target arm7tdmi little 0 arm7tdmi-s_r4}\r
+\r
+# speed up memory downloads\r
+openocd {arm7 fast_memory_access enable}\r
+openocd {arm7_9 dcc_downloads enable}\r
+\r
+# OpenOCD does not have a flash driver for for AT91FR40162S \r
+openocd {target_script 0 reset event/at91eb40a_reset.script}\r
+\r
+#flash driver\r
+openocd {flash bank ecosflash 0x01000000 0x200000 2 2 0 ecos/at91eb40a.elf}\r
+\r
+# required for usable performance. Used for lots of\r
+# other things than flash programming.\r
+openocd {working_area 0 0x00000000 0x20000 nobackup}\r
+\r
+#force hardware values - we're running out of flash more\r
+#often than not. The user can disable this in his\r
+#subsequent config script.\r
+openocd {arm7_9 force_hw_bkpts enable}\r
+\r
+set reset_count 0\r
+\r
+proc target_reset_0 {} {\r
+ global reset_count\r
+ # Reset script for AT91EB40a\r
+ openocd {reg cpsr 0x000000D3} \r
+ openocd {mww 0xFFE00020 0x1}\r
+ openocd {mww 0xFFE00024 0x00000000} \r
+ openocd {mww 0xFFE00000 0x01002539} \r
+ openocd {mww 0xFFFFF124 0xFFFFFFFF} \r
+ openocd {mww 0xffff0010 0x100}\r
+ openocd {mww 0xffff0034 0x100}\r
+ set reset_count [expr $reset_count+1]\r
+ puts "Testing reset $reset_count !"\r
+}\r