mips32: fix typos

Change-Id: Ibb98fe3da68bf670a5bb83600bb49647db8a4163
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Reviewed-on: http://openocd.zylin.com/2338
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>

diff --git a/src/target/mips32.c b/src/target/mips32.c
index d842705fffd1ba8561c328d9e2d2d0dbefa50275..75197f170f85f5368e2bce18a1eda6d67522dac7 100644 (file)
--- a/src/target/mips32.c
+++ b/src/target/mips32.c
@@ -289,7 +289,7 @@ int mips32_init_arch_info(struct target *target, struct mips32_common *mips32, s
        mips32->common_magic = MIPS32_COMMON_MAGIC;
        mips32->fast_data_area = NULL;
 
-       /* has breakpoint/watchpint unit been scanned */
+       /* has breakpoint/watchpoint unit been scanned */
        mips32->bp_scanned = 0;
        mips32->data_break_list = NULL;
 

diff --git a/src/target/mips32.h b/src/target/mips32.h
index 951b2ed72659c1bfb2b2be518d71c11c62fee094..4f44384a38088c729d7bc361fdc2021c963265ea 100644 (file)
--- a/src/target/mips32.h
+++ b/src/target/mips32.h
@@ -203,7 +203,7 @@ struct mips32_algorithm {
 #define MIPS32_SYNCI_STEP      0x1     /* reg num od address step size to be used with synci instruction */
 
 /**
- * Cache operations definietions
+ * Cache operations definitions
  * Operation field is 5 bits long :
  * 1) bits 1..0 hold cache type
  * 2) bits 4..2 hold operation code