]> git.sur5r.net Git - openocd/commitdiff
aarch64: fix error recovery in aarch64_dpm_prepare
authorMatthias Welwarsky <matthias.welwarsky@sysgo.com>
Fri, 16 Sep 2016 09:06:42 +0000 (11:06 +0200)
committerMatthias Welwarsky <matthias.welwarsky@sysgo.com>
Fri, 10 Feb 2017 13:01:38 +0000 (14:01 +0100)
Flush DTRRX with a dummy read if it's full, clear sticky errors
by writing CSE bit to EDRCR register.

Change-Id: Ia42ae9d3859ba6cbe892d48584e21acdd4e25c84
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
src/target/aarch64.c

index 4097d116066ee6d8a27b570e993f9a9e75b33f14..fcf600d17c8efef54a472ed0ece00639757aa107 100644 (file)
@@ -360,10 +360,14 @@ static int aarch64_dpm_prepare(struct arm_dpm *dpm)
        if (dscr & DSCR_DTR_RX_FULL) {
                LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr);
                /* Clear DCCRX */
-               retval = aarch64_exec_opcode(
-                               a8->armv8_common.arm.target,
-                               0xd5130400,
-                               &dscr);
+               retval = mem_ap_read_u32(a8->armv8_common.debug_ap,
+                       a8->armv8_common.debug_base + CPUV8_DBG_DTRRX, &dscr);
+               if (retval != ERROR_OK)
+                       return retval;
+
+               /* Clear sticky error */
+               retval = mem_ap_write_u32(a8->armv8_common.debug_ap,
+                       a8->armv8_common.debug_base + CPUV8_DBG_DRCR, DRCR_CSE);
                if (retval != ERROR_OK)
                        return retval;
        }