build: fix clang warnings

Change-Id: I3c6a63a18034535f0a8c2c62ba8a708f09d7839b
Signed-off-by: Martin Nowak <dawg@dawgfoto.de>
Reviewed-on: http://openocd.zylin.com/765
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>

diff --git a/src/flash/mflash.c b/src/flash/mflash.c
index 5d1f3b6ed88cb3baf27ce7ea44d3497201316915..4ef8cb69eedad2b8171bad4e9bd74b7171cb3097 100644 (file)
--- a/src/flash/mflash.c
+++ b/src/flash/mflash.c
@@ -510,7 +510,7 @@ static int mg_mflash_read_sects(void *buff, uint32_t sect_num, uint32_t sect_cnt
 }
 
 static int mg_mflash_do_write_sects(void *buff, uint32_t sect_num, uint32_t sect_cnt,
-       mg_io_type_cmd cmd)
+       uint8_t cmd)
 {
        uint32_t i, address;
        int ret;

diff --git a/src/target/arm_disassembler.c b/src/target/arm_disassembler.c
index f11a5221a15968d0619f955fe1b7c7c0941d0c0a..abeb08e9bfa223424a44757a54a997a076a049f0 100644 (file)
--- a/src/target/arm_disassembler.c
+++ b/src/target/arm_disassembler.c
@@ -2890,7 +2890,7 @@ static int t2ev_cond_b(uint32_t opcode, uint32_t address,
        offset = opcode & 0x7ff;
        offset |= (opcode & 0x003f0000) >> 5;
        if (opcode & (1 << 26)) {
-               offset |= 0xffff << 19;
+               offset |= 0x1fff << 19;
                if ((opcode & (1 << 11)) == 0)
                        b17 = 0;
                if ((opcode & (1 << 13)) == 0)

diff --git a/src/target/arm_simulator.c b/src/target/arm_simulator.c
index 215739d67222072d93e121ac76f77b2d7a3fd2c5..9ddc85be06a67339110c0de986151e85d9159af5 100644 (file)
--- a/src/target/arm_simulator.c
+++ b/src/target/arm_simulator.c
@@ -524,7 +524,7 @@ static int arm_simulate_step_core(struct target *target,
 
                switch (instruction.info.load_store_multiple.addressing_mode) {
                        case 0: /* Increment after */
-                               Rn = Rn;
+                               /* Rn = Rn; */
                                break;
                        case 1: /* Increment before */
                                Rn = Rn + 4;
@@ -604,7 +604,7 @@ static int arm_simulate_step_core(struct target *target,
 
                        switch (instruction.info.load_store_multiple.addressing_mode) {
                                case 0: /* Increment after */
-                                       Rn = Rn;
+                                       /* Rn = Rn; */
                                        break;
                                case 1: /* Increment before */
                                        Rn = Rn + 4;

diff --git a/src/target/armv7a.c b/src/target/armv7a.c
index 48fdf8b3cde36879caca7b882b488aaecdf9d806..e95e99b07b32cf1e655166137bc0fc41fbdbccfa 100644 (file)
--- a/src/target/armv7a.c
+++ b/src/target/armv7a.c
@@ -387,7 +387,7 @@ static int  armv7a_flush_all_data(struct target *target)
                head = target->head;
                while (head != (struct target_list *)NULL) {
                        curr = head->target;
-                       if ((curr->state == TARGET_HALTED)) {
+                       if (curr->state == TARGET_HALTED) {
                                LOG_INFO("Wait flushing data l1 on core %d", curr->coreid);
                                retval = _armv7a_flush_all_data(curr);
                        }