--- /dev/null
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+</cconfiguration>\r
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+</storageModule>\r
+</cproject>\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
+<projectDescription>\r
+ <name>RTOSDemo</name>\r
+ <comment></comment>\r
+ <projects>\r
+ </projects>\r
+ <buildSpec>\r
+ <buildCommand>\r
+ <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>\r
+ <arguments>\r
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+ <value></value>\r
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+ <value>true</value>\r
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+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.autoBuildTarget</key>\r
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+ </dictionary>\r
+ <dictionary>\r
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+ <value></value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.buildCommand</key>\r
+ <value>make</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.buildLocation</key>\r
+ <value>${workspace_loc:/RTOSDemo/Debug}</value>\r
+ </dictionary>\r
+ <dictionary>\r
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+ <value>clean</value>\r
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+ <dictionary>\r
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+ <value>all</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.stopOnError</key>\r
+ <value>true</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>\r
+ <value>true</value>\r
+ </dictionary>\r
+ </arguments>\r
+ </buildCommand>\r
+ <buildCommand>\r
+ <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>\r
+ <arguments>\r
+ </arguments>\r
+ </buildCommand>\r
+ </buildSpec>\r
+ <natures>\r
+ <nature>org.eclipse.cdt.core.cnature</nature>\r
+ <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>\r
+ <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>\r
+ </natures>\r
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--- /dev/null
+#Sun Apr 03 18:36:27 BST 2011\r
+eclipse.preferences.version=1\r
+org.eclipse.ltk.core.refactoring.enable.project.refactoring.history=false\r
--- /dev/null
+REM This file should be executed from the command line prior to the first\r
+REM build. It will be necessary to refresh the Eclipse project once the\r
+REM .bat file has been executed (normally just press F5 to refresh).\r
+\r
+REM Copies all the required files from their location within the standard\r
+REM FreeRTOS directory structure to under the Eclipse project directory.\r
+REM This permits the Eclipse project to be used in 'managed' mode and without\r
+REM having to setup any linked resources.\r
+\r
+REM Have the files already been copied?\r
+IF EXIST FreeRTOS_Source Goto END\r
+\r
+ REM Create the required directory structure.\r
+ MD FreeRTOS_Source\r
+ MD FreeRTOS_Source\include \r
+ MD FreeRTOS_Source\portable\GCC\r
+ MD FreeRTOS_Source\portable\GCC\ARM_CM3\r
+ MD FreeRTOS_Source\portable\MemMang \r
+ \r
+ REM Copy the core kernel files.\r
+ copy ..\..\Source\tasks.c FreeRTOS_Source\r
+ copy ..\..\Source\queue.c FreeRTOS_Source\r
+ copy ..\..\Source\list.c FreeRTOS_Source\r
+ copy ..\..\Source\timers.c FreeRTOS_Source\r
+ \r
+ REM Copy the common header files\r
+\r
+ copy ..\..\Source\include\*.* FreeRTOS_Source\include\r
+ \r
+ REM Copy the portable layer files\r
+ copy ..\..\Source\portable\GCC\ARM_CM3\*.* FreeRTOS_Source\portable\GCC\ARM_CM3\r
+ \r
+ REM Copy the basic memory allocation files\r
+ copy ..\..\Source\portable\MemMang\heap_1.c FreeRTOS_Source\portable\MemMang\r
+ \r
+: END\r
--- /dev/null
+/*\r
+ FreeRTOS V6.1.1 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * If you are: *\r
+ * *\r
+ * + New to FreeRTOS, *\r
+ * + Wanting to learn FreeRTOS or multitasking in general quickly *\r
+ * + Looking for basic training, *\r
+ * + Wanting to improve your FreeRTOS skills and productivity *\r
+ * *\r
+ * then take a look at the FreeRTOS books - available as PDF or paperback *\r
+ * *\r
+ * "Using the FreeRTOS Real Time Kernel - a Practical Guide" *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ * A pdf reference manual is also available. Both are usually delivered *\r
+ * to your inbox within 20 minutes to two hours when purchased between 8am *\r
+ * and 8pm GMT (although please allow up to 24 hours in case of *\r
+ * exceptional circumstances). Thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ ***NOTE*** The exception to the GPL is included to allow you to distribute\r
+ a combined work that includes FreeRTOS without being obliged to provide the\r
+ source code for proprietary components outside of the FreeRTOS kernel.\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT\r
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+\r
+/* The following #error directive is to remind users that a batch file must be\r
+ * executed prior to this project being built. The batch file *cannot* be \r
+ * executed from within CCS4! Once it has been executed, re-open or refresh \r
+ * the CCS4 project and remove the #error line below.\r
+ */\r
+//#error Ensure CreateProjectDirectoryStructure.bat has been executed before building. See comment immediately above.\r
+\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\r
+ *\r
+ * See http://www.freertos.org/a00110.html.\r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 1\r
+#define configUSE_TICK_HOOK 0\r
+#define configCPU_CLOCK_HZ ( 75000000UL )\r
+#define configTICK_RATE_HZ ( ( portTickType ) 1000 )\r
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 70 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 7 * 1024 ) )\r
+#define configMAX_TASK_NAME_LEN ( 10 )\r
+#define configUSE_TRACE_FACILITY 0\r
+#define configUSE_16_BIT_TICKS 0\r
+#define configIDLE_SHOULD_YIELD 1\r
+#define configUSE_MUTEXES 1\r
+#define configQUEUE_REGISTRY_SIZE 0\r
+#define configGENERATE_RUN_TIME_STATS 0\r
+#define configCHECK_FOR_STACK_OVERFLOW 2\r
+#define configUSE_RECURSIVE_MUTEXES 0\r
+#define configUSE_MALLOC_FAILED_HOOK 1\r
+#define configUSE_APPLICATION_TASK_TAG 0\r
+#define configUSE_COUNTING_SEMAPHORES 0\r
+\r
+/* Co-routine definitions. */\r
+#define configUSE_CO_ROUTINES 0\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Software timer definitions. */\r
+#define configUSE_TIMERS 1\r
+#define configTIMER_TASK_PRIORITY ( 3 )\r
+#define configTIMER_QUEUE_LENGTH 5\r
+#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 1\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskCleanUpResources 1\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+\r
+/* Use the system definition, if there is one */\r
+#ifdef __NVIC_PRIO_BITS\r
+ #define configPRIO_BITS __NVIC_PRIO_BITS\r
+#else\r
+ #define configPRIO_BITS 4 /* 15 priority levels */\r
+#endif\r
+\r
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 15\r
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5\r
+\r
+/* The lowest priority. */\r
+#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )\r
+/* Priority 5, or 160 as only the top three bits are implemented. */\r
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )\r
+ \r
+#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); } \r
+ \r
+#define vPortSVCHandler SVC_Handler\r
+#define xPortPendSVHandler PendSV_Handler\r
+#define vPortSVCHandler SVC_Handler\r
+#define xPortSysTickHandler SysTick_Handler\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
+\r
--- /dev/null
+/*******************************************************************************\r
+ * (c) Copyright 2009 Actel Corporation. All rights reserved.\r
+ * \r
+ * SmartFusion A2FxxxM3 Cortex Microcontroller Software Interface - Peripheral\r
+ * Access Layer.\r
+ *\r
+ * This file describes the interrupt assignment and peripheral registers for\r
+ * the SmartFusion A2FxxxM3 familly of devices. \r
+ *\r
+ * SVN $Revision: 2331 $\r
+ * SVN $Date: 2010-02-26 12:02:06 +0000 (Fri, 26 Feb 2010) $\r
+ */\r
+#ifndef __A2FXXXM3_H__\r
+#define __A2FXXXM3_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif \r
+\r
+/*\r
+ * ==========================================================================\r
+ * ---------- Interrupt Number Definition -----------------------------------\r
+ * ==========================================================================\r
+ */\r
+\r
+typedef enum IRQn\r
+{\r
+/****** Cortex-M3 Processor Exceptions Numbers *********************************************************/\r
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */\r
+ HardFault_IRQn = -13, /*!< 2 Hard Fault Interrupt */\r
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */\r
+ BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */\r
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */\r
+ SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */\r
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */\r
+ PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */\r
+\r
+/****** SmartFusion specific Interrupt Numbers *********************************************************/\r
+ WdogWakeup_IRQn = 0, /*!< WatchDog wakeup interrupt */\r
+ BrownOut_1_5V_IRQn = 1, /*!< Supply dropped below 1.5V */\r
+ BrownOut_3_3V_IRQn = 2, /*!< Supply dropped below 1.5V */\r
+ RTC_Match_IRQn = 3, /*!< RTC match interrupt */\r
+ RTCIF_Pub_IRQn = 4, /*!< RTC interface push button interrupt */\r
+ EthernetMAC_IRQn = 5, /*!< Ethernet MAC interrupt */\r
+ IAP_IRQn = 6, /*!< In Application Programming (IAP) interrupt */\r
+ ENVM0_IRQn = 7, /*!< eNVM0 operation completion interrupt */\r
+ ENVM1_IRQn = 8, /*!< eNVM1 operation completion interrupt */\r
+ DMA_IRQn = 9, /*!< Peripheral DMA interrupt */\r
+ UART0_IRQn = 10, /*!< UART0 interrupt */\r
+ UART1_IRQn = 11, /*!< UART1 interrupt */\r
+ SPI0_IRQn = 12, /*!< SPI0 interrupt */\r
+ SPI1_IRQn = 13, /*!< SP1 interrupt */\r
+ I2C0_IRQn = 14, /*!< I2C0 interrupt */\r
+ I2C0_SMBAlert_IRQn = 15, /*!< I2C0 SMBus Alert interrupt */\r
+ I2C0_SMBus_IRQn = 16, /*!< I2C0 SMBus Suspend interrupt */\r
+ I2C1_IRQn = 17, /*!< I2C1 interrupt */\r
+ I2C1_SMBAlert_IRQn = 18, /*!< I2C1 SMBus Alert interrupt */\r
+ I2C1_SMBus_IRQn = 19, /*!< I2C1 SMBus Suspend interrupt */\r
+ Timer1_IRQn = 20, /*!< Timer1 interrupt */\r
+ Timer2_IRQn = 21, /*!< Timer2 interrupt */\r
+ PLL_Lock_IRQn = 22, /*!< PLL lock interrupt */\r
+ PLL_LockLost_IRQn = 23, /*!< PLL loss of lock interrupt */\r
+ CommError_IRQn = 24, /*!< Communications Matrix error interrupt */\r
+ Fabric_IRQn = 31, /*!< FPGA fabric interrupt */\r
+ GPIO0_IRQn = 32, /*!< GPIO 0 interrupt */\r
+ GPIO1_IRQn = 33, /*!< GPIO 1 interrupt */\r
+ GPIO2_IRQn = 34, /*!< GPIO 2 interrupt */\r
+ GPIO3_IRQn = 35, /*!< GPIO 3 interrupt */\r
+ GPIO4_IRQn = 36, /*!< GPIO 4 interrupt */\r
+ GPIO5_IRQn = 37, /*!< GPIO 5 interrupt */\r
+ GPIO6_IRQn = 38, /*!< GPIO 6 interrupt */\r
+ GPIO7_IRQn = 39, /*!< GPIO 7 interrupt */\r
+ GPIO8_IRQn = 40, /*!< GPIO 8 interrupt */\r
+ GPIO9_IRQn = 41, /*!< GPIO 9 interrupt */\r
+ GPIO10_IRQn = 42, /*!< GPIO 10 interrupt */\r
+ GPIO11_IRQn = 43, /*!< GPIO 11 interrupt */\r
+ GPIO12_IRQn = 44, /*!< GPIO 12 interrupt */\r
+ GPIO13_IRQn = 45, /*!< GPIO 13 interrupt */\r
+ GPIO14_IRQn = 46, /*!< GPIO 14 interrupt */\r
+ GPIO15_IRQn = 47, /*!< GPIO 15 interrupt */\r
+ GPIO16_IRQn = 48, /*!< GPIO 16 interrupt */\r
+ GPIO17_IRQn = 49, /*!< GPIO 17 interrupt */\r
+ GPIO18_IRQn = 50, /*!< GPIO 18 interrupt */\r
+ GPIO19_IRQn = 51, /*!< GPIO 19 interrupt */\r
+ GPIO20_IRQn = 52, /*!< GPIO 20 interrupt */\r
+ GPIO21_IRQn = 53, /*!< GPIO 21 interrupt */\r
+ GPIO22_IRQn = 54, /*!< GPIO 22 interrupt */\r
+ GPIO23_IRQn = 55, /*!< GPIO 23 interrupt */\r
+ GPIO24_IRQn = 56, /*!< GPIO 24 interrupt */\r
+ GPIO25_IRQn = 57, /*!< GPIO 25 interrupt */\r
+ GPIO26_IRQn = 58, /*!< GPIO 26 interrupt */\r
+ GPIO27_IRQn = 59, /*!< GPIO 27 interrupt */\r
+ GPIO28_IRQn = 60, /*!< GPIO 28 interrupt */\r
+ GPIO29_IRQn = 61, /*!< GPIO 29 interrupt */\r
+ GPIO30_IRQn = 62, /*!< GPIO 30 interrupt */\r
+ GPIO31_IRQn = 63, /*!< GPIO 31 interrupt */\r
+ ACE_PC0_Flag0_IRQn = 64, /*!< ACE SSE program counter 0 flag 0 interrupt */\r
+ ACE_PC0_Flag1_IRQn = 65, /*!< ACE SSE program counter 0 flag 1 interrupt */\r
+ ACE_PC0_Flag2_IRQn = 66, /*!< ACE SSE program counter 0 flag 2 interrupt */\r
+ ACE_PC0_Flag3_IRQn = 67, /*!< ACE SSE program counter 0 flag 3 interrupt */\r
+ ACE_PC1_Flag0_IRQn = 68, /*!< ACE SSE program counter 1 flag 0 interrupt */\r
+ ACE_PC1_Flag1_IRQn = 69, /*!< ACE SSE program counter 1 flag 1 interrupt */\r
+ ACE_PC1_Flag2_IRQn = 70, /*!< ACE SSE program counter 1 flag 2 interrupt */\r
+ ACE_PC1_Flag3_IRQn = 71, /*!< ACE SSE program counter 1 flag 3 interrupt */\r
+ ACE_PC2_Flag0_IRQn = 72, /*!< ACE SSE program counter 2 flag 0 interrupt */\r
+ ACE_PC2_Flag1_IRQn = 73, /*!< ACE SSE program counter 2 flag 1 interrupt */\r
+ ACE_PC2_Flag2_IRQn = 74, /*!< ACE SSE program counter 2 flag 2 interrupt */\r
+ ACE_PC2_Flag3_IRQn = 75, /*!< ACE SSE program counter 2 flag 3 interrupt */\r
+ ACE_ADC0_DataValid_IRQn = 76, /*!< ACE ADC0 data valid interrupt */\r
+ ACE_ADC1_DataValid_IRQn = 77, /*!< ACE ADC1 data valid interrupt */\r
+ ACE_ADC2_DataValid_IRQn = 78, /*!< ACE ADC2 data valid interrupt */\r
+ ACE_ADC0_CalDone_IRQn = 79, /*!< ACE ADC0 calibration done interrupt */\r
+ ACE_ADC1_CalDone_IRQn = 80, /*!< ACE ADC1 calibration done interrupt */\r
+ ACE_ADC2_CalDone_IRQn = 81, /*!< ACE ADC2 calibration done interrupt */\r
+ ACE_ADC0_CalStart_IRQn = 82, /*!< ACE ADC0 calibration start interrupt */\r
+ ACE_ADC1_CalStart_IRQn = 83, /*!< ACE ADC1 calibration start interrupt */\r
+ ACE_ADC2_CalStart_IRQn = 84, /*!< ACE ADC2 calibration start interrupt */\r
+ ACE_Comp0_Fall_IRQn = 85, /*!< ACE comparator 0 falling under reference interrupt */\r
+ ACE_Comp1_Fall_IRQn = 86, /*!< ACE comparator 1 falling under reference interrupt */\r
+ ACE_Comp2_Fall_IRQn = 87, /*!< ACE comparator 2 falling under reference interrupt */\r
+ ACE_Comp3_Fall_IRQn = 88, /*!< ACE comparator 3 falling under reference interrupt */\r
+ ACE_Comp4_Fall_IRQn = 89, /*!< ACE comparator 4 falling under reference interrupt */\r
+ ACE_Comp5_Fall_IRQn = 90, /*!< ACE comparator 5 falling under reference interrupt */\r
+ ACE_Comp6_Fall_IRQn = 91, /*!< ACE comparator 6 falling under reference interrupt */\r
+ ACE_Comp7_Fall_IRQn = 92, /*!< ACE comparator 7 falling under reference interrupt */\r
+ ACE_Comp8_Fall_IRQn = 93, /*!< ACE comparator 8 falling under reference interrupt */\r
+ ACE_Comp9_Fall_IRQn = 94, /*!< ACE comparator 9 falling under reference interrupt */\r
+ ACE_Comp10_Fall_IRQn = 95, /*!< ACE comparator 10 falling under reference interrupt */\r
+ ACE_Comp11_Fall_IRQn = 96, /*!< ACE comparator 11 falling under reference interrupt */\r
+ ACE_Comp0_Rise_IRQn = 97, /*!< ACE comparator 0 rising over reference interrupt */\r
+ ACE_Comp1_Rise_IRQn = 98, /*!< ACE comparator 1 rising over reference interrupt */\r
+ ACE_Comp2_Rise_IRQn = 99, /*!< ACE comparator 2 rising over reference interrupt */\r
+ ACE_Comp3_Rise_IRQn = 100, /*!< ACE comparator 3 rising over reference interrupt */\r
+ ACE_Comp4_Rise_IRQn = 101, /*!< ACE comparator 4 rising over reference interrupt */\r
+ ACE_Comp5_Rise_IRQn = 102, /*!< ACE comparator 5 rising over reference interrupt */\r
+ ACE_Comp6_Rise_IRQn = 103, /*!< ACE comparator 6 rising over reference interrupt */\r
+ ACE_Comp7_Rise_IRQn = 104, /*!< ACE comparator 7 rising over reference interrupt */\r
+ ACE_Comp8_Rise_IRQn = 105, /*!< ACE comparator 8 rising over reference interrupt */\r
+ ACE_Comp9_Rise_IRQn = 106, /*!< ACE comparator 9 rising over reference interrupt */\r
+ ACE_Comp10_Rise_IRQn = 107, /*!< ACE comparator 10 rising over reference interrupt */\r
+ ACE_Comp11_Rise_IRQn = 108, /*!< ACE comparator 11 rising over reference interrupt */\r
+ ACE_ADC0_FifoFull_IRQn = 109, /*!< ACE ADC0 FIFO full interrupt */\r
+ ACE_ADC0_FifoAFull_IRQn = 110, /*!< ACE ADC0 FIFO almost full interrupt */\r
+ ACE_ADC0_FifoEmpty_IRQn = 111, /*!< ACE ADC0 FIFO empty interrupt */\r
+ ACE_ADC1_FifoFull_IRQn = 112, /*!< ACE ADC1 FIFO full interrupt */\r
+ ACE_ADC1_FifoAFull_IRQn = 113, /*!< ACE ADC1 FIFO almost full interrupt */\r
+ ACE_ADC1_FifoEmpty_IRQn = 114, /*!< ACE ADC1 FIFO empty interrupt */\r
+ ACE_ADC2_FifoFull_IRQn = 115, /*!< ACE ADC2 FIFO full interrupt */\r
+ ACE_ADC2_FifoAFull_IRQn = 116, /*!< ACE ADC2 FIFO almost full interrupt */\r
+ ACE_ADC2_FifoEmpty_IRQn = 117, /*!< ACE ADC2 FIFO empty interrupt */\r
+ ACE_PPE_Flag0_IRQn = 118, /*!< ACE post processing engine flag 0 interrupt */\r
+ ACE_PPE_Flag1_IRQn = 119, /*!< ACE post processing engine flag 1 interrupt */\r
+ ACE_PPE_Flag2_IRQn = 120, /*!< ACE post processing engine flag 2 interrupt */\r
+ ACE_PPE_Flag3_IRQn = 121, /*!< ACE post processing engine flag 3 interrupt */\r
+ ACE_PPE_Flag4_IRQn = 122, /*!< ACE post processing engine flag 4 interrupt */\r
+ ACE_PPE_Flag5_IRQn = 123, /*!< ACE post processing engine flag 5 interrupt */\r
+ ACE_PPE_Flag6_IRQn = 124, /*!< ACE post processing engine flag 6 interrupt */\r
+ ACE_PPE_Flag7_IRQn = 125, /*!< ACE post processing engine flag 7 interrupt */\r
+ ACE_PPE_Flag8_IRQn = 126, /*!< ACE post processing engine flag 8 interrupt */\r
+ ACE_PPE_Flag9_IRQn = 127, /*!< ACE post processing engine flag 9 interrupt */\r
+ ACE_PPE_Flag10_IRQn = 128, /*!< ACE post processing engine flag 10 interrupt */\r
+ ACE_PPE_Flag11_IRQn = 129, /*!< ACE post processing engine flag 11 interrupt */\r
+ ACE_PPE_Flag12_IRQn = 130, /*!< ACE post processing engine flag 12 interrupt */\r
+ ACE_PPE_Flag13_IRQn = 131, /*!< ACE post processing engine flag 13 interrupt */\r
+ ACE_PPE_Flag14_IRQn = 132, /*!< ACE post processing engine flag 14 interrupt */\r
+ ACE_PPE_Flag15_IRQn = 133, /*!< ACE post processing engine flag 15 interrupt */\r
+ ACE_PPE_Flag16_IRQn = 134, /*!< ACE post processing engine flag 16 interrupt */\r
+ ACE_PPE_Flag17_IRQn = 135, /*!< ACE post processing engine flag 17 interrupt */\r
+ ACE_PPE_Flag18_IRQn = 136, /*!< ACE post processing engine flag 18 interrupt */\r
+ ACE_PPE_Flag19_IRQn = 137, /*!< ACE post processing engine flag 19 interrupt */\r
+ ACE_PPE_Flag20_IRQn = 138, /*!< ACE post processing engine flag 20 interrupt */\r
+ ACE_PPE_Flag21_IRQn = 139, /*!< ACE post processing engine flag 21 interrupt */\r
+ ACE_PPE_Flag22_IRQn = 140, /*!< ACE post processing engine flag 22 interrupt */\r
+ ACE_PPE_Flag23_IRQn = 141, /*!< ACE post processing engine flag 23 interrupt */\r
+ ACE_PPE_Flag24_IRQn = 142, /*!< ACE post processing engine flag 24 interrupt */\r
+ ACE_PPE_Flag25_IRQn = 143, /*!< ACE post processing engine flag 25 interrupt */\r
+ ACE_PPE_Flag26_IRQn = 144, /*!< ACE post processing engine flag 26 interrupt */\r
+ ACE_PPE_Flag27_IRQn = 145, /*!< ACE post processing engine flag 27 interrupt */\r
+ ACE_PPE_Flag28_IRQn = 146, /*!< ACE post processing engine flag 28 interrupt */\r
+ ACE_PPE_Flag29_IRQn = 147, /*!< ACE post processing engine flag 29 interrupt */\r
+ ACE_PPE_Flag30_IRQn = 148, /*!< ACE post processing engine flag 30 interrupt */\r
+ ACE_PPE_Flag31_IRQn = 149 /*!< ACE post processing engine flag 31 interrupt */\r
+} IRQn_Type;\r
+\r
+\r
+/*\r
+ * ==========================================================================\r
+ * ----------- Processor and Core Peripheral Section ------------------------\r
+ * ==========================================================================\r
+ */\r
+\r
+/* Configuration of the Cortex-M3 Processor and Core Peripherals */\r
+#define __MPU_PRESENT 1 /*!< SmartFusion includes a MPU */\r
+#define __NVIC_PRIO_BITS 5 /*!< SmartFusion uses 5 Bits for the Priority Levels */\r
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */\r
+\r
+\r
+#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */\r
+#include "system_a2fxxxm3.h" /* SmartFusion System */\r
+\r
+/******************************************************************************/\r
+/* Device Specific Peripheral registers structures */\r
+/******************************************************************************/\r
+#if defined ( __CC_ARM )\r
+ /* Enable anonymous unions when building using Keil-MDK */\r
+ #pragma anon_unions\r
+#endif\r
+/*----------------------------------------------------------------------------*/\r
+/*----------------------------------- UART -----------------------------------*/\r
+/*----------------------------------------------------------------------------*/\r
+typedef struct\r
+{\r
+ union\r
+ {\r
+ __I uint8_t RBR;\r
+ __O uint8_t THR;\r
+ __IO uint8_t DLR;\r
+ uint32_t RESERVED0;\r
+ };\r
+\r
+ union\r
+ {\r
+ __IO uint8_t DMR;\r
+ __IO uint8_t IER;\r
+ uint32_t RESERVED1;\r
+ };\r
+\r
+ union\r
+ {\r
+ __IO uint8_t IIR;\r
+ __IO uint8_t FCR;\r
+ uint32_t RESERVED2;\r
+ }; \r
+\r
+ __IO uint8_t LCR;\r
+ uint8_t RESERVED3;\r
+ uint16_t RESERVED4;\r
+ __IO uint8_t MCR;\r
+ uint8_t RESERVED5;\r
+ uint16_t RESERVED6;\r
+ __I uint8_t LSR;\r
+ uint8_t RESERVED7;\r
+ uint16_t RESERVED8;\r
+ __I uint8_t MSR;\r
+ uint8_t RESERVED9;\r
+ uint16_t RESERVED10;\r
+ __IO uint8_t SR;\r
+ uint8_t RESERVED11;\r
+ uint16_t RESERVED12;\r
+} UART_TypeDef;\r
+\r
+/*------------------------------------------------------------------------------\r
+ *\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[32];\r
+ \r
+ __IO uint32_t IER_ERBFI;\r
+ __IO uint32_t IER_ETBEI;\r
+ __IO uint32_t IER_ELSI;\r
+ __IO uint32_t IER_EDSSI;\r
+ \r
+ uint32_t RESERVED1[28];\r
+ \r
+ __IO uint32_t FCR_ENABLE;\r
+ __IO uint32_t FCR_CLEAR_RX_FIFO;\r
+ __IO uint32_t FCR_CLEAR_TX_FIFO;\r
+ __IO uint32_t FCR_RXRDY_TXRDYN_EN;\r
+ __IO uint32_t FCR_RESERVED0;\r
+ __IO uint32_t FCR_RESERVED1;\r
+ __IO uint32_t FCR_RX_TRIG0;\r
+ __IO uint32_t FCR_RX_TRIG1;\r
+ \r
+ uint32_t RESERVED2[24];\r
+ \r
+ __IO uint32_t LCR_WLS0;\r
+ __IO uint32_t LCR_WLS1;\r
+ __IO uint32_t LCR_STB;\r
+ __IO uint32_t LCR_PEN;\r
+ __IO uint32_t LCR_EPS;\r
+ __IO uint32_t LCR_SP;\r
+ __IO uint32_t LCR_SB;\r
+ __IO uint32_t LCR_DLAB;\r
+ \r
+ uint32_t RESERVED3[24];\r
+ \r
+ __IO uint32_t MCR_DTR;\r
+ __IO uint32_t MCR_RTS;\r
+ __IO uint32_t MCR_OUT1;\r
+ __IO uint32_t MCR_OUT2;\r
+ __IO uint32_t MCR_LOOP;\r
+ \r
+ uint32_t RESERVED4[27];\r
+ \r
+ __I uint32_t LSR_DR;\r
+ __I uint32_t LSR_OE;\r
+ __I uint32_t LSR_PE;\r
+ __I uint32_t LSR_FE;\r
+ __I uint32_t LSR_BI;\r
+ __I uint32_t LSR_THRE;\r
+ __I uint32_t LSR_TEMT;\r
+ __I uint32_t LSR_FIER;\r
+ \r
+ uint32_t RESERVED5[24];\r
+ \r
+ __I uint32_t MSR_DCTS;\r
+ __I uint32_t MSR_DDSR;\r
+ __I uint32_t MSR_TERI;\r
+ __I uint32_t MSR_DDCD;\r
+ __I uint32_t MSR_CTS;\r
+ __I uint32_t MSR_DSR;\r
+ __I uint32_t MSR_RI;\r
+ __I uint32_t MSR_DCD;\r
+ \r
+} UART_BitBand_TypeDef;\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/*----------------------------------- I2C ------------------------------------*/\r
+/*----------------------------------------------------------------------------*/\r
+typedef struct\r
+{\r
+ __IO uint8_t CTRL;\r
+ uint8_t RESERVED0;\r
+ uint16_t RESERVED1;\r
+ uint8_t STATUS;\r
+ uint8_t RESERVED2;\r
+ uint16_t RESERVED3;\r
+ __IO uint8_t DATA;\r
+ uint8_t RESERVED4;\r
+ uint16_t RESERVED5;\r
+ __IO uint8_t ADDR;\r
+ uint8_t RESERVED6;\r
+ uint16_t RESERVED7;\r
+ __IO uint8_t SMBUS;\r
+ uint8_t RESERVED8;\r
+ uint16_t RESERVED9;\r
+ __IO uint8_t FREQ;\r
+ uint8_t RESERVED10;\r
+ uint16_t RESERVED11;\r
+ __IO uint8_t GLITCHREG;\r
+ uint8_t RESERVED12;\r
+ uint16_t RESERVED13;\r
+} I2C_TypeDef;\r
+\r
+/*------------------------------------------------------------------------------\r
+ *\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t CTRL_CR0;\r
+ uint32_t CTRL_CR1;\r
+ uint32_t CTRL_AA;\r
+ uint32_t CTRL_SI;\r
+ uint32_t CTRL_STO;\r
+ uint32_t CTRL_STA;\r
+ uint32_t CTRL_ENS1;\r
+ uint32_t CTRL_CR2;\r
+ uint32_t RESERVED0[56];\r
+ uint32_t DATA_DIR;\r
+ uint32_t RESERVED1[31];\r
+ uint32_t ADDR_GC;\r
+} I2C_BitBand_TypeDef;\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/*----------------------------------- SPI ------------------------------------*/\r
+/*----------------------------------------------------------------------------*/\r
+typedef struct\r
+{\r
+ __IO uint32_t CONTROL;\r
+ __IO uint32_t TXRXDF_SIZE;\r
+ __I uint32_t STATUS;\r
+ __O uint32_t INT_CLEAR;\r
+ __I uint32_t RX_DATA;\r
+ __O uint32_t TX_DATA;\r
+ __IO uint32_t CLK_GEN;\r
+ __IO uint32_t SLAVE_SELECT;\r
+ __I uint32_t MIS;\r
+ __I uint32_t RIS;\r
+} SPI_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL_ENABLE;\r
+ __IO uint32_t CTRL_MASTER;\r
+ __IO uint32_t CTRL_MODE[2];\r
+ __IO uint32_t CTRL_RX_INT_EN;\r
+ __IO uint32_t CTRL_TX_INT_EN;\r
+ __IO uint32_t CTRL_RX_OVERFLOW_INT_EN;\r
+ __IO uint32_t CTRL_TX_UNDERRUN_INT_EN;\r
+ __IO uint32_t CTRL_TXRXDFCOUNT[16];\r
+ __IO uint32_t CTRL_SPO;\r
+ __IO uint32_t CTRL_SPH;\r
+ __IO uint32_t CTRL_RESERVED[6];\r
+ \r
+ __IO uint32_t TXRXDF_SIZE[32];\r
+ \r
+ __I uint32_t STATUS_TX_DONE;\r
+ __I uint32_t STATUS_RX_RDY;\r
+ __I uint32_t STATUS_RX_CH_OV;\r
+ __I uint32_t STATUS_TX_CH_UV;\r
+ __I uint32_t STATUS_RX_FIFO_FULL;\r
+ __I uint32_t STATUS_RX_FIFO_FULL_NEXT;\r
+ __I uint32_t STATUS_RX_FIFO_EMPTY;\r
+ __I uint32_t STATUS_RX_FIFO_EMPTY_NEXT;\r
+ __I uint32_t STATUS_TX_FIFO_FULL;\r
+ __I uint32_t STATUS_TX_FIFO_FULL_NEXT;\r
+ __I uint32_t STATUS_TX_FIFO_EMPTY;\r
+ __I uint32_t STATUS_TX_FIFO_EMPTY_NEXT;\r
+ __I uint32_t STATUS_RESERVED[20];\r
+ \r
+ __O uint32_t INT_CLEAR_TX_DONE;\r
+ __O uint32_t INT_CLEAR_RX_RDY;\r
+ __O uint32_t INT_CLEAR_RX_OVER;\r
+ __O uint32_t INT_CLEAR_TX_UNDER;\r
+ __O uint32_t INT_CLEAR[28];\r
+ \r
+ __I uint32_t RX_DATA[32];\r
+ __O uint32_t TX_DATA[32];\r
+ __IO uint32_t CLK_GEN[32];\r
+ __IO uint32_t SLAVE_SELECT[32];\r
+ __I uint32_t MIS_TX_DONE;\r
+ __I uint32_t MIS_RX_RDY;\r
+ __I uint32_t MIS_RX_OVER;\r
+ __I uint32_t MIS_TX_UNDER;\r
+ __I uint32_t MIS[28];\r
+ __I uint32_t RIS[32];\r
+} SPI_BitBand_TypeDef;\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/*----------------------------------- GPIO -----------------------------------*/\r
+/*----------------------------------------------------------------------------*/\r
+typedef struct\r
+{\r
+ __IO uint32_t GPIO_0_CFG;\r
+ __IO uint32_t GPIO_1_CFG;\r
+ __IO uint32_t GPIO_2_CFG;\r
+ __IO uint32_t GPIO_3_CFG;\r
+ __IO uint32_t GPIO_4_CFG;\r
+ __IO uint32_t GPIO_5_CFG;\r
+ __IO uint32_t GPIO_6_CFG;\r
+ __IO uint32_t GPIO_7_CFG;\r
+ __IO uint32_t GPIO_8_CFG;\r
+ __IO uint32_t GPIO_9_CFG;\r
+ __IO uint32_t GPIO_10_CFG;\r
+ __IO uint32_t GPIO_11_CFG;\r
+ __IO uint32_t GPIO_12_CFG;\r
+ __IO uint32_t GPIO_13_CFG;\r
+ __IO uint32_t GPIO_14_CFG;\r
+ __IO uint32_t GPIO_15_CFG;\r
+ __IO uint32_t GPIO_16_CFG;\r
+ __IO uint32_t GPIO_17_CFG;\r
+ __IO uint32_t GPIO_18_CFG;\r
+ __IO uint32_t GPIO_19_CFG;\r
+ __IO uint32_t GPIO_20_CFG;\r
+ __IO uint32_t GPIO_21_CFG;\r
+ __IO uint32_t GPIO_22_CFG;\r
+ __IO uint32_t GPIO_23_CFG;\r
+ __IO uint32_t GPIO_24_CFG;\r
+ __IO uint32_t GPIO_25_CFG;\r
+ __IO uint32_t GPIO_26_CFG;\r
+ __IO uint32_t GPIO_27_CFG;\r
+ __IO uint32_t GPIO_28_CFG;\r
+ __IO uint32_t GPIO_29_CFG;\r
+ __IO uint32_t GPIO_30_CFG;\r
+ __IO uint32_t GPIO_31_CFG;\r
+ __IO uint32_t GPIO_IRQ;\r
+ __I uint32_t GPIO_IN;\r
+ __IO uint32_t GPIO_OUT;\r
+} GPIO_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t GPIO_0_CFG[32];\r
+ __IO uint32_t GPIO_1_CFG[32];\r
+ __IO uint32_t GPIO_2_CFG[32];\r
+ __IO uint32_t GPIO_3_CFG[32];\r
+ __IO uint32_t GPIO_4_CFG[32];\r
+ __IO uint32_t GPIO_5_CFG[32];\r
+ __IO uint32_t GPIO_6_CFG[32];\r
+ __IO uint32_t GPIO_7_CFG[32];\r
+ __IO uint32_t GPIO_8_CFG[32];\r
+ __IO uint32_t GPIO_9_CFG[32];\r
+ __IO uint32_t GPIO_10_CFG[32];\r
+ __IO uint32_t GPIO_11_CFG[32];\r
+ __IO uint32_t GPIO_12_CFG[32];\r
+ __IO uint32_t GPIO_13_CFG[32];\r
+ __IO uint32_t GPIO_14_CFG[32];\r
+ __IO uint32_t GPIO_15_CFG[32];\r
+ __IO uint32_t GPIO_16_CFG[32];\r
+ __IO uint32_t GPIO_17_CFG[32];\r
+ __IO uint32_t GPIO_18_CFG[32];\r
+ __IO uint32_t GPIO_19_CFG[32];\r
+ __IO uint32_t GPIO_20_CFG[32];\r
+ __IO uint32_t GPIO_21_CFG[32];\r
+ __IO uint32_t GPIO_22_CFG[32];\r
+ __IO uint32_t GPIO_23_CFG[32];\r
+ __IO uint32_t GPIO_24_CFG[32];\r
+ __IO uint32_t GPIO_25_CFG[32];\r
+ __IO uint32_t GPIO_26_CFG[32];\r
+ __IO uint32_t GPIO_27_CFG[32];\r
+ __IO uint32_t GPIO_28_CFG[32];\r
+ __IO uint32_t GPIO_29_CFG[32];\r
+ __IO uint32_t GPIO_30_CFG[32];\r
+ __IO uint32_t GPIO_31_CFG[32];\r
+ __IO uint32_t GPIO_IRQ[32];\r
+ __I uint32_t GPIO_IN[32];\r
+ __IO uint32_t GPIO_OUT[32];\r
+} GPIO_BitBand_TypeDef;\r
+\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/*----------------------------------- RTC ------------------------------------*/\r
+/*----------------------------------------------------------------------------*/\r
+typedef struct\r
+{\r
+ __IO uint32_t COUNTER0_REG;\r
+ __IO uint32_t COUNTER1_REG;\r
+ __IO uint32_t COUNTER2_REG;\r
+ __IO uint32_t COUNTER3_REG;\r
+ __IO uint32_t COUNTER4_REG;\r
+\r
+ __IO uint32_t RESERVED0[3];\r
+ \r
+ __IO uint32_t MATCHREG0_REG;\r
+ __IO uint32_t MATCHREG1_REG;\r
+ __IO uint32_t MATCHREG2_REG;\r
+ __IO uint32_t MATCHREG3_REG;\r
+ __IO uint32_t MATCHREG4_REG;\r
+\r
+ __IO uint32_t RESERVED1[3];\r
+ \r
+ __IO uint32_t MATCHBITS0_REG;\r
+ __IO uint32_t MATCHBITS1_REG;\r
+ __IO uint32_t MATCHBITS2_REG;\r
+ __IO uint32_t MATCHBITS3_REG;\r
+ __IO uint32_t MATCHBITS4_REG;\r
+\r
+ __IO uint32_t RESERVED2[3];\r
+ \r
+ __IO uint32_t CTRL_STAT_REG;\r
+} RTC_TypeDef;\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/*---------------------------------- Timer -----------------------------------*/\r
+/*----------------------------------------------------------------------------*/\r
+typedef struct\r
+{\r
+ __I uint32_t TIM1_VAL;\r
+ __IO uint32_t TIM1_LOADVAL;\r
+ __IO uint32_t TIM1_BGLOADVAL;\r
+ __IO uint32_t TIM1_CTRL;\r
+ __IO uint32_t TIM1_RIS;\r
+ __I uint32_t TIM1_MIS;\r
+ \r
+ __I uint32_t TIM2_VAL;\r
+ __IO uint32_t TIM2_LOADVAL;\r
+ __IO uint32_t TIM2_BGLOADVAL;\r
+ __IO uint32_t TIM2_CTRL;\r
+ __IO uint32_t TIM2_RIS;\r
+ __I uint32_t TIM2_MIS;\r
+ \r
+ __I uint32_t TIM64_VAL_U;\r
+ __I uint32_t TIM64_VAL_L;\r
+ __IO uint32_t TIM64_LOADVAL_U;\r
+ __IO uint32_t TIM64_LOADVAL_L;\r
+ __IO uint32_t TIM64_BGLOADVAL_U;\r
+ __IO uint32_t TIM64_BGLOADVAL_L;\r
+ __IO uint32_t TIM64_CTRL;\r
+ __IO uint32_t TIM64_RIS;\r
+ __I uint32_t TIM64_MIS;\r
+ __IO uint32_t TIM64_MODE;\r
+} TIMER_TypeDef;\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Timer bit band\r
+ */\r
+typedef struct\r
+{\r
+ __I uint32_t TIM1_VALUE_BIT[32];\r
+ __IO uint32_t TIM1_LOADVAL[32];\r
+ __IO uint32_t TIM1_BGLOADVAL[32];\r
+ \r
+ __IO uint32_t TIM1ENABLE;\r
+ __IO uint32_t TIM1MODE;\r
+ __IO uint32_t TIM1INTEN;\r
+ __IO uint32_t TIM1_CTRL_RESERVED[29];\r
+ __IO uint32_t TIM1_RIS[32];\r
+ __I uint32_t TIM1_MIS[32];\r
+ \r
+ __I uint32_t TIM2_VALUE[32];\r
+ __IO uint32_t TIM2_LOADVAL[32];\r
+ __IO uint32_t TIM2_BGLOADVAL[32];\r
+ \r
+ __IO uint32_t TIM2ENABLE;\r
+ __IO uint32_t TIM2MODE;\r
+ __IO uint32_t TIM2INTEN;\r
+ __IO uint32_t TIM2_CTRL[29];\r
+ __IO uint32_t TIM2_RIS[32];\r
+ __I uint32_t TIM2_MIS[32];\r
+ \r
+ __I uint32_t TIM64VALUEU[32];\r
+ __I uint32_t TIM64VALUEL[32];\r
+ __IO uint32_t TIM64LOADVALUEU[32];\r
+ __IO uint32_t TIM64LOADVALUEL[32];\r
+ __IO uint32_t TIM64BGLOADVALUEU[32];\r
+ __IO uint32_t TIM64BGLOADVALUEL[32];\r
+ __IO uint32_t TIM64ENABLE;\r
+ __IO uint32_t TIM64MODE;\r
+ __IO uint32_t TIM64INTEN;\r
+ __IO uint32_t TIM64_CTRL[29];\r
+ __IO uint32_t TIM64_RIS[32];\r
+ __I uint32_t TIM64_MIS[32];\r
+ __IO uint32_t TIM64_MODE[32];\r
+} TIMER_BitBand_TypeDef;\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/*--------------------------------- Watchdog ---------------------------------*/\r
+/*----------------------------------------------------------------------------*/\r
+typedef struct\r
+{\r
+ __I uint32_t WDOGVALUE;\r
+ __IO uint32_t WDOGLOAD;\r
+ __IO uint32_t WDOGMVRP;\r
+ __O uint32_t WDOGREFRESH;\r
+ __IO uint32_t WDOGENABLE;\r
+ __IO uint32_t WDOGCONTROL;\r
+ __I uint32_t WDOGSTATUS;\r
+ __IO uint32_t WDOGRIS;\r
+ __I uint32_t WDOGMIS;\r
+} WATCHDOG_TypeDef;\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/*----------------------------- Real Time Clock ------------------------------*/\r
+/*----------------------------------------------------------------------------*/\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/*----------------------------- Peripherals DMA ------------------------------*/\r
+/*----------------------------------------------------------------------------*/\r
+typedef struct\r
+{\r
+ __IO uint32_t CRTL;\r
+ __IO uint32_t STATUS;\r
+ __IO uint32_t BUFFER_A_SRC_ADDR;\r
+ __IO uint32_t BUFFER_A_DEST_ADDR;\r
+ __IO uint32_t BUFFER_A_TRANSFER_COUNT;\r
+ __IO uint32_t BUFFER_B_SRC_ADDR;\r
+ __IO uint32_t BUFFER_B_DEST_ADDR;\r
+ __IO uint32_t BUFFER_B_TRANSFER_COUNT;\r
+} PDMA_Channel_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t RATIO_HIGH_LOW;\r
+ __IO uint32_t BUFFER_STATUS;\r
+ uint32_t RESERVED[6];\r
+ PDMA_Channel_TypeDef CHANNEL[8];\r
+} PDMA_TypeDef;\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/*------------------------------ Ethernet MAC --------------------------------*/\r
+/*----------------------------------------------------------------------------*/\r
+typedef struct\r
+{\r
+ __IO uint32_t CSR0;\r
+ uint32_t RESERVED0;\r
+ __IO uint32_t CSR1;\r
+ uint32_t RESERVED1;\r
+ __IO uint32_t CSR2;\r
+ uint32_t RESERVED2;\r
+ __IO uint32_t CSR3;\r
+ uint32_t RESERVED3;\r
+ __IO uint32_t CSR4;\r
+ uint32_t RESERVED4;\r
+ __IO uint32_t CSR5;\r
+ uint32_t RESERVED5;\r
+ __IO uint32_t CSR6;\r
+ uint32_t RESERVED6;\r
+ __IO uint32_t CSR7;\r
+ uint32_t RESERVED7;\r
+ __IO uint32_t CSR8;\r
+ uint32_t RESERVED8;\r
+ __IO uint32_t CSR9;\r
+ uint32_t RESERVED9;\r
+ uint32_t RESERVED10;\r
+ uint32_t RESERVED11;\r
+ __IO uint32_t CSR11;\r
+} MAC_TypeDef;\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/*---------------------- Analog Conversion Engine (ACE) ----------------------*/\r
+/*----------------------------------------------------------------------------*/\r
+/* Analog quad configuration */\r
+typedef struct\r
+{\r
+ __IO uint8_t b0;\r
+ uint8_t reserved0_0;\r
+ uint16_t reserved0_1;\r
+ __IO uint8_t b1;\r
+ uint8_t reserved1_0;\r
+ uint16_t reserved1_1;\r
+ __IO uint8_t b2;\r
+ uint8_t reserved2_0;\r
+ uint16_t reserved2_1;\r
+ __IO uint8_t b3;\r
+ uint8_t reserved3_0;\r
+ uint16_t reserved3_1;\r
+ __IO uint8_t b4;\r
+ uint8_t reserved4_0;\r
+ uint16_t reserved4_1;\r
+ __IO uint8_t b5;\r
+ uint8_t reserved5_0;\r
+ uint16_t reserved5_1;\r
+ __IO uint8_t b6;\r
+ uint8_t reserved6_0;\r
+ uint16_t reserved6_1;\r
+ __IO uint8_t b7;\r
+ uint8_t reserved7_0;\r
+ uint16_t reserved7_1;\r
+ __IO uint8_t b8;\r
+ uint8_t reserved8_0;\r
+ uint16_t reserved8_1;\r
+ __IO uint8_t b9;\r
+ uint8_t reserved9_0;\r
+ uint16_t reserved9_1;\r
+ __IO uint8_t b10;\r
+ uint8_t reserved10_0;\r
+ uint16_t reserved10_1;\r
+ __IO uint8_t b11;\r
+ uint8_t reserved11_0;\r
+ uint16_t reserved11_1;\r
+} AQ_config_t;\r
+\r
+/* ACE memory map layout */\r
+typedef struct\r
+{\r
+ __O uint32_t NOP;\r
+ __IO uint32_t SSE_TS_CTRL;\r
+ __IO uint32_t ADC_SYNC_CONV;\r
+ __IO uint32_t ANA_COMM_CTRL;\r
+ __IO uint32_t DAC_SYNC_CTRL;\r
+ __IO uint32_t PDMA_REQUEST;\r
+ uint32_t RESERVED0[10];\r
+ __O uint32_t PC0_LO;\r
+ __O uint32_t PC0_HI;\r
+ __IO uint32_t PC0_CTRL;\r
+ __IO uint32_t PC0_DLY;\r
+ __IO uint32_t ADC0_CONV_CTRL;\r
+ __IO uint32_t ADC0_STC;\r
+ __IO uint32_t ADC0_TVC;\r
+ __IO uint32_t ADC0_MISC_CTRL;\r
+ __IO uint32_t DAC0_CTRL;\r
+ __IO uint32_t DAC0_BYTE0;\r
+ __IO uint32_t DAC0_BYTE1;\r
+ __IO uint32_t DAC0_BYTE2;\r
+ __IO uint32_t LC0;\r
+ __O uint32_t LC0_JMP_LO;\r
+ __O uint32_t LC0_JMP_HI;\r
+ __O uint32_t PC0_FLAGS;\r
+ __O uint32_t PC1_LO;\r
+ __O uint32_t PC1_HI;\r
+ __IO uint32_t PC1_CTRL;\r
+ __IO uint32_t PC1_DLY;\r
+ __IO uint32_t ADC1_CONV_CTRL;\r
+ __IO uint32_t ADC1_STC;\r
+ __IO uint32_t ADC1_TVC;\r
+ __IO uint32_t ADC1_MISC_CTRL;\r
+ __IO uint32_t DAC1_CTRL;\r
+ __IO uint32_t DAC1_BYTE0;\r
+ __IO uint32_t DAC1_BYTE1;\r
+ __IO uint32_t DAC1_BYTE2;\r
+ __IO uint32_t LC1;\r
+ __O uint32_t LC1_JMP_LO;\r
+ __O uint32_t LC1_JMP_HI;\r
+ __O uint32_t PC1_FLAGS;\r
+ __O uint32_t PC2_LO;\r
+ __O uint32_t PC2_HI;\r
+ __IO uint32_t PC2_CTRL;\r
+ __IO uint32_t PC2_DLY;\r
+ __IO uint32_t ADC2_CONV_CTRL;\r
+ __IO uint32_t ADC2_STC;\r
+ __IO uint32_t ADC2_TVC;\r
+ __IO uint32_t ADC2_MISC_CTRL;\r
+ __IO uint32_t DAC2_CTRL;\r
+ __IO uint32_t DAC2_BYTE0;\r
+ __IO uint32_t DAC2_BYTE1;\r
+ __IO uint32_t DAC2_BYTE2;\r
+ __IO uint32_t LC2;\r
+ __O uint32_t LC2_JMP_LO;\r
+ __O uint32_t LC2_JMP_HI;\r
+ __O uint32_t PC2_FLAGS;\r
+ uint32_t RESERVED1;\r
+ uint32_t RESERVED2;\r
+ __IO uint32_t SSE_RAM_LO_IDATA;\r
+ __IO uint32_t SSE_RAM_HI_IDATA;\r
+ uint32_t RESERVED3[61];\r
+ AQ_config_t ACB_DATA[6]; \r
+ uint32_t RESERVED4[59];\r
+ __IO uint32_t SSE_PC0;\r
+ __IO uint32_t SSE_PC1;\r
+ __IO uint32_t SSE_PC2;\r
+ uint32_t RESERVED5[57];\r
+ __IO uint32_t SSE_DAC0_BYTES01;\r
+ __IO uint32_t SSE_DAC1_BYTES01;\r
+ __IO uint32_t SSE_DAC2_BYTES01;\r
+ uint32_t RESERVED6[61];\r
+ __O uint32_t SSE_ADC0_RESULTS;\r
+ __O uint32_t SSE_ADC1_RESULTS;\r
+ __O uint32_t SSE_ADC2_RESULTS;\r
+ uint32_t RESERVED7[61];\r
+ __O uint32_t SSE_PDMA_DATAIN;\r
+ uint32_t RESERVED8[63];\r
+ __IO uint32_t SSE_RAM_DATA[512];\r
+ __I uint32_t ADC0_STATUS;\r
+ __I uint32_t ADC1_STATUS;\r
+ __I uint32_t ADC2_STATUS;\r
+ __I uint32_t COMPARATOR_STATUS;\r
+ uint32_t RESERVED9[124];\r
+ __IO uint32_t SSE_IRQ_EN;\r
+ __I uint32_t SSE_IRQ;\r
+ __O uint32_t SSE_IRQ_CLR;\r
+ __IO uint32_t COMP_IRQ_EN;\r
+ __I uint32_t COMP_IRQ;\r
+ __O uint32_t COMP_IRQ_CLR;\r
+ __IO uint32_t PPE_FIFO_IRQ_EN;\r
+ __I uint32_t PPE_FIFO_IRQ;\r
+ __O uint32_t PPE_FIFO_IRQ_CLR;\r
+ __IO uint32_t PPE_FLAGS0_IRQ_EN;\r
+ __I uint32_t PPE_FLAGS0_IRQ;\r
+ __O uint32_t PPE_FLAGS0_IRQ_CLR;\r
+ __IO uint32_t PPE_FLAGS1_IRQ_EN;\r
+ __I uint32_t PPE_FLAGS1_IRQ;\r
+ __O uint32_t PPE_FLAGS1_IRQ_CLR;\r
+ __IO uint32_t PPE_FLAGS2_IRQ_EN;\r
+ __I uint32_t PPE_FLAGS2_IRQ;\r
+ __O uint32_t PPE_FLAGS2_IRQ_CLR;\r
+ __IO uint32_t PPE_FLAGS3_IRQ_EN;\r
+ __I uint32_t PPE_FLAGS3_IRQ;\r
+ __O uint32_t PPE_FLAGS3_IRQ_CLR;\r
+ __IO uint32_t PPE_SFFLAGS_IRQ_EN;\r
+ __I uint32_t PPE_SFFLAGS_IRQ;\r
+ __O uint32_t PPE_SFFLAGS_IRQ_CLR;\r
+ __IO uint32_t FPGA_FLAGS_SEL;\r
+ uint32_t RESERVED10[39];\r
+ __IO uint32_t PPE_PDMA_CTRL;\r
+ __I uint32_t PDMA_STATUS;\r
+ __IO uint32_t PPE_PDMA_DATAOUT;\r
+ uint32_t RESERVED11[61];\r
+ __I uint32_t PPE_NOP;\r
+ __IO uint32_t PPE_CTRL;\r
+ __IO uint32_t PPE_PC_ETC;\r
+ __IO uint32_t PPE_SF;\r
+ __IO uint32_t PPE_SCRATCH;\r
+ uint32_t RESERVED12;\r
+ __IO uint32_t ALU_CTRL;\r
+ __I uint32_t ALU_STATUS;\r
+ __IO uint32_t ALU_A;\r
+ uint32_t RESERVED50;\r
+ __IO uint32_t ALU_B;\r
+ uint32_t RESERVED53;\r
+ __IO uint32_t ALU_C;\r
+ uint32_t RESERVED51;\r
+ __IO uint32_t ALU_D;\r
+ uint32_t RESERVED52;\r
+ __IO uint32_t ALU_E;\r
+ uint32_t RESERVED54;\r
+ __IO uint32_t PPE_FPTR;\r
+ uint32_t RESERVED55;\r
+ __IO uint32_t PPE_FLAGS0;\r
+ __IO uint32_t PPE_FLAGS1;\r
+ __IO uint32_t PPE_FLAGS2;\r
+ __IO uint32_t PPE_FLAGS3;\r
+ __IO uint32_t PPE_SFFLAGS;\r
+ uint32_t RESERVED13[11];\r
+ __IO uint32_t ADC0_FIFO_CTRL;\r
+ __I uint32_t ADC0_FIFO_STATUS;\r
+ __IO uint32_t ADC0_FIFO_DATA;\r
+ __IO uint32_t ADC1_FIFO_CTRL;\r
+ __I uint32_t ADC1_FIFO_STATUS;\r
+ __IO uint32_t ADC1_FIFO_DATA;\r
+ __IO uint32_t ADC2_FIFO_CTRL;\r
+ __I uint32_t ADC2_FIFO_STATUS;\r
+ __IO uint32_t ADC2_FIFO_DATA;\r
+ uint32_t RESERVED14[19];\r
+ __I uint32_t ADC0_FIFO_DATA_PEEK;\r
+ __I uint32_t ADC0_FIFO_DATA0;\r
+ __I uint32_t ADC0_FIFO_DATA1;\r
+ __I uint32_t ADC0_FIFO_DATA2;\r
+ __I uint32_t ADC0_FIFO_DATA3;\r
+ __I uint32_t ADC1_FIFO_DATA_PEEK;\r
+ __I uint32_t ADC1_FIFO_DATA0;\r
+ __I uint32_t ADC1_FIFO_DATA1;\r
+ __I uint32_t ADC1_FIFO_DATA2;\r
+ __I uint32_t ADC1_FIFO_DATA3;\r
+ __I uint32_t ADC2_FIFO_DATA_PEEK;\r
+ __I uint32_t ADC2_FIFO_DATA0;\r
+ __I uint32_t ADC2_FIFO_DATA1;\r
+ __I uint32_t ADC2_FIFO_DATA2;\r
+ __I uint32_t ADC2_FIFO_DATA3;\r
+ uint32_t RESERVED15[177]; \r
+ __IO uint32_t PPE_RAM_DATA[512];\r
+} ACE_TypeDef;\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/*------------------------ In Application Programming ------------------------*/\r
+/*----------------------------------------------------------------------------*/\r
+typedef struct\r
+{\r
+ __IO uint32_t IAP_IR;\r
+ __IO uint32_t IAP_DR2;\r
+ __IO uint32_t IAP_DR3;\r
+ __IO uint32_t IAP_DR5;\r
+ __IO uint32_t IAP_DR26;\r
+ __IO uint32_t IAP_DR32;\r
+ __IO uint32_t IAP_DR;\r
+ __IO uint32_t IAP_DR_LENGTH;\r
+ __IO uint32_t IAP_TAP_NEW_STATE;\r
+ __IO uint32_t IAP_TAP_CONTROL;\r
+ __I uint32_t IAP_STATUS;\r
+} IAP_TypeDef;\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/*---------------------- eNVM Special Function Registers ---------------------*/\r
+/*----------------------------------------------------------------------------*/\r
+typedef struct\r
+{\r
+ __IO uint32_t STATUS;\r
+ __IO uint32_t CONTROL;\r
+ __IO uint32_t ENABLE;\r
+ uint32_t RESERVED0;\r
+ __IO uint32_t CONFIG_0;\r
+ __IO uint32_t CONFIG_1;\r
+ __IO uint32_t PAGE_STATUS_0;\r
+ __IO uint32_t PAGE_STATUS_1;\r
+ __IO uint32_t SEGMENT;\r
+ __IO uint32_t ENVM_SELECT;\r
+} NVM_TypeDef;\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/*---------------------- eNVM Special Function Registers ---------------------*/\r
+/*----------------------------------------------------------------------------*/\r
+typedef struct\r
+{\r
+ __IO uint32_t MSSIRQ_EN0;\r
+ __IO uint32_t MSSIRQ_EN1;\r
+ __IO uint32_t MSSIRQ_EN2;\r
+ __IO uint32_t MSSIRQ_EN3;\r
+ __IO uint32_t MSSIRQ_EN4;\r
+ __IO uint32_t MSSIRQ_EN5;\r
+ __IO uint32_t MSSIRQ_EN6;\r
+ __IO uint32_t MSSIRQ_EN7;\r
+ __I uint32_t MSSIRQ_SRC0;\r
+ __I uint32_t MSSIRQ_SRC1;\r
+ __I uint32_t MSSIRQ_SRC2;\r
+ __I uint32_t MSSIRQ_SRC3;\r
+ __I uint32_t MSSIRQ_SRC4;\r
+ __I uint32_t MSSIRQ_SRC5;\r
+ __I uint32_t MSSIRQ_SRC6;\r
+ __I uint32_t MSSIRQ_SRC7;\r
+ __IO uint32_t FIIC_MR;\r
+} MSS_IRQ_CTRL_TypeDef;\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/*------------------------------ System Registers ----------------------------*/\r
+/*----------------------------------------------------------------------------*/\r
+typedef struct\r
+{\r
+ __IO uint32_t ESRAM_CR;\r
+ __IO uint32_t ENVM_CR;\r
+ __IO uint32_t ENVM_REMAP_SYS_CR;\r
+ __IO uint32_t ENVM_REMAP_FAB_CR;\r
+ __IO uint32_t FAB_PROT_SIZE_CR;\r
+ __IO uint32_t FAB_PROT_BASE_CR;\r
+ __IO uint32_t AHB_MATRIX_CR;\r
+ __IO uint32_t MSS_SR;\r
+ __IO uint32_t CLR_MSS_SR;\r
+ __IO uint32_t EFROM_CR;\r
+ __IO uint32_t IAP_CR;\r
+ __IO uint32_t SOFT_IRQ_CR;\r
+ __IO uint32_t SOFT_RST_CR;\r
+ __IO uint32_t DEVICE_SR;\r
+ __IO uint32_t SYSTICK_CR;\r
+ __IO uint32_t EMC_MUX_CR;\r
+ __IO uint32_t EMC_CS_0_CR;\r
+ __IO uint32_t EMC_CS_1_CR;\r
+ __IO uint32_t MSS_CLK_CR;\r
+ __IO uint32_t MSS_CCC_DIV_CR;\r
+ __IO uint32_t MSS_CCC_MUX_CR;\r
+ __IO uint32_t MSS_CCC_PLL_CR;\r
+ __IO uint32_t MSS_CCC_DLY_CR;\r
+ __IO uint32_t MSS_CCC_SR;\r
+ __IO uint32_t MSS_RCOSC_CR;\r
+ __IO uint32_t VRPSM_CR;\r
+ __IO uint32_t RESERVED;\r
+ __IO uint32_t FAB_IF_CR;\r
+ __IO uint32_t FAB_APB_HIWORD_DR;\r
+ __IO uint32_t LOOPBACK_CR;\r
+ __IO uint32_t MSS_IO_BANK_CR;\r
+ __IO uint32_t GPIN_SOURCE_CR;\r
+ __IO uint32_t TEST_SR;\r
+ __IO uint32_t RED_REP_ADDR0;\r
+ __I uint32_t RED_REP_LOW_LOCS0;\r
+ __I uint32_t RED_REP_HIGH_LOCS0;\r
+ __IO uint32_t RED_REP_ADDR1;\r
+ __I uint32_t RED_REP_LOW_LOCS1;\r
+ __I uint32_t RED_REP_HIGH_LOCS1;\r
+ __IO uint32_t FABRIC_CR;\r
+ uint32_t RESERVED1[24];\r
+ __IO uint32_t IOMUX_CR[83];\r
+} SYSREG_TypeDef;\r
+\r
+#define SYSREG_ENVM_SOFTRESET_MASK (uint32_t)0x00000001\r
+#define SYSREG_ESRAM0_SOFTRESET_MASK (uint32_t)0x00000002\r
+#define SYSREG_ESRAM1_SOFTRESET_MASK (uint32_t)0x00000004\r
+#define SYSREG_EMC_SOFTRESET_MASK (uint32_t)0x00000008\r
+#define SYSREG_MAC_SOFTRESET_MASK (uint32_t)0x00000010\r
+#define SYSREG_PDMA_SOFTRESET_MASK (uint32_t)0x00000020\r
+#define SYSREG_TIMER_SOFTRESET_MASK (uint32_t)0x00000040\r
+#define SYSREG_UART0_SOFTRESET_MASK (uint32_t)0x00000080\r
+#define SYSREG_UART1_SOFTRESET_MASK (uint32_t)0x00000100\r
+#define SYSREG_SPI0_SOFTRESET_MASK (uint32_t)0x00000200\r
+#define SYSREG_SPI1_SOFTRESET_MASK (uint32_t)0x00000400\r
+#define SYSREG_I2C0_SOFTRESET_MASK (uint32_t)0x00000800\r
+#define SYSREG_I2C1_SOFTRESET_MASK (uint32_t)0x00001000\r
+#define SYSREG_ACE_SOFTRESET_MASK (uint32_t)0x00002000\r
+#define SYSREG_GPIO_SOFTRESET_MASK (uint32_t)0x00004000\r
+#define SYSREG_IAP_SOFTRESET_MASK (uint32_t)0x00008000\r
+#define SYSREG_EXT_SOFTRESET_MASK (uint32_t)0x00010000\r
+#define SYSREG_FPGA_SOFTRESET_MASK (uint32_t)0x00020000\r
+#define SYSREG_F2M_RESET_ENABLE_MASK (uint32_t)0x00040000 \r
+#define SYSREG_PADRESET_ENABLE_MASK (uint32_t)0x00080000\r
+\r
+/******************************************************************************/\r
+/* Peripheral memory map */\r
+/******************************************************************************/\r
+#define UART0_BASE 0x40000000U\r
+#define SPI0_BASE 0x40001000U\r
+#define I2C0_BASE 0x40002000U\r
+#define MAC_BASE 0x40003000U\r
+#define PDMA_BASE 0x40004000U\r
+#define TIMER_BASE 0x40005000U\r
+#define WATCHDOG_BASE 0x40006000U\r
+#define H2F_IRQ_CTRL_BASE 0x40007000U\r
+#define UART1_BASE 0x40010000U\r
+#define SPI1_BASE 0x40011000U\r
+#define I2C1_BASE 0x40012000U\r
+#define GPIO_BASE 0x40013000U\r
+#define RTC_BASE 0x40014100U\r
+#define FROM_BASE 0x40015000U\r
+#define IAP_BASE 0x40016000U\r
+#define ACE_BASE 0x40020000U\r
+#define FPGA_FABRIC_RAM_BASE 0x40040000U\r
+#define FPGA_FABRIC_BASE 0x40050000U\r
+#define ENVM_BASE 0x60000000U\r
+#define ENVM_REGS_BASE 0x60100000U\r
+#define SYSREG_BASE 0xE0042000U\r
+\r
+/******************************************************************************/\r
+/* bitband address calcualtion macro */\r
+/******************************************************************************/\r
+#define BITBAND_ADDRESS(X) ((X & 0xF0000000U) + 0x02000000U + ((X & 0xFFFFFU) << 5))\r
+\r
+/******************************************************************************/\r
+/* Peripheral declaration */\r
+/******************************************************************************/\r
+#define UART0 ((UART_TypeDef *) UART0_BASE)\r
+#define UART0_BITBAND ((UART_BitBand_TypeDef *) BITBAND_ADDRESS(UART0_BASE))\r
+#define SPI0 ((SPI_TypeDef *) SPI0_BASE)\r
+#define SPI0_BITBAND ((SPI_BitBand_TypeDef *) BITBAND_ADDRESS(SPI0_BASE))\r
+#define I2C0 ((I2C_TypeDef *) I2C0_BASE)\r
+#define I2C0_BITBAND ((I2C_BitBand_TypeDef *) BITBAND_ADDRESS(I2C0_BASE))\r
+#define MAC ((MAC_TypeDef *) MAC_BASE)\r
+#define PDMA ((PDMA_TypeDef *) PDMA_BASE)\r
+#define TIMER ((TIMER_TypeDef *) TIMER_BASE)\r
+#define TIMER_BITBAND ((TIMER_BitBand_TypeDef *) BITBAND_ADDRESS(TIMER_BASE))\r
+#define WATCHDOG ((WATCHDOG_TypeDef *) WATCHDOG_BASE)\r
+#define MSS_IRQ_CTRL ((MSS_IRQ_CTRL_TypeDef *) H2F_IRQ_CTRL_BASE)\r
+#define UART1 ((UART_TypeDef *) UART1_BASE)\r
+#define UART1_BITBAND ((UART_BitBand_TypeDef *) BITBAND_ADDRESS(UART1_BASE))\r
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)\r
+#define SPI1_BITBAND ((SPI_BitBand_TypeDef *) BITBAND_ADDRESS(SPI1_BASE))\r
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)\r
+#define I2C1_BITBAND ((I2C_BitBand_TypeDef *) BITBAND_ADDRESS(I2C1_BASE))\r
+#define GPIO ((GPIO_TypeDef *) GPIO_BASE)\r
+#define GPIO_BITBAND ((GPIO_BitBand_TypeDef *) BITBAND_ADDRESS(GPIO_BASE))\r
+#define RTC ((RTC_TypeDef *) RTC_BASE)\r
+#define FROM ((void *) FROM_BASE)\r
+#define IAP ((IAP_TypeDef *) IAP_BASE)\r
+#define ACE ((ACE_TypeDef *) ACE_BASE)\r
+#define FPGA_FABRIC_RAM ((void *) FPGA_FABRIC_RAM_BASE)\r
+#define FPGA_FABRIC ((void *) FPGA_FABRIC_BASE)\r
+#define ENVM ((void *) ENVM_BASE)\r
+#define ENVM_REGS ((NVM_TypeDef *) ENVM_REGS_BASE)\r
+#define SYSREG ((SYSREG_TypeDef *) SYSREG_BASE)\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __A2FXXXM3_H__ */\r
+\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cm3.c\r
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File\r
+ * @version V1.30\r
+ * @date 30. October 2009\r
+ *\r
+ * @note\r
+ * Copyright (C) 2009 ARM Limited. All rights reserved.\r
+ *\r
+ * @par\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M \r
+ * processor based microcontrollers. This file can be freely distributed \r
+ * within development tools that are supporting such ARM based processors. \r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#include <stdint.h>\r
+\r
+/* define compiler specific symbols */\r
+#if defined ( __CC_ARM )\r
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */\r
+\r
+#elif defined ( __GNUC__ )\r
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
+\r
+#elif defined ( __TASKING__ )\r
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
+\r
+#endif\r
+\r
+\r
+/* ################### Compiler specific Intrinsics ########################### */\r
+\r
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r
+/* ARM armcc specific functions */\r
+\r
+/**\r
+ * @brief Return the Process Stack Pointer\r
+ *\r
+ * @return ProcessStackPointer\r
+ *\r
+ * Return the actual process stack pointer\r
+ */\r
+__ASM uint32_t __get_PSP(void)\r
+{\r
+ mrs r0, psp\r
+ bx lr\r
+}\r
+\r
+/**\r
+ * @brief Set the Process Stack Pointer\r
+ *\r
+ * @param topOfProcStack Process Stack Pointer\r
+ *\r
+ * Assign the value ProcessStackPointer to the MSP \r
+ * (process stack pointer) Cortex processor register\r
+ */\r
+__ASM void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+ msr psp, r0\r
+ bx lr\r
+}\r
+\r
+/**\r
+ * @brief Return the Main Stack Pointer\r
+ *\r
+ * @return Main Stack Pointer\r
+ *\r
+ * Return the current value of the MSP (main stack pointer)\r
+ * Cortex processor register\r
+ */\r
+__ASM uint32_t __get_MSP(void)\r
+{\r
+ mrs r0, msp\r
+ bx lr\r
+}\r
+\r
+/**\r
+ * @brief Set the Main Stack Pointer\r
+ *\r
+ * @param topOfMainStack Main Stack Pointer\r
+ *\r
+ * Assign the value mainStackPointer to the MSP \r
+ * (main stack pointer) Cortex processor register\r
+ */\r
+__ASM void __set_MSP(uint32_t mainStackPointer)\r
+{\r
+ msr msp, r0\r
+ bx lr\r
+}\r
+\r
+/**\r
+ * @brief Reverse byte order in unsigned short value\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse byte order in unsigned short value\r
+ */\r
+__ASM uint32_t __REV16(uint16_t value)\r
+{\r
+ rev16 r0, r0\r
+ bx lr\r
+}\r
+\r
+/**\r
+ * @brief Reverse byte order in signed short value with sign extension to integer\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse byte order in signed short value with sign extension to integer\r
+ */\r
+__ASM int32_t __REVSH(int16_t value)\r
+{\r
+ revsh r0, r0\r
+ bx lr\r
+}\r
+\r
+\r
+#if (__ARMCC_VERSION < 400000)\r
+\r
+/**\r
+ * @brief Remove the exclusive lock created by ldrex\r
+ *\r
+ * Removes the exclusive lock which is created by ldrex.\r
+ */\r
+__ASM void __CLREX(void)\r
+{\r
+ clrex\r
+}\r
+\r
+/**\r
+ * @brief Return the Base Priority value\r
+ *\r
+ * @return BasePriority\r
+ *\r
+ * Return the content of the base priority register\r
+ */\r
+__ASM uint32_t __get_BASEPRI(void)\r
+{\r
+ mrs r0, basepri\r
+ bx lr\r
+}\r
+\r
+/**\r
+ * @brief Set the Base Priority value\r
+ *\r
+ * @param basePri BasePriority\r
+ *\r
+ * Set the base priority register\r
+ */\r
+__ASM void __set_BASEPRI(uint32_t basePri)\r
+{\r
+ msr basepri, r0\r
+ bx lr\r
+}\r
+\r
+/**\r
+ * @brief Return the Priority Mask value\r
+ *\r
+ * @return PriMask\r
+ *\r
+ * Return state of the priority mask bit from the priority mask register\r
+ */\r
+__ASM uint32_t __get_PRIMASK(void)\r
+{\r
+ mrs r0, primask\r
+ bx lr\r
+}\r
+\r
+/**\r
+ * @brief Set the Priority Mask value\r
+ *\r
+ * @param priMask PriMask\r
+ *\r
+ * Set the priority mask bit in the priority mask register\r
+ */\r
+__ASM void __set_PRIMASK(uint32_t priMask)\r
+{\r
+ msr primask, r0\r
+ bx lr\r
+}\r
+\r
+/**\r
+ * @brief Return the Fault Mask value\r
+ *\r
+ * @return FaultMask\r
+ *\r
+ * Return the content of the fault mask register\r
+ */\r
+__ASM uint32_t __get_FAULTMASK(void)\r
+{\r
+ mrs r0, faultmask\r
+ bx lr\r
+}\r
+\r
+/**\r
+ * @brief Set the Fault Mask value\r
+ *\r
+ * @param faultMask faultMask value\r
+ *\r
+ * Set the fault mask register\r
+ */\r
+__ASM void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+ msr faultmask, r0\r
+ bx lr\r
+}\r
+\r
+/**\r
+ * @brief Return the Control Register value\r
+ * \r
+ * @return Control value\r
+ *\r
+ * Return the content of the control register\r
+ */\r
+__ASM uint32_t __get_CONTROL(void)\r
+{\r
+ mrs r0, control\r
+ bx lr\r
+}\r
+\r
+/**\r
+ * @brief Set the Control Register value\r
+ *\r
+ * @param control Control value\r
+ *\r
+ * Set the control register\r
+ */\r
+__ASM void __set_CONTROL(uint32_t control)\r
+{\r
+ msr control, r0\r
+ bx lr\r
+}\r
+\r
+#endif /* __ARMCC_VERSION */ \r
+\r
+\r
+\r
+#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/\r
+/* IAR iccarm specific functions */\r
+#pragma diag_suppress=Pe940\r
+\r
+/**\r
+ * @brief Return the Process Stack Pointer\r
+ *\r
+ * @return ProcessStackPointer\r
+ *\r
+ * Return the actual process stack pointer\r
+ */\r
+uint32_t __get_PSP(void)\r
+{\r
+ __ASM("mrs r0, psp");\r
+ __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief Set the Process Stack Pointer\r
+ *\r
+ * @param topOfProcStack Process Stack Pointer\r
+ *\r
+ * Assign the value ProcessStackPointer to the MSP \r
+ * (process stack pointer) Cortex processor register\r
+ */\r
+void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+ __ASM("msr psp, r0");\r
+ __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief Return the Main Stack Pointer\r
+ *\r
+ * @return Main Stack Pointer\r
+ *\r
+ * Return the current value of the MSP (main stack pointer)\r
+ * Cortex processor register\r
+ */\r
+uint32_t __get_MSP(void)\r
+{\r
+ __ASM("mrs r0, msp");\r
+ __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief Set the Main Stack Pointer\r
+ *\r
+ * @param topOfMainStack Main Stack Pointer\r
+ *\r
+ * Assign the value mainStackPointer to the MSP \r
+ * (main stack pointer) Cortex processor register\r
+ */\r
+void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+ __ASM("msr msp, r0");\r
+ __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief Reverse byte order in unsigned short value\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse byte order in unsigned short value\r
+ */\r
+uint32_t __REV16(uint16_t value)\r
+{\r
+ __ASM("rev16 r0, r0");\r
+ __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief Reverse bit order of value\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse bit order of value\r
+ */\r
+uint32_t __RBIT(uint32_t value)\r
+{\r
+ __ASM("rbit r0, r0");\r
+ __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief LDR Exclusive (8 bit)\r
+ *\r
+ * @param *addr address pointer\r
+ * @return value of (*address)\r
+ *\r
+ * Exclusive LDR command for 8 bit values)\r
+ */\r
+uint8_t __LDREXB(uint8_t *addr)\r
+{\r
+ __ASM("ldrexb r0, [r0]");\r
+ __ASM("bx lr"); \r
+}\r
+\r
+/**\r
+ * @brief LDR Exclusive (16 bit)\r
+ *\r
+ * @param *addr address pointer\r
+ * @return value of (*address)\r
+ *\r
+ * Exclusive LDR command for 16 bit values\r
+ */\r
+uint16_t __LDREXH(uint16_t *addr)\r
+{\r
+ __ASM("ldrexh r0, [r0]");\r
+ __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief LDR Exclusive (32 bit)\r
+ *\r
+ * @param *addr address pointer\r
+ * @return value of (*address)\r
+ *\r
+ * Exclusive LDR command for 32 bit values\r
+ */\r
+uint32_t __LDREXW(uint32_t *addr)\r
+{\r
+ __ASM("ldrex r0, [r0]");\r
+ __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief STR Exclusive (8 bit)\r
+ *\r
+ * @param value value to store\r
+ * @param *addr address pointer\r
+ * @return successful / failed\r
+ *\r
+ * Exclusive STR command for 8 bit values\r
+ */\r
+uint32_t __STREXB(uint8_t value, uint8_t *addr)\r
+{\r
+ __ASM("strexb r0, r0, [r1]");\r
+ __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief STR Exclusive (16 bit)\r
+ *\r
+ * @param value value to store\r
+ * @param *addr address pointer\r
+ * @return successful / failed\r
+ *\r
+ * Exclusive STR command for 16 bit values\r
+ */\r
+uint32_t __STREXH(uint16_t value, uint16_t *addr)\r
+{\r
+ __ASM("strexh r0, r0, [r1]");\r
+ __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief STR Exclusive (32 bit)\r
+ *\r
+ * @param value value to store\r
+ * @param *addr address pointer\r
+ * @return successful / failed\r
+ *\r
+ * Exclusive STR command for 32 bit values\r
+ */\r
+uint32_t __STREXW(uint32_t value, uint32_t *addr)\r
+{\r
+ __ASM("strex r0, r0, [r1]");\r
+ __ASM("bx lr");\r
+}\r
+\r
+#pragma diag_default=Pe940\r
+\r
+\r
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/\r
+/* GNU gcc specific functions */\r
+\r
+/**\r
+ * @brief Return the Process Stack Pointer\r
+ *\r
+ * @return ProcessStackPointer\r
+ *\r
+ * Return the actual process stack pointer\r
+ */\r
+uint32_t __get_PSP(void) __attribute__( ( naked ) );\r
+uint32_t __get_PSP(void)\r
+{\r
+ uint32_t result=0;\r
+\r
+ __ASM volatile ("MRS %0, psp\n\t" \r
+ "MOV r0, %0 \n\t"\r
+ "BX lr \n\t" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief Set the Process Stack Pointer\r
+ *\r
+ * @param topOfProcStack Process Stack Pointer\r
+ *\r
+ * Assign the value ProcessStackPointer to the MSP \r
+ * (process stack pointer) Cortex processor register\r
+ */\r
+void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) );\r
+void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+ __ASM volatile ("MSR psp, %0\n\t"\r
+ "BX lr \n\t" : : "r" (topOfProcStack) );\r
+}\r
+\r
+/**\r
+ * @brief Return the Main Stack Pointer\r
+ *\r
+ * @return Main Stack Pointer\r
+ *\r
+ * Return the current value of the MSP (main stack pointer)\r
+ * Cortex processor register\r
+ */\r
+uint32_t __get_MSP(void) __attribute__( ( naked ) );\r
+uint32_t __get_MSP(void)\r
+{\r
+ uint32_t result=0;\r
+\r
+ __ASM volatile ("MRS %0, msp\n\t" \r
+ "MOV r0, %0 \n\t"\r
+ "BX lr \n\t" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief Set the Main Stack Pointer\r
+ *\r
+ * @param topOfMainStack Main Stack Pointer\r
+ *\r
+ * Assign the value mainStackPointer to the MSP \r
+ * (main stack pointer) Cortex processor register\r
+ */\r
+void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) );\r
+void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+ __ASM volatile ("MSR msp, %0\n\t"\r
+ "BX lr \n\t" : : "r" (topOfMainStack) );\r
+}\r
+\r
+/**\r
+ * @brief Return the Base Priority value\r
+ *\r
+ * @return BasePriority\r
+ *\r
+ * Return the content of the base priority register\r
+ */\r
+uint32_t __get_BASEPRI(void)\r
+{\r
+ uint32_t result=0;\r
+ \r
+ __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief Set the Base Priority value\r
+ *\r
+ * @param basePri BasePriority\r
+ *\r
+ * Set the base priority register\r
+ */\r
+void __set_BASEPRI(uint32_t value)\r
+{\r
+ __ASM volatile ("MSR basepri, %0" : : "r" (value) );\r
+}\r
+\r
+/**\r
+ * @brief Return the Priority Mask value\r
+ *\r
+ * @return PriMask\r
+ *\r
+ * Return state of the priority mask bit from the priority mask register\r
+ */\r
+uint32_t __get_PRIMASK(void)\r
+{\r
+ uint32_t result=0;\r
+\r
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief Set the Priority Mask value\r
+ *\r
+ * @param priMask PriMask\r
+ *\r
+ * Set the priority mask bit in the priority mask register\r
+ */\r
+void __set_PRIMASK(uint32_t priMask)\r
+{\r
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) );\r
+}\r
+\r
+/**\r
+ * @brief Return the Fault Mask value\r
+ *\r
+ * @return FaultMask\r
+ *\r
+ * Return the content of the fault mask register\r
+ */\r
+uint32_t __get_FAULTMASK(void)\r
+{\r
+ uint32_t result=0;\r
+ \r
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief Set the Fault Mask value\r
+ *\r
+ * @param faultMask faultMask value\r
+ *\r
+ * Set the fault mask register\r
+ */\r
+void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );\r
+}\r
+\r
+/**\r
+ * @brief Return the Control Register value\r
+* \r
+* @return Control value\r
+ *\r
+ * Return the content of the control register\r
+ */\r
+uint32_t __get_CONTROL(void)\r
+{\r
+ uint32_t result=0;\r
+\r
+ __ASM volatile ("MRS %0, control" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief Set the Control Register value\r
+ *\r
+ * @param control Control value\r
+ *\r
+ * Set the control register\r
+ */\r
+void __set_CONTROL(uint32_t control)\r
+{\r
+ __ASM volatile ("MSR control, %0" : : "r" (control) );\r
+}\r
+\r
+\r
+/**\r
+ * @brief Reverse byte order in integer value\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse byte order in integer value\r
+ */\r
+uint32_t __REV(uint32_t value)\r
+{\r
+ uint32_t result=0;\r
+ \r
+ __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief Reverse byte order in unsigned short value\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse byte order in unsigned short value\r
+ */\r
+uint32_t __REV16(uint16_t value)\r
+{\r
+ uint32_t result=0;\r
+ \r
+ __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief Reverse byte order in signed short value with sign extension to integer\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse byte order in signed short value with sign extension to integer\r
+ */\r
+int32_t __REVSH(int16_t value)\r
+{\r
+ uint32_t result=0;\r
+ \r
+ __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief Reverse bit order of value\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse bit order of value\r
+ */\r
+uint32_t __RBIT(uint32_t value)\r
+{\r
+ uint32_t result=0;\r
+ \r
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief LDR Exclusive (8 bit)\r
+ *\r
+ * @param *addr address pointer\r
+ * @return value of (*address)\r
+ *\r
+ * Exclusive LDR command for 8 bit value\r
+ */\r
+uint8_t __LDREXB(uint8_t *addr)\r
+{\r
+ uint8_t result=0;\r
+ \r
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief LDR Exclusive (16 bit)\r
+ *\r
+ * @param *addr address pointer\r
+ * @return value of (*address)\r
+ *\r
+ * Exclusive LDR command for 16 bit values\r
+ */\r
+uint16_t __LDREXH(uint16_t *addr)\r
+{\r
+ uint16_t result=0;\r
+ \r
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief LDR Exclusive (32 bit)\r
+ *\r
+ * @param *addr address pointer\r
+ * @return value of (*address)\r
+ *\r
+ * Exclusive LDR command for 32 bit values\r
+ */\r
+uint32_t __LDREXW(uint32_t *addr)\r
+{\r
+ uint32_t result=0;\r
+ \r
+ __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief STR Exclusive (8 bit)\r
+ *\r
+ * @param value value to store\r
+ * @param *addr address pointer\r
+ * @return successful / failed\r
+ *\r
+ * Exclusive STR command for 8 bit values\r
+ */\r
+uint32_t __STREXB(uint8_t value, uint8_t *addr)\r
+{\r
+ uint32_t result=0;\r
+ \r
+ __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief STR Exclusive (16 bit)\r
+ *\r
+ * @param value value to store\r
+ * @param *addr address pointer\r
+ * @return successful / failed\r
+ *\r
+ * Exclusive STR command for 16 bit values\r
+ */\r
+uint32_t __STREXH(uint16_t value, uint16_t *addr)\r
+{\r
+ uint32_t result=0;\r
+ \r
+ __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief STR Exclusive (32 bit)\r
+ *\r
+ * @param value value to store\r
+ * @param *addr address pointer\r
+ * @return successful / failed\r
+ *\r
+ * Exclusive STR command for 32 bit values\r
+ */\r
+uint32_t __STREXW(uint32_t value, uint32_t *addr)\r
+{\r
+ uint32_t result=0;\r
+ \r
+ __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/\r
+/* TASKING carm specific functions */\r
+\r
+/*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all instrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
+\r
+#endif\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cm3.h\r
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File\r
+ * @version V1.30\r
+ * @date 30. October 2009\r
+ *\r
+ * @note\r
+ * Copyright (C) 2009 ARM Limited. All rights reserved.\r
+ *\r
+ * @par\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M \r
+ * processor based microcontrollers. This file can be freely distributed \r
+ * within development tools that are supporting such ARM based processors. \r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#ifndef __CM3_CORE_H__\r
+#define __CM3_CORE_H__\r
+\r
+/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration\r
+ *\r
+ * List of Lint messages which will be suppressed and not shown:\r
+ * - Error 10: \n\r
+ * register uint32_t __regBasePri __asm("basepri"); \n\r
+ * Error 10: Expecting ';'\r
+ * .\r
+ * - Error 530: \n\r
+ * return(__regBasePri); \n\r
+ * Warning 530: Symbol '__regBasePri' (line 264) not initialized\r
+ * . \r
+ * - Error 550: \n\r
+ * __regBasePri = (basePri & 0x1ff); \n\r
+ * Warning 550: Symbol '__regBasePri' (line 271) not accessed\r
+ * .\r
+ * - Error 754: \n\r
+ * uint32_t RESERVED0[24]; \n\r
+ * Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced\r
+ * .\r
+ * - Error 750: \n\r
+ * #define __CM3_CORE_H__ \n\r
+ * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced\r
+ * .\r
+ * - Error 528: \n\r
+ * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n\r
+ * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced\r
+ * .\r
+ * - Error 751: \n\r
+ * } InterruptType_Type; \n\r
+ * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced\r
+ * .\r
+ * Note: To re-enable a Message, insert a space before 'lint' *\r
+ *\r
+ */\r
+\r
+/*lint -save */\r
+/*lint -e10 */\r
+/*lint -e530 */\r
+/*lint -e550 */\r
+/*lint -e754 */\r
+/*lint -e750 */\r
+/*lint -e528 */\r
+/*lint -e751 */\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions\r
+ This file defines all structures and symbols for CMSIS core:\r
+ - CMSIS version number\r
+ - Cortex-M core registers and bitfields\r
+ - Cortex-M core peripheral base address\r
+ @{\r
+ */\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif \r
+\r
+#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */\r
+#define __CM3_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */\r
+#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */\r
+\r
+#define __CORTEX_M (0x03) /*!< Cortex core */\r
+\r
+#include <stdint.h> /* Include standard types */\r
+\r
+#if defined (__ICCARM__)\r
+ #include <intrinsics.h> /* IAR Intrinsics */\r
+#endif\r
+\r
+\r
+#ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */\r
+#endif\r
+\r
+\r
+\r
+\r
+/**\r
+ * IO definitions\r
+ *\r
+ * define access restrictions to peripheral registers\r
+ */\r
+\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< defines 'write only' permissions */\r
+#define __IO volatile /*!< defines 'read / write' permissions */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ ******************************************************************************/\r
+/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register\r
+ @{\r
+*/\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC\r
+ memory mapped structure for Nested Vectored Interrupt Controller (NVIC)\r
+ @{\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t ISER[8]; /*!< Offset: 0x000 Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[24]; \r
+ __IO uint32_t ICER[8]; /*!< Offset: 0x080 Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[24]; \r
+ __IO uint32_t ISPR[8]; /*!< Offset: 0x100 Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[24]; \r
+ __IO uint32_t ICPR[8]; /*!< Offset: 0x180 Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[24]; \r
+ __IO uint32_t IABR[8]; /*!< Offset: 0x200 Interrupt Active bit Register */\r
+ uint32_t RESERVED4[56]; \r
+ __IO uint8_t IP[240]; /*!< Offset: 0x300 Interrupt Priority Register (8Bit wide) */\r
+ uint32_t RESERVED5[644]; \r
+ __O uint32_t STIR; /*!< Offset: 0xE00 Software Trigger Interrupt Register */\r
+} NVIC_Type; \r
+/*@}*/ /* end of group CMSIS_CM3_NVIC */\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB\r
+ memory mapped structure for System Control Block (SCB)\r
+ @{\r
+ */\r
+typedef struct\r
+{\r
+ __I uint32_t CPUID; /*!< Offset: 0x00 CPU ID Base Register */\r
+ __IO uint32_t ICSR; /*!< Offset: 0x04 Interrupt Control State Register */\r
+ __IO uint32_t VTOR; /*!< Offset: 0x08 Vector Table Offset Register */\r
+ __IO uint32_t AIRCR; /*!< Offset: 0x0C Application Interrupt / Reset Control Register */\r
+ __IO uint32_t SCR; /*!< Offset: 0x10 System Control Register */\r
+ __IO uint32_t CCR; /*!< Offset: 0x14 Configuration Control Register */\r
+ __IO uint8_t SHP[12]; /*!< Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
+ __IO uint32_t SHCSR; /*!< Offset: 0x24 System Handler Control and State Register */\r
+ __IO uint32_t CFSR; /*!< Offset: 0x28 Configurable Fault Status Register */\r
+ __IO uint32_t HFSR; /*!< Offset: 0x2C Hard Fault Status Register */\r
+ __IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register */\r
+ __IO uint32_t MMFAR; /*!< Offset: 0x34 Mem Manage Address Register */\r
+ __IO uint32_t BFAR; /*!< Offset: 0x38 Bus Fault Address Register */\r
+ __IO uint32_t AFSR; /*!< Offset: 0x3C Auxiliary Fault Status Register */\r
+ __I uint32_t PFR[2]; /*!< Offset: 0x40 Processor Feature Register */\r
+ __I uint32_t DFR; /*!< Offset: 0x48 Debug Feature Register */\r
+ __I uint32_t ADR; /*!< Offset: 0x4C Auxiliary Feature Register */\r
+ __I uint32_t MMFR[4]; /*!< Offset: 0x50 Memory Model Feature Register */\r
+ __I uint32_t ISAR[5]; /*!< Offset: 0x60 ISA Feature Register */\r
+} SCB_Type; \r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */\r
+#define SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */\r
+#define SCB_VTOR_TBLBASE_Msk (0x1FFul << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */\r
+\r
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */\r
+#define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */\r
+#define SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */\r
+#define SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */\r
+#define SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */\r
+#define SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
+\r
+#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */\r
+#define SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */\r
+#define SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */\r
+#define SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */\r
+#define SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */\r
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */\r
+#define SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
+\r
+#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */\r
+#define SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
+\r
+#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */\r
+#define SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r
+\r
+#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */\r
+#define SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
+ \r
+#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */\r
+#define SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */\r
+#define SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */\r
+#define SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
+\r
+/* SCB Configurable Fault Status Registers Definitions */\r
+#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */\r
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */\r
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
+\r
+/* SCB Hard Fault Status Registers Definitions */\r
+#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */\r
+#define SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r
+\r
+#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */\r
+#define SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r
+\r
+#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */\r
+#define SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r
+\r
+/* SCB Debug Fault Status Register Definitions */\r
+#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */\r
+#define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r
+\r
+#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */\r
+#define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r
+\r
+#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */\r
+#define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r
+\r
+#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */\r
+#define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
+\r
+#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */\r
+#define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */\r
+/*@}*/ /* end of group CMSIS_CM3_SCB */\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick\r
+ memory mapped structure for SysTick\r
+ @{\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */\r
+ __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */\r
+ __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */\r
+ __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */\r
+/*@}*/ /* end of group CMSIS_CM3_SysTick */\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM\r
+ memory mapped structure for Instrumentation Trace Macrocell (ITM)\r
+ @{\r
+ */\r
+typedef struct\r
+{\r
+ __O union \r
+ {\r
+ __O uint8_t u8; /*!< Offset: ITM Stimulus Port 8-bit */\r
+ __O uint16_t u16; /*!< Offset: ITM Stimulus Port 16-bit */\r
+ __O uint32_t u32; /*!< Offset: ITM Stimulus Port 32-bit */\r
+ } PORT [32]; /*!< Offset: 0x00 ITM Stimulus Port Registers */\r
+ uint32_t RESERVED0[864]; \r
+ __IO uint32_t TER; /*!< Offset: ITM Trace Enable Register */\r
+ uint32_t RESERVED1[15]; \r
+ __IO uint32_t TPR; /*!< Offset: ITM Trace Privilege Register */\r
+ uint32_t RESERVED2[15]; \r
+ __IO uint32_t TCR; /*!< Offset: ITM Trace Control Register */\r
+ uint32_t RESERVED3[29]; \r
+ __IO uint32_t IWR; /*!< Offset: ITM Integration Write Register */\r
+ __IO uint32_t IRR; /*!< Offset: ITM Integration Read Register */\r
+ __IO uint32_t IMCR; /*!< Offset: ITM Integration Mode Control Register */\r
+ uint32_t RESERVED4[43]; \r
+ __IO uint32_t LAR; /*!< Offset: ITM Lock Access Register */\r
+ __IO uint32_t LSR; /*!< Offset: ITM Lock Status Register */\r
+ uint32_t RESERVED5[6]; \r
+ __I uint32_t PID4; /*!< Offset: ITM Peripheral Identification Register #4 */\r
+ __I uint32_t PID5; /*!< Offset: ITM Peripheral Identification Register #5 */\r
+ __I uint32_t PID6; /*!< Offset: ITM Peripheral Identification Register #6 */\r
+ __I uint32_t PID7; /*!< Offset: ITM Peripheral Identification Register #7 */\r
+ __I uint32_t PID0; /*!< Offset: ITM Peripheral Identification Register #0 */\r
+ __I uint32_t PID1; /*!< Offset: ITM Peripheral Identification Register #1 */\r
+ __I uint32_t PID2; /*!< Offset: ITM Peripheral Identification Register #2 */\r
+ __I uint32_t PID3; /*!< Offset: ITM Peripheral Identification Register #3 */\r
+ __I uint32_t CID0; /*!< Offset: ITM Component Identification Register #0 */\r
+ __I uint32_t CID1; /*!< Offset: ITM Component Identification Register #1 */\r
+ __I uint32_t CID2; /*!< Offset: ITM Component Identification Register #2 */\r
+ __I uint32_t CID3; /*!< Offset: ITM Component Identification Register #3 */\r
+} ITM_Type; \r
+\r
+/* ITM Trace Privilege Register Definitions */\r
+#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */\r
+#define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */\r
+\r
+/* ITM Trace Control Register Definitions */\r
+#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */\r
+#define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r
+\r
+#define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */\r
+#define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */\r
+\r
+#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */\r
+#define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */\r
+\r
+#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */\r
+#define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r
+\r
+#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */\r
+#define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */\r
+\r
+#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */\r
+#define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r
+\r
+#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */\r
+#define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
+\r
+#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */\r
+#define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */\r
+\r
+/* ITM Integration Write Register Definitions */\r
+#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */\r
+#define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */\r
+\r
+/* ITM Integration Read Register Definitions */\r
+#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */\r
+#define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */\r
+\r
+/* ITM Integration Mode Control Register Definitions */\r
+#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */\r
+#define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */\r
+\r
+/* ITM Lock Status Register Definitions */\r
+#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */\r
+#define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */\r
+\r
+#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */\r
+#define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */\r
+\r
+#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */\r
+#define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */\r
+/*@}*/ /* end of group CMSIS_CM3_ITM */\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type\r
+ memory mapped structure for Interrupt Type\r
+ @{\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0;\r
+ __I uint32_t ICTR; /*!< Offset: 0x04 Interrupt Control Type Register */\r
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))\r
+ __IO uint32_t ACTLR; /*!< Offset: 0x08 Auxiliary Control Register */\r
+#else\r
+ uint32_t RESERVED1;\r
+#endif\r
+} InterruptType_Type;\r
+\r
+/* Interrupt Controller Type Register Definitions */\r
+#define InterruptType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */\r
+#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */\r
+\r
+/* Auxiliary Control Register Definitions */\r
+#define InterruptType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */\r
+#define InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */\r
+\r
+#define InterruptType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */\r
+#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */\r
+\r
+#define InterruptType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */\r
+#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */\r
+/*@}*/ /* end of group CMSIS_CM3_InterruptType */\r
+\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)\r
+/** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU\r
+ memory mapped structure for Memory Protection Unit (MPU)\r
+ @{\r
+ */\r
+typedef struct\r
+{\r
+ __I uint32_t TYPE; /*!< Offset: 0x00 MPU Type Register */\r
+ __IO uint32_t CTRL; /*!< Offset: 0x04 MPU Control Register */\r
+ __IO uint32_t RNR; /*!< Offset: 0x08 MPU Region RNRber Register */\r
+ __IO uint32_t RBAR; /*!< Offset: 0x0C MPU Region Base Address Register */\r
+ __IO uint32_t RASR; /*!< Offset: 0x10 MPU Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A1; /*!< Offset: 0x14 MPU Alias 1 Region Base Address Register */\r
+ __IO uint32_t RASR_A1; /*!< Offset: 0x18 MPU Alias 1 Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A2; /*!< Offset: 0x1C MPU Alias 2 Region Base Address Register */\r
+ __IO uint32_t RASR_A2; /*!< Offset: 0x20 MPU Alias 2 Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A3; /*!< Offset: 0x24 MPU Alias 3 Region Base Address Register */\r
+ __IO uint32_t RASR_A3; /*!< Offset: 0x28 MPU Alias 3 Region Attribute and Size Register */\r
+} MPU_Type; \r
+\r
+/* MPU Type Register */\r
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk (0xFFul << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk (0xFFul << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk (1ul << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register */\r
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk (1ul << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk (1ul << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk (1ul << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register */\r
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk (0xFFul << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register */\r
+#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */\r
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFul << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
+\r
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */\r
+#define MPU_RBAR_VALID_Msk (1ul << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
+\r
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */\r
+#define MPU_RBAR_REGION_Msk (0xFul << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */\r
+\r
+/* MPU Region Attribute and Size Register */\r
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */\r
+#define MPU_RASR_XN_Msk (1ul << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */\r
+\r
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */\r
+#define MPU_RASR_AP_Msk (7ul << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */\r
+\r
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */\r
+#define MPU_RASR_TEX_Msk (7ul << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */\r
+\r
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */\r
+#define MPU_RASR_S_Msk (1ul << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */\r
+\r
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */\r
+#define MPU_RASR_C_Msk (1ul << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */\r
+\r
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */\r
+#define MPU_RASR_B_Msk (1ul << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */\r
+\r
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */\r
+#define MPU_RASR_SRD_Msk (0xFFul << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
+\r
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */\r
+#define MPU_RASR_SIZE_Msk (0x1Ful << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
+\r
+#define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */\r
+#define MPU_RASR_ENA_Msk (0x1Ful << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_CM3_MPU */\r
+#endif\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug\r
+ memory mapped structure for Core Debug Register\r
+ @{\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t DHCSR; /*!< Offset: 0x00 Debug Halting Control and Status Register */\r
+ __O uint32_t DCRSR; /*!< Offset: 0x04 Debug Core Register Selector Register */\r
+ __IO uint32_t DCRDR; /*!< Offset: 0x08 Debug Core Register Data Register */\r
+ __IO uint32_t DEMCR; /*!< Offset: 0x0C Debug Exception and Monitor Control Register */\r
+} CoreDebug_Type;\r
+\r
+/* Debug Halting Control and Status Register */\r
+#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */\r
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */\r
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */\r
+#define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */\r
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
+\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
+\r
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
+\r
+#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */\r
+#define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
+\r
+#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */\r
+#define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+\r
+/* Debug Core Register Selector Register */\r
+#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */\r
+#define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
+\r
+#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */\r
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */\r
+\r
+/* Debug Exception and Monitor Control Register */\r
+#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */\r
+#define CoreDebug_DEMCR_TRCENA_Msk (1ul << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */\r
+#define CoreDebug_DEMCR_MON_REQ_Msk (1ul << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */\r
+#define CoreDebug_DEMCR_MON_STEP_Msk (1ul << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */\r
+#define CoreDebug_DEMCR_MON_PEND_Msk (1ul << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */\r
+#define CoreDebug_DEMCR_MON_EN_Msk (1ul << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */\r
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1ul << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */\r
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1ul << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */\r
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1ul << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+/*@}*/ /* end of group CMSIS_CM3_CoreDebug */\r
+\r
+\r
+/* Memory mapping of Cortex-M3 Hardware */\r
+#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */\r
+#define ITM_BASE (0xE0000000) /*!< ITM Base Address */\r
+#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */\r
+#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */\r
+#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */\r
+#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */\r
+\r
+#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */\r
+#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */\r
+#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */\r
+#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */\r
+#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */\r
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */\r
+#endif\r
+\r
+/*@}*/ /* end of group CMSIS_CM3_core_register */\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ ******************************************************************************/\r
+\r
+#if defined ( __CC_ARM )\r
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */\r
+\r
+#elif defined ( __GNUC__ )\r
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
+\r
+#elif defined ( __TASKING__ )\r
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
+\r
+#endif\r
+\r
+\r
+/* ################### Compiler specific Intrinsics ########################### */\r
+\r
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r
+/* ARM armcc specific functions */\r
+\r
+#define __enable_fault_irq __enable_fiq\r
+#define __disable_fault_irq __disable_fiq\r
+\r
+#define __NOP __nop\r
+#define __WFI __wfi\r
+#define __WFE __wfe\r
+#define __SEV __sev\r
+#define __ISB() __isb(0)\r
+#define __DSB() __dsb(0)\r
+#define __DMB() __dmb(0)\r
+#define __REV __rev\r
+#define __RBIT __rbit\r
+#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr))\r
+#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr))\r
+#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr))\r
+#define __STREXB(value, ptr) __strex(value, ptr)\r
+#define __STREXH(value, ptr) __strex(value, ptr)\r
+#define __STREXW(value, ptr) __strex(value, ptr)\r
+\r
+\r
+/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */\r
+/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */\r
+/* intrinsic void __enable_irq(); */\r
+/* intrinsic void __disable_irq(); */\r
+\r
+\r
+/**\r
+ * @brief Return the Process Stack Pointer\r
+ *\r
+ * @return ProcessStackPointer\r
+ *\r
+ * Return the actual process stack pointer\r
+ */\r
+extern uint32_t __get_PSP(void);\r
+\r
+/**\r
+ * @brief Set the Process Stack Pointer\r
+ *\r
+ * @param topOfProcStack Process Stack Pointer\r
+ *\r
+ * Assign the value ProcessStackPointer to the MSP \r
+ * (process stack pointer) Cortex processor register\r
+ */\r
+extern void __set_PSP(uint32_t topOfProcStack);\r
+\r
+/**\r
+ * @brief Return the Main Stack Pointer\r
+ *\r
+ * @return Main Stack Pointer\r
+ *\r
+ * Return the current value of the MSP (main stack pointer)\r
+ * Cortex processor register\r
+ */\r
+extern uint32_t __get_MSP(void);\r
+\r
+/**\r
+ * @brief Set the Main Stack Pointer\r
+ *\r
+ * @param topOfMainStack Main Stack Pointer\r
+ *\r
+ * Assign the value mainStackPointer to the MSP \r
+ * (main stack pointer) Cortex processor register\r
+ */\r
+extern void __set_MSP(uint32_t topOfMainStack);\r
+\r
+/**\r
+ * @brief Reverse byte order in unsigned short value\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse byte order in unsigned short value\r
+ */\r
+extern uint32_t __REV16(uint16_t value);\r
+\r
+/**\r
+ * @brief Reverse byte order in signed short value with sign extension to integer\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse byte order in signed short value with sign extension to integer\r
+ */\r
+extern int32_t __REVSH(int16_t value);\r
+\r
+\r
+#if (__ARMCC_VERSION < 400000)\r
+\r
+/**\r
+ * @brief Remove the exclusive lock created by ldrex\r
+ *\r
+ * Removes the exclusive lock which is created by ldrex.\r
+ */\r
+extern void __CLREX(void);\r
+\r
+/**\r
+ * @brief Return the Base Priority value\r
+ *\r
+ * @return BasePriority\r
+ *\r
+ * Return the content of the base priority register\r
+ */\r
+extern uint32_t __get_BASEPRI(void);\r
+\r
+/**\r
+ * @brief Set the Base Priority value\r
+ *\r
+ * @param basePri BasePriority\r
+ *\r
+ * Set the base priority register\r
+ */\r
+extern void __set_BASEPRI(uint32_t basePri);\r
+\r
+/**\r
+ * @brief Return the Priority Mask value\r
+ *\r
+ * @return PriMask\r
+ *\r
+ * Return state of the priority mask bit from the priority mask register\r
+ */\r
+extern uint32_t __get_PRIMASK(void);\r
+\r
+/**\r
+ * @brief Set the Priority Mask value\r
+ *\r
+ * @param priMask PriMask\r
+ *\r
+ * Set the priority mask bit in the priority mask register\r
+ */\r
+extern void __set_PRIMASK(uint32_t priMask);\r
+\r
+/**\r
+ * @brief Return the Fault Mask value\r
+ *\r
+ * @return FaultMask\r
+ *\r
+ * Return the content of the fault mask register\r
+ */\r
+extern uint32_t __get_FAULTMASK(void);\r
+\r
+/**\r
+ * @brief Set the Fault Mask value\r
+ *\r
+ * @param faultMask faultMask value\r
+ *\r
+ * Set the fault mask register\r
+ */\r
+extern void __set_FAULTMASK(uint32_t faultMask);\r
+\r
+/**\r
+ * @brief Return the Control Register value\r
+ * \r
+ * @return Control value\r
+ *\r
+ * Return the content of the control register\r
+ */\r
+extern uint32_t __get_CONTROL(void);\r
+\r
+/**\r
+ * @brief Set the Control Register value\r
+ *\r
+ * @param control Control value\r
+ *\r
+ * Set the control register\r
+ */\r
+extern void __set_CONTROL(uint32_t control);\r
+\r
+#else /* (__ARMCC_VERSION >= 400000) */\r
+\r
+/**\r
+ * @brief Remove the exclusive lock created by ldrex\r
+ *\r
+ * Removes the exclusive lock which is created by ldrex.\r
+ */\r
+#define __CLREX __clrex\r
+\r
+/**\r
+ * @brief Return the Base Priority value\r
+ *\r
+ * @return BasePriority\r
+ *\r
+ * Return the content of the base priority register\r
+ */\r
+static __INLINE uint32_t __get_BASEPRI(void)\r
+{\r
+ register uint32_t __regBasePri __ASM("basepri");\r
+ return(__regBasePri);\r
+}\r
+\r
+/**\r
+ * @brief Set the Base Priority value\r
+ *\r
+ * @param basePri BasePriority\r
+ *\r
+ * Set the base priority register\r
+ */\r
+static __INLINE void __set_BASEPRI(uint32_t basePri)\r
+{\r
+ register uint32_t __regBasePri __ASM("basepri");\r
+ __regBasePri = (basePri & 0xff);\r
+}\r
+\r
+/**\r
+ * @brief Return the Priority Mask value\r
+ *\r
+ * @return PriMask\r
+ *\r
+ * Return state of the priority mask bit from the priority mask register\r
+ */\r
+static __INLINE uint32_t __get_PRIMASK(void)\r
+{\r
+ register uint32_t __regPriMask __ASM("primask");\r
+ return(__regPriMask);\r
+}\r
+\r
+/**\r
+ * @brief Set the Priority Mask value\r
+ *\r
+ * @param priMask PriMask\r
+ *\r
+ * Set the priority mask bit in the priority mask register\r
+ */\r
+static __INLINE void __set_PRIMASK(uint32_t priMask)\r
+{\r
+ register uint32_t __regPriMask __ASM("primask");\r
+ __regPriMask = (priMask);\r
+}\r
+\r
+/**\r
+ * @brief Return the Fault Mask value\r
+ *\r
+ * @return FaultMask\r
+ *\r
+ * Return the content of the fault mask register\r
+ */\r
+static __INLINE uint32_t __get_FAULTMASK(void)\r
+{\r
+ register uint32_t __regFaultMask __ASM("faultmask");\r
+ return(__regFaultMask);\r
+}\r
+\r
+/**\r
+ * @brief Set the Fault Mask value\r
+ *\r
+ * @param faultMask faultMask value\r
+ *\r
+ * Set the fault mask register\r
+ */\r
+static __INLINE void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+ register uint32_t __regFaultMask __ASM("faultmask");\r
+ __regFaultMask = (faultMask & 1);\r
+}\r
+\r
+/**\r
+ * @brief Return the Control Register value\r
+ * \r
+ * @return Control value\r
+ *\r
+ * Return the content of the control register\r
+ */\r
+static __INLINE uint32_t __get_CONTROL(void)\r
+{\r
+ register uint32_t __regControl __ASM("control");\r
+ return(__regControl);\r
+}\r
+\r
+/**\r
+ * @brief Set the Control Register value\r
+ *\r
+ * @param control Control value\r
+ *\r
+ * Set the control register\r
+ */\r
+static __INLINE void __set_CONTROL(uint32_t control)\r
+{\r
+ register uint32_t __regControl __ASM("control");\r
+ __regControl = control;\r
+}\r
+\r
+#endif /* __ARMCC_VERSION */ \r
+\r
+\r
+\r
+#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/\r
+/* IAR iccarm specific functions */\r
+\r
+#define __enable_irq __enable_interrupt /*!< global Interrupt enable */\r
+#define __disable_irq __disable_interrupt /*!< global Interrupt disable */\r
+\r
+static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); }\r
+static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); }\r
+\r
+#define __NOP __no_operation /*!< no operation intrinsic in IAR Compiler */ \r
+static __INLINE void __WFI() { __ASM ("wfi"); }\r
+static __INLINE void __WFE() { __ASM ("wfe"); }\r
+static __INLINE void __SEV() { __ASM ("sev"); }\r
+static __INLINE void __CLREX() { __ASM ("clrex"); }\r
+\r
+/* intrinsic void __ISB(void) */\r
+/* intrinsic void __DSB(void) */\r
+/* intrinsic void __DMB(void) */\r
+/* intrinsic void __set_PRIMASK(); */\r
+/* intrinsic void __get_PRIMASK(); */\r
+/* intrinsic void __set_FAULTMASK(); */\r
+/* intrinsic void __get_FAULTMASK(); */\r
+/* intrinsic uint32_t __REV(uint32_t value); */\r
+/* intrinsic uint32_t __REVSH(uint32_t value); */\r
+/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */\r
+/* intrinsic unsigned long __LDREX(unsigned long *); */\r
+\r
+\r
+/**\r
+ * @brief Return the Process Stack Pointer\r
+ *\r
+ * @return ProcessStackPointer\r
+ *\r
+ * Return the actual process stack pointer\r
+ */\r
+extern uint32_t __get_PSP(void);\r
+\r
+/**\r
+ * @brief Set the Process Stack Pointer\r
+ *\r
+ * @param topOfProcStack Process Stack Pointer\r
+ *\r
+ * Assign the value ProcessStackPointer to the MSP \r
+ * (process stack pointer) Cortex processor register\r
+ */\r
+extern void __set_PSP(uint32_t topOfProcStack);\r
+\r
+/**\r
+ * @brief Return the Main Stack Pointer\r
+ *\r
+ * @return Main Stack Pointer\r
+ *\r
+ * Return the current value of the MSP (main stack pointer)\r
+ * Cortex processor register\r
+ */\r
+extern uint32_t __get_MSP(void);\r
+\r
+/**\r
+ * @brief Set the Main Stack Pointer\r
+ *\r
+ * @param topOfMainStack Main Stack Pointer\r
+ *\r
+ * Assign the value mainStackPointer to the MSP \r
+ * (main stack pointer) Cortex processor register\r
+ */\r
+extern void __set_MSP(uint32_t topOfMainStack);\r
+\r
+/**\r
+ * @brief Reverse byte order in unsigned short value\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse byte order in unsigned short value\r
+ */\r
+extern uint32_t __REV16(uint16_t value);\r
+\r
+/**\r
+ * @brief Reverse bit order of value\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse bit order of value\r
+ */\r
+extern uint32_t __RBIT(uint32_t value);\r
+\r
+/**\r
+ * @brief LDR Exclusive (8 bit)\r
+ *\r
+ * @param *addr address pointer\r
+ * @return value of (*address)\r
+ *\r
+ * Exclusive LDR command for 8 bit values)\r
+ */\r
+extern uint8_t __LDREXB(uint8_t *addr);\r
+\r
+/**\r
+ * @brief LDR Exclusive (16 bit)\r
+ *\r
+ * @param *addr address pointer\r
+ * @return value of (*address)\r
+ *\r
+ * Exclusive LDR command for 16 bit values\r
+ */\r
+extern uint16_t __LDREXH(uint16_t *addr);\r
+\r
+/**\r
+ * @brief LDR Exclusive (32 bit)\r
+ *\r
+ * @param *addr address pointer\r
+ * @return value of (*address)\r
+ *\r
+ * Exclusive LDR command for 32 bit values\r
+ */\r
+extern uint32_t __LDREXW(uint32_t *addr);\r
+\r
+/**\r
+ * @brief STR Exclusive (8 bit)\r
+ *\r
+ * @param value value to store\r
+ * @param *addr address pointer\r
+ * @return successful / failed\r
+ *\r
+ * Exclusive STR command for 8 bit values\r
+ */\r
+extern uint32_t __STREXB(uint8_t value, uint8_t *addr);\r
+\r
+/**\r
+ * @brief STR Exclusive (16 bit)\r
+ *\r
+ * @param value value to store\r
+ * @param *addr address pointer\r
+ * @return successful / failed\r
+ *\r
+ * Exclusive STR command for 16 bit values\r
+ */\r
+extern uint32_t __STREXH(uint16_t value, uint16_t *addr);\r
+\r
+/**\r
+ * @brief STR Exclusive (32 bit)\r
+ *\r
+ * @param value value to store\r
+ * @param *addr address pointer\r
+ * @return successful / failed\r
+ *\r
+ * Exclusive STR command for 32 bit values\r
+ */\r
+extern uint32_t __STREXW(uint32_t value, uint32_t *addr);\r
+\r
+\r
+\r
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/\r
+/* GNU gcc specific functions */\r
+\r
+static __INLINE void __enable_irq(void) { __ASM volatile ("cpsie i"); }\r
+static __INLINE void __disable_irq(void) { __ASM volatile ("cpsid i"); }\r
+\r
+static __INLINE void __enable_fault_irq(void) { __ASM volatile ("cpsie f"); }\r
+static __INLINE void __disable_fault_irq(void) { __ASM volatile ("cpsid f"); }\r
+\r
+static __INLINE void __NOP(void) { __ASM volatile ("nop"); }\r
+static __INLINE void __WFI(void) { __ASM volatile ("wfi"); }\r
+static __INLINE void __WFE(void) { __ASM volatile ("wfe"); }\r
+static __INLINE void __SEV(void) { __ASM volatile ("sev"); }\r
+static __INLINE void __ISB(void) { __ASM volatile ("isb"); }\r
+static __INLINE void __DSB(void) { __ASM volatile ("dsb"); }\r
+static __INLINE void __DMB(void) { __ASM volatile ("dmb"); }\r
+static __INLINE void __CLREX(void) { __ASM volatile ("clrex"); }\r
+\r
+\r
+/**\r
+ * @brief Return the Process Stack Pointer\r
+ *\r
+ * @return ProcessStackPointer\r
+ *\r
+ * Return the actual process stack pointer\r
+ */\r
+extern uint32_t __get_PSP(void);\r
+\r
+/**\r
+ * @brief Set the Process Stack Pointer\r
+ *\r
+ * @param topOfProcStack Process Stack Pointer\r
+ *\r
+ * Assign the value ProcessStackPointer to the MSP \r
+ * (process stack pointer) Cortex processor register\r
+ */\r
+extern void __set_PSP(uint32_t topOfProcStack);\r
+\r
+/**\r
+ * @brief Return the Main Stack Pointer\r
+ *\r
+ * @return Main Stack Pointer\r
+ *\r
+ * Return the current value of the MSP (main stack pointer)\r
+ * Cortex processor register\r
+ */\r
+extern uint32_t __get_MSP(void);\r
+\r
+/**\r
+ * @brief Set the Main Stack Pointer\r
+ *\r
+ * @param topOfMainStack Main Stack Pointer\r
+ *\r
+ * Assign the value mainStackPointer to the MSP \r
+ * (main stack pointer) Cortex processor register\r
+ */\r
+extern void __set_MSP(uint32_t topOfMainStack);\r
+\r
+/**\r
+ * @brief Return the Base Priority value\r
+ *\r
+ * @return BasePriority\r
+ *\r
+ * Return the content of the base priority register\r
+ */\r
+extern uint32_t __get_BASEPRI(void);\r
+\r
+/**\r
+ * @brief Set the Base Priority value\r
+ *\r
+ * @param basePri BasePriority\r
+ *\r
+ * Set the base priority register\r
+ */\r
+extern void __set_BASEPRI(uint32_t basePri);\r
+\r
+/**\r
+ * @brief Return the Priority Mask value\r
+ *\r
+ * @return PriMask\r
+ *\r
+ * Return state of the priority mask bit from the priority mask register\r
+ */\r
+extern uint32_t __get_PRIMASK(void);\r
+\r
+/**\r
+ * @brief Set the Priority Mask value\r
+ *\r
+ * @param priMask PriMask\r
+ *\r
+ * Set the priority mask bit in the priority mask register\r
+ */\r
+extern void __set_PRIMASK(uint32_t priMask);\r
+\r
+/**\r
+ * @brief Return the Fault Mask value\r
+ *\r
+ * @return FaultMask\r
+ *\r
+ * Return the content of the fault mask register\r
+ */\r
+extern uint32_t __get_FAULTMASK(void);\r
+\r
+/**\r
+ * @brief Set the Fault Mask value\r
+ *\r
+ * @param faultMask faultMask value\r
+ *\r
+ * Set the fault mask register\r
+ */\r
+extern void __set_FAULTMASK(uint32_t faultMask);\r
+\r
+/**\r
+ * @brief Return the Control Register value\r
+* \r
+* @return Control value\r
+ *\r
+ * Return the content of the control register\r
+ */\r
+extern uint32_t __get_CONTROL(void);\r
+\r
+/**\r
+ * @brief Set the Control Register value\r
+ *\r
+ * @param control Control value\r
+ *\r
+ * Set the control register\r
+ */\r
+extern void __set_CONTROL(uint32_t control);\r
+\r
+/**\r
+ * @brief Reverse byte order in integer value\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse byte order in integer value\r
+ */\r
+extern uint32_t __REV(uint32_t value);\r
+\r
+/**\r
+ * @brief Reverse byte order in unsigned short value\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse byte order in unsigned short value\r
+ */\r
+extern uint32_t __REV16(uint16_t value);\r
+\r
+/**\r
+ * @brief Reverse byte order in signed short value with sign extension to integer\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse byte order in signed short value with sign extension to integer\r
+ */\r
+extern int32_t __REVSH(int16_t value);\r
+\r
+/**\r
+ * @brief Reverse bit order of value\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse bit order of value\r
+ */\r
+extern uint32_t __RBIT(uint32_t value);\r
+\r
+/**\r
+ * @brief LDR Exclusive (8 bit)\r
+ *\r
+ * @param *addr address pointer\r
+ * @return value of (*address)\r
+ *\r
+ * Exclusive LDR command for 8 bit value\r
+ */\r
+extern uint8_t __LDREXB(uint8_t *addr);\r
+\r
+/**\r
+ * @brief LDR Exclusive (16 bit)\r
+ *\r
+ * @param *addr address pointer\r
+ * @return value of (*address)\r
+ *\r
+ * Exclusive LDR command for 16 bit values\r
+ */\r
+extern uint16_t __LDREXH(uint16_t *addr);\r
+\r
+/**\r
+ * @brief LDR Exclusive (32 bit)\r
+ *\r
+ * @param *addr address pointer\r
+ * @return value of (*address)\r
+ *\r
+ * Exclusive LDR command for 32 bit values\r
+ */\r
+extern uint32_t __LDREXW(uint32_t *addr);\r
+\r
+/**\r
+ * @brief STR Exclusive (8 bit)\r
+ *\r
+ * @param value value to store\r
+ * @param *addr address pointer\r
+ * @return successful / failed\r
+ *\r
+ * Exclusive STR command for 8 bit values\r
+ */\r
+extern uint32_t __STREXB(uint8_t value, uint8_t *addr);\r
+\r
+/**\r
+ * @brief STR Exclusive (16 bit)\r
+ *\r
+ * @param value value to store\r
+ * @param *addr address pointer\r
+ * @return successful / failed\r
+ *\r
+ * Exclusive STR command for 16 bit values\r
+ */\r
+extern uint32_t __STREXH(uint16_t value, uint16_t *addr);\r
+\r
+/**\r
+ * @brief STR Exclusive (32 bit)\r
+ *\r
+ * @param value value to store\r
+ * @param *addr address pointer\r
+ * @return successful / failed\r
+ *\r
+ * Exclusive STR command for 32 bit values\r
+ */\r
+extern uint32_t __STREXW(uint32_t value, uint32_t *addr);\r
+\r
+\r
+#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/\r
+/* TASKING carm specific functions */\r
+\r
+/*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all instrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
+\r
+#endif\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface\r
+ Core Function Interface containing:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Reset Functions\r
+*/\r
+/*@{*/\r
+\r
+/* ########################## NVIC functions #################################### */\r
+\r
+/**\r
+ * @brief Set the Priority Grouping in NVIC Interrupt Controller\r
+ *\r
+ * @param PriorityGroup is priority grouping field\r
+ *\r
+ * Set the priority grouping field using the required unlock sequence.\r
+ * The parameter priority_grouping is assigned to the field \r
+ * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used.\r
+ * In case of a conflict between priority grouping and available\r
+ * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+ */\r
+static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
+{\r
+ uint32_t reg_value;\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ \r
+ reg_value = SCB->AIRCR; /* read old register configuration */\r
+ reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */\r
+ reg_value = (reg_value |\r
+ (0x5FA << SCB_AIRCR_VECTKEY_Pos) | \r
+ (PriorityGroupTmp << 8)); /* Insert write key and priorty group */\r
+ SCB->AIRCR = reg_value;\r
+}\r
+\r
+/**\r
+ * @brief Get the Priority Grouping from NVIC Interrupt Controller\r
+ *\r
+ * @return priority grouping field \r
+ *\r
+ * Get the priority grouping from NVIC Interrupt Controller.\r
+ * priority grouping is SCB->AIRCR [10:8] PRIGROUP field.\r
+ */\r
+static __INLINE uint32_t NVIC_GetPriorityGrouping(void)\r
+{\r
+ return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */\r
+}\r
+\r
+/**\r
+ * @brief Enable Interrupt in NVIC Interrupt Controller\r
+ *\r
+ * @param IRQn The positive number of the external interrupt to enable\r
+ *\r
+ * Enable a device specific interupt in the NVIC interrupt controller.\r
+ * The interrupt number cannot be a negative value.\r
+ */\r
+static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */\r
+}\r
+\r
+/**\r
+ * @brief Disable the interrupt line for external interrupt specified\r
+ * \r
+ * @param IRQn The positive number of the external interrupt to disable\r
+ * \r
+ * Disable a device specific interupt in the NVIC interrupt controller.\r
+ * The interrupt number cannot be a negative value.\r
+ */\r
+static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */\r
+}\r
+\r
+/**\r
+ * @brief Read the interrupt pending bit for a device specific interrupt source\r
+ * \r
+ * @param IRQn The number of the device specifc interrupt\r
+ * @return 1 = interrupt pending, 0 = interrupt not pending\r
+ *\r
+ * Read the pending register in NVIC and return 1 if its status is pending, \r
+ * otherwise it returns 0\r
+ */\r
+static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */\r
+}\r
+\r
+/**\r
+ * @brief Set the pending bit for an external interrupt\r
+ * \r
+ * @param IRQn The number of the interrupt for set pending\r
+ *\r
+ * Set the pending bit for the specified interrupt.\r
+ * The interrupt number cannot be a negative value.\r
+ */\r
+static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */\r
+}\r
+\r
+/**\r
+ * @brief Clear the pending bit for an external interrupt\r
+ *\r
+ * @param IRQn The number of the interrupt for clear pending\r
+ *\r
+ * Clear the pending bit for the specified interrupt. \r
+ * The interrupt number cannot be a negative value.\r
+ */\r
+static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */\r
+}\r
+\r
+/**\r
+ * @brief Read the active bit for an external interrupt\r
+ *\r
+ * @param IRQn The number of the interrupt for read active bit\r
+ * @return 1 = interrupt active, 0 = interrupt not active\r
+ *\r
+ * Read the active register in NVIC and returns 1 if its status is active, \r
+ * otherwise it returns 0.\r
+ */\r
+static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+ return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */\r
+}\r
+\r
+/**\r
+ * @brief Set the priority for an interrupt\r
+ *\r
+ * @param IRQn The number of the interrupt for set priority\r
+ * @param priority The priority to set\r
+ *\r
+ * Set the priority for the specified interrupt. The interrupt \r
+ * number can be positive to specify an external (device specific) \r
+ * interrupt, or negative to specify an internal (core) interrupt.\r
+ *\r
+ * Note: The priority cannot be set for every core interrupt.\r
+ */\r
+static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if(IRQn < 0) {\r
+ SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */\r
+ else {\r
+ NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */\r
+}\r
+\r
+/**\r
+ * @brief Read the priority for an interrupt\r
+ *\r
+ * @param IRQn The number of the interrupt for get priority\r
+ * @return The priority for the interrupt\r
+ *\r
+ * Read the priority for the specified interrupt. The interrupt \r
+ * number can be positive to specify an external (device specific) \r
+ * interrupt, or negative to specify an internal (core) interrupt.\r
+ *\r
+ * The returned priority value is automatically aligned to the implemented\r
+ * priority bits of the microcontroller.\r
+ *\r
+ * Note: The priority cannot be set for every core interrupt.\r
+ */\r
+static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if(IRQn < 0) {\r
+ return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */\r
+ else {\r
+ return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */\r
+}\r
+\r
+\r
+/**\r
+ * @brief Encode the priority for an interrupt\r
+ *\r
+ * @param PriorityGroup The used priority group\r
+ * @param PreemptPriority The preemptive priority value (starting from 0)\r
+ * @param SubPriority The sub priority value (starting from 0)\r
+ * @return The encoded priority for the interrupt\r
+ *\r
+ * Encode the priority for an interrupt with the given priority group,\r
+ * preemptive priority value and sub priority value.\r
+ * In case of a conflict between priority grouping and available\r
+ * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.\r
+ *\r
+ * The returned priority value can be used for NVIC_SetPriority(...) function\r
+ */\r
+static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
+ \r
+ return (\r
+ ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |\r
+ ((SubPriority & ((1 << (SubPriorityBits )) - 1)))\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ * @brief Decode the priority of an interrupt\r
+ *\r
+ * @param Priority The priority for the interrupt\r
+ * @param PriorityGroup The used priority group\r
+ * @param pPreemptPriority The preemptive priority value (starting from 0)\r
+ * @param pSubPriority The sub priority value (starting from 0)\r
+ *\r
+ * Decode an interrupt priority value with the given priority group to \r
+ * preemptive priority value and sub priority value.\r
+ * In case of a conflict between priority grouping and available\r
+ * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.\r
+ *\r
+ * The priority value can be retrieved with NVIC_GetPriority(...) function\r
+ */\r
+static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
+ \r
+ *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);\r
+ *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);\r
+}\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+\r
+#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0)\r
+\r
+/**\r
+ * @brief Initialize and start the SysTick counter and its interrupt.\r
+ *\r
+ * @param ticks number of ticks between two interrupts\r
+ * @return 1 = failed, 0 = successful\r
+ *\r
+ * Initialise the system tick timer and its interrupt and start the\r
+ * system tick timer / counter in free running mode to generate \r
+ * periodical interrupts.\r
+ */\r
+static __INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{ \r
+ if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */\r
+ \r
+ SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | \r
+ SysTick_CTRL_TICKINT_Msk | \r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0); /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+\r
+\r
+\r
+/* ################################## Reset function ############################################ */\r
+\r
+/**\r
+ * @brief Initiate a system reset request.\r
+ *\r
+ * Initiate a system reset request to reset the MCU\r
+ */\r
+static __INLINE void NVIC_SystemReset(void)\r
+{\r
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | \r
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | \r
+ SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */\r
+ __DSB(); /* Ensure completion of memory access */ \r
+ while(1); /* wait until reset */\r
+}\r
+\r
+/*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */\r
+\r
+\r
+\r
+/* ##################################### Debug In/Output function ########################################### */\r
+\r
+/** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface\r
+ Core Debug Interface containing:\r
+ - Core Debug Receive / Transmit Functions\r
+ - Core Debug Defines\r
+ - Core Debug Variables\r
+*/\r
+/*@{*/\r
+\r
+extern volatile int ITM_RxBuffer; /*!< variable to receive characters */\r
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */\r
+\r
+\r
+/**\r
+ * @brief Outputs a character via the ITM channel 0\r
+ *\r
+ * @param ch character to output\r
+ * @return character to output\r
+ *\r
+ * The function outputs a character via the ITM channel 0. \r
+ * The function returns when no debugger is connected that has booked the output. \r
+ * It is blocking when a debugger is connected, but the previous character send is not transmitted. \r
+ */\r
+static __INLINE uint32_t ITM_SendChar (uint32_t ch)\r
+{\r
+ if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */\r
+ (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */\r
+ (ITM->TER & (1ul << 0) ) ) /* ITM Port #0 enabled */\r
+ {\r
+ while (ITM->PORT[0].u32 == 0);\r
+ ITM->PORT[0].u8 = (uint8_t) ch;\r
+ } \r
+ return (ch);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Inputs a character via variable ITM_RxBuffer\r
+ *\r
+ * @return received character, -1 = no character received\r
+ *\r
+ * The function inputs a character via variable ITM_RxBuffer. \r
+ * The function returns when no debugger is connected that has booked the output. \r
+ * It is blocking when a debugger is connected, but the previous character send is not transmitted. \r
+ */\r
+static __INLINE int ITM_ReceiveChar (void) {\r
+ int ch = -1; /* no character available */\r
+\r
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {\r
+ ch = ITM_RxBuffer;\r
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r
+ }\r
+ \r
+ return (ch); \r
+}\r
+\r
+\r
+/**\r
+ * @brief Check if a character via variable ITM_RxBuffer is available\r
+ *\r
+ * @return 1 = character available, 0 = no character available\r
+ *\r
+ * The function checks variable ITM_RxBuffer whether a character is available or not. \r
+ * The function returns '1' if a character is available and '0' if no character is available. \r
+ */\r
+static __INLINE int ITM_CheckChar (void) {\r
+\r
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {\r
+ return (0); /* no character available */\r
+ } else {\r
+ return (1); /* character available */\r
+ }\r
+}\r
+\r
+/*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/*@}*/ /* end of group CMSIS_CM3_core_definitions */\r
+\r
+#endif /* __CM3_CORE_H__ */\r
+\r
+/*lint -restore */\r
--- /dev/null
+/*******************************************************************************\r
+ * (c) Copyright 2009 Actel Corporation. All rights reserved.\r
+ * \r
+ * Assertion implementation.\r
+ *\r
+ * This file provides the implementation of the ASSERT macro. This file can be\r
+ * modified to cater for project specific requirements regarding the way\r
+ * assertions are handled.\r
+ *\r
+ * SVN $Revision: 1676 $\r
+ * SVN $Date: 2009-12-02 16:47:03 +0000 (Wed, 02 Dec 2009) $\r
+ */\r
+#ifndef __MSS_ASSERT_H_\r
+#define __MSS_ASSERT_H_\r
+\r
+#include <assert.h>\r
+\r
+#if defined ( __GNUC__ )\r
+\r
+#if defined(NDEBUG)\r
+\r
+#define ASSERT(CHECK)\r
+\r
+#else /* NDEBUG */\r
+/*\r
+ * SoftConsole assertion handling\r
+ */\r
+#define ASSERT(CHECK) \\r
+ do { \\r
+ if (!(CHECK)) \\r
+ { \\r
+ __asm volatile ("BKPT\n\t"); \\r
+ } \\r
+ } while (0);\r
+ \r
+#endif /* NDEBUG */\r
+\r
+#else\r
+/*\r
+ * IAR Embedded Workbench or Keil assertion handling.\r
+ * Call C library assert function which should result in error message\r
+ * displayed in debugger.\r
+ */\r
+#define ASSERT(X) assert(X)\r
+\r
+#endif\r
+\r
+#endif /* __MSS_ASSERT_H_ */\r
--- /dev/null
+/*******************************************************************************
+ * (c) Copyright 2009 Actel Corporation. All rights reserved.
+ *
+ * SmartFusion/Cortex-M3 linker script for creating a SoftConsole downloadable
+ * debug image executing in SmartFusion internal eNVM.
+ *
+ * SVN $Revision: 1677 $
+ * SVN $Date: 2009-12-02 16:57:29 +0000 (Wed, 02 Dec 2009) $
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm",
+ "elf32-littlearm")
+GROUP(-lc -lgcc -lm)
+OUTPUT_ARCH(arm)
+ENTRY(Reset_Handler)
+SEARCH_DIR(.)
+__DYNAMIC = 0;
+
+/*******************************************************************************
+ * Start of board customization.
+ *******************************************************************************/
+MEMORY
+{
+ /*
+ * WARNING: The words "SOFTCONSOLE", "FLASH", and "USE", the colon ":", and
+ * the name of the type of flash memory are all in a specific order.
+ * Please do not modify that comment line, in order to ensure
+ * debugging of your application will use the flash memory correctly.
+ */
+
+ /* SOFTCONSOLE FLASH USE: actel-smartfusion-envm */
+ rom (rx) : ORIGIN = 0x60000000, LENGTH = 256k
+
+ /* SmartFusion internal eNVM mirrored to 0x00000000 */
+ romMirror (rx) : ORIGIN = 0x00000000, LENGTH = 256k
+
+ /* SmartFusion internal eSRAM */
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 64k
+}
+
+RAM_START_ADDRESS = 0x20000000; /* Must be the same value MEMORY region ram ORIGIN above. */
+RAM_SIZE = 64k; /* Must be the same value MEMORY region ram LENGTH above. */
+MAIN_STACK_SIZE = 8k; /* Cortex main stack size. */
+PROCESS_STACK_SIZE = 4k; /* Cortex process stack size (only available with OS extensions).*/
+
+/*******************************************************************************
+ * End of board customization.
+ *******************************************************************************/
+
+PROVIDE (__main_stack_start = RAM_START_ADDRESS + RAM_SIZE);
+PROVIDE (__process_stack_start = __main_stack_start - MAIN_STACK_SIZE);
+PROVIDE (_estack = __main_stack_start);
+PROVIDE (__mirrored_nvm = 1); /* Indicate to startup code that NVM is mirrored to VMA address and no text copy is required. */
+
+SECTIONS
+{
+ .init :
+ {
+ *(.isr_vector)
+ *sys_boot.o(.text)
+ . = ALIGN(0x4);
+ } >romMirror AT>rom
+
+ .text :
+ {
+ CREATE_OBJECT_SYMBOLS
+ __text_load = LOADADDR(.text);
+ __text_start = .;
+
+ *(.text .text.* .gnu.linkonce.t.*)
+ *(.plt)
+ *(.gnu.warning)
+ *(.glue_7t) *(.glue_7) *(.vfp11_veneer)
+
+ . = ALIGN(0x4);
+ /* These are for running static constructors and destructors under ELF. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ *(.rodata .rodata.* .gnu.linkonce.r.*)
+
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ *(.gcc_except_table)
+ *(.eh_frame_hdr)
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } >romMirror AT>rom
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } >ram AT>rom
+ __exidx_end = .;
+ _etext = .;
+
+ .data :
+ {
+ __data_load = LOADADDR(.data);
+ _sidata = LOADADDR (.data);
+ __data_start = .;
+ _sdata = .;
+ KEEP(*(.jcr))
+ *(.got.plt) *(.got)
+ *(.shdata)
+ *(.data .data.* .gnu.linkonce.d.*)
+ . = ALIGN (4);
+ _edata = .;
+ } >ram AT>rom
+
+ .bss :
+ {
+ __bss_start__ = . ;
+ _sbss = .;
+ *(.shbss)
+ *(.bss .bss.* .gnu.linkonce.b.*)
+ *(COMMON)
+ . = ALIGN (8);
+ __bss_end__ = .;
+ _end = .;
+ __end = _end;
+ _ebss = .;
+ PROVIDE(end = .);
+ } >ram AT>rom
+
+ .stab 0 (NOLOAD) :
+ {
+ *(.stab)
+ }
+
+ .stabstr 0 (NOLOAD) :
+ {
+ *(.stabstr)
+ }
+ /* DWARF debug sections.
+ Symbols in the DWARF debugging sections are relative to the beginning
+ of the section so we begin them at 0. */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2 */
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2 */
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+ .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
+ .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }
+ /DISCARD/ : { *(.note.GNU-stack) }
+}
--- /dev/null
+/*******************************************************************************
+ * (c) Copyright 2009 Actel Corporation. All rights reserved.
+ *
+ * SmartFusion/Cortex-M3 linker script for creating a SoftConsole downloadable
+ * debug image executing in SmartFusion internal eSRAM.
+ *
+ * SVN $Revision: 1677 $
+ * SVN $Date: 2009-12-02 16:57:29 +0000 (Wed, 02 Dec 2009) $
+ */
+
+ OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm",
+ "elf32-littlearm")
+GROUP(-lc -lgcc -lm)
+OUTPUT_ARCH(arm)
+ENTRY(Reset_Handler)
+SEARCH_DIR(.)
+__DYNAMIC = 0;
+
+/*******************************************************************************
+ * Start of board customization.
+ *******************************************************************************/
+MEMORY
+{
+ /* SmartFusion internal eSRAM */
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 64k
+}
+
+RAM_START_ADDRESS = 0x20000000; /* Must be the same value MEMORY region ram ORIGIN above. */
+RAM_SIZE = 64k; /* Must be the same value MEMORY region ram LENGTH above. */
+MAIN_STACK_SIZE = 8k; /* Cortex main stack size. */
+PROCESS_STACK_SIZE = 4k; /* Cortex process stack size (only available with OS extensions).*/
+
+/*******************************************************************************
+ * End of board customization.
+ *******************************************************************************/
+
+PROVIDE (__main_stack_start = RAM_START_ADDRESS + RAM_SIZE);
+PROVIDE (__process_stack_start = __main_stack_start - MAIN_STACK_SIZE);
+PROVIDE (_estack = __main_stack_start);
+PROVIDE (__mirrored_nvm = 0); /* Indicate to startup code that NVM is not mirrored to VMA address .text copy is required. */
+
+SECTIONS
+{
+ .text :
+ {
+ CREATE_OBJECT_SYMBOLS
+ __text_load = LOADADDR(.text);
+ __text_start = .;
+ *(.isr_vector)
+ *(.text .text.* .gnu.linkonce.t.*)
+ *(.plt)
+ *(.gnu.warning)
+ *(.glue_7t) *(.glue_7) *(.vfp11_veneer)
+
+ . = ALIGN(0x4);
+ /* These are for running static constructors and destructors under ELF. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ *(.rodata .rodata.* .gnu.linkonce.r.*)
+
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ *(.gcc_except_table)
+ *(.eh_frame_hdr)
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } >ram
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } >ram
+ __exidx_end = .;
+ _etext = .;
+ PROVIDE(__text_end = .);
+
+ .data :
+ {
+ __data_load = LOADADDR (.data);
+ _sidata = LOADADDR (.data);
+ __data_start = .;
+ _sdata = .;
+ KEEP(*(.jcr))
+ *(.got.plt) *(.got)
+ *(.shdata)
+ *(.data .data.* .gnu.linkonce.d.*)
+ . = ALIGN (4);
+ _edata = .;
+ } >ram
+
+ .bss :
+ {
+ __bss_start__ = . ;
+ _sbss = .;
+ *(.shbss)
+ *(.bss .bss.* .gnu.linkonce.b.*)
+ *(COMMON)
+ . = ALIGN (8);
+ __bss_end__ = .;
+ _end = .;
+ __end = _end;
+ _ebss = .;
+ PROVIDE(end = .);
+ } >ram
+
+ /*
+ * The .stack section is only specified here in order for the linker to generate
+ * an error if the ram is full.
+ */
+ .stack :
+ {
+ . = ALIGN(4);
+ . += PROCESS_STACK_SIZE;
+ . = ALIGN(4);
+ . += MAIN_STACK_SIZE;
+ . = ALIGN(4);
+ } >ram
+
+ .stab 0 (NOLOAD) :
+ {
+ *(.stab)
+ }
+
+ .stabstr 0 (NOLOAD) :
+ {
+ *(.stabstr)
+ }
+ /* DWARF debug sections.
+ Symbols in the DWARF debugging sections are relative to the beginning
+ of the section so we begin them at 0. */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2 */
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2 */
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+ .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
+ .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }
+ /DISCARD/ : { *(.note.GNU-stack) *(.isr_vector) }
+}
--- /dev/null
+/*******************************************************************************
+ * (c) Copyright 2009 Actel Corporation. All rights reserved.
+ *
+ * SmartFusion/Cortex-M3 linker script for creating a SoftConsole downloadable
+ * debug image executing in SmartFusion development board external RAM.
+ *
+ * SVN $Revision: 2014 $
+ * SVN $Date: 2010-01-20 10:37:26 +0000 (Wed, 20 Jan 2010) $
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm",
+ "elf32-littlearm")
+GROUP(-lc -lgcc -lm)
+OUTPUT_ARCH(arm)
+ENTRY(Reset_Handler)
+SEARCH_DIR(.)
+__DYNAMIC = 0;
+
+/*******************************************************************************
+ * Start of board customization.
+ *******************************************************************************/
+MEMORY
+{
+ /* SmartFusion internal eSRAM */
+ esram (rwx) : ORIGIN = 0x20000000, LENGTH = 64k
+
+ /* SmartFusion development board external RAM */
+ external_ram (rwx) : ORIGIN = 0x70000000, LENGTH = 2M
+}
+
+RAM_START_ADDRESS = 0x70000000; /* Must be the same value MEMORY region ram ORIGIN above. */
+RAM_SIZE = 64k; /* Must be the same value MEMORY region ram LENGTH above. */
+MAIN_STACK_SIZE = 8k; /* Cortex main stack size. */
+PROCESS_STACK_SIZE = 4k; /* Cortex process stack size (only available with OS extensions).*/
+
+/*******************************************************************************
+ * End of board customization.
+ *******************************************************************************/
+
+PROVIDE (__main_stack_start = RAM_START_ADDRESS + RAM_SIZE);
+PROVIDE (__process_stack_start = __main_stack_start - MAIN_STACK_SIZE);
+PROVIDE (_estack = __main_stack_start);
+PROVIDE (__mirrored_nvm = 0); /* Indicate to startup code that NVM is not mirrored to VMA address .text copy is required. */
+
+SECTIONS
+{
+ .init :
+ {
+ *(.isr_vector)
+ . = ALIGN(0x4);
+ } >esram
+
+ .text :
+ {
+ CREATE_OBJECT_SYMBOLS
+ __text_load = LOADADDR(.text);
+ __text_start = .;
+ *(.text .text.* .gnu.linkonce.t.*)
+ *(.plt)
+ *(.gnu.warning)
+ *(.glue_7t) *(.glue_7) *(.vfp11_veneer)
+
+ . = ALIGN(0x4);
+ /* These are for running static constructors and destructors under ELF. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ *(.rodata .rodata.* .gnu.linkonce.r.*)
+
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ *(.gcc_except_table)
+ *(.eh_frame_hdr)
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } >external_ram
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } >external_ram
+ __exidx_end = .;
+ _etext = .;
+ PROVIDE(__text_end = .);
+
+ .data :
+ {
+ __data_load = LOADADDR (.data);
+ _sidata = LOADADDR (.data);
+ __data_start = .;
+ _sdata = .;
+ KEEP(*(.jcr))
+ *(.got.plt) *(.got)
+ *(.shdata)
+ *(.data .data.* .gnu.linkonce.d.*)
+ . = ALIGN (4);
+ _edata = .;
+ } >external_ram
+
+ .bss :
+ {
+ __bss_start__ = . ;
+ _sbss = .;
+ *(.shbss)
+ *(.bss .bss.* .gnu.linkonce.b.*)
+ *(COMMON)
+ . = ALIGN (8);
+ __bss_end__ = .;
+ _end = .;
+ __end = _end;
+ _ebss = .;
+ PROVIDE(end = .);
+ } >external_ram
+
+ /*
+ * The .stack section is only specified here in order for the linker to generate
+ * an error if the esram is full.
+ */
+ .stack :
+ {
+ . = ALIGN(4);
+ . += PROCESS_STACK_SIZE;
+ . = ALIGN(4);
+ . += MAIN_STACK_SIZE;
+ . = ALIGN(4);
+ } >external_ram
+
+ .stab 0 (NOLOAD) :
+ {
+ *(.stab)
+ }
+
+ .stabstr 0 (NOLOAD) :
+ {
+ *(.stabstr)
+ }
+ /* DWARF debug sections.
+ Symbols in the DWARF debugging sections are relative to the beginning
+ of the section so we begin them at 0. */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2 */
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2 */
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+ .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
+ .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }
+ /DISCARD/ : { *(.note.GNU-stack) *(.isr_vector) }
+}
--- /dev/null
+/*******************************************************************************\r
+ * (c) Copyright 2009 Actel Corporation. All rights reserved.\r
+ * \r
+ * Stubs for Newlib system calls.\r
+ * \r
+ * SVN $Revision: 2020 $\r
+ * SVN $Date: 2010-01-20 14:51:50 +0000 (Wed, 20 Jan 2010) $\r
+ */\r
+#include <stdlib.h>\r
+#include <sys/unistd.h>\r
+#include <sys/stat.h>\r
+#include <sys/times.h>\r
+#include <errno.h>\r
+#undef errno\r
+extern int errno;\r
+\r
+/*==============================================================================\r
+ * Redirection of standard output to a SmartFusion MSS UART.\r
+ *------------------------------------------------------------------------------\r
+ * A default implementation for the redirection of the output of printf() to a\r
+ * UART is provided as the bottom of this file. This redirection is enabled by\r
+ * adding the symbol/define ACTEL_STDIO_THRU_UART to your project and\r
+ * specifying the baud rate using the ACTEL_STDIO_BAUD_RATE define.\r
+ */\r
+#ifdef ACTEL_STDIO_THRU_UART\r
+#include "../../drivers/mss_uart/mss_uart.h"\r
+\r
+#ifndef ACTEL_STDIO_BAUD_RATE\r
+#define ACTEL_STDIO_BAUD_RATE MSS_UART_57600_BAUD\r
+#endif\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Global flag used to indicate if the UART driver needs to be initialized.\r
+ */\r
+static int g_stdio_uart_init_done = 0;\r
+\r
+#endif /* ACTEL_STDIO_THRU_UART */\r
+\r
+/*==============================================================================\r
+ * Environment variables.\r
+ * A pointer to a list of environment variables and their values. For a minimal\r
+ * environment, this empty list is adequate:\r
+ */\r
+char *__env[1] = { 0 };\r
+char **environ = __env;\r
+\r
+/*==============================================================================\r
+ * Close a file.\r
+ */\r
+int _close(int file)\r
+{\r
+ return -1;\r
+}\r
+\r
+/*==============================================================================\r
+ * Transfer control to a new process.\r
+ */\r
+int _execve(char *name, char **argv, char **env)\r
+{\r
+ errno = ENOMEM;\r
+ return -1;\r
+}\r
+\r
+/*==============================================================================\r
+ * Exit a program without cleaning up files.\r
+ */\r
+void _exit( int code )\r
+{\r
+ /* Should we force a system reset? */\r
+ while( 1 )\r
+ {\r
+ ;\r
+ }\r
+}\r
+\r
+/*==============================================================================\r
+ * Create a new process.\r
+ */\r
+int _fork(void)\r
+{\r
+ errno = EAGAIN;\r
+ return -1;\r
+}\r
+\r
+/*==============================================================================\r
+ * Status of an open file.\r
+ */\r
+int _fstat(int file, struct stat *st)\r
+{\r
+ st->st_mode = S_IFCHR;\r
+ return 0;\r
+}\r
+\r
+/*==============================================================================\r
+ * Process-ID\r
+ */\r
+int _getpid(void)\r
+{\r
+ return 1;\r
+}\r
+\r
+/*==============================================================================\r
+ * Query whether output stream is a terminal.\r
+ */\r
+int _isatty(int file)\r
+{\r
+ return 1;\r
+}\r
+\r
+/*==============================================================================\r
+ * Send a signal.\r
+ */\r
+int _kill(int pid, int sig)\r
+{\r
+ errno = EINVAL;\r
+ return -1;\r
+}\r
+\r
+/*==============================================================================\r
+ * Establish a new name for an existing file.\r
+ */\r
+int _link(char *old, char *new)\r
+{\r
+ errno = EMLINK;\r
+ return -1;\r
+}\r
+\r
+/*==============================================================================\r
+ * Set position in a file.\r
+ */\r
+int _lseek(int file, int ptr, int dir)\r
+{\r
+ return 0;\r
+}\r
+\r
+/*==============================================================================\r
+ * Open a file.\r
+ */\r
+int _open(const char *name, int flags, int mode)\r
+{\r
+ return -1;\r
+}\r
+\r
+/*==============================================================================\r
+ * Read from a file.\r
+ */\r
+int _read(int file, char *ptr, int len)\r
+{\r
+ return 0;\r
+}\r
+\r
+/*==============================================================================\r
+ * Increase program data space. As malloc and related functions depend on this,\r
+ * it is useful to have a working implementation. The following suffices for a\r
+ * standalone system; it exploits the symbol _end automatically defined by the\r
+ * GNU linker. \r
+ */\r
+caddr_t _sbrk(int incr)\r
+{\r
+ extern char _end; /* Defined by the linker */\r
+ static char *heap_end;\r
+ char *prev_heap_end;\r
+ char * stack_ptr;\r
+ \r
+ if (heap_end == 0)\r
+ {\r
+ heap_end = &_end;\r
+ }\r
+ \r
+ prev_heap_end = heap_end;\r
+ asm volatile ("MRS %0, msp" : "=r" (stack_ptr) );\r
+ if (heap_end + incr > stack_ptr)\r
+ {\r
+ write (1, "Heap and stack collision\n", 25);\r
+ abort ();\r
+ }\r
+ \r
+ heap_end += incr;\r
+ return (caddr_t) prev_heap_end;\r
+}\r
+\r
+/*==============================================================================\r
+ * Status of a file (by name).\r
+ */\r
+int _stat(char *file, struct stat *st)\r
+{\r
+ st->st_mode = S_IFCHR;\r
+ return 0;\r
+}\r
+\r
+/*==============================================================================\r
+ * Timing information for current process.\r
+ */\r
+int _times(struct tms *buf)\r
+{\r
+ return -1;\r
+}\r
+\r
+/*==============================================================================\r
+ * Remove a file's directory entry.\r
+ */\r
+int _unlink(char *name)\r
+{\r
+ errno = ENOENT;\r
+ return -1;\r
+}\r
+\r
+/*==============================================================================\r
+ * Wait for a child process.\r
+ */\r
+int _wait(int *status)\r
+{\r
+ errno = ECHILD;\r
+ return -1;\r
+}\r
+\r
+/*==============================================================================\r
+ * Write to a file. libc subroutines will use this system routine for output to\r
+ * all files, including stdout\97so if you need to generate any output, for\r
+ * example to a serial port for debugging, you should make your minimal write\r
+ * capable of doing this.\r
+ */\r
+int _write_r( void * reent, int file, char * ptr, int len )\r
+{\r
+#ifdef ACTEL_STDIO_THRU_UART\r
+ /*--------------------------------------------------------------------------\r
+ * Initialize the UART driver if it is the first time this function is\r
+ * called.\r
+ */\r
+ if ( !g_stdio_uart_init_done )\r
+ {\r
+ MSS_UART_init( &g_mss_uart0, ACTEL_STDIO_BAUD_RATE, (MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY));\r
+ g_stdio_uart_init_done = 1;\r
+ }\r
+ \r
+ /*--------------------------------------------------------------------------\r
+ * Output text to the UART.\r
+ */\r
+ MSS_UART_polled_tx( &g_mss_uart0, (uint8_t *)ptr, len );\r
+ \r
+ return len;\r
+#else /* ACTEL_STDIO_THRU_UART */\r
+ return 0;\r
+#endif /* ACTEL_STDIO_THRU_UART */\r
+}\r
+\r
+\r
--- /dev/null
+/*******************************************************************************
+ * (c) Copyright 2009 Actel Corporation. All rights reserved.
+ *
+ * SmartFusion/Cortex-M3 linker script creating an executable image for use in
+ * the Libero flow for executing code in place in internal eNVM.
+ *
+ * SVN $Revision: 1766 $
+ * SVN $Date: 2009-12-11 16:33:35 +0000 (Fri, 11 Dec 2009) $
+ */
+OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm",
+ "elf32-littlearm")
+GROUP(-lc -lgcc -lm)
+OUTPUT_ARCH(arm)
+ENTRY(Reset_Handler)
+SEARCH_DIR(.)
+__DYNAMIC = 0;
+
+/*******************************************************************************
+ * Start of board customization.
+ *******************************************************************************/
+MEMORY
+{
+ /* SmartFusion internal eNVM */
+ rom (rx) : ORIGIN = 0, LENGTH = 256k
+
+ /* SmartFusion internal eSRAM */
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 64k
+}
+
+RAM_START_ADDRESS = 0x20000000; /* Must be the same value as MEMORY region ram ORIGIN above. */
+RAM_SIZE = 64k; /* Must be the same value as MEMORY region ram LENGTH above. */
+MAIN_STACK_SIZE = 8k; /* Cortex main stack size. */
+PROCESS_STACK_SIZE = 4k; /* Cortex process stack size (only available with OS extensions).*/
+
+/*******************************************************************************
+ * End of board customization.
+ *******************************************************************************/
+
+PROVIDE (__main_stack_start = RAM_START_ADDRESS + RAM_SIZE);
+PROVIDE (__process_stack_start = __main_stack_start - MAIN_STACK_SIZE);
+PROVIDE (_estack = __main_stack_start);
+PROVIDE (__mirrored_nvm = 0); /* Indicate to startup code that NVM is not mirrored to VMA address .text copy is required. */
+
+SECTIONS
+{
+ .reset :
+ {
+ *(.isr_vector)
+ *sys_boot.o(.text)
+ . = ALIGN(0x4);
+ } >rom
+
+ .text :
+ {
+ CREATE_OBJECT_SYMBOLS
+ __text_load = LOADADDR(.text);
+ __text_start = .;
+
+ *(.text .text.* .gnu.linkonce.t.*)
+ *(.plt)
+ *(.gnu.warning)
+ *(.glue_7t) *(.glue_7) *(.vfp11_veneer)
+
+ . = ALIGN(0x4);
+ /* These are for running static constructors and destructors under ELF. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ *(.rodata .rodata.* .gnu.linkonce.r.*)
+
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ *(.gcc_except_table)
+ *(.eh_frame_hdr)
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } >rom
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } >rom
+ __exidx_end = .;
+ _etext = .;
+
+ .data :
+ {
+ __data_load = LOADADDR(.data);
+ _sidata = LOADADDR (.data);
+ __data_start = .;
+ _sdata = .;
+ KEEP(*(.jcr))
+ *(.got.plt) *(.got)
+ *(.shdata)
+ *(.data .data.* .gnu.linkonce.d.*)
+ . = ALIGN (4);
+ _edata = .;
+ } >ram AT>rom
+
+ .bss :
+ {
+ __bss_start__ = . ;
+ _sbss = .;
+ *(.shbss)
+ *(.bss .bss.* .gnu.linkonce.b.*)
+ *(COMMON)
+ . = ALIGN (8);
+ __bss_end__ = .;
+ _end = .;
+ __end = _end;
+ _ebss = .;
+ PROVIDE(end = .);
+ } >ram AT>rom
+
+ .stab 0 (NOLOAD) :
+ {
+ *(.stab)
+ }
+
+ .stabstr 0 (NOLOAD) :
+ {
+ *(.stabstr)
+ }
+ /* DWARF debug sections.
+ Symbols in the DWARF debugging sections are relative to the beginning
+ of the section so we begin them at 0. */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2 */
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2 */
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+ .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
+ .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }
+ /DISCARD/ : { *(.note.GNU-stack) }
+}
--- /dev/null
+/*******************************************************************************
+ * (c) Copyright 2009 Actel Corporation. All rights reserved.
+ *
+ * SmartFusion/Cortex-M3 linker script creating an executable image for use in
+ * the Libero flow for relocating executable from internal eNVM to external RAM
+ * before starting execution.
+ *
+ * SVN $Revision: 1766 $
+ * SVN $Date: 2009-12-11 16:33:35 +0000 (Fri, 11 Dec 2009) $
+ */
+OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm",
+ "elf32-littlearm")
+GROUP(-lc -lgcc -lm)
+OUTPUT_ARCH(arm)
+ENTRY(Reset_Handler)
+SEARCH_DIR(.)
+__DYNAMIC = 0;
+
+/*******************************************************************************
+ * Start of board customization.
+ *******************************************************************************/
+MEMORY
+{
+ /* SmartFusion internal eNVM */
+ rom (rx) : ORIGIN = 0, LENGTH = 256k
+
+ /* SmartFusion internal eSRAM */
+ esram (rwx) : ORIGIN = 0x20000000, LENGTH = 64k
+
+ /* SmartFusion development board external RAM */
+ external_ram (rwx) : ORIGIN = 0x70000000, LENGTH = 2M
+}
+
+RAM_START_ADDRESS = 0x20000000; /* Must be the same value as MEMORY region esram ORIGIN above. */
+RAM_SIZE = 64k; /* Must be the same value as MEMORY region esram LENGTH above. */
+MAIN_STACK_SIZE = 8k; /* Cortex main stack size. */
+PROCESS_STACK_SIZE = 4k; /* Cortex process stack size (only available with OS extensions).*/
+
+/*******************************************************************************
+ * End of board customization.
+ *******************************************************************************/
+
+PROVIDE (__main_stack_start = RAM_START_ADDRESS + RAM_SIZE);
+PROVIDE (__process_stack_start = __main_stack_start - MAIN_STACK_SIZE);
+PROVIDE (_estack = __main_stack_start);
+PROVIDE (__mirrored_nvm = 0); /* Indicate to startup code that NVM is not mirrored to VMA address .text copy is required. */
+
+SECTIONS
+{
+ .reset :
+ {
+ *(.isr_vector)
+/* *sys_boot.o(.text)*/
+ . = ALIGN(0x4);
+ } >rom
+
+ .text :
+ {
+ CREATE_OBJECT_SYMBOLS
+ __text_load = LOADADDR(.text);
+ __text_start = .;
+
+ *(.text .text.* .gnu.linkonce.t.*)
+ *(.plt)
+ *(.gnu.warning)
+ *(.glue_7t) *(.glue_7) *(.vfp11_veneer)
+
+ . = ALIGN(0x4);
+ /* These are for running static constructors and destructors under ELF. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ *(.rodata .rodata.* .gnu.linkonce.r.*)
+
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ *(.gcc_except_table)
+ *(.eh_frame_hdr)
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } >external_ram AT>rom
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } >external_ram AT>rom
+ __exidx_end = .;
+ _etext = .;
+
+ .data :
+ {
+ __data_load = LOADADDR(.data);
+ _sidata = LOADADDR (.data);
+ __data_start = .;
+ _sdata = .;
+ KEEP(*(.jcr))
+ *(.got.plt) *(.got)
+ *(.shdata)
+ *(.data .data.* .gnu.linkonce.d.*)
+ . = ALIGN (4);
+ _edata = .;
+ } >esram AT>rom
+
+ .bss :
+ {
+ __bss_start__ = . ;
+ _sbss = .;
+ *(.shbss)
+ *(.bss .bss.* .gnu.linkonce.b.*)
+ *(COMMON)
+ . = ALIGN (8);
+ __bss_end__ = .;
+ _end = .;
+ __end = _end;
+ _ebss = .;
+ PROVIDE(end = .);
+ } >esram AT>rom
+
+ .stab 0 (NOLOAD) :
+ {
+ *(.stab)
+ }
+
+ .stabstr 0 (NOLOAD) :
+ {
+ *(.stabstr)
+ }
+ /* DWARF debug sections.
+ Symbols in the DWARF debugging sections are relative to the beginning
+ of the section so we begin them at 0. */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2 */
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2 */
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+ .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
+ .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }
+ /DISCARD/ : { *(.note.GNU-stack) }
+}
--- /dev/null
+/*******************************************************************************\r
+ * (c) Copyright 2009 Actel Corporation. All rights reserved.\r
+ * \r
+ * SmartFusion A2FXXXM3 vector table and startup code.\r
+ *\r
+ * SVN $Revision: 2068 $\r
+ * SVN $Date: 2010-01-27 17:27:41 +0000 (Wed, 27 Jan 2010) $\r
+ */\r
+\r
+ .syntax unified\r
+ .cpu cortex-m3\r
+ .thumb\r
+ \r
+\r
+/*==============================================================================\r
+ * Vector table\r
+ */\r
+ .global g_pfnVectors\r
+ .section .isr_vector,"a",%progbits\r
+ .type g_pfnVectors, %object\r
+ .size g_pfnVectors, .-g_pfnVectors\r
+ \r
+g_pfnVectors:\r
+ .word _estack\r
+ .word Reset_Handler\r
+ .word NMI_Handler\r
+ .word HardFault_Handler\r
+ .word MemManage_Handler\r
+ .word BusFault_Handler\r
+ .word UsageFault_Handler\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word SVC_Handler\r
+ .word DebugMon_Handler\r
+ .word 0\r
+ .word PendSV_Handler\r
+ .word SysTick_Handler\r
+ .word WdogWakeup_IRQHandler\r
+ .word BrownOut_1_5V_IRQHandler\r
+ .word BrownOut_3_3V_IRQHandler\r
+ .word RTC_Match_IRQHandler\r
+ .word RTCIF_Pub_IRQHandler\r
+ .word EthernetMAC_IRQHandler\r
+ .word IAP_IRQHandler\r
+ .word ENVM0_IRQHandler\r
+ .word ENVM1_IRQHandler\r
+ .word DMA_IRQHandler\r
+ .word UART0_IRQHandler\r
+ .word UART1_IRQHandler\r
+ .word SPI0_IRQHandler\r
+ .word SPI1_IRQHandler\r
+ .word I2C0_IRQHandler\r
+ .word I2C0_SMBAlert_IRQHandler\r
+ .word I2C0_SMBus_IRQHandler\r
+ .word I2C1_IRQHandler\r
+ .word I2C1_SMBAlert_IRQHandler\r
+ .word I2C1_SMBus_IRQHandler\r
+ .word Timer1_IRQHandler\r
+ .word Timer2_IRQHandler\r
+ .word PLL_Lock_IRQHandler\r
+ .word PLL_LockLost_IRQHandler\r
+ .word CommError_IRQHandler\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word Fabric_IRQHandler\r
+ .word GPIO0_IRQHandler\r
+ .word GPIO1_IRQHandler\r
+ .word GPIO2_IRQHandler\r
+ .word GPIO3_IRQHandler\r
+ .word GPIO4_IRQHandler\r
+ .word GPIO5_IRQHandler\r
+ .word GPIO6_IRQHandler\r
+ .word GPIO7_IRQHandler\r
+ .word GPIO8_IRQHandler\r
+ .word GPIO9_IRQHandler\r
+ .word GPIO10_IRQHandler\r
+ .word GPIO11_IRQHandler\r
+ .word GPIO12_IRQHandler\r
+ .word GPIO13_IRQHandler\r
+ .word GPIO14_IRQHandler\r
+ .word GPIO15_IRQHandler\r
+ .word GPIO16_IRQHandler\r
+ .word GPIO17_IRQHandler\r
+ .word GPIO18_IRQHandler\r
+ .word GPIO19_IRQHandler\r
+ .word GPIO20_IRQHandler\r
+ .word GPIO21_IRQHandler\r
+ .word GPIO22_IRQHandler\r
+ .word GPIO23_IRQHandler\r
+ .word GPIO24_IRQHandler\r
+ .word GPIO25_IRQHandler\r
+ .word GPIO26_IRQHandler\r
+ .word GPIO27_IRQHandler\r
+ .word GPIO28_IRQHandler\r
+ .word GPIO29_IRQHandler\r
+ .word GPIO30_IRQHandler\r
+ .word GPIO31_IRQHandler\r
+ .word ACE_PC0_Flag0_IRQHandler\r
+ .word ACE_PC0_Flag1_IRQHandler\r
+ .word ACE_PC0_Flag2_IRQHandler\r
+ .word ACE_PC0_Flag3_IRQHandler\r
+ .word ACE_PC1_Flag0_IRQHandler\r
+ .word ACE_PC1_Flag1_IRQHandler\r
+ .word ACE_PC1_Flag2_IRQHandler\r
+ .word ACE_PC1_Flag3_IRQHandler\r
+ .word ACE_PC2_Flag0_IRQHandler\r
+ .word ACE_PC2_Flag1_IRQHandler\r
+ .word ACE_PC2_Flag2_IRQHandler\r
+ .word ACE_PC2_Flag3_IRQHandler\r
+ .word ACE_ADC0_DataValid_IRQHandler\r
+ .word ACE_ADC1_DataValid_IRQHandler\r
+ .word ACE_ADC2_DataValid_IRQHandler\r
+ .word ACE_ADC0_CalDone_IRQHandler\r
+ .word ACE_ADC1_CalDone_IRQHandler\r
+ .word ACE_ADC2_CalDone_IRQHandler\r
+ .word ACE_ADC0_CalStart_IRQHandler\r
+ .word ACE_ADC1_CalStart_IRQHandler\r
+ .word ACE_ADC2_CalStart_IRQHandler\r
+ .word ACE_Comp0_Fall_IRQHandler\r
+ .word ACE_Comp1_Fall_IRQHandler\r
+ .word ACE_Comp2_Fall_IRQHandler\r
+ .word ACE_Comp3_Fall_IRQHandler\r
+ .word ACE_Comp4_Fall_IRQHandler\r
+ .word ACE_Comp5_Fall_IRQHandler\r
+ .word ACE_Comp6_Fall_IRQHandler\r
+ .word ACE_Comp7_Fall_IRQHandler\r
+ .word ACE_Comp8_Fall_IRQHandler\r
+ .word ACE_Comp9_Fall_IRQHandler\r
+ .word ACE_Comp10_Fall_IRQHandler\r
+ .word ACE_Comp11_Fall_IRQHandler\r
+ .word ACE_Comp0_Rise_IRQHandler\r
+ .word ACE_Comp1_Rise_IRQHandler\r
+ .word ACE_Comp2_Rise_IRQHandler\r
+ .word ACE_Comp3_Rise_IRQHandler\r
+ .word ACE_Comp4_Rise_IRQHandler\r
+ .word ACE_Comp5_Rise_IRQHandler\r
+ .word ACE_Comp6_Rise_IRQHandler\r
+ .word ACE_Comp7_Rise_IRQHandler\r
+ .word ACE_Comp8_Rise_IRQHandler\r
+ .word ACE_Comp9_Rise_IRQHandler\r
+ .word ACE_Comp10_Rise_IRQHandler\r
+ .word ACE_Comp11_Rise_IRQHandler\r
+ .word ACE_ADC0_FifoFull_IRQHandler\r
+ .word ACE_ADC0_FifoAFull_IRQHandler\r
+ .word ACE_ADC0_FifoEmpty_IRQHandler\r
+ .word ACE_ADC1_FifoFull_IRQHandler\r
+ .word ACE_ADC1_FifoAFull_IRQHandler\r
+ .word ACE_ADC1_FifoEmpty_IRQHandler\r
+ .word ACE_ADC2_FifoFull_IRQHandler\r
+ .word ACE_ADC2_FifoAFull_IRQHandler\r
+ .word ACE_ADC2_FifoEmpty_IRQHandler\r
+ .word ACE_PPE_Flag0_IRQHandler\r
+ .word ACE_PPE_Flag1_IRQHandler\r
+ .word ACE_PPE_Flag2_IRQHandler\r
+ .word ACE_PPE_Flag3_IRQHandler\r
+ .word ACE_PPE_Flag4_IRQHandler\r
+ .word ACE_PPE_Flag5_IRQHandler\r
+ .word ACE_PPE_Flag6_IRQHandler\r
+ .word ACE_PPE_Flag7_IRQHandler\r
+ .word ACE_PPE_Flag8_IRQHandler\r
+ .word ACE_PPE_Flag9_IRQHandler\r
+ .word ACE_PPE_Flag10_IRQHandler\r
+ .word ACE_PPE_Flag11_IRQHandler\r
+ .word ACE_PPE_Flag12_IRQHandler\r
+ .word ACE_PPE_Flag13_IRQHandler\r
+ .word ACE_PPE_Flag14_IRQHandler\r
+ .word ACE_PPE_Flag15_IRQHandler\r
+ .word ACE_PPE_Flag16_IRQHandler\r
+ .word ACE_PPE_Flag17_IRQHandler\r
+ .word ACE_PPE_Flag18_IRQHandler\r
+ .word ACE_PPE_Flag19_IRQHandler\r
+ .word ACE_PPE_Flag20_IRQHandler\r
+ .word ACE_PPE_Flag21_IRQHandler\r
+ .word ACE_PPE_Flag22_IRQHandler\r
+ .word ACE_PPE_Flag23_IRQHandler\r
+ .word ACE_PPE_Flag24_IRQHandler\r
+ .word ACE_PPE_Flag25_IRQHandler\r
+ .word ACE_PPE_Flag26_IRQHandler\r
+ .word ACE_PPE_Flag27_IRQHandler\r
+ .word ACE_PPE_Flag28_IRQHandler\r
+ .word ACE_PPE_Flag29_IRQHandler\r
+ .word ACE_PPE_Flag30_IRQHandler\r
+ .word ACE_PPE_Flag31_IRQHandler\r
+\r
+ \r
+/*==============================================================================\r
+ * Reset_Handler\r
+ */\r
+ .global Reset_Handler\r
+ .type Reset_Handler, %function\r
+Reset_Handler:\r
+_start:\r
+/*------------------------------------------------------------------------------ \r
+ * Call CMSIS system init function.\r
+ * This is not actually required for SmartFusioon as all low initialisations are\r
+ * done as part of the system boot.\r
+ */\r
+; ldr r0, =SystemInit\r
+; blx r0\r
+ \r
+/*------------------------------------------------------------------------------ \r
+ * Check if the executable is built for NVM LMA mirrored to VMA address.\r
+ * This is done for debugging executables running out of eNVM with SoftConsole.\r
+ * The .text section should not be copied in this case since both the LMA and\r
+ * VMA point at the eNVM despite the LMA and VMa having different values.\r
+ */\r
+ ldr r0, =__mirrored_nvm\r
+ cmp r0, #0\r
+ bne copy_data\r
+ \r
+/*------------------------------------------------------------------------------ \r
+ * Copy code section.\r
+ */\r
+ ldr r0, =__text_load\r
+ ldr r1, =__text_start\r
+ ldr r2, =_etext\r
+ cmp r0, r1\r
+ beq copy_data\r
+copy_code_loop:\r
+ cmp r1, r2\r
+ itt ne\r
+ ldrne r3, [r0], #4\r
+ strne r3, [r1], #4\r
+ bne copy_code_loop\r
+\r
+/*------------------------------------------------------------------------------ \r
+ * Copy data section.\r
+ */\r
+copy_data:\r
+ ldr r0, =__data_load\r
+ ldr r1, =__data_start\r
+ ldr r2, =_edata\r
+ cmp r0, r1\r
+ beq clear_bss\r
+copy_data_loop:\r
+ cmp r1, r2\r
+ itt ne\r
+ ldrne r3, [r0], #4\r
+ strne r3, [r1], #4\r
+ bne copy_data_loop\r
+ \r
+/*------------------------------------------------------------------------------ \r
+ * Clear .bss\r
+ */\r
+clear_bss:\r
+ ldr r0, =0\r
+ ldr r1, =__bss_start__\r
+ ldr r2, =__bss_end__\r
+clear_bss_loop:\r
+ cmp r1, r2\r
+ it ne\r
+ strne r0, [r1], #4\r
+ bne clear_bss_loop\r
+\r
+/*------------------------------------------------------------------------------ \r
+ * Call global constructors\r
+ */\r
+call_glob_ctor:\r
+ ldr r0, =__libc_init_array\r
+ add lr, pc, #3\r
+ bx r0\r
+\r
+/*------------------------------------------------------------------------------ \r
+ * branch to main.\r
+ */\r
+branch_to_main: \r
+ mov r0, #0 /* no arguments */\r
+ mov r1, #0 /* no argv either */\r
+ ldr pc, =main\r
+\r
+ExitLoop:\r
+ B ExitLoop\r
+\r
+/*==============================================================================\r
+ * NMI_Handler\r
+ */\r
+ .weak NMI_Handler\r
+ .type NMI_Handler, %function\r
+NMI_Handler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * HardFault_Handler\r
+ */\r
+ .weak HardFault_Handler\r
+ .type HardFault_Handler, %function\r
+HardFault_Handler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * MemManage_Handler\r
+ */\r
+ .weak MemManage_Handler\r
+ .type MemManage_Handler, %function\r
+MemManage_Handler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * BusFault_Handler\r
+ */\r
+ .weak BusFault_Handler\r
+ .type BusFault_Handler, %function\r
+BusFault_Handler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * UsageFault_Handler\r
+ */\r
+ .weak UsageFault_Handler\r
+ .type UsageFault_Handler, %function\r
+UsageFault_Handler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * SVC_Handler\r
+ */\r
+ .weak SVC_Handler\r
+ .type SVC_Handler, %function\r
+SVC_Handler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * DebugMon_Handler\r
+ */\r
+ .weak DebugMon_Handler\r
+ .type DebugMon_Handler, %function\r
+DebugMon_Handler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * PendSV_Handler\r
+ */\r
+ .weak PendSV_Handler\r
+ .type PendSV_Handler, %function\r
+PendSV_Handler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * SysTick_Handler\r
+ */\r
+ .weak SysTick_Handler\r
+ .type SysTick_Handler, %function\r
+SysTick_Handler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * WdogWakeup_IRQHandler\r
+ */\r
+ .weak WdogWakeup_IRQHandler\r
+ .type WdogWakeup_IRQHandler, %function\r
+WdogWakeup_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * BrownOut_1_5V_IRQHandler\r
+ */\r
+ .weak BrownOut_1_5V_IRQHandler\r
+ .type BrownOut_1_5V_IRQHandler, %function\r
+BrownOut_1_5V_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * BrownOut_3_3V_IRQHandler\r
+ */\r
+ .weak BrownOut_3_3V_IRQHandler\r
+ .type BrownOut_3_3V_IRQHandler, %function\r
+BrownOut_3_3V_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * RTC_Match_IRQHandler\r
+ */\r
+ .weak RTC_Match_IRQHandler\r
+ .type RTC_Match_IRQHandler, %function\r
+RTC_Match_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * RTCIF_Pub_IRQHandler\r
+ */\r
+ .weak RTCIF_Pub_IRQHandler\r
+ .type RTCIF_Pub_IRQHandler, %function\r
+RTCIF_Pub_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * EthernetMAC_IRQHandler\r
+ */\r
+ .weak EthernetMAC_IRQHandler\r
+ .type EthernetMAC_IRQHandler, %function\r
+EthernetMAC_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * IAP_IRQHandler\r
+ */\r
+ .weak IAP_IRQHandler\r
+ .type IAP_IRQHandler, %function\r
+IAP_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ENVM0_IRQHandler\r
+ */\r
+ .weak ENVM0_IRQHandler\r
+ .type ENVM0_IRQHandler, %function\r
+ENVM0_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ENVM1_IRQHandler\r
+ */\r
+ .weak ENVM1_IRQHandler\r
+ .type ENVM1_IRQHandler, %function\r
+ENVM1_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * DMA_IRQHandler\r
+ */\r
+ .weak DMA_IRQHandler\r
+ .type DMA_IRQHandler, %function\r
+DMA_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * UART0_IRQHandler\r
+ */\r
+ .weak UART0_IRQHandler\r
+ .type UART0_IRQHandler, %function\r
+UART0_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * UART1_IRQHandler\r
+ */\r
+ .weak UART1_IRQHandler\r
+ .type UART1_IRQHandler, %function\r
+UART1_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * SPI0_IRQHandler\r
+ */\r
+ .weak SPI0_IRQHandler\r
+ .type SPI0_IRQHandler, %function\r
+SPI0_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * SPI1_IRQHandler\r
+ */\r
+ .weak SPI1_IRQHandler\r
+ .type SPI1_IRQHandler, %function\r
+SPI1_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * I2C0_IRQHandler\r
+ */\r
+ .weak I2C0_IRQHandler\r
+ .type I2C0_IRQHandler, %function\r
+I2C0_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * I2C0_SMBAlert_IRQHandler\r
+ */\r
+ .weak I2C0_SMBAlert_IRQHandler\r
+ .type I2C0_SMBAlert_IRQHandler, %function\r
+I2C0_SMBAlert_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * I2C0_SMBus_IRQHandler\r
+ */\r
+ .weak I2C0_SMBus_IRQHandler\r
+ .type I2C0_SMBus_IRQHandler, %function\r
+I2C0_SMBus_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * I2C1_IRQHandler\r
+ */\r
+ .weak I2C1_IRQHandler\r
+ .type I2C1_IRQHandler, %function\r
+I2C1_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * I2C1_SMBAlert_IRQHandler\r
+ */\r
+ .weak I2C1_SMBAlert_IRQHandler\r
+ .type I2C1_SMBAlert_IRQHandler, %function\r
+I2C1_SMBAlert_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * I2C1_SMBus_IRQHandler\r
+ */\r
+ .weak I2C1_SMBus_IRQHandler\r
+ .type I2C1_SMBus_IRQHandler, %function\r
+I2C1_SMBus_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * Timer1_IRQHandler\r
+ */\r
+ .weak Timer1_IRQHandler\r
+ .type Timer1_IRQHandler, %function\r
+Timer1_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * Timer2_IRQHandler\r
+ */\r
+ .weak Timer2_IRQHandler\r
+ .type Timer2_IRQHandler, %function\r
+Timer2_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * PLL_Lock_IRQHandler\r
+ */\r
+ .weak PLL_Lock_IRQHandler\r
+ .type PLL_Lock_IRQHandler, %function\r
+PLL_Lock_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * PLL_LockLost_IRQHandler\r
+ */\r
+ .weak PLL_LockLost_IRQHandler\r
+ .type PLL_LockLost_IRQHandler, %function\r
+PLL_LockLost_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * CommError_IRQHandler\r
+ */\r
+ .weak CommError_IRQHandler\r
+ .type CommError_IRQHandler, %function\r
+CommError_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * Fabric_IRQHandler\r
+ */\r
+ .weak Fabric_IRQHandler\r
+ .type Fabric_IRQHandler, %function\r
+Fabric_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * GPIO0_IRQHandler\r
+ */\r
+ .weak GPIO0_IRQHandler\r
+ .type GPIO0_IRQHandler, %function\r
+GPIO0_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * GPIO1_IRQHandler\r
+ */\r
+ .weak GPIO1_IRQHandler\r
+ .type GPIO1_IRQHandler, %function\r
+GPIO1_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * GPIO2_IRQHandler\r
+ */\r
+ .weak GPIO2_IRQHandler\r
+ .type GPIO2_IRQHandler, %function\r
+GPIO2_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * GPIO3_IRQHandler\r
+ */\r
+ .weak GPIO3_IRQHandler\r
+ .type GPIO3_IRQHandler, %function\r
+GPIO3_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * GPIO4_IRQHandler\r
+ */\r
+ .weak GPIO4_IRQHandler\r
+ .type GPIO4_IRQHandler, %function\r
+GPIO4_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * GPIO5_IRQHandler\r
+ */\r
+ .weak GPIO5_IRQHandler\r
+ .type GPIO5_IRQHandler, %function\r
+GPIO5_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * GPIO6_IRQHandler\r
+ */\r
+ .weak GPIO6_IRQHandler\r
+ .type GPIO6_IRQHandler, %function\r
+GPIO6_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * GPIO7_IRQHandler\r
+ */\r
+ .weak GPIO7_IRQHandler\r
+ .type GPIO7_IRQHandler, %function\r
+GPIO7_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * GPIO8_IRQHandler\r
+ */\r
+ .weak GPIO8_IRQHandler\r
+ .type GPIO8_IRQHandler, %function\r
+GPIO8_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * GPIO9_IRQHandler\r
+ */\r
+ .weak GPIO9_IRQHandler\r
+ .type GPIO9_IRQHandler, %function\r
+GPIO9_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * GPIO10_IRQHandler\r
+ */\r
+ .weak GPIO10_IRQHandler\r
+ .type GPIO10_IRQHandler, %function\r
+GPIO10_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * GPIO11_IRQHandler\r
+ */\r
+ .weak GPIO11_IRQHandler\r
+ .type GPIO11_IRQHandler, %function\r
+GPIO11_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * GPIO12_IRQHandler\r
+ */\r
+ .weak GPIO12_IRQHandler\r
+ .type GPIO12_IRQHandler, %function\r
+GPIO12_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * GPIO13_IRQHandler\r
+ */\r
+ .weak GPIO13_IRQHandler\r
+ .type GPIO13_IRQHandler, %function\r
+GPIO13_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * GPIO14_IRQHandler\r
+ */\r
+ .weak GPIO14_IRQHandler\r
+ .type GPIO14_IRQHandler, %function\r
+GPIO14_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * GPIO15_IRQHandler\r
+ */\r
+ .weak GPIO15_IRQHandler\r
+ .type GPIO15_IRQHandler, %function\r
+GPIO15_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * GPIO16_IRQHandler\r
+ */\r
+ .weak GPIO16_IRQHandler\r
+ .type GPIO16_IRQHandler, %function\r
+GPIO16_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * GPIO17_IRQHandler\r
+ */\r
+ .weak GPIO17_IRQHandler\r
+ .type GPIO17_IRQHandler, %function\r
+GPIO17_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * GPIO18_IRQHandler\r
+ */\r
+ .weak GPIO18_IRQHandler\r
+ .type GPIO18_IRQHandler, %function\r
+GPIO18_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * GPIO19_IRQHandler\r
+ */\r
+ .weak GPIO19_IRQHandler\r
+ .type GPIO19_IRQHandler, %function\r
+GPIO19_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * GPIO20_IRQHandler\r
+ */\r
+ .weak GPIO20_IRQHandler\r
+ .type GPIO20_IRQHandler, %function\r
+GPIO20_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * GPIO21_IRQHandler\r
+ */\r
+ .weak GPIO21_IRQHandler\r
+ .type GPIO21_IRQHandler, %function\r
+GPIO21_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * GPIO22_IRQHandler\r
+ */\r
+ .weak GPIO22_IRQHandler\r
+ .type GPIO22_IRQHandler, %function\r
+GPIO22_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * GPIO23_IRQHandler\r
+ */\r
+ .weak GPIO23_IRQHandler\r
+ .type GPIO23_IRQHandler, %function\r
+GPIO23_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * GPIO24_IRQHandler\r
+ */\r
+ .weak GPIO24_IRQHandler\r
+ .type GPIO24_IRQHandler, %function\r
+GPIO24_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * GPIO25_IRQHandler\r
+ */\r
+ .weak GPIO25_IRQHandler\r
+ .type GPIO25_IRQHandler, %function\r
+GPIO25_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * GPIO26_IRQHandler\r
+ */\r
+ .weak GPIO26_IRQHandler\r
+ .type GPIO26_IRQHandler, %function\r
+GPIO26_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * GPIO27_IRQHandler\r
+ */\r
+ .weak GPIO27_IRQHandler\r
+ .type GPIO27_IRQHandler, %function\r
+GPIO27_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * GPIO28_IRQHandler\r
+ */\r
+ .weak GPIO28_IRQHandler\r
+ .type GPIO28_IRQHandler, %function\r
+GPIO28_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * GPIO29_IRQHandler\r
+ */\r
+ .weak GPIO29_IRQHandler\r
+ .type GPIO29_IRQHandler, %function\r
+GPIO29_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * GPIO30_IRQHandler\r
+ */\r
+ .weak GPIO30_IRQHandler\r
+ .type GPIO30_IRQHandler, %function\r
+GPIO30_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * GPIO31_IRQHandler\r
+ */\r
+ .weak GPIO31_IRQHandler\r
+ .type GPIO31_IRQHandler, %function\r
+GPIO31_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_PC0_Flag0_IRQHandler\r
+ */\r
+ .weak ACE_PC0_Flag0_IRQHandler\r
+ .type ACE_PC0_Flag0_IRQHandler, %function\r
+ACE_PC0_Flag0_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_PC0_Flag1_IRQHandler\r
+ */\r
+ .weak ACE_PC0_Flag1_IRQHandler\r
+ .type ACE_PC0_Flag1_IRQHandler, %function\r
+ACE_PC0_Flag1_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_PC0_Flag2_IRQHandler\r
+ */\r
+ .weak ACE_PC0_Flag2_IRQHandler\r
+ .type ACE_PC0_Flag2_IRQHandler, %function\r
+ACE_PC0_Flag2_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_PC0_Flag3_IRQHandler\r
+ */\r
+ .weak ACE_PC0_Flag3_IRQHandler\r
+ .type ACE_PC0_Flag3_IRQHandler, %function\r
+ACE_PC0_Flag3_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_PC1_Flag0_IRQHandler\r
+ */\r
+ .weak ACE_PC1_Flag0_IRQHandler\r
+ .type ACE_PC1_Flag0_IRQHandler, %function\r
+ACE_PC1_Flag0_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_PC1_Flag1_IRQHandler\r
+ */\r
+ .weak ACE_PC1_Flag1_IRQHandler\r
+ .type ACE_PC1_Flag1_IRQHandler, %function\r
+ACE_PC1_Flag1_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_PC1_Flag2_IRQHandler\r
+ */\r
+ .weak ACE_PC1_Flag2_IRQHandler\r
+ .type ACE_PC1_Flag2_IRQHandler, %function\r
+ACE_PC1_Flag2_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_PC1_Flag3_IRQHandler\r
+ */\r
+ .weak ACE_PC1_Flag3_IRQHandler\r
+ .type ACE_PC1_Flag3_IRQHandler, %function\r
+ACE_PC1_Flag3_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_PC2_Flag0_IRQHandler\r
+ */\r
+ .weak ACE_PC2_Flag0_IRQHandler\r
+ .type ACE_PC2_Flag0_IRQHandler, %function\r
+ACE_PC2_Flag0_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_PC2_Flag1_IRQHandler\r
+ */\r
+ .weak ACE_PC2_Flag1_IRQHandler\r
+ .type ACE_PC2_Flag1_IRQHandler, %function\r
+ACE_PC2_Flag1_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_PC2_Flag2_IRQHandler\r
+ */\r
+ .weak ACE_PC2_Flag2_IRQHandler\r
+ .type ACE_PC2_Flag2_IRQHandler, %function\r
+ACE_PC2_Flag2_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_PC2_Flag3_IRQHandler\r
+ */\r
+ .weak ACE_PC2_Flag3_IRQHandler\r
+ .type ACE_PC2_Flag3_IRQHandler, %function\r
+ACE_PC2_Flag3_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_ADC0_DataValid_IRQHandler\r
+ */\r
+ .weak ACE_ADC0_DataValid_IRQHandler\r
+ .type ACE_ADC0_DataValid_IRQHandler, %function\r
+ACE_ADC0_DataValid_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_ADC1_DataValid_IRQHandler\r
+ */\r
+ .weak ACE_ADC1_DataValid_IRQHandler\r
+ .type ACE_ADC1_DataValid_IRQHandler, %function\r
+ACE_ADC1_DataValid_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_ADC2_DataValid_IRQHandler\r
+ */\r
+ .weak ACE_ADC2_DataValid_IRQHandler\r
+ .type ACE_ADC2_DataValid_IRQHandler, %function\r
+ACE_ADC2_DataValid_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_ADC0_CalDone_IRQHandler\r
+ */\r
+ .weak ACE_ADC0_CalDone_IRQHandler\r
+ .type ACE_ADC0_CalDone_IRQHandler, %function\r
+ACE_ADC0_CalDone_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_ADC1_CalDone_IRQHandler\r
+ */\r
+ .weak ACE_ADC1_CalDone_IRQHandler\r
+ .type ACE_ADC1_CalDone_IRQHandler, %function\r
+ACE_ADC1_CalDone_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_ADC2_CalDone_IRQHandler\r
+ */\r
+ .weak ACE_ADC2_CalDone_IRQHandler\r
+ .type ACE_ADC2_CalDone_IRQHandler, %function\r
+ACE_ADC2_CalDone_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_ADC0_CalStart_IRQHandler\r
+ */\r
+ .weak ACE_ADC0_CalStart_IRQHandler\r
+ .type ACE_ADC0_CalStart_IRQHandler, %function\r
+ACE_ADC0_CalStart_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_ADC1_CalStart_IRQHandler\r
+ */\r
+ .weak ACE_ADC1_CalStart_IRQHandler\r
+ .type ACE_ADC1_CalStart_IRQHandler, %function\r
+ACE_ADC1_CalStart_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_ADC2_CalStart_IRQHandler\r
+ */\r
+ .weak ACE_ADC2_CalStart_IRQHandler\r
+ .type ACE_ADC2_CalStart_IRQHandler, %function\r
+ACE_ADC2_CalStart_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_Comp0_Fall_IRQHandler\r
+ */\r
+ .weak ACE_Comp0_Fall_IRQHandler\r
+ .type ACE_Comp0_Fall_IRQHandler, %function\r
+ACE_Comp0_Fall_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_Comp1_Fall_IRQHandler\r
+ */\r
+ .weak ACE_Comp1_Fall_IRQHandler\r
+ .type ACE_Comp1_Fall_IRQHandler, %function\r
+ACE_Comp1_Fall_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_Comp2_Fall_IRQHandler\r
+ */\r
+ .weak ACE_Comp2_Fall_IRQHandler\r
+ .type ACE_Comp2_Fall_IRQHandler, %function\r
+ACE_Comp2_Fall_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_Comp3_Fall_IRQHandler\r
+ */\r
+ .weak ACE_Comp3_Fall_IRQHandler\r
+ .type ACE_Comp3_Fall_IRQHandler, %function\r
+ACE_Comp3_Fall_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_Comp4_Fall_IRQHandler\r
+ */\r
+ .weak ACE_Comp4_Fall_IRQHandler\r
+ .type ACE_Comp4_Fall_IRQHandler, %function\r
+ACE_Comp4_Fall_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_Comp5_Fall_IRQHandler\r
+ */\r
+ .weak ACE_Comp5_Fall_IRQHandler\r
+ .type ACE_Comp5_Fall_IRQHandler, %function\r
+ACE_Comp5_Fall_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_Comp6_Fall_IRQHandler\r
+ */\r
+ .weak ACE_Comp6_Fall_IRQHandler\r
+ .type ACE_Comp6_Fall_IRQHandler, %function\r
+ACE_Comp6_Fall_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_Comp7_Fall_IRQHandler\r
+ */\r
+ .weak ACE_Comp7_Fall_IRQHandler\r
+ .type ACE_Comp7_Fall_IRQHandler, %function\r
+ACE_Comp7_Fall_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_Comp8_Fall_IRQHandler\r
+ */\r
+ .weak ACE_Comp8_Fall_IRQHandler\r
+ .type ACE_Comp8_Fall_IRQHandler, %function\r
+ACE_Comp8_Fall_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_Comp9_Fall_IRQHandler\r
+ */\r
+ .weak ACE_Comp9_Fall_IRQHandler\r
+ .type ACE_Comp9_Fall_IRQHandler, %function\r
+ACE_Comp9_Fall_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_Comp10_Fall_IRQHandler\r
+ */\r
+ .weak ACE_Comp10_Fall_IRQHandler\r
+ .type ACE_Comp10_Fall_IRQHandler, %function\r
+ACE_Comp10_Fall_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_Comp11_Fall_IRQHandler\r
+ */\r
+ .weak ACE_Comp11_Fall_IRQHandler\r
+ .type ACE_Comp11_Fall_IRQHandler, %function\r
+ACE_Comp11_Fall_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_Comp0_Rise_IRQHandler\r
+ */\r
+ .weak ACE_Comp0_Rise_IRQHandler\r
+ .type ACE_Comp0_Rise_IRQHandler, %function\r
+ACE_Comp0_Rise_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_Comp1_Rise_IRQHandler\r
+ */\r
+ .weak ACE_Comp1_Rise_IRQHandler\r
+ .type ACE_Comp1_Rise_IRQHandler, %function\r
+ACE_Comp1_Rise_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_Comp2_Rise_IRQHandler\r
+ */\r
+ .weak ACE_Comp2_Rise_IRQHandler\r
+ .type ACE_Comp2_Rise_IRQHandler, %function\r
+ACE_Comp2_Rise_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_Comp3_Rise_IRQHandler\r
+ */\r
+ .weak ACE_Comp3_Rise_IRQHandler\r
+ .type ACE_Comp3_Rise_IRQHandler, %function\r
+ACE_Comp3_Rise_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_Comp4_Rise_IRQHandler\r
+ */\r
+ .weak ACE_Comp4_Rise_IRQHandler\r
+ .type ACE_Comp4_Rise_IRQHandler, %function\r
+ACE_Comp4_Rise_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_Comp5_Rise_IRQHandler\r
+ */\r
+ .weak ACE_Comp5_Rise_IRQHandler\r
+ .type ACE_Comp5_Rise_IRQHandler, %function\r
+ACE_Comp5_Rise_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_Comp6_Rise_IRQHandler\r
+ */\r
+ .weak ACE_Comp6_Rise_IRQHandler\r
+ .type ACE_Comp6_Rise_IRQHandler, %function\r
+ACE_Comp6_Rise_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_Comp7_Rise_IRQHandler\r
+ */\r
+ .weak ACE_Comp7_Rise_IRQHandler\r
+ .type ACE_Comp7_Rise_IRQHandler, %function\r
+ACE_Comp7_Rise_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_Comp8_Rise_IRQHandler\r
+ */\r
+ .weak ACE_Comp8_Rise_IRQHandler\r
+ .type ACE_Comp8_Rise_IRQHandler, %function\r
+ACE_Comp8_Rise_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_Comp9_Rise_IRQHandler\r
+ */\r
+ .weak ACE_Comp9_Rise_IRQHandler\r
+ .type ACE_Comp9_Rise_IRQHandler, %function\r
+ACE_Comp9_Rise_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_Comp10_Rise_IRQHandler\r
+ */\r
+ .weak ACE_Comp10_Rise_IRQHandler\r
+ .type ACE_Comp10_Rise_IRQHandler, %function\r
+ACE_Comp10_Rise_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_Comp11_Rise_IRQHandler\r
+ */\r
+ .weak ACE_Comp11_Rise_IRQHandler\r
+ .type ACE_Comp11_Rise_IRQHandler, %function\r
+ACE_Comp11_Rise_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_ADC0_FifoFull_IRQHandler\r
+ */\r
+ .weak ACE_ADC0_FifoFull_IRQHandler\r
+ .type ACE_ADC0_FifoFull_IRQHandler, %function\r
+ACE_ADC0_FifoFull_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_ADC0_FifoAFull_IRQHandler\r
+ */\r
+ .weak ACE_ADC0_FifoAFull_IRQHandler\r
+ .type ACE_ADC0_FifoAFull_IRQHandler, %function\r
+ACE_ADC0_FifoAFull_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_ADC0_FifoEmpty_IRQHandler\r
+ */\r
+ .weak ACE_ADC0_FifoEmpty_IRQHandler\r
+ .type ACE_ADC0_FifoEmpty_IRQHandler, %function\r
+ACE_ADC0_FifoEmpty_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_ADC1_FifoFull_IRQHandler\r
+ */\r
+ .weak ACE_ADC1_FifoFull_IRQHandler\r
+ .type ACE_ADC1_FifoFull_IRQHandler, %function\r
+ACE_ADC1_FifoFull_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_ADC1_FifoAFull_IRQHandler\r
+ */\r
+ .weak ACE_ADC1_FifoAFull_IRQHandler\r
+ .type ACE_ADC1_FifoAFull_IRQHandler, %function\r
+ACE_ADC1_FifoAFull_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_ADC1_FifoEmpty_IRQHandler\r
+ */\r
+ .weak ACE_ADC1_FifoEmpty_IRQHandler\r
+ .type ACE_ADC1_FifoEmpty_IRQHandler, %function\r
+ACE_ADC1_FifoEmpty_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_ADC2_FifoFull_IRQHandler\r
+ */\r
+ .weak ACE_ADC2_FifoFull_IRQHandler\r
+ .type ACE_ADC2_FifoFull_IRQHandler, %function\r
+ACE_ADC2_FifoFull_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_ADC2_FifoAFull_IRQHandler\r
+ */\r
+ .weak ACE_ADC2_FifoAFull_IRQHandler\r
+ .type ACE_ADC2_FifoAFull_IRQHandler, %function\r
+ACE_ADC2_FifoAFull_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_ADC2_FifoEmpty_IRQHandler\r
+ */\r
+ .weak ACE_ADC2_FifoEmpty_IRQHandler\r
+ .type ACE_ADC2_FifoEmpty_IRQHandler, %function\r
+ACE_ADC2_FifoEmpty_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_PPE_Flag0_IRQHandler\r
+ */\r
+ .weak ACE_PPE_Flag0_IRQHandler\r
+ .type ACE_PPE_Flag0_IRQHandler, %function\r
+ACE_PPE_Flag0_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_PPE_Flag1_IRQHandler\r
+ */\r
+ .weak ACE_PPE_Flag1_IRQHandler\r
+ .type ACE_PPE_Flag1_IRQHandler, %function\r
+ACE_PPE_Flag1_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_PPE_Flag2_IRQHandler\r
+ */\r
+ .weak ACE_PPE_Flag2_IRQHandler\r
+ .type ACE_PPE_Flag2_IRQHandler, %function\r
+ACE_PPE_Flag2_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_PPE_Flag3_IRQHandler\r
+ */\r
+ .weak ACE_PPE_Flag3_IRQHandler\r
+ .type ACE_PPE_Flag3_IRQHandler, %function\r
+ACE_PPE_Flag3_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_PPE_Flag4_IRQHandler\r
+ */\r
+ .weak ACE_PPE_Flag4_IRQHandler\r
+ .type ACE_PPE_Flag4_IRQHandler, %function\r
+ACE_PPE_Flag4_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_PPE_Flag5_IRQHandler\r
+ */\r
+ .weak ACE_PPE_Flag5_IRQHandler\r
+ .type ACE_PPE_Flag5_IRQHandler, %function\r
+ACE_PPE_Flag5_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_PPE_Flag6_IRQHandler\r
+ */\r
+ .weak ACE_PPE_Flag6_IRQHandler\r
+ .type ACE_PPE_Flag6_IRQHandler, %function\r
+ACE_PPE_Flag6_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_PPE_Flag7_IRQHandler\r
+ */\r
+ .weak ACE_PPE_Flag7_IRQHandler\r
+ .type ACE_PPE_Flag7_IRQHandler, %function\r
+ACE_PPE_Flag7_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_PPE_Flag8_IRQHandler\r
+ */\r
+ .weak ACE_PPE_Flag8_IRQHandler\r
+ .type ACE_PPE_Flag8_IRQHandler, %function\r
+ACE_PPE_Flag8_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_PPE_Flag9_IRQHandler\r
+ */\r
+ .weak ACE_PPE_Flag9_IRQHandler\r
+ .type ACE_PPE_Flag9_IRQHandler, %function\r
+ACE_PPE_Flag9_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_PPE_Flag10_IRQHandler\r
+ */\r
+ .weak ACE_PPE_Flag10_IRQHandler\r
+ .type ACE_PPE_Flag10_IRQHandler, %function\r
+ACE_PPE_Flag10_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_PPE_Flag11_IRQHandler\r
+ */\r
+ .weak ACE_PPE_Flag11_IRQHandler\r
+ .type ACE_PPE_Flag11_IRQHandler, %function\r
+ACE_PPE_Flag11_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_PPE_Flag12_IRQHandler\r
+ */\r
+ .weak ACE_PPE_Flag12_IRQHandler\r
+ .type ACE_PPE_Flag12_IRQHandler, %function\r
+ACE_PPE_Flag12_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_PPE_Flag13_IRQHandler\r
+ */\r
+ .weak ACE_PPE_Flag13_IRQHandler\r
+ .type ACE_PPE_Flag13_IRQHandler, %function\r
+ACE_PPE_Flag13_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_PPE_Flag14_IRQHandler\r
+ */\r
+ .weak ACE_PPE_Flag14_IRQHandler\r
+ .type ACE_PPE_Flag14_IRQHandler, %function\r
+ACE_PPE_Flag14_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_PPE_Flag15_IRQHandler\r
+ */\r
+ .weak ACE_PPE_Flag15_IRQHandler\r
+ .type ACE_PPE_Flag15_IRQHandler, %function\r
+ACE_PPE_Flag15_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_PPE_Flag16_IRQHandler\r
+ */\r
+ .weak ACE_PPE_Flag16_IRQHandler\r
+ .type ACE_PPE_Flag16_IRQHandler, %function\r
+ACE_PPE_Flag16_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_PPE_Flag17_IRQHandler\r
+ */\r
+ .weak ACE_PPE_Flag17_IRQHandler\r
+ .type ACE_PPE_Flag17_IRQHandler, %function\r
+ACE_PPE_Flag17_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_PPE_Flag18_IRQHandler\r
+ */\r
+ .weak ACE_PPE_Flag18_IRQHandler\r
+ .type ACE_PPE_Flag18_IRQHandler, %function\r
+ACE_PPE_Flag18_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_PPE_Flag19_IRQHandler\r
+ */\r
+ .weak ACE_PPE_Flag19_IRQHandler\r
+ .type ACE_PPE_Flag19_IRQHandler, %function\r
+ACE_PPE_Flag19_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_PPE_Flag20_IRQHandler\r
+ */\r
+ .weak ACE_PPE_Flag20_IRQHandler\r
+ .type ACE_PPE_Flag20_IRQHandler, %function\r
+ACE_PPE_Flag20_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_PPE_Flag21_IRQHandler\r
+ */\r
+ .weak ACE_PPE_Flag21_IRQHandler\r
+ .type ACE_PPE_Flag21_IRQHandler, %function\r
+ACE_PPE_Flag21_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_PPE_Flag22_IRQHandler\r
+ */\r
+ .weak ACE_PPE_Flag22_IRQHandler\r
+ .type ACE_PPE_Flag22_IRQHandler, %function\r
+ACE_PPE_Flag22_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_PPE_Flag23_IRQHandler\r
+ */\r
+ .weak ACE_PPE_Flag23_IRQHandler\r
+ .type ACE_PPE_Flag23_IRQHandler, %function\r
+ACE_PPE_Flag23_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_PPE_Flag24_IRQHandler\r
+ */\r
+ .weak ACE_PPE_Flag24_IRQHandler\r
+ .type ACE_PPE_Flag24_IRQHandler, %function\r
+ACE_PPE_Flag24_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_PPE_Flag25_IRQHandler\r
+ */\r
+ .weak ACE_PPE_Flag25_IRQHandler\r
+ .type ACE_PPE_Flag25_IRQHandler, %function\r
+ACE_PPE_Flag25_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_PPE_Flag26_IRQHandler\r
+ */\r
+ .weak ACE_PPE_Flag26_IRQHandler\r
+ .type ACE_PPE_Flag26_IRQHandler, %function\r
+ACE_PPE_Flag26_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_PPE_Flag27_IRQHandler\r
+ */\r
+ .weak ACE_PPE_Flag27_IRQHandler\r
+ .type ACE_PPE_Flag27_IRQHandler, %function\r
+ACE_PPE_Flag27_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_PPE_Flag28_IRQHandler\r
+ */\r
+ .weak ACE_PPE_Flag28_IRQHandler\r
+ .type ACE_PPE_Flag28_IRQHandler, %function\r
+ACE_PPE_Flag28_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_PPE_Flag29_IRQHandler\r
+ */\r
+ .weak ACE_PPE_Flag29_IRQHandler\r
+ .type ACE_PPE_Flag29_IRQHandler, %function\r
+ACE_PPE_Flag29_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_PPE_Flag30_IRQHandler\r
+ */\r
+ .weak ACE_PPE_Flag30_IRQHandler\r
+ .type ACE_PPE_Flag30_IRQHandler, %function\r
+ACE_PPE_Flag30_IRQHandler:\r
+ B .\r
+\r
+/*==============================================================================\r
+ * ACE_PPE_Flag31_IRQHandler\r
+ */\r
+ .weak ACE_PPE_Flag31_IRQHandler\r
+ .type ACE_PPE_Flag31_IRQHandler, %function\r
+ACE_PPE_Flag31_IRQHandler:\r
+ B .\r
+\r
+.end\r
--- /dev/null
+/*******************************************************************************\r
+ * (c) Copyright 2009 Actel Corporation. All rights reserved.\r
+ * \r
+ * SmartFusion A2FxxxM3 CMSIS system initialization.\r
+ *\r
+ * SVN $Revision: 2069 $\r
+ * SVN $Date: 2010-01-28 00:23:48 +0000 (Thu, 28 Jan 2010) $\r
+ */\r
+#include "a2fxxxm3.h"\r
+#include "mss_assert.h"\r
+\r
+/* System frequency (FCLK) coming out of reset is 25MHz. */\r
+#define RESET_SYSCLCK_FREQ 25000000uL\r
+\r
+/*\r
+ * SmartFusion Microcontroller Subsystem FLCK frequency.\r
+ * The value of SMARTFUSION_FCLK_FREQ is used to report the system's clock\r
+ * frequency in system's which either do not use the Actel System Boot or\r
+ * a version of the Actel System Boot older than 1.3.1. In eitehr of these cases\r
+ * SMARTFUSION_FCLK_FREQ should be defined in the projects settings to reflect\r
+ * the FCLK frequency selected in the Libero MSS configurator.\r
+ * Systems using the Actel System Boot version 1.3.1 or later do not require this\r
+ * define since the system's frequency is retrieved from eNVM spare pages where\r
+ * the MSS Configurator stored the frequency selected during hardware design/configuration.\r
+ */\r
+#ifdef SMARTFUSION_FCLK_FREQ\r
+#define SMARTFUSION_FCLK_FREQ_DEFINED 1\r
+#else\r
+#define SMARTFUSION_FCLK_FREQ_DEFINED 0\r
+#define SMARTFUSION_FCLK_FREQ RESET_SYSCLCK_FREQ\r
+#endif\r
+\r
+/* Divider values for APB0, APB1 and ACE clocks. */\r
+#define RESET_PCLK0_DIV 4uL\r
+#define RESET_PCLK1_DIV 4uL\r
+#define RESET_ACE_DIV 4uL\r
+#define RESET_FPGA_CLK_DIV 4uL\r
+\r
+/* System register clock control mask and shift for PCLK dividers. */\r
+#define PCLK_DIV_MASK 0x00000003uL\r
+#define PCLK0_DIV_SHIFT 2uL\r
+#define PCLK1_DIV_SHIFT 4uL\r
+#define ACE_DIV_SHIFT 6uL\r
+\r
+/* System register MSS_CCC_DIV_CR mask and shift for GLB (FPGA fabric clock). */\r
+#define OBDIV_SHIFT 8uL\r
+#define OBDIV_MASK 0x0000001FuL\r
+#define OBDIVHALF_SHIFT 13uL\r
+#define OBDIVHALF_MASK 0x00000001uL\r
+\r
+/*\r
+ * Actel system boot version defines used to extract the system clock from eNVM\r
+ * spare pages.\r
+ * These defines allow detecting the presence of Actel system boot in eNVM spare\r
+ * pages and the version of that system boot executable and associated\r
+ * configuration data.\r
+ */\r
+#define SYSBOOT_KEY_ADDR (uint32_t *)0x6008081C\r
+#define SYSBOOT_KEY_VALUE 0x4C544341uL\r
+#define SYSBOOT_VERSION_ADDR (uint32_t *)0x60080840\r
+#define SYSBOOT_1_3_FCLK_ADDR (uint32_t *)0x6008162C\r
+#define SYSBOOT_2_x_FCLK_ADDR (uint32_t *)0x60081EAC\r
+\r
+/*\r
+ * The system boot version is stored in the least significant 24 bits of a word.\r
+ * The FCLK is stored in eNVM from version 1.3.1 of the system boot. We expect\r
+ * that the major version number of the system boot version will change if the\r
+ * system boot configuration data layout needs to change. \r
+ */\r
+#define SYSBOOT_VERSION_MASK 0x00FFFFFFuL\r
+#define MIN_SYSBOOT_VERSION 0x00010301uL\r
+#define SYSBOOT_VERSION_2_X 0x00020000uL\r
+#define MAX_SYSBOOT_VERSION 0x00030000uL\r
+\r
+/* Standard CMSIS global variables. */\r
+uint32_t SystemFrequency = SMARTFUSION_FCLK_FREQ; /*!< System Clock Frequency (Core Clock) */\r
+uint32_t SystemCoreClock = SMARTFUSION_FCLK_FREQ; /*!< System Clock Frequency (Core Clock) */\r
+\r
+/* SmartFusion specific clocks. */\r
+uint32_t g_FrequencyPCLK0 = (SMARTFUSION_FCLK_FREQ / RESET_PCLK0_DIV); /*!< Clock frequency of APB bus 0. */ \r
+uint32_t g_FrequencyPCLK1 = (SMARTFUSION_FCLK_FREQ / RESET_PCLK1_DIV); /*!< Clock frequency of APB bus 1. */\r
+uint32_t g_FrequencyACE = (SMARTFUSION_FCLK_FREQ / RESET_ACE_DIV); /*!< Clock frequency of Analog Compute Engine. */\r
+uint32_t g_FrequencyFPGA = (SMARTFUSION_FCLK_FREQ / RESET_FPGA_CLK_DIV); /*!< Clock frequecny of FPGA fabric */\r
+\r
+/* Local functions */\r
+static uint32_t GetSystemClock( void );\r
+\r
+/***************************************************************************//**\r
+ * See system_a2fm3fxxx.h for details.\r
+ */\r
+void SystemInit(void)\r
+{\r
+}\r
+\r
+/***************************************************************************//**\r
+ *\r
+ */\r
+void SystemCoreClockUpdate (void)\r
+{\r
+ uint32_t PclkDiv0;\r
+ uint32_t PclkDiv1;\r
+ uint32_t AceDiv;\r
+ uint32_t FabDiv;\r
+\r
+ const uint32_t pclk_div_lut[4] = { 1uL, 2uL, 4uL, 1uL };\r
+\r
+ /* Read PCLK dividers from system registers. Multiply the value read from\r
+ * system register by two to get actual divider value. */\r
+ PclkDiv0 = pclk_div_lut[((SYSREG->MSS_CLK_CR >> PCLK0_DIV_SHIFT) & PCLK_DIV_MASK)];\r
+ PclkDiv1 = pclk_div_lut[((SYSREG->MSS_CLK_CR >> PCLK1_DIV_SHIFT) & PCLK_DIV_MASK)];\r
+ AceDiv = pclk_div_lut[((SYSREG->MSS_CLK_CR >> ACE_DIV_SHIFT) & PCLK_DIV_MASK)];\r
+ {\r
+ /* Compute the FPGA fabric frequency divider. */\r
+ uint32_t obdiv;\r
+ uint32_t obdivhalf;\r
+ \r
+ obdiv = (SYSREG->MSS_CCC_DIV_CR >> OBDIV_SHIFT) & OBDIV_MASK;\r
+ obdivhalf = (SYSREG->MSS_CCC_DIV_CR >> OBDIVHALF_SHIFT) & OBDIVHALF_MASK;\r
+ FabDiv = obdiv + 1uL;\r
+ if ( obdivhalf != 0uL )\r
+ {\r
+ FabDiv = FabDiv * 2uL;\r
+ }\r
+ }\r
+ \r
+ /* Retrieve FCLK from eNVM spare pages if Actel system boot programmed as part of the system. */\r
+ \r
+ /* Read system clock from eNVM spare pages. */\r
+ SystemCoreClock = GetSystemClock();\r
+ g_FrequencyPCLK0 = SystemCoreClock / PclkDiv0;\r
+ g_FrequencyPCLK1 = SystemCoreClock / PclkDiv1;\r
+ g_FrequencyACE = SystemCoreClock / AceDiv;\r
+ g_FrequencyFPGA = SystemCoreClock / FabDiv;\r
+ \r
+ /* Keep SystemFrequency as well as SystemCoreClock for legacy reasons. */\r
+ SystemFrequency = SystemCoreClock;\r
+}\r
+\r
+/***************************************************************************//**\r
+ * Retrieve the system clock frequency from eNVM spare page if available.\r
+ * Returns the frequency defined through SMARTFUSION_FCLK_FREQ if FCLK cannot be\r
+ * retrieved from eNVM spare pages.\r
+ * The FCLK frequency value selected in the MSS Configurator software tool is\r
+ * stored in eNVM spare pages as part of the Actel system boot configuration data.\r
+ */\r
+uint32_t GetSystemClock( void )\r
+{\r
+ uint32_t fclk = 0uL;\r
+ \r
+ uint32_t * p_sysboot_key = SYSBOOT_KEY_ADDR;\r
+ \r
+ if ( SYSBOOT_KEY_VALUE == *p_sysboot_key )\r
+ {\r
+ /* Actel system boot programmed, check if it has the FCLK value stored. */\r
+ uint32_t *p_sysboot_version = SYSBOOT_VERSION_ADDR;\r
+ uint32_t sysboot_version = *p_sysboot_version;\r
+ \r
+ sysboot_version &= SYSBOOT_VERSION_MASK;\r
+ \r
+ if ( sysboot_version >= MIN_SYSBOOT_VERSION )\r
+ {\r
+ /* Handle change of eNVM location of FCLK between 1.3.x and 2.x.x versions of the system boot. */\r
+ if ( sysboot_version < SYSBOOT_VERSION_2_X )\r
+ {\r
+ /* Read FCLK value from MSS configurator generated configuration\r
+ * data stored in eNVM spare pages as part of system boot version 1.3.x\r
+ * configuration tables. */\r
+ uint32_t *p_fclk = SYSBOOT_1_3_FCLK_ADDR;\r
+ fclk = *p_fclk;\r
+ }\r
+ else if ( sysboot_version < MAX_SYSBOOT_VERSION )\r
+ {\r
+ /* Read FCLK value from MSS configurator generated configuration\r
+ * data stored in eNVM spare pages as part of system boot version 2.x.x\r
+ * configuration tables. */\r
+ uint32_t *p_fclk = SYSBOOT_2_x_FCLK_ADDR;\r
+ fclk = *p_fclk;\r
+ }\r
+ else\r
+ {\r
+ fclk = 0uL;\r
+ }\r
+ }\r
+ }\r
+ \r
+ if ( 0uL == fclk )\r
+ {\r
+ /* \r
+ * Could not retrieve FCLK from system boot configuration data. Fall back\r
+ * to using SMARTFUSION_FCLK_FREQ which must then be defined as part of\r
+ * project settings.\r
+ */\r
+ ASSERT( SMARTFUSION_FCLK_FREQ_DEFINED );\r
+ fclk = SMARTFUSION_FCLK_FREQ;\r
+ }\r
+ \r
+ return fclk;\r
+}\r
+\r
--- /dev/null
+/*******************************************************************************\r
+ * (c) Copyright 2009 Actel Corporation. All rights reserved.\r
+ * \r
+ * SmartFusion A2FxxxM3 CMSIS system initialization.\r
+ *\r
+ * SVN $Revision: 2064 $\r
+ * SVN $Date: 2010-01-27 15:05:58 +0000 (Wed, 27 Jan 2010) $\r
+ */\r
+\r
+#ifndef __SYSTEM_A2FM3FXX_H__\r
+#define __SYSTEM_A2FM3FXX_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif \r
+\r
+/* Standard CMSIS global variables. */\r
+extern uint32_t SystemFrequency; /*!< System Clock Frequency (Core Clock) */\r
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */\r
+\r
+/* SmartFusion specific clocks. */\r
+extern uint32_t g_FrequencyPCLK0; /*!< Clock frequency of APB bus 0. */ \r
+extern uint32_t g_FrequencyPCLK1; /*!< Clock frequency of APB bus 1. */\r
+extern uint32_t g_FrequencyACE; /*!< Clock frequency of Analog Compute Engine. */\r
+extern uint32_t g_FrequencyFPGA; /*!< Clock frequecny of FPGA fabric */\r
+\r
+/***************************************************************************//**\r
+ * The SystemInit() is a standard CMSIS function called during system startup.\r
+ * It is meant to perform low level hardware setup such as configuring PLLs. In\r
+ * the case of SmartFusion these hardware setup operations are performed by the\r
+ * chip boot which executed before the application started. Therefore this\r
+ * function does not need to perform any hardware setup.\r
+ */\r
+void SystemInit(void);\r
+\r
+/***************************************************************************//**\r
+ * The SystemCoreClockUpdate() is a standard CMSIS function which can be called\r
+ * by the application in order to ensure that the SystemCoreClock global\r
+ * variable contains the up to date Cortex-M3 core frequency. Calling this\r
+ * function also updates the global variables containing the frequencies of the\r
+ * APB busses connecting the peripherals and the ACE frequency.\r
+ */\r
+void SystemCoreClockUpdate(void);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif\r
--- /dev/null
+/*******************************************************************************\r
+ * (c) Copyright 2009 SLS Corporation,All Rights Reserved.\r
+ *\r
+ * tcpip.h:header file for TCP/IP implementation.\r
+ * Version Author Comment\r
+ * 1.0.0 SLS corp. First release\r
+ */\r
+/***************************************************************************//**\r
+ * This header file contains the definition and datastructures for the TCP/IP \r
+ * stack implementation.\r
+ */\r
+#ifndef _NETTYPE_H_\r
+#define _NETTYPE_H_\r
+\r
+#define BUF_LEN 1500\r
+\r
+/* IP header length in terms of 16-bit words */\r
+#define IP_HDR_LEN 10\r
+#define IP_HDR_CSUM_OFFSET 5\r
+#define TCP_HDR_CSUM_OFFSET 8\r
+\r
+#define ETH_ADDR_LEN 6\r
+#define IP_ADDR_LEN 4\r
+#define ETH_TYPE_LEN 2\r
+#define ARP_HW_TYPE_LEN 2\r
+#define ARP_PROTO_TYPE_LEN 2\r
+#define ARP_OPCODE_LEN 2\r
+\r
+#define ETH_TYPE_0 0x08 /* both IP and ARP have 08 as the first byte */\r
+#define ETH_TYPE_ARP_1 0x06 /* 0806 is ARP */\r
+#define ETH_TYPE_IP_1 0x00 /* 0800 is IP */\r
+\r
+#define ARP_HW_TYPE_0 0x00 /* 0001 for ethernet */\r
+#define ARP_HW_TYPE_1 0x01 /* 0001 for ethernet */\r
+\r
+#define ARP_PROTO_TYPE_0 0x08 /* 0800 is IP */\r
+#define ARP_PROTO_TYPE_1 0x00 \r
+\r
+#define ARP_OPCODE_0 0x00 /* same for req and reply */\r
+#define ARP_OPCODE_REQ_1 0x01 /* 0001 is Request */\r
+#define ARP_OPCODE_REPLY_1 0x02 /* 0002 is Reply */\r
+\r
+extern unsigned char my_IP_address[IP_ADDR_LEN];\r
+\r
+typedef struct ether_hdr {\r
+ unsigned char da[ETH_ADDR_LEN]; /* destination MAC address */\r
+ unsigned char sa[ETH_ADDR_LEN]; /* source MAC address */\r
+ unsigned char type_code[ETH_TYPE_LEN]; /* type code */\r
+} ether_hdr_t;\r
+\r
+typedef struct arp_pkt {\r
+ unsigned char hw_type[ARP_HW_TYPE_LEN]; /* Hardware Type */\r
+ unsigned char proto_type[ARP_PROTO_TYPE_LEN]; /* Protocol Type */\r
+ unsigned char hw_addr_len; /* Hardware Address Length */\r
+ unsigned char proto_addr_len; /* Protocol Address Length */\r
+ unsigned char opcode[ARP_OPCODE_LEN]; /* Opcode */\r
+ unsigned char mac_sa[ETH_ADDR_LEN]; /* sender MAC address */\r
+ unsigned char ip_sa[IP_ADDR_LEN]; /* sender IP address */\r
+ unsigned char mac_ta[ETH_ADDR_LEN]; /* target MAC address */\r
+ unsigned char ip_ta[IP_ADDR_LEN]; /* target IP address */\r
+} arp_pkt_t;\r
+\r
+#define ICMP_PROTO 0x01\r
+#define TCP_PROTO 0x06\r
+#define UDP_PROTO 0x11\r
+\r
+#define IP_CSUM_LEN 2\r
+#define IP_ID_LEN 2\r
+#define IP_TLEN_LEN 2\r
+#define IP_FRAG_OFF_LEN 2\r
+\r
+typedef struct ip_hdr {\r
+ unsigned char ver_hlen; /* version - 4 bits; IP hdr len - 4 bits */\r
+ unsigned char tos; /* Type of service */\r
+ unsigned char tlen[IP_TLEN_LEN]; /* Size of datagram (header + data) */\r
+ unsigned char id[IP_ID_LEN]; /* together with sa, uniequly identifies pkt */\r
+ unsigned char frag_off[IP_FRAG_OFF_LEN]; /* flags - 3 bits; fragment offset - 13 bits */\r
+ unsigned char ttl; /* time to live */\r
+ unsigned char proto; /* protocol */\r
+ unsigned char csum[IP_CSUM_LEN]; /* header checksum */\r
+ unsigned char sa[IP_ADDR_LEN]; /* IP source address */\r
+ unsigned char da[IP_ADDR_LEN]; /* IP dest address */\r
+} ip_hdr_t;\r
+\r
+\r
+#define ICMP_TYPE_ECHO_REQUEST 8\r
+#define ICMP_TYPE_ECHO_REPLY 0\r
+\r
+typedef struct icmp_hdr {\r
+ unsigned char type;\r
+ unsigned char icode;\r
+ unsigned char csum[IP_CSUM_LEN];\r
+} icmp_hdr_t;\r
+\r
+#define TCP_PORT_LEN 2\r
+#define TCP_SEQ_LEN 4\r
+#define TCP_WSIZE_LEN 2\r
+#define TCP_UPTR_LEN 2\r
+#define TCP_CSUM_LEN 2\r
+#define TCP_PLEN_LEN 2\r
+\r
+typedef struct tcp_hdr {\r
+ unsigned char sp[TCP_PORT_LEN]; /* Source port */\r
+ unsigned char dp[TCP_PORT_LEN]; /* Destination port */\r
+ unsigned char seqnum[TCP_SEQ_LEN]; /* Sequence number */\r
+ unsigned char acknum[TCP_SEQ_LEN]; /* Acknowledgement number */\r
+ unsigned char data_off; /* Data Offset - 4 upper bits are valid */\r
+ unsigned char urg_ack_psh_rst_syn_fin; /* 6 lower bits are valid */\r
+ unsigned char wsize[TCP_WSIZE_LEN]; /* Window */\r
+ unsigned char csum[TCP_CSUM_LEN]; /* Chekcsum */\r
+ unsigned char uptr[TCP_UPTR_LEN]; /* Urgent pointer */\r
+} tcp_hdr_t; \r
+\r
+#define UDP_LEN_LEN 2\r
+#define UDP_CSUM_LEN 2\r
+\r
+typedef struct udp_hdr {\r
+ unsigned char sp[TCP_PORT_LEN]; /* Source port */\r
+ unsigned char dp[TCP_PORT_LEN]; /* Destination port */\r
+ unsigned char len[UDP_LEN_LEN]; /* length of packet */\r
+ unsigned char csum[UDP_CSUM_LEN]; /* checksum */\r
+} udp_hdr_t;\r
+\r
+#define BOOTP_OPTCODE_DHCP_SUBNET 1 /* Subnet mask */\r
+#define BOOTP_OPTCODE_DHCP_ROUTER 3 /* Router*/\r
+#define BOOTP_OPTCODE_DHCP_DOMAIN 6 /* Domain */\r
+#define BOOTP_OPTCODE_DHCP_LEASE 51 /* Lease time*/ \r
+#define BOOTP_OPTCODE_DHCP_TYPE 53 /* 53, 1, DHCP_TYPE_* */\r
+#define BOOTP_OPTCODE_DHCP_SID 54 /* 54, 4, a.b.c.d, Server ID */\r
+#define BOOTP_OPTCODE_DHCP_RENEW 58 /* Renewal time */\r
+#define BOOTP_OPTCODE_DHCP_REBIND 59 /* Rebinding time */\r
+\r
+#define BOOTP_OPTCODE_END 255 /* last in options */\r
+\r
+#define DHCP_TYPE_DISCOVER 1 \r
+#define DHCP_TYPE_OFFER 2 \r
+#define DHCP_TYPE_REQUEST 3 \r
+#define DHCP_TYPE_DECLINE 4 \r
+#define DHCP_TYPE_ACK 5 \r
+#define DHCP_TYPE_NAK 6 \r
+#define DHCP_TYPE_RELEASE 7 \r
+\r
+\r
+#define BOOTP_OP_REQUEST 1\r
+#define BOOTP_OP_REPLY 2\r
+#define BOOTP_HWTYPE_ETH 1\r
+#define BOOTP_XID_LEN 4\r
+#define BOOTP_SEC_LEN 2\r
+#define BOOTP_CHLEN 16\r
+#define BOOTP_SN_LEN 64\r
+#define BOOTP_FL_LEN 128\r
+#define BOOTP_VEN_LEN 64\r
+\r
+#define BOOTP_CLIENT_PORT 68\r
+#define BOOTP_SERVER_PORT 67\r
+\r
+typedef struct bootp_pkt {\r
+ unsigned char op; /* packet op code */\r
+ unsigned char hwtype; /* hardware type */\r
+ unsigned char hlen; /* hardware address length */\r
+ unsigned char hops; /* client sets to zero */\r
+ unsigned char xid[BOOTP_XID_LEN]; /* transaction ID, random */\r
+ unsigned char secs[BOOTP_SEC_LEN]; /* seconds since boot */\r
+ unsigned char flags[2]; /* flags */\r
+ unsigned char ciaddr[IP_ADDR_LEN]; /* client IP ADDR */\r
+ unsigned char yiaddr[IP_ADDR_LEN]; /* Your IP Addr */\r
+ unsigned char siaddr[IP_ADDR_LEN]; /* Server IP ADDR */\r
+ unsigned char giaddr[IP_ADDR_LEN]; /* Gateway IP ADDR */\r
+ unsigned char chaddr[BOOTP_CHLEN]; /* Client Hardware Addr */\r
+ unsigned char sname[BOOTP_SN_LEN]; /* Server Name */\r
+ unsigned char file[BOOTP_FL_LEN]; /* File Path */\r
+ unsigned char vend[BOOTP_VEN_LEN]; /* Vendor Data */\r
+} bootp_pkt_t;\r
+\r
+typedef struct tcp_pseudo_hdr {\r
+ unsigned char sa[IP_ADDR_LEN];\r
+ unsigned char da[IP_ADDR_LEN];\r
+ unsigned char zero;\r
+ unsigned char proto;\r
+ unsigned char plen[TCP_PLEN_LEN];\r
+} tcp_pseudo_hdr_t;\r
+\r
+typedef enum tcp_state_e {\r
+ TCP_STATE_LISTEN = 0,\r
+ TCP_STATE_SYN_RECVD,\r
+ TCP_STATE_ESTABLISHED,\r
+ TCP_STATE_LAST_ACK,\r
+ TCP_STATE_MY_LAST,\r
+ TCP_STATE_CLOSED\r
+} tcp_state_t;\r
+\r
+typedef struct tcp_control_block {\r
+ unsigned char local_port[TCP_PORT_LEN];\r
+ unsigned char remote_port[TCP_PORT_LEN];\r
+ unsigned char remote_addr[IP_ADDR_LEN];\r
+ tcp_state_t state;\r
+ unsigned int local_seq;\r
+ unsigned int remote_seq;\r
+ unsigned char remote_mac[ETH_ADDR_LEN]; /* this really doesn't belong here */\r
+//<CJ>: \r
+ const uint8_t * tx_block_addr;\r
+ unsigned short int tx_block_size;\r
+ unsigned short int tx_block_idx;\r
+ uint8_t * tcp_packet;\r
+} tcp_control_block_t;\r
+\r
+\r
+typedef enum tcp_cntrol_flags_e {\r
+ TCP_CNTRL_FIN = 0x01,\r
+ TCP_CNTRL_SYN = 0x02,\r
+ TCP_CNTRL_RST = 0x04,\r
+ TCP_CNTRL_PSH = 0x08,\r
+ TCP_CNTRL_ACK = 0x10,\r
+ TCP_CNTRL_URG = 0x20\r
+} tcp_control_flags_t;\r
+\r
+\r
+typedef struct arp_entry {\r
+ unsigned char mac[ETH_ADDR_LEN]; /* MAC address */\r
+ unsigned char ip[IP_ADDR_LEN]; /* IP address */\r
+ unsigned char used; /* Is this entry used? */\r
+} arp_entry_t;\r
+\r
+typedef arp_pkt_t *arp_pkt_xp;\r
+typedef ether_hdr_t *eth_hdr_xp;\r
+typedef ip_hdr_t *ip_hdr_xp;\r
+typedef icmp_hdr_t *icmp_hdr_xp;\r
+typedef udp_hdr_t *udp_hdr_xp;\r
+typedef tcp_hdr_t *tcp_hdr_xp;\r
+typedef tcp_pseudo_hdr_t *tcp_pseudo_hdr_xp;\r
+typedef bootp_pkt_t *bootp_pkt_xp;\r
+\r
+#endif /* _NETTYPE_H_ */\r
--- /dev/null
+/*******************************************************************************\r
+ * (c) Copyright 2009 Actel Corporation,All Rights Reserved. \r
+ * \r
+ * tcpip.c:TCP/IP implementation for webserver.\r
+ */\r
+#include "../port_config/cpu_types.h"\r
+#include "nettype.h"\r
+#include "../mss_ethernet_mac/mss_ethernet_mac.h"\r
+#include "../mss_ethernet_mac/mss_ethernet_mac_regs.h"\r
+#include "tcpip.h"\r
+#include <string.h>\r
+#include <stdio.h>\r
+#include <math.h>\r
+#define OK 0\r
+#define ERR 1\r
+#define MAC_BASE_ADDRESS 0x40003000\r
+\r
+\r
+extern char ethAddr[6];\r
+\r
+unsigned char my_ip[IP_ADDR_LEN]={192,168,0,14};\r
+unsigned char my_mac[ETH_ADDR_LEN]={0xAA,0xBB,0xCC,0x11,0x22,0x33};\r
+unsigned char tcp_packet[1532];\r
+unsigned char ip_known;\r
+unsigned char dhcp_ip_found;\r
+unsigned short int ip_id;\r
+unsigned char selected_mode = 0;\r
+unsigned char selectedwaveform = 0;\r
+unsigned char rtc_count[5]={0,0,0,0,0};\r
+unsigned char rtc_match_count[5]={0,5,0,0,0};\r
+unsigned char get_count[5];\r
+unsigned int num_pkt_tx = 0,num_pkt_rx = 0;\r
+#define TCP_START_SEQ 0x10203040\r
+static const unsigned char g_client_ip[IP_ADDR_LEN] = { 192, 168, 1, 10 };\r
+unsigned char oled_string[20];\r
+tcp_control_block_t tcb;\r
+MAC_instance_t g_mac;\r
+\r
+\r
+/***************************************************************************//**\r
+ * See tcpip.h for more information.\r
+ */\r
+unsigned char send_arp_reply(unsigned char *buf)\r
+{\r
+ /* Modify the packet in place */\r
+\r
+ arp_pkt_xp arp_pkt = (arp_pkt_xp )(buf + sizeof(ether_hdr_t));\r
+ eth_hdr_xp eth_hdr = (eth_hdr_xp ) buf;\r
+\r
+ memcpy(eth_hdr->da, eth_hdr->sa, ETH_ADDR_LEN);\r
+ memcpy(eth_hdr->sa, my_mac, ETH_ADDR_LEN);\r
+ arp_pkt->opcode[1] = ARP_OPCODE_REPLY_1;\r
+ memcpy(arp_pkt->mac_ta, arp_pkt->mac_sa, ETH_ADDR_LEN);\r
+ memcpy(arp_pkt->ip_ta, arp_pkt->ip_sa, IP_ADDR_LEN);\r
+ memcpy(arp_pkt->mac_sa, my_mac, ETH_ADDR_LEN);\r
+ memcpy(arp_pkt->ip_sa, my_ip, IP_ADDR_LEN);\r
+ num_pkt_tx++;\r
+ MSS_MAC_tx_packet(buf,42, MSS_MAC_BLOCKING);\r
+ return OK;\r
+}\r
+/***************************************************************************//**\r
+ * See tcpip.h for more information.\r
+ */\r
+void send_gratuitous_arp(unsigned char *buf)\r
+{\r
+ arp_pkt_xp arp_pkt = (arp_pkt_xp )(buf + sizeof(ether_hdr_t));\r
+ eth_hdr_xp eth_hdr = (eth_hdr_xp ) buf;\r
+ memset(eth_hdr->da, 0xFF, ETH_ADDR_LEN); /* broadcast */\r
+ memcpy(eth_hdr->sa, my_mac, ETH_ADDR_LEN);\r
+ eth_hdr->type_code[0] = ETH_TYPE_0;\r
+ eth_hdr->type_code[1] = ETH_TYPE_ARP_1;\r
+ arp_pkt->hw_type[0] = ARP_HW_TYPE_0;\r
+ arp_pkt->hw_type[1] = ARP_HW_TYPE_1;\r
+ arp_pkt->proto_type[0] = ETH_TYPE_0;\r
+ arp_pkt->proto_type[1] = ETH_TYPE_IP_1;\r
+ arp_pkt->hw_addr_len = ETH_ADDR_LEN;\r
+ arp_pkt->proto_addr_len = IP_ADDR_LEN;\r
+ arp_pkt->opcode[0] = ARP_OPCODE_0;\r
+ arp_pkt->opcode[1] = ARP_OPCODE_REQ_1;\r
+ memcpy(arp_pkt->mac_sa, my_mac, ETH_ADDR_LEN);\r
+ memcpy(arp_pkt->ip_sa, my_ip, IP_ADDR_LEN);\r
+ memset(arp_pkt->mac_ta, 0x00, ETH_ADDR_LEN);\r
+ memcpy(arp_pkt->ip_ta, my_ip, IP_ADDR_LEN);\r
+ //mac_tx_send(buf,42,0);\r
+ num_pkt_tx++;\r
+ MSS_MAC_tx_packet(buf,42, MSS_MAC_BLOCKING);\r
+}\r
+/***************************************************************************//**\r
+ * See tcpip.h for more information.\r
+ * \r
+ */\r
+unsigned short int get_checksum(unsigned char *buf, unsigned short int len, unsigned short int pos)\r
+{\r
+ unsigned int sum; /* our accumulated sum */\r
+ unsigned short int delta; /* the next 16-bit quantity to add */\r
+ unsigned short int i; \r
+ unsigned short int ilen; \r
+ sum = (unsigned int) 0; \r
+ ilen=(len&1)?len-1:len; \r
+ for (i = 0; i < ilen; i += 2) { \r
+ if (i == pos) continue;\r
+ delta = (unsigned short int)buf[i+1] + (unsigned short int)((unsigned short int)buf[i] << 8); \r
+ sum += delta; \r
+ if (sum & (unsigned int) 0x10000) { /* if there's a carry... */\r
+ sum &= 0xffff; /* get rid of the carry bit */\r
+ sum++; /* and move it down here */\r
+ } \r
+ } \r
+ if ( len & 1) {\r
+ delta = (unsigned short int)((unsigned short int)buf[i] << 8); \r
+ sum += delta; \r
+ if (sum & (unsigned int) 0x10000) { /* if there's a carry... */\r
+ sum &= 0xffff; /* get rid of the carry bit */\r
+ sum++; /* and move it down here */\r
+ } \r
+ }\r
+ sum = ~sum; \r
+ return sum;\r
+ \r
+} //end calc_checksum \r
+/***************************************************************************//**\r
+ * See tcpip.h for more information.\r
+ */\r
+unsigned char fix_checksum(unsigned char *buf, unsigned short int len, unsigned short int pos)\r
+{\r
+ unsigned short int sum = get_checksum(buf,len,pos); \r
+ buf[pos] = (unsigned char)(sum >> 8);\r
+ buf[pos+1] = (unsigned char)sum;\r
+ return OK;\r
+}\r
+\r
+/***************************************************************************//**\r
+ * See tcpip.h for more information.\r
+ */\r
+unsigned char check_checksum(unsigned char *buf, unsigned short int len, unsigned short int pos, char type)\r
+{\r
+ unsigned short int sum = get_checksum(buf,len,pos);\r
+ \r
+ if ((buf[pos] != (unsigned char)(sum >> 8)) || \r
+ (buf[pos+1] != (unsigned char) sum)) {\r
+\r
+ type = 0; /* get around compiler warning */\r
+ return ERR;\r
+ } else {\r
+ return OK;\r
+ }\r
+}\r
+/***************************************************************************//**\r
+ * See tcpip.h for more information.\r
+ */\r
+unsigned char send_icmp_echo_reply(unsigned char *buf)\r
+{\r
+ eth_hdr_xp eth_hdr = (eth_hdr_xp ) buf;\r
+ ip_hdr_xp ip_hdr = (ip_hdr_xp ) (buf + sizeof (ether_hdr_t));\r
+ icmp_hdr_xp icmp_hdr = (icmp_hdr_xp ) \r
+ (buf + sizeof (ether_hdr_t) + sizeof(ip_hdr_t));\r
+ unsigned short int elen = ((unsigned short int)ip_hdr->tlen[0] << 8) + (unsigned short int)ip_hdr->tlen[1] - sizeof(ip_hdr_t);\r
+ memcpy(eth_hdr->da, eth_hdr->sa, ETH_ADDR_LEN);\r
+ memcpy(eth_hdr->sa, my_mac, ETH_ADDR_LEN);\r
+ memcpy(ip_hdr->da, ip_hdr->sa, IP_ADDR_LEN);\r
+ memcpy(ip_hdr->sa, my_ip, IP_ADDR_LEN);\r
+ ip_hdr->ttl--;\r
+ fix_checksum((unsigned char *)ip_hdr, (unsigned short int) 20, (unsigned short int) 10);\r
+ icmp_hdr->type = ICMP_TYPE_ECHO_REPLY;\r
+ if (elen & 1) {\r
+ ((unsigned char *)icmp_hdr)[elen] = 0;\r
+ }\r
+ fix_checksum((unsigned char *)icmp_hdr, (unsigned short int) elen, (unsigned short int) 2);\r
+ num_pkt_tx++;\r
+ MSS_MAC_tx_packet(buf,elen + sizeof(ether_hdr_t) + sizeof(ip_hdr_t), MSS_MAC_BLOCKING);\r
+ return OK;\r
+}\r
+/***************************************************************************//**\r
+ * See tcpip.h for more information.\r
+ */\r
+void dtoa_reverse(unsigned short int n, unsigned char *buf)\r
+{\r
+ buf--;\r
+ if (n == 0) {\r
+ *buf = '0';\r
+ return;\r
+ }\r
+ while (n > 0) {\r
+ *buf-- = (n % 10) + '0';\r
+ n = n / 10;\r
+ }\r
+}\r
+/***************************************************************************//**\r
+ * See tcpip.h for more information.\r
+ */\r
+void send_bootp_packet (unsigned char *buf)\r
+{\r
+ /* output packet */\r
+ eth_hdr_xp eth_hdr = (eth_hdr_xp ) tcp_packet;\r
+ ip_hdr_xp ip_hdr = (ip_hdr_xp ) (tcp_packet + sizeof(ether_hdr_t));\r
+ udp_hdr_xp udp_hdr = (udp_hdr_xp ) (tcp_packet + sizeof(ether_hdr_t) + sizeof(ip_hdr_t));\r
+ bootp_pkt_xp bootp_pkt = (bootp_pkt_xp )((unsigned char *)udp_hdr + sizeof(udp_hdr_t));\r
+ unsigned char *opts = bootp_pkt->vend;\r
+ /* input packet */\r
+ // eth_hdr_xp ieth_hdr = (eth_hdr_xp ) buf;\r
+ // ip_hdr_xp iip_hdr = (ip_hdr_xp ) (buf + sizeof(ether_hdr_t));\r
+ udp_hdr_xp iudp_hdr = (udp_hdr_xp ) (buf + sizeof(ether_hdr_t) + sizeof(ip_hdr_t));\r
+ bootp_pkt_xp ibootp_pkt = (bootp_pkt_xp )((unsigned char *)iudp_hdr + sizeof(udp_hdr_t));\r
+ unsigned short int plen;\r
+ /* Set up Bootp */\r
+ memset(bootp_pkt, 0, sizeof(bootp_pkt_t));\r
+ bootp_pkt->op = BOOTP_OP_REQUEST;\r
+ bootp_pkt->hwtype = BOOTP_HWTYPE_ETH;\r
+ bootp_pkt->hlen = ETH_ADDR_LEN;\r
+ bootp_pkt->secs[1] = 0x64;\r
+ memcpy(bootp_pkt->chaddr, my_mac, ETH_ADDR_LEN);\r
+ bootp_pkt->flags[0] = 0x80; /* ask for a broadcast */\r
+ if (buf) {\r
+ if (memcmp(my_mac, ibootp_pkt->chaddr, ETH_ADDR_LEN)) /* not for me ignore */\r
+ return;\r
+ memcpy(my_ip, ibootp_pkt->yiaddr, IP_ADDR_LEN);\r
+ ip_known = 1;\r
+ dhcp_ip_found = 1;\r
+ memcpy(bootp_pkt->ciaddr, ibootp_pkt->yiaddr, IP_ADDR_LEN);\r
+ memcpy(bootp_pkt->xid, ibootp_pkt->xid, BOOTP_XID_LEN);\r
+ } else {\r
+ bootp_pkt->xid[0] = 0x90;\r
+ }\r
+ *opts++ = 99; /* magic number */\r
+ *opts++ = 130;\r
+ *opts++ = 83;\r
+ *opts++ = 99;\r
+ *opts++ = BOOTP_OPTCODE_DHCP_TYPE;\r
+ *opts++ = 1;\r
+ if (buf) {\r
+ *opts++ = DHCP_TYPE_REQUEST;\r
+ *opts++ = BOOTP_OPTCODE_DHCP_SID;\r
+ *opts++ = 4;\r
+ *opts++ = ibootp_pkt->siaddr[0];\r
+ *opts++ = ibootp_pkt->siaddr[1];\r
+ *opts++ = ibootp_pkt->siaddr[2];\r
+ *opts++ = ibootp_pkt->siaddr[3];\r
+ } else {\r
+ *opts++ = DHCP_TYPE_DISCOVER;\r
+ }\r
+ *opts++ = BOOTP_OPTCODE_END;\r
+\r
+ /* Set up Udp */\r
+ memset(udp_hdr, 0, sizeof(udp_hdr_t));\r
+ udp_hdr->sp[1] = BOOTP_CLIENT_PORT;\r
+ udp_hdr->dp[1] = BOOTP_SERVER_PORT;\r
+ plen = sizeof(udp_hdr_t) + sizeof(bootp_pkt_t);\r
+ udp_hdr->len[0] = plen >> 8;\r
+ udp_hdr->len[1] = (unsigned char) plen;\r
+ /* leave csum 0 */\r
+\r
+ /* Set up IP */\r
+ memset(ip_hdr, 0, sizeof(ip_hdr_t));\r
+ ip_hdr->ver_hlen = 0x45; /* IPv4 with 20 byte header */\r
+ plen += sizeof(ip_hdr_t);\r
+ ip_hdr->tlen[0] = plen >> 8;\r
+ ip_hdr->tlen[1] = (unsigned char) plen;\r
+ ip_hdr->id[0] = ip_id >> 8;\r
+ ip_hdr->id[1] = (unsigned char) ip_id;\r
+ ip_id++;\r
+ ip_hdr->ttl = 32; /* max 32 hops */\r
+ ip_hdr->proto = UDP_PROTO; \r
+ memset(ip_hdr->da, 0xFF, IP_ADDR_LEN);\r
+ fix_checksum((unsigned char *)ip_hdr, sizeof(ip_hdr_t), 10);\r
+ /* Set up Ethernet */\r
+ eth_hdr->type_code[0] = ETH_TYPE_0;\r
+ eth_hdr->type_code[1] = ETH_TYPE_IP_1;\r
+ memcpy(eth_hdr->sa, my_mac, ETH_ADDR_LEN);\r
+ memset(eth_hdr->da, 0xFF, ETH_ADDR_LEN); /* broadcast */\r
+ num_pkt_tx++;\r
+ MSS_MAC_tx_packet(tcp_packet,plen + sizeof(ether_hdr_t), MSS_MAC_BLOCKING);\r
+}\r
+/***************************************************************************//**\r
+ * See tcpip.h for more information.\r
+ */\r
+void send_dhcp_server_packet (unsigned char *buf)\r
+{\r
+ unsigned char * tcp_packet = tcp_packet;\r
+ /* output packet */\r
+ eth_hdr_xp eth_hdr = (eth_hdr_xp ) tcp_packet;\r
+ ip_hdr_xp ip_hdr = (ip_hdr_xp ) (tcp_packet + sizeof(ether_hdr_t));\r
+ udp_hdr_xp udp_hdr = (udp_hdr_xp ) (tcp_packet + sizeof(ether_hdr_t) + sizeof(ip_hdr_t));\r
+ bootp_pkt_xp bootp_pkt = (bootp_pkt_xp )((unsigned char *)udp_hdr + sizeof(udp_hdr_t));\r
+ unsigned char *opts = bootp_pkt->vend;\r
+\r
+ /* input packet */\r
+ eth_hdr_xp ieth_hdr = (eth_hdr_xp ) buf;\r
+ // ip_hdr_xp iip_hdr = (ip_hdr_xp ) (buf + sizeof(ether_hdr_t));\r
+ udp_hdr_xp iudp_hdr = (udp_hdr_xp ) (buf + sizeof(ether_hdr_t) + sizeof(ip_hdr_t));\r
+ bootp_pkt_xp ibootp_pkt = (bootp_pkt_xp )((unsigned char *)iudp_hdr + sizeof(udp_hdr_t));\r
+ unsigned char *iopts = ibootp_pkt->vend;\r
+\r
+ unsigned short int plen;\r
+\r
+ /* Set up Bootp */\r
+ memset(bootp_pkt, 0, sizeof(bootp_pkt_t));\r
+ bootp_pkt->op = BOOTP_OP_REPLY;\r
+ bootp_pkt->hwtype = BOOTP_HWTYPE_ETH;\r
+ bootp_pkt->hlen = ETH_ADDR_LEN;\r
+ bootp_pkt->secs[1] = 0x64;\r
+ memcpy(bootp_pkt->chaddr, ieth_hdr->sa, ETH_ADDR_LEN);\r
+ bootp_pkt->flags[0] = 0x00;\r
+ if (buf) {\r
+ memcpy(bootp_pkt->ciaddr, ibootp_pkt->yiaddr, IP_ADDR_LEN);\r
+ memcpy(bootp_pkt->yiaddr, g_client_ip, IP_ADDR_LEN);\r
+ memcpy(bootp_pkt->xid, ibootp_pkt->xid, BOOTP_XID_LEN);\r
+ } else {\r
+ bootp_pkt->xid[0] = 0x90;\r
+ }\r
+ *opts++ = 99; /* magic number */\r
+ *opts++ = 130;\r
+ *opts++ = 83;\r
+ *opts++ = 99;\r
+ *opts++ = BOOTP_OPTCODE_DHCP_TYPE;\r
+ *opts++ = 1;\r
+ if (iopts[6] == DHCP_TYPE_DISCOVER)\r
+ {\r
+ *opts++ = DHCP_TYPE_OFFER;\r
+ }\r
+ else\r
+ {\r
+ *opts++ = DHCP_TYPE_ACK;\r
+ } \r
+ /* Server ID */\r
+ *opts++ = BOOTP_OPTCODE_DHCP_SID;\r
+ *opts++ = 4;\r
+ *opts++ = my_ip[0];\r
+ *opts++ = my_ip[1];\r
+ *opts++ = my_ip[2];\r
+ *opts++ = my_ip[3];\r
+ /* Lease time (1 our) */\r
+ *opts++ = BOOTP_OPTCODE_DHCP_LEASE;\r
+ *opts++ = 4;\r
+ *opts++ = 0x00;\r
+ *opts++ = 0x00;\r
+ *opts++ = 0x0E;\r
+ *opts++ = 0x10;\r
+ /* Renewal time */\r
+ *opts++ = BOOTP_OPTCODE_DHCP_RENEW;\r
+ *opts++ = 4;\r
+ *opts++ = 0x00;\r
+ *opts++ = 0x00;\r
+ *opts++ = 0x07;\r
+ *opts++ = 0x08;\r
+ /* Rebinding time */\r
+ *opts++ = BOOTP_OPTCODE_DHCP_REBIND;\r
+ *opts++ = 4;\r
+ *opts++ = 0x00;\r
+ *opts++ = 0x00;\r
+ *opts++ = 0x0C;\r
+ *opts++ = 0x4E;\r
+ /* Subnet mask */\r
+ *opts++ = BOOTP_OPTCODE_DHCP_SUBNET;\r
+ *opts++ = 4;\r
+ *opts++ = 0xFF;\r
+ *opts++ = 0xFF;\r
+ *opts++ = 0xFF;\r
+ *opts++ = 0x00;\r
+ /* Router */\r
+ *opts++ = BOOTP_OPTCODE_DHCP_ROUTER;\r
+ *opts++ = 4;\r
+ *opts++ = my_ip[0];\r
+ *opts++ = my_ip[1];\r
+ *opts++ = my_ip[2];\r
+ *opts++ = my_ip[3];\r
+ /* Domain */\r
+ *opts++ = BOOTP_OPTCODE_DHCP_DOMAIN;\r
+ *opts++ = 4;\r
+ *opts++ = my_ip[0];\r
+ *opts++ = my_ip[1];\r
+ *opts++ = my_ip[2];\r
+ *opts++ = my_ip[3];\r
+ \r
+ *opts++ = BOOTP_OPTCODE_END;\r
+\r
+ /* Set up Udp */\r
+ memset(udp_hdr, 0, sizeof(udp_hdr_t));\r
+ udp_hdr->sp[1] = BOOTP_SERVER_PORT;\r
+ udp_hdr->dp[1] = BOOTP_CLIENT_PORT;\r
+ plen = sizeof(udp_hdr_t) + sizeof(bootp_pkt_t);\r
+ udp_hdr->len[0] = plen >> 8;\r
+ udp_hdr->len[1] = (unsigned char) plen;\r
+ /* leave csum 0 */\r
+\r
+ /* Set up IP */\r
+ memset(ip_hdr, 0, sizeof(ip_hdr_t));\r
+ ip_hdr->ver_hlen = 0x45; /* IPv4 with 20 byte header */\r
+ plen += sizeof(ip_hdr_t);\r
+ ip_hdr->tlen[0] = plen >> 8;\r
+ ip_hdr->tlen[1] = (unsigned char) plen;\r
+ ip_hdr->id[0] = ip_id >> 8;\r
+ ip_hdr->id[1] = (unsigned char) ip_id;\r
+ ip_id++;\r
+ ip_hdr->ttl = 255;\r
+ ip_hdr->proto = UDP_PROTO;\r
+ memcpy(ip_hdr->sa, my_ip, IP_ADDR_LEN);\r
+ memset(ip_hdr->da, 0xFF, IP_ADDR_LEN);\r
+ fix_checksum((unsigned char *)ip_hdr, sizeof(ip_hdr_t), 10);\r
+ \r
+ /* Set up Ethernet */\r
+ eth_hdr->type_code[0] = ETH_TYPE_0;\r
+ eth_hdr->type_code[1] = ETH_TYPE_IP_1;\r
+ memcpy(eth_hdr->sa, my_mac, ETH_ADDR_LEN); \r
+ memset(eth_hdr->da, 0xFF, ETH_ADDR_LEN); /* broadcast */\r
+ num_pkt_tx++;\r
+ MSS_MAC_tx_packet(tcp_packet,plen + sizeof(ether_hdr_t), MSS_MAC_BLOCKING);\r
+}\r
+/***************************************************************************//**\r
+ * See tcpip.h for more information.\r
+ */\r
+unsigned char process_udp_packet (unsigned char *buf)\r
+{\r
+ \r
+ udp_hdr_xp udp_hdr = (udp_hdr_xp ) (buf + sizeof(ether_hdr_t) + sizeof(ip_hdr_t));\r
+ \r
+ if (udp_hdr->dp[1] != BOOTP_CLIENT_PORT) {\r
+ send_dhcp_server_packet( buf );\r
+ return OK;\r
+ }\r
+ if (ip_known) {\r
+ return ERR;\r
+ }\r
+ /* some more error checking here? */\r
+ send_bootp_packet(buf);\r
+ return OK;\r
+}\r
+/***************************************************************************//**\r
+ * See tcpip.h for more information.\r
+ */\r
+\r
+void send_tcp_packet (unsigned char control_bits,unsigned short int buflen) \r
+{\r
+ \r
+ eth_hdr_xp eth_hdr = (eth_hdr_xp ) tcp_packet;\r
+ ip_hdr_xp ip_hdr = (ip_hdr_xp ) (tcp_packet + sizeof(ether_hdr_t));\r
+ tcp_hdr_xp tcp_hdr = (tcp_hdr_xp ) \r
+ (tcp_packet + sizeof(ether_hdr_t) + sizeof(ip_hdr_t));\r
+ tcp_pseudo_hdr_xp tcp_pseudo_hdr = (tcp_pseudo_hdr_xp )\r
+ (((unsigned char *)tcp_hdr) - sizeof(tcp_pseudo_hdr_t));\r
+ unsigned char *tcp_data = tcp_packet + sizeof(ether_hdr_t) + sizeof(ip_hdr_t) + sizeof (tcp_hdr_t);\r
+ unsigned char *seqp = (unsigned char *)(&tcb.local_seq);\r
+ unsigned short int plen;\r
+ memset(tcp_hdr, 0, sizeof(tcp_hdr_t));\r
+ memcpy(tcp_hdr->sp, tcb.local_port, TCP_PORT_LEN);\r
+ memcpy(tcp_hdr->dp, tcb.remote_port, TCP_PORT_LEN);\r
+ tcp_hdr->seqnum[0] = seqp[3];\r
+ tcp_hdr->seqnum[1] = seqp[2];\r
+ tcp_hdr->seqnum[2] = seqp[1];\r
+ tcp_hdr->seqnum[3] = seqp[0];\r
+ tcb.local_seq++;\r
+ if (buflen) {\r
+ tcb.local_seq += buflen - 1;\r
+ }\r
+ if (control_bits & TCP_CNTRL_ACK) {\r
+ seqp = (unsigned char *)(&tcb.remote_seq);\r
+ tcp_hdr->acknum[3] = seqp[0];\r
+ tcp_hdr->acknum[2] = seqp[1];\r
+ tcp_hdr->acknum[1] = seqp[2];\r
+ tcp_hdr->acknum[0] = seqp[3];\r
+ }\r
+ tcp_hdr->data_off = 0x50; /* always 5 32 bit words for us */\r
+ tcp_hdr->urg_ack_psh_rst_syn_fin = control_bits;\r
+ tcp_hdr->wsize[0] = 0x08; /* this is 0x0800, which is 2K */\r
+ if (buflen & 1) {\r
+ tcp_data[buflen] = 0;\r
+ }\r
+ /* memset(tcp_pseudo_hdr, 0, sizeof(tcp_pseudo_hdr_t)); */\r
+ memcpy(tcp_pseudo_hdr->sa, my_ip, IP_ADDR_LEN);\r
+ memcpy(tcp_pseudo_hdr->da, tcb.remote_addr, IP_ADDR_LEN);\r
+ tcp_pseudo_hdr->zero = 0;\r
+ tcp_pseudo_hdr->proto = TCP_PROTO;\r
+ plen = buflen + sizeof(tcp_hdr_t);\r
+ tcp_pseudo_hdr->plen[0] = plen >> 8;\r
+ tcp_pseudo_hdr->plen[1] = (unsigned char)plen;\r
+ fix_checksum((unsigned char *)tcp_pseudo_hdr, \r
+ (unsigned short int)(plen + sizeof(tcp_pseudo_hdr_t)), (unsigned short int)28);\r
+\r
+ memset(ip_hdr, 0, sizeof(ip_hdr_t));\r
+\r
+ ip_hdr->ver_hlen = 0x45; /* IPv4 with 20 byte header */\r
+ plen += sizeof(ip_hdr_t); /* add the size of the IP Header */\r
+ ip_hdr->tlen[0] = plen >> 8;\r
+ ip_hdr->tlen[1] = (unsigned char) plen;\r
+ ip_hdr->id[0] = ip_id >> 8;\r
+ ip_hdr->id[1] = (unsigned char) ip_id;\r
+ ip_id++;\r
+ ip_hdr->ttl = 32; /* max 32 hops */\r
+ ip_hdr->proto = TCP_PROTO;\r
+ memcpy(ip_hdr->sa, my_ip, IP_ADDR_LEN);\r
+ memcpy(ip_hdr->da, tcb.remote_addr, IP_ADDR_LEN);\r
+ fix_checksum((unsigned char *)ip_hdr, sizeof(ip_hdr_t), 10);\r
+ /* Fix the Ethernet Header */\r
+ eth_hdr->type_code[0] = ETH_TYPE_0;\r
+ eth_hdr->type_code[1] = ETH_TYPE_IP_1;\r
+ memcpy(eth_hdr->sa, my_mac, ETH_ADDR_LEN);\r
+ memcpy(eth_hdr->da, tcb.remote_mac, ETH_ADDR_LEN); /* should be table lookup */\r
+ num_pkt_tx++; \r
+ MSS_MAC_tx_packet(tcp_packet,plen + sizeof(ether_hdr_t), MSS_MAC_BLOCKING);\r
+}\r
+/***************************************************************************//**\r
+ * See tcpip.h for more information.\r
+ */\r
+unsigned char tcp_init(void)\r
+{\r
+ memset(&tcb,0,sizeof(tcp_control_block_t));\r
+ tcb.state = TCP_STATE_LISTEN;\r
+ ip_id = 0;\r
+ ip_known = 0;\r
+ return OK;\r
+}\r
+\r
+/***************************************************************************//**\r
+ * See tcpip.h for more information.\r
+ */\r
+unsigned char hex_digits_to_byte(unsigned char u, unsigned char l) \r
+{\r
+ if (u > '9')\r
+ u = u - 'A' + 10;\r
+ else\r
+ u = u - '0';\r
+ if (l > '9')\r
+ l = l - 'A' + 10;\r
+ else\r
+ l = l - '0';\r
+ return (u << 4) + l;\r
+}\r
+/***************************************************************************//**\r
+ * See tcpip.h for more information.\r
+ */\r
+unsigned char process_icmp_packet(unsigned char *buf)\r
+{\r
+ ip_hdr_xp ip_hdr = (ip_hdr_xp ) (buf + sizeof (ether_hdr_t));\r
+ icmp_hdr_xp icmp_hdr = (icmp_hdr_xp ) \r
+ (buf + sizeof (ether_hdr_t) + sizeof(ip_hdr_t));\r
+ unsigned short int elen = ((unsigned short int)ip_hdr->tlen[0] << 8) + (unsigned short int)ip_hdr->tlen[1] - sizeof(ip_hdr_t);\r
+ if (check_checksum((unsigned char *)icmp_hdr, (unsigned short int) elen, (unsigned short int) 2, 'M') != OK) \r
+ return ERR;\r
+ if (icmp_hdr->type != ICMP_TYPE_ECHO_REQUEST) {\r
+ return ERR;\r
+ }\r
+ return send_icmp_echo_reply(buf);\r
+}\r
+\r
+ /* See tcpip.h for more information.\r
+ */\r
+\r
+/***************************************************************************//**\r
+ * See tcpip.h for more information.\r
+ */\r
+unsigned char process_tcp_packet(unsigned char *buf)\r
+{\r
+ eth_hdr_xp eth_hdr = (eth_hdr_xp )buf;\r
+ ip_hdr_xp ip_hdr = (ip_hdr_xp ) (buf + sizeof (ether_hdr_t));\r
+ tcp_hdr_xp tcp_hdr = (tcp_hdr_xp ) \r
+ (buf + sizeof (ether_hdr_t) + sizeof(ip_hdr_t));\r
+ unsigned short int elen = ((unsigned short int)ip_hdr->tlen[0] << 8) + (unsigned short int)ip_hdr->tlen[1] - sizeof(ip_hdr_t);\r
+ unsigned char state;\r
+ if ( !memcmp(tcb.remote_addr, ip_hdr->sa, IP_ADDR_LEN) && /* same source IP */\r
+ !memcmp(tcb.remote_port, tcp_hdr->sp, TCP_PORT_LEN) && /* same source port */\r
+ !memcmp(tcb.local_port, tcp_hdr->dp, TCP_PORT_LEN)) { /* same dest port */\r
+ state = tcb.state;\r
+ } else { /* copy it over, a new IP wants in */\r
+ memcpy(tcb.remote_addr, ip_hdr->sa, IP_ADDR_LEN);\r
+ memcpy(tcb.remote_port, tcp_hdr->sp, TCP_PORT_LEN);\r
+ memcpy(tcb.local_port, tcp_hdr->dp, TCP_PORT_LEN);\r
+ memcpy(tcb.remote_mac, eth_hdr->sa, ETH_ADDR_LEN);\r
+ state = TCP_STATE_LISTEN;\r
+ } \r
+ switch (state) {\r
+ case TCP_STATE_LISTEN:\r
+ if (tcp_hdr->urg_ack_psh_rst_syn_fin & TCP_CNTRL_SYN) {\r
+ /* recd SYN : new connection; send SYN+ACK */ \r
+ \r
+ tcb.local_seq = TCP_START_SEQ;\r
+ tcb.remote_seq = 0;\r
+ tcb.remote_seq = (tcb.remote_seq | tcp_hdr->seqnum[0]);\r
+ tcb.remote_seq = ((tcb.remote_seq << 8) |tcp_hdr->seqnum[1]);\r
+ tcb.remote_seq = ((tcb.remote_seq << 8) |tcp_hdr->seqnum[2]);\r
+ tcb.remote_seq = ((tcb.remote_seq << 8) |tcp_hdr->seqnum[3]); \r
+ tcb.remote_seq++;\r
+ send_tcp_packet( TCP_CNTRL_SYN | TCP_CNTRL_ACK, 0);\r
+ tcb.state = TCP_STATE_SYN_RECVD;\r
+ } \r
+ break; \r
+ case TCP_STATE_SYN_RECVD: \r
+ if (tcp_hdr->urg_ack_psh_rst_syn_fin & TCP_CNTRL_ACK) { \r
+ /* recd ack; send nothing */\r
+ tcb.state = TCP_STATE_ESTABLISHED;\r
+ } \r
+ else { \r
+ tcb.state = TCP_STATE_LISTEN;\r
+ } \r
+ break;\r
+ case TCP_STATE_ESTABLISHED: \r
+ if (tcp_hdr->urg_ack_psh_rst_syn_fin & TCP_CNTRL_FIN) {\r
+ /* recd fin; send ack */\r
+ /* skip CLOSE_WAIT state; send fin along with ack */\r
+ tcb.remote_seq = 0;\r
+ tcb.remote_seq = (tcb.remote_seq | tcp_hdr->seqnum[0]);\r
+ tcb.remote_seq = ((tcb.remote_seq << 8) |tcp_hdr->seqnum[1]);\r
+ tcb.remote_seq = ((tcb.remote_seq << 8) |tcp_hdr->seqnum[2]);\r
+ tcb.remote_seq = ((tcb.remote_seq << 8) |tcp_hdr->seqnum[3]); \r
+ tcb.remote_seq++;\r
+ send_tcp_packet(TCP_CNTRL_ACK | TCP_CNTRL_FIN, 0);\r
+ tcb.state = TCP_STATE_LAST_ACK; \r
+ /* Default scroll message on OLED */\r
+ }\r
+ else if (tcp_hdr->dp[0] != 0 || \\r
+ tcp_hdr->dp[1] != 80) { /* HTTP Port */\r
+ break;\r
+ }\r
+ else if (elen > sizeof(tcp_hdr_t)) { /* dont respond to empty packets*/\r
+ tcb.remote_seq = 0;\r
+ tcb.remote_seq = (tcb.remote_seq | tcp_hdr->seqnum[0]);\r
+ tcb.remote_seq = ((tcb.remote_seq << 8) |tcp_hdr->seqnum[1]);\r
+ tcb.remote_seq = ((tcb.remote_seq << 8) |tcp_hdr->seqnum[2]);\r
+ tcb.remote_seq = ((tcb.remote_seq << 8) |tcp_hdr->seqnum[3]); \r
+ tcb.remote_seq += (unsigned long) (elen - sizeof(tcp_hdr_t));\r
+ //send_http_response(((unsigned char *)(tcp_hdr)) + sizeof (tcp_hdr_t));\r
+ tcb.state = TCP_STATE_MY_LAST; \r
+ } \r
+ break;\r
+ case TCP_STATE_MY_LAST: \r
+ if (tcp_hdr->urg_ack_psh_rst_syn_fin & TCP_CNTRL_FIN) {\r
+ /* sent fin, got fin, ack the fin */\r
+ tcb.remote_seq = 0;\r
+ tcb.remote_seq = (tcb.remote_seq | tcp_hdr->seqnum[0]);\r
+ tcb.remote_seq = ((tcb.remote_seq << 8) |tcp_hdr->seqnum[1]);\r
+ tcb.remote_seq = ((tcb.remote_seq << 8) |tcp_hdr->seqnum[2]);\r
+ tcb.remote_seq = ((tcb.remote_seq << 8) |tcp_hdr->seqnum[3]); \r
+ tcb.remote_seq++;\r
+ send_tcp_packet(TCP_CNTRL_ACK, 0);\r
+ tcb.state = TCP_STATE_CLOSED;\r
+ }\r
+ break;\r
+ case TCP_STATE_LAST_ACK:\r
+ \r
+ if (tcp_hdr->urg_ack_psh_rst_syn_fin & TCP_CNTRL_ACK) {\r
+ /* recd ack; send nothing */\r
+ tcb.state = TCP_STATE_CLOSED;\r
+ }\r
+ /* no break here... go on to CLOSED directly */\r
+ case TCP_STATE_CLOSED: \r
+ memset (&tcb, 0, sizeof (tcp_control_block_t));\r
+ break; \r
+ default:\r
+ break;\r
+ }\r
+ return 0;\r
+}\r
+/***************************************************************************//**\r
+ * See tcpip.h for more information.\r
+ */\r
+unsigned char process_ip_packet(unsigned char *buf)\r
+{\r
+ ip_hdr_xp ip_hdr = (ip_hdr_xp ) (buf + sizeof (ether_hdr_t));\r
+ /* Is the incoming pkt for me?\r
+ (either explicity addressed to me or a broadcast address) */\r
+ if (memcmp(my_ip, ip_hdr->da, IP_ADDR_LEN)) /* not my IP */ {\r
+ if (ip_known) {\r
+ return ERR;\r
+ }\r
+ if (ip_hdr->da[0] != 0xFF || ip_hdr->da[1] != 0xFF ||\r
+ ip_hdr->da[2] != 0xFF || ip_hdr->da[3] != 0xFF) {\r
+ return ERR;\r
+ }\r
+ }\r
+ if (check_checksum((unsigned char *)ip_hdr, (unsigned short int) 20, (unsigned short int) 10, 'I') != OK)\r
+ return ERR;\r
+ switch (ip_hdr->proto) \r
+ {\r
+ case TCP_PROTO:\r
+ return process_tcp_packet(buf);\r
+ case ICMP_PROTO:\r
+ return process_icmp_packet(buf);\r
+ case UDP_PROTO:\r
+ return process_udp_packet(buf);\r
+ default: {\r
+ return ERR;\r
+ }\r
+ }\r
+ return ERR;\r
+}\r
+/***************************************************************************//**\r
+ * See tcpip.h for more information.\r
+ */\r
+unsigned char process_arp_packet(unsigned char *buf)\r
+{\r
+ arp_pkt_xp arp_pkt = (arp_pkt_xp )(buf + sizeof(ether_hdr_t));\r
+ if (arp_pkt->opcode[1] != ARP_OPCODE_REQ_1) { \r
+ if (arp_pkt->opcode[1] == ARP_OPCODE_REPLY_1)\r
+ { \r
+ if (!memcmp(my_ip, arp_pkt->ip_sa, IP_ADDR_LEN))\r
+ { \r
+ //printf("IP conflict with MAC");\r
+ //printf("%02x:%02x:%02x:%02x:%02x:%02x",arp_pkt->mac_sa[0],arp_pkt->mac_sa[1],arp_pkt->mac_sa[2],arp_pkt->mac_sa[3],arp_pkt->mac_sa[4],arp_pkt->mac_sa[5]);\r
+ } \r
+ }\r
+ return ERR;\r
+ } \r
+ if (memcmp(my_ip, arp_pkt->ip_ta, IP_ADDR_LEN)) {\r
+ return ERR;\r
+ } \r
+ return send_arp_reply(buf);\r
+}\r
+/***************************************************************************//**\r
+ * See tcpip.h for more information.\r
+ */\r
+unsigned char process_packet( unsigned char * buf )\r
+{\r
+ eth_hdr_xp eth_hdr;\r
+ unsigned char typ;\r
+ eth_hdr = (eth_hdr_xp ) buf;\r
+ typ = eth_hdr->type_code[0];\r
+ if (typ != ETH_TYPE_0)\r
+ {\r
+ return ERR;\r
+ }\r
+ typ = eth_hdr->type_code[1];\r
+ if (typ == ETH_TYPE_ARP_1) \r
+ {\r
+ return process_arp_packet(buf);\r
+ }\r
+ else if (typ == ETH_TYPE_IP_1) {\r
+ return process_ip_packet(buf);\r
+ } \r
+ else\r
+ {\r
+ return ERR;\r
+ }\r
+ return ERR;\r
+}\r
+/***************************************************************************//**\r
+ * See tcpip.h for more information.\r
+ */\r
+unsigned char *xstrcpy(unsigned char *d, const unsigned char *s)\r
+{\r
+ unsigned char c;\r
+\r
+ while ((c = *s++)) \r
+ (*d++ = c) ;\r
+ return d;\r
+}\r
+/***************************************************************************//**\r
+ * See tcpip.h for more information.\r
+ */\r
+// updated html page with fusion board link on page:\r
+\r
--- /dev/null
+/*******************************************************************************\r
+ * (c) Copyright 2009 SLS Corporation,All Rights Reserved. \r
+ * \r
+ * tcpip.h:header file of TCP/IP implementation.\r
+ * \r
+ * Version Author Comment\r
+ * 1.0.0 SLS corp. First release,16 Jan 2009\r
+ */\r
+#ifndef TCPIP_H_\r
+#define TCPIP_H_\r
+\r
+#define FLASH_CONTEXT_INDICATOR 0x20000000\r
+#define FLASH_SELFWAKEUP_INDICATOR 0x20000001\r
+#define FLASH_CONTEXT_LOCATION 0x20000002\r
+\r
+/***************************************************************************//**\r
+ * Replies to ARP requests.\r
+ * \r
+ * @param buf Pointer to the recieved buffer from Ethernet MAC.\r
+ * \r
+ */\r
+unsigned char send_arp_reply(unsigned char *buf);\r
+/***************************************************************************//**\r
+ * Sends gratuitous arp brodcast message to the LAN.\r
+ * \r
+ * @param buf Pointer to the recieved buffer from Ethernet MAC.\r
+ * \r
+ */\r
+void send_gratuitous_arp(unsigned char *buf);\r
+/***************************************************************************//**\r
+ * Calculates the checksum for Ethernet data in the header.\r
+ * \r
+ * @param buf Pointer to the recieved buffer from Ethernet MAC.\r
+ * @param len Number of bytes.\r
+ * @param pos position for the check sum. \r
+ * \r
+ * @return value of the checksum\r
+ */\r
+unsigned short int get_checksum(unsigned char *buf, unsigned short int len, unsigned short int pos);\r
+/***************************************************************************//**\r
+ * Calls internally to get_checksum and fixes the value of the checksum to\r
+ * position.\r
+ * \r
+ * @param buf Pointer to the recieved buffer from Ethernet MAC.\r
+ * @param len Number of bytes.\r
+ * @param pos position for the check sum.\r
+ * \r
+ * @return OK\r
+ */\r
+unsigned char fix_checksum(unsigned char *buf, unsigned short int len, unsigned short int pos);\r
+/***************************************************************************//**\r
+ * Checks the calculated checksum for the errors.\r
+ * \r
+ * @param buf Pointer to the recieved buffer from Ethernet MAC.\r
+ * @param len Number of bytes.\r
+ * @param pos position for the check sum.\r
+ * \r
+ * @return OK If there is no error\r
+ * ERR If there is error in the data \r
+ */\r
+unsigned char check_checksum(unsigned char *buf, unsigned short int len, unsigned short int pos, char type);\r
+/***************************************************************************//**\r
+ * Sends the reply to ICMP request like PING.\r
+ * \r
+ * @param buf Pointer to the recieved buffer from Ethernet MAC.\r
+ */\r
+unsigned char send_icmp_echo_reply(unsigned char *buf);\r
+/***************************************************************************//**\r
+ * Converts the input integer to the ascii char and fills in the buffer. \r
+ * \r
+ * @param buf To filled in by the ascii value.\r
+ * @param n integer number\r
+ */\r
+void dtoa_reverse(unsigned short int n, unsigned char *buf);\r
+/***************************************************************************//**\r
+ * Sends DHCP request to the server available in LAN.\r
+ * \r
+ * @param buf Pointer to the recieved data in case of DHCP reply.Zero for request. \r
+ */\r
+void send_bootp_packet (unsigned char *buf);\r
+/***************************************************************************//**\r
+ * Processes the UDP datagram.\r
+ * \r
+ * @param buf Pointer to the recieved buffer from Ethernet MAC.\r
+ */\r
+unsigned char process_udp_packet (unsigned char *buf);\r
+/***************************************************************************//**\r
+ * Sends TCP packet to the network.\r
+ * \r
+ * @param buf Pointer to the transmitt buffer to Ethernet MAC.\r
+ */\r
+void send_tcp_packet (unsigned char control_bits,unsigned short int buflen);\r
+/***************************************************************************//**\r
+ * Initialize TCP for the software TCP/IP stack.\r
+ * \r
+ * @return OK\r
+ */\r
+unsigned char tcp_init(void);\r
+/***************************************************************************//**\r
+ * Converts two hex decimal ascii digits into a sigle integer digit.\r
+ * \r
+ * @param u ascii hex digit \r
+ * l ascii hex digit\r
+ * @returm converted integer byte\r
+ * \r
+ */\r
+unsigned char hex_digits_to_byte(unsigned char u, unsigned char l);\r
+/***************************************************************************//**\r
+ * Processes ICMP packets\r
+ * \r
+ * @param buf Pointer to the recieved buffer from Ethernet MAC.\r
+ * \r
+ * @return ERR if there is an error in the data\r
+ * or calls further necessary functions.\r
+ */\r
+unsigned char process_icmp_packet(unsigned char *buf);\r
+/***************************************************************************//**\r
+ * Sends logo of ACTEL on the network over HTTP protocol.\r
+ * @return OK\r
+ */\r
+unsigned char http_send_logo ();\r
+/***************************************************************************//**\r
+ * Sends appropriate answer to the different HTTP requests.\r
+ * \r
+ * @param buf Pointer to the recieved buffer from Ethernet MAC.\r
+ * @return OK\r
+ */\r
+unsigned char send_http_response(unsigned char *buf);\r
+/***************************************************************************//**\r
+ * Process incoming TCP requests and handles the TCP state machine.\r
+ * \r
+ * @param buf Pointer to the recieved buffer from Ethernet MAC.\r
+ * @return OK\r
+ */\r
+unsigned char process_tcp_packet(unsigned char *buf);\r
+/***************************************************************************//**\r
+ * Process incoming IP datagrams and handles the TCP state machine.\r
+ * \r
+ * @param buf Pointer to the recieved buffer from Ethernet MAC.\r
+ * @return OK\r
+ */\r
+unsigned char process_ip_packet(unsigned char *buf);\r
+/***************************************************************************//**\r
+ * Processes the ARP packets. \r
+ * @param buf Pointer to the recieved buffer from Ethernet MAC.\r
+ * @return OK \r
+ */\r
+unsigned char process_arp_packet(unsigned char *buf);\r
+/***************************************************************************//**\r
+ * Processes incoming packets and identifies its type.\r
+ * \r
+ * @param buf Pointer to the recieved buffer from Ethernet MAC.\r
+ * @return call the function for further process\r
+ * ERR if any error\r
+ */\r
+unsigned char process_packet( unsigned char * buf );\r
+/***************************************************************************//**\r
+ * copies source string to destination address.\r
+ * \r
+ * @param d Pointer to the destination\r
+ * @param s Pointer to the source\r
+ * @return The last location after copy\r
+ * \r
+ */\r
+unsigned char *xstrcpy(unsigned char *d, const unsigned char *s);\r
+/***************************************************************************//**\r
+ * Sends the home page of the demonstration webserver.\r
+ * \r
+ */\r
+void http_send_packet();\r
+/***************************************************************************//**\r
+ * Sends the packet for waveform mode.\r
+ * \r
+ */\r
+void http_send_packet_waveform();\r
+/***************************************************************************//**\r
+ * Sends the packet for multimeter mode.\r
+ * \r
+ */\r
+void http_send_packet_multimeter();\r
+/***************************************************************************//**\r
+ * Sends the packet for DAC mode.\r
+ * \r
+ */\r
+void http_send_packet_DAC();\r
+/***************************************************************************//**\r
+ * Sends the packet for sleeping stopwatch.\r
+ * \r
+ */\r
+void http_send_packet_SLEEPING_STOPWATCH();\r
+/***************************************************************************//**\r
+ * Sends the packet for text terminal.\r
+ * \r
+ */\r
+void http_send_packet_textterminal();\r
+/***************************************************************************//**\r
+ * Sends the packet for VIT auxiliary mode.\r
+ * \r
+ */\r
+void http_send_packet_VIT();\r
+/***************************************************************************//**\r
+ * Sends the packet for Real Time Data Display.\r
+ * \r
+ */\r
+void http_send_packet_RTDD();\r
+/***************************************************************************//**\r
+ * Sends the packet for Stock Ticker.\r
+ * \r
+ */\r
+void http_send_packet_Stockticker();\r
+/***************************************************************************//**\r
+ * Sends the packet for Gadgets mode.\r
+ * \r
+ */\r
+void http_send_packet_weatherblog();\r
+/***************************************************************************//**\r
+ * Sends the packet for Selfwakeup.\r
+ * \r
+ */\r
+void http_send_packet_SELFWAKEUP();\r
+/***************************************************************************//**\r
+ * Same as above mentioned functions but following functions are applicable\r
+ * to Internet Explorer.\r
+ * \r
+ */\r
+void http_send_packet_IE();\r
+void http_send_packet_SELFWAKEUP_IE();\r
+void http_send_packet_VIT_IE();\r
+void http_send_packet_waveform_IE();\r
+void http_send_packet_SLEEPING_STOPWATCH_IE();\r
+void http_send_packet_DAC_IE();\r
+void http_send_packet_multimeter_IE();\r
+void http_send_packet_RTDD_IE();\r
+#endif /*TCPIP_H_*/\r
--- /dev/null
+/*******************************************************************************\r
+ * (c) Copyright 2009 Actel Corporation. All rights reserved.\r
+ * \r
+ * SVN $Revision: 2905 $\r
+ * SVN $Date: 2010-08-20 14:03:28 +0100 (Fri, 20 Aug 2010) $\r
+ */\r
+#include "mss_ace.h"\r
+#include "mss_ace_configurator.h"\r
+#include "../../CMSIS/a2fxxxm3.h"\r
+#include "../../CMSIS/mss_assert.h"\r
+#include "../../drivers_config/mss_ace/ace_handles.h"\r
+#include "../../drivers_config/mss_ace/ace_config.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif \r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+extern ace_channel_desc_t g_ace_channel_desc_table[ACE_NB_OF_INPUT_CHANNELS];\r
+extern ace_adc_config_t g_ace_adc_config[ACE_NB_OF_ADC];\r
+extern const uint32_t g_ace_current_resistors[ACE_NB_OF_CURRENT_MONITORS];\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+static uint16_t convert_mV_to_ppe_value\r
+(\r
+ ace_channel_handle_t channel_handle,\r
+ uint32_t voltage\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+void ace_init_convert(void);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ * \r
+ */\r
+#define VOLTAGE_CHANNEL 0u\r
+#define CURRENT_CHANNEL 1u\r
+#define TEMPERATURE_CHANNEL 2u\r
+#define INVALID_CHANNEL 0xFFu\r
+\r
+static const uint8_t channel_type_lut[] =\r
+{\r
+ VOLTAGE_CHANNEL, /* ADC0_1P5V = 0 */\r
+ VOLTAGE_CHANNEL, /* ABPS0 = 1 */\r
+ VOLTAGE_CHANNEL, /* ABPS1 = 2 */\r
+ CURRENT_CHANNEL, /* CM0 = 3 */\r
+ TEMPERATURE_CHANNEL, /* TM0 = 4 */\r
+ VOLTAGE_CHANNEL, /* ABPS2 = 5 */\r
+ VOLTAGE_CHANNEL, /* ABPS3 = 6 */\r
+ CURRENT_CHANNEL, /* CM1 = 7 */\r
+ TEMPERATURE_CHANNEL, /* TM1 = 8 */\r
+ VOLTAGE_CHANNEL, /* ADC0 = 9 */\r
+ VOLTAGE_CHANNEL, /* ADC1 = 10 */\r
+ VOLTAGE_CHANNEL, /* ADC2 = 11 */\r
+ VOLTAGE_CHANNEL, /* ADC3 = 12 */\r
+ INVALID_CHANNEL,\r
+ INVALID_CHANNEL,\r
+ VOLTAGE_CHANNEL, /* SDD0_IN = 15 */\r
+\r
+ VOLTAGE_CHANNEL, /* ADC1_1P5V = 16 */\r
+ VOLTAGE_CHANNEL, /* ABPS4 = 17 */\r
+ VOLTAGE_CHANNEL, /* ABPS5 = 18 */\r
+ CURRENT_CHANNEL, /* CM2 = 19 */\r
+ TEMPERATURE_CHANNEL, /* TM2 = 20 */\r
+ VOLTAGE_CHANNEL, /* ABPS6 = 21 */\r
+ VOLTAGE_CHANNEL, /* ABPS7 = 22 */\r
+ CURRENT_CHANNEL, /* CM3 = 23 */\r
+ TEMPERATURE_CHANNEL, /* TM3 = 24 */\r
+ VOLTAGE_CHANNEL, /* ADC4 = 25 */\r
+ VOLTAGE_CHANNEL, /* ADC5 = 26 */\r
+ VOLTAGE_CHANNEL, /* ADC6 = 27 */\r
+ VOLTAGE_CHANNEL, /* ADC7 = 28 */\r
+ INVALID_CHANNEL,\r
+ INVALID_CHANNEL,\r
+ VOLTAGE_CHANNEL, /* SDD1_IN = 31 */\r
+\r
+ VOLTAGE_CHANNEL, /* ADC2_1P5V = 32 */\r
+ VOLTAGE_CHANNEL, /* ABPS8 = 33 */\r
+ VOLTAGE_CHANNEL, /* ABPS9 = 34 */\r
+ CURRENT_CHANNEL, /* CM4 = 35 */\r
+ TEMPERATURE_CHANNEL, /* TM4 = 36 */\r
+ VOLTAGE_CHANNEL, /* ABPS10 = 37 */\r
+ VOLTAGE_CHANNEL, /* ABPS11 = 38 */\r
+ CURRENT_CHANNEL, /* CM5 = 39 */\r
+ TEMPERATURE_CHANNEL, /* TM5 = 40 */\r
+ VOLTAGE_CHANNEL, /* ADC8 = 41 */\r
+ VOLTAGE_CHANNEL, /* ADC9 = 42 */\r
+ VOLTAGE_CHANNEL, /* ADC10 = 43 */\r
+ VOLTAGE_CHANNEL, /* ADC11 = 44 */\r
+ INVALID_CHANNEL,\r
+ INVALID_CHANNEL,\r
+ VOLTAGE_CHANNEL /* SDD2_IN = 47 */\r
+};\r
+\r
+static const uint8_t channel_quad_lut[] =\r
+{\r
+ 0xFFu, /* ADC0_1P5V = 0 */\r
+ 0u, /* ABPS0 = 1 */\r
+ 0u, /* ABPS1 = 2 */\r
+ 0u, /* CM0 = 3 */\r
+ 0u, /* TM0 = 4 */\r
+ 1u, /* ABPS2 = 5 */\r
+ 1u, /* ABPS3 = 6 */\r
+ 1u, /* CM1 = 7 */\r
+ 1u, /* TM1 = 8 */\r
+ 0xFFu, /* ADC0 = 9 */\r
+ 0xFFu, /* ADC1 = 10 */\r
+ 0xFFu, /* ADC2 = 11 */\r
+ 0xFFu, /* ADC3 = 12 */\r
+ INVALID_CHANNEL,\r
+ INVALID_CHANNEL,\r
+ 0xFFu, /* SDD0_IN = 15 */\r
+\r
+ 0xFFu, /* ADC1_1P5V = 16 */\r
+ 2u, /* ABPS4 = 17 */\r
+ 2u, /* ABPS5 = 18 */\r
+ 2u, /* CM2 = 19 */\r
+ 2u, /* TM2 = 20 */\r
+ 3u, /* ABPS6 = 21 */\r
+ 3u, /* ABPS7 = 22 */\r
+ 3u, /* CM3 = 23 */\r
+ 3u, /* TM3 = 24 */\r
+ 0xFFu, /* ADC4 = 25 */\r
+ 0xFFu, /* ADC5 = 26 */\r
+ 0xFFu, /* ADC6 = 27 */\r
+ 0xFFu, /* ADC7 = 28 */\r
+ INVALID_CHANNEL,\r
+ INVALID_CHANNEL,\r
+ 0xFFu, /* SDD1_IN = 31 */\r
+\r
+ 0xFFu, /* ADC2_1P5V = 32 */\r
+ 4u, /* ABPS8 = 33 */\r
+ 4u, /* ABPS9 = 34 */\r
+ 4u, /* CM4 = 35 */\r
+ 4u, /* TM4 = 36 */\r
+ 5u, /* ABPS10 = 37 */\r
+ 5u, /* ABPS11 = 38 */\r
+ 5u, /* CM5 = 39 */\r
+ 5u, /* TM5 = 40 */\r
+ 0xFFu, /* ADC8 = 41 */\r
+ 0xFFu, /* ADC9 = 42 */\r
+ 0xFFu, /* ADC10 = 43 */\r
+ 0xFFu, /* ADC11 = 44 */\r
+ INVALID_CHANNEL,\r
+ INVALID_CHANNEL,\r
+ 0xFFu /* SDD2_IN = 47 */\r
+};\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+#define NON_ABPS_CHANNEL 0xFFu\r
+#define MAX_NB_OF_APBS 12u\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ * Lookup of the quad to which an ABPS belongs\r
+ */\r
+static const uint8_t abps_channel_lut[] =\r
+{\r
+ NON_ABPS_CHANNEL, /* ADC0_1P5V = 0 */\r
+ 0u, /* ABPS0 = 1 */\r
+ 0u, /* ABPS1 = 2 */\r
+ NON_ABPS_CHANNEL, /* CM0 = 3 */\r
+ NON_ABPS_CHANNEL, /* TM0 = 4 */\r
+ 1u, /* ABPS2 = 5 */\r
+ 1u, /* ABPS3 = 6 */\r
+ NON_ABPS_CHANNEL, /* CM1 = 7 */\r
+ NON_ABPS_CHANNEL, /* TM1 = 8 */\r
+ NON_ABPS_CHANNEL, /* ADC0 = 9 */\r
+ NON_ABPS_CHANNEL, /* ADC1 = 10 */\r
+ NON_ABPS_CHANNEL, /* ADC2 = 11 */\r
+ NON_ABPS_CHANNEL, /* ADC3 = 12 */\r
+ INVALID_CHANNEL,\r
+ INVALID_CHANNEL,\r
+ NON_ABPS_CHANNEL, /* SDD0_IN = 15 */\r
+\r
+ NON_ABPS_CHANNEL, /* ADC1_1P5V = 16 */\r
+ 2u, /* ABPS4 = 17 */\r
+ 2u, /* ABPS5 = 18 */\r
+ NON_ABPS_CHANNEL, /* CM2 = 19 */\r
+ NON_ABPS_CHANNEL, /* TM2 = 20 */\r
+ 3u, /* ABPS6 = 21 */\r
+ 3u, /* ABPS7 = 22 */\r
+ NON_ABPS_CHANNEL, /* CM3 = 23 */\r
+ NON_ABPS_CHANNEL, /* TM3 = 24 */\r
+ NON_ABPS_CHANNEL, /* ADC4 = 25 */\r
+ NON_ABPS_CHANNEL, /* ADC5 = 26 */\r
+ NON_ABPS_CHANNEL, /* ADC6 = 27 */\r
+ NON_ABPS_CHANNEL, /* ADC7 = 28 */\r
+ INVALID_CHANNEL,\r
+ INVALID_CHANNEL,\r
+ NON_ABPS_CHANNEL, /* SDD1_IN = 31 */\r
+\r
+ NON_ABPS_CHANNEL, /* ADC2_1P5V = 32 */\r
+ 4u, /* ABPS8 = 33 */\r
+ 4u, /* ABPS9 = 34 */\r
+ NON_ABPS_CHANNEL, /* CM4 = 35 */\r
+ NON_ABPS_CHANNEL, /* TM4 = 36 */\r
+ 5u, /* ABPS10 = 37 */\r
+ 5u, /* ABPS11 = 38 */\r
+ NON_ABPS_CHANNEL, /* CM5 = 39 */\r
+ NON_ABPS_CHANNEL, /* TM5 = 40 */\r
+ NON_ABPS_CHANNEL, /* ADC8 = 41 */\r
+ NON_ABPS_CHANNEL, /* ADC9 = 42 */\r
+ NON_ABPS_CHANNEL, /* ADC10 = 43 */\r
+ NON_ABPS_CHANNEL, /* ADC11 = 44 */\r
+ INVALID_CHANNEL,\r
+ INVALID_CHANNEL,\r
+ NON_ABPS_CHANNEL /* SDD2_IN = 47 */\r
+};\r
+\r
+static const uint8_t abps_idx_lut[] =\r
+{\r
+ NON_ABPS_CHANNEL, /* ADC0_1P5V = 0 */\r
+ 0u, /* ABPS0 = 1 */\r
+ 1u, /* ABPS1 = 2 */\r
+ NON_ABPS_CHANNEL, /* CM0 = 3 */\r
+ NON_ABPS_CHANNEL, /* TM0 = 4 */\r
+ 2u, /* ABPS2 = 5 */\r
+ 3u, /* ABPS3 = 6 */\r
+ NON_ABPS_CHANNEL, /* CM1 = 7 */\r
+ NON_ABPS_CHANNEL, /* TM1 = 8 */\r
+ NON_ABPS_CHANNEL, /* ADC0 = 9 */\r
+ NON_ABPS_CHANNEL, /* ADC1 = 10 */\r
+ NON_ABPS_CHANNEL, /* ADC2 = 11 */\r
+ NON_ABPS_CHANNEL, /* ADC3 = 12 */\r
+ INVALID_CHANNEL,\r
+ INVALID_CHANNEL,\r
+ NON_ABPS_CHANNEL, /* SDD0_IN = 15 */\r
+\r
+ NON_ABPS_CHANNEL, /* ADC1_1P5V = 16 */\r
+ 4u, /* ABPS4 = 17 */\r
+ 5u, /* ABPS5 = 18 */\r
+ NON_ABPS_CHANNEL, /* CM2 = 19 */\r
+ NON_ABPS_CHANNEL, /* TM2 = 20 */\r
+ 6u, /* ABPS6 = 21 */\r
+ 7u, /* ABPS7 = 22 */\r
+ NON_ABPS_CHANNEL, /* CM3 = 23 */\r
+ NON_ABPS_CHANNEL, /* TM3 = 24 */\r
+ NON_ABPS_CHANNEL, /* ADC4 = 25 */\r
+ NON_ABPS_CHANNEL, /* ADC5 = 26 */\r
+ NON_ABPS_CHANNEL, /* ADC6 = 27 */\r
+ NON_ABPS_CHANNEL, /* ADC7 = 28 */\r
+ INVALID_CHANNEL,\r
+ INVALID_CHANNEL,\r
+ NON_ABPS_CHANNEL, /* SDD1_IN = 31 */\r
+\r
+ NON_ABPS_CHANNEL, /* ADC2_1P5V = 32 */\r
+ 8u, /* ABPS8 = 33 */\r
+ 9u, /* ABPS9 = 34 */\r
+ NON_ABPS_CHANNEL, /* CM4 = 35 */\r
+ NON_ABPS_CHANNEL, /* TM4 = 36 */\r
+ 10u, /* ABPS10 = 37 */\r
+ 11u, /* ABPS11 = 38 */\r
+ NON_ABPS_CHANNEL, /* CM5 = 39 */\r
+ NON_ABPS_CHANNEL, /* TM5 = 40 */\r
+ NON_ABPS_CHANNEL, /* ADC8 = 41 */\r
+ NON_ABPS_CHANNEL, /* ADC9 = 42 */\r
+ NON_ABPS_CHANNEL, /* ADC10 = 43 */\r
+ NON_ABPS_CHANNEL, /* ADC11 = 44 */\r
+ INVALID_CHANNEL,\r
+ INVALID_CHANNEL,\r
+ NON_ABPS_CHANNEL /* SDD2_IN = 47 */\r
+};\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+static const int8_t apbs_gain_lut[] =\r
+{\r
+ 12,\r
+ 8,\r
+ 4,\r
+ 2\r
+};\r
+\r
+static const int16_t apbs_range[] =\r
+{\r
+ 15360,\r
+ 10240,\r
+ 5120,\r
+ 2560\r
+};\r
+\r
+static uint8_t g_gdec_lut[MAX_NB_OF_APBS];\r
+static channel_type_t channel_type_lut_h[ACE_NB_OF_INPUT_CHANNELS];\r
+\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+channel_type_t\r
+ACE_get_channel_type\r
+(\r
+ ace_channel_handle_t channel_handle\r
+)\r
+{\r
+ channel_type_t channel_type = VOLTAGE;\r
+ \r
+ ASSERT(channel_handle < ACE_NB_OF_INPUT_CHANNELS);\r
+ \r
+ if((int32_t)channel_handle < ACE_NB_OF_INPUT_CHANNELS)\r
+ {\r
+ channel_type = channel_type_lut_h[channel_handle];\r
+ }\r
+ else\r
+ {\r
+ channel_type = VOLTAGE;\r
+ }\r
+ \r
+ return channel_type;\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+uint32_t ACE_convert_adc_input_to_mV\r
+(\r
+ ace_channel_handle_t channel_handle,\r
+ uint16_t sample_value\r
+)\r
+{\r
+ uint32_t voltage;\r
+ adc_channel_id_t channel_id;\r
+ uint8_t adc_id;\r
+ \r
+ channel_id = g_ace_channel_desc_table[channel_handle].signal_id;\r
+ adc_id = (uint8_t)channel_id >> 4u;\r
+ voltage = ( g_ace_adc_config[adc_id].va_ref * (uint32_t)sample_value ) / g_ace_adc_config[adc_id].adc_resolution;\r
+ \r
+ return voltage;\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+#define PPE_SAMPLES_RESOLUTION 4095u\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+void ace_init_convert(void)\r
+{\r
+ uint8_t abps_idx;\r
+ int32_t channel;\r
+ uint32_t saved_pc2_ctrl;\r
+ \r
+ /* Pause the SSE PC2 while accesses to ACB from APB3 are taking place. */\r
+ saved_pc2_ctrl = ACE->PC2_CTRL;\r
+ ACE->PC2_CTRL = 0u;\r
+ \r
+ /* Populate the g_gdec_lut look-up table. */\r
+ for(abps_idx = 0u; abps_idx < MAX_NB_OF_APBS; ++abps_idx)\r
+ {\r
+ uint8_t quad_id;\r
+ uint8_t acb_config_byte;\r
+ uint32_t channel_is_abps2;\r
+ \r
+ quad_id = abps_idx / 2u;\r
+ acb_config_byte = ACE->ACB_DATA[quad_id].b8;\r
+ channel_is_abps2 = abps_idx & 0x01uL;\r
+ if(channel_is_abps2)\r
+ {\r
+ /* ABPS2 */\r
+ g_gdec_lut[abps_idx] = (acb_config_byte >> 5u) & 0x03u;\r
+ }\r
+ else\r
+ {\r
+ /* ABPS1 */\r
+ g_gdec_lut[abps_idx] = (acb_config_byte >> 1u) & 0x03u;\r
+ }\r
+ }\r
+ \r
+ /* Populate the channel_type_lut_h look-up table. */\r
+ for(channel = 0; channel < ACE_NB_OF_INPUT_CHANNELS; ++channel)\r
+ {\r
+ uint8_t quad_id;\r
+ uint8_t acb_config_byte;\r
+ adc_channel_id_t channel_id;\r
+ channel_type_t channel_type;\r
+ \r
+ channel_id = g_ace_channel_desc_table[channel].signal_id;\r
+ quad_id = channel_quad_lut[channel_id];\r
+ \r
+ switch (channel_type_lut[channel_id])\r
+ {\r
+ case VOLTAGE_CHANNEL:\r
+ channel_type = VOLTAGE;\r
+ break;\r
+ \r
+ case CURRENT_CHANNEL:\r
+ ASSERT( quad_id != 0xFFu );\r
+ acb_config_byte = ACE->ACB_DATA[quad_id].b9;\r
+ if ( acb_config_byte & 0x01u )\r
+ {\r
+ channel_type = VOLTAGE;\r
+ }\r
+ else\r
+ {\r
+ channel_type = CURRENT;\r
+ }\r
+ break;\r
+ \r
+ case TEMPERATURE_CHANNEL:\r
+ ASSERT( quad_id != 0xFFu );\r
+ acb_config_byte = ACE->ACB_DATA[quad_id].b10;\r
+ if ( acb_config_byte & 0x01u )\r
+ {\r
+ channel_type = VOLTAGE;\r
+ }\r
+ else\r
+ {\r
+ channel_type = TEMPERATURE;\r
+ }\r
+ break;\r
+ \r
+ default:\r
+ ASSERT(0);\r
+ channel_type = VOLTAGE;\r
+ break;\r
+ }\r
+ \r
+ channel_type_lut_h[channel] = channel_type;\r
+ }\r
+ \r
+ /* Restore SSE PC2 operations. */\r
+ ACE->PC2_CTRL = saved_pc2_ctrl;\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+int32_t ACE_convert_to_mV\r
+(\r
+ ace_channel_handle_t channel_handle,\r
+ uint16_t sample_value\r
+)\r
+{\r
+ uint32_t adc_voltage;\r
+ int32_t voltage;\r
+ adc_channel_id_t channel_id;\r
+ uint8_t adc_id;\r
+ uint8_t apbs_idx;\r
+ \r
+ channel_id = g_ace_channel_desc_table[channel_handle].signal_id;\r
+ adc_id = (uint8_t)channel_id >> 4u;\r
+ adc_voltage = ( g_ace_adc_config[adc_id].va_ref * (uint32_t)sample_value ) / PPE_SAMPLES_RESOLUTION;\r
+ voltage = (int32_t)adc_voltage;\r
+\r
+ apbs_idx = abps_idx_lut[channel_id];\r
+ if ( abps_channel_lut[channel_id] != NON_ABPS_CHANNEL )\r
+ {\r
+ uint8_t gdec;\r
+ gdec = g_gdec_lut[apbs_idx];\r
+ voltage = (voltage * apbs_gain_lut[gdec]) - apbs_range[gdec];\r
+ }\r
+ return voltage;\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+uint32_t ACE_convert_to_mA\r
+(\r
+ ace_channel_handle_t channel_handle,\r
+ uint16_t sample_value\r
+)\r
+{\r
+ uint32_t current = 0u;\r
+ \r
+ ASSERT(channel_handle < ACE_NB_OF_INPUT_CHANNELS);\r
+ \r
+ if((int32_t)channel_handle < ACE_NB_OF_INPUT_CHANNELS)\r
+ {\r
+ adc_channel_id_t channel_id;\r
+ uint8_t current_monitor_idx;\r
+ \r
+ channel_id = g_ace_channel_desc_table[channel_handle].signal_id;\r
+ ASSERT(channel_id < sizeof(channel_type_lut));\r
+ if(CURRENT_CHANNEL == channel_type_lut[channel_id])\r
+ {\r
+ uint32_t resistor;\r
+ uint32_t voltage;\r
+ \r
+ /* Compute index into g_ace_current_resistors[] from the current\r
+ * channel number. This uses bit 2, 4 and 5 of the channel number\r
+ * to derive the index as follows:\r
+ * channel name : channel number : index\r
+ * CM0 : 0x03 : 0\r
+ * CM1 : 0x07 : 1\r
+ * CM2 : 0x13 : 2\r
+ * CM3 : 0x17 : 3\r
+ * CM4 : 0x23 : 4\r
+ * CM5 : 0x27 : 5\r
+ */\r
+ current_monitor_idx\r
+ = (((uint8_t)channel_id & 0x04u) >> 2u) + (((uint8_t)channel_id & 0x30u) >> 3u);\r
+ \r
+ if(current_monitor_idx < (uint8_t)ACE_NB_OF_CURRENT_MONITORS)\r
+ {\r
+ /* Retrieve the current sensing external resistor value from \r
+ * the ACE configuration data generated by the ACE configurator. */\r
+ resistor = g_ace_current_resistors[current_monitor_idx];\r
+ \r
+ /* Compute mA current value taking into account the amplication\r
+ * factor of 50 used within the current monitor hardware. */\r
+ voltage = ACE_convert_adc_input_to_mV(channel_handle, sample_value);\r
+ current = (voltage * (1000u / 50u)) / resistor;\r
+;\r
+ }\r
+ }\r
+ }\r
+ \r
+ return current;\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+uint32_t ACE_convert_to_Kelvin\r
+(\r
+ ace_channel_handle_t channel_handle,\r
+ uint16_t sample_value\r
+)\r
+{\r
+ uint32_t temperature;\r
+ uint32_t voltage;\r
+ \r
+ voltage = ACE_convert_adc_input_to_mV( channel_handle, sample_value );\r
+ \r
+ /* Tk = (V * 10^3) / 2.5 */\r
+ temperature = (voltage * 10u) / 25u;\r
+ \r
+ return temperature;\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+int32_t ACE_convert_to_Celsius\r
+(\r
+ ace_channel_handle_t channel_handle,\r
+ uint16_t sample_value\r
+)\r
+{\r
+ int32_t temperature;\r
+ int32_t voltage;\r
+ \r
+ voltage = (int32_t)ACE_convert_adc_input_to_mV( channel_handle, sample_value );\r
+ \r
+ /* Tk = (V * 10^3) / 2.5 */\r
+ /* Tc = Tk - 273.15 */\r
+ temperature = (voltage * 4) - 2731;\r
+ \r
+ return temperature;\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+int32_t ACE_convert_to_Fahrenheit\r
+(\r
+ ace_channel_handle_t channel_handle,\r
+ uint16_t sample_value\r
+)\r
+{\r
+ int32_t temperature;\r
+ \r
+ temperature = (int32_t)ACE_convert_to_Kelvin( channel_handle, sample_value );\r
+ \r
+ /* F = (K * 9/5) - 459.67 */\r
+ temperature = ((temperature * 9) / 5) - 459;\r
+ \r
+ return temperature;\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+const uint8_t * ACE_get_channel_name\r
+(\r
+ ace_channel_handle_t channel_handle\r
+)\r
+{\r
+ const uint8_t * p_channel_name = 0;\r
+ \r
+ if ( channel_handle < NB_OF_ACE_CHANNEL_HANDLES)\r
+ {\r
+ p_channel_name = g_ace_channel_desc_table[channel_handle].p_sz_channel_name;\r
+ }\r
+ \r
+ return p_channel_name;\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+uint16_t ACE_convert_mV_to_adc_value\r
+(\r
+ ace_channel_handle_t channel_handle,\r
+ uint32_t voltage\r
+)\r
+{\r
+ uint16_t sample_value;\r
+ adc_channel_id_t channel_id;\r
+ uint8_t adc_id;\r
+ \r
+ channel_id = g_ace_channel_desc_table[channel_handle].signal_id;\r
+ adc_id = (uint8_t)channel_id >> 4u;\r
+ \r
+ if (voltage > g_ace_adc_config[adc_id].va_ref)\r
+ {\r
+ sample_value = g_ace_adc_config[adc_id].adc_resolution - 1u;\r
+ }\r
+ else\r
+ {\r
+ sample_value = (uint16_t)((voltage * (g_ace_adc_config[adc_id].adc_resolution - 1)) / g_ace_adc_config[adc_id].va_ref);\r
+ }\r
+ \r
+ return sample_value;\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+static uint16_t convert_mV_to_ppe_value\r
+(\r
+ ace_channel_handle_t channel_handle,\r
+ uint32_t voltage\r
+)\r
+{\r
+ uint16_t sample_value;\r
+ adc_channel_id_t channel_id;\r
+ uint8_t adc_id;\r
+ \r
+ channel_id = g_ace_channel_desc_table[channel_handle].signal_id;\r
+ adc_id = (uint8_t)channel_id >> 4u;\r
+ \r
+ if (voltage > g_ace_adc_config[adc_id].va_ref)\r
+ {\r
+ sample_value = PPE_SAMPLES_RESOLUTION;\r
+ }\r
+ else\r
+ {\r
+ sample_value = (uint16_t)((voltage * PPE_SAMPLES_RESOLUTION) / g_ace_adc_config[adc_id].va_ref);\r
+ }\r
+ \r
+ return sample_value;\r
+}\r
+\r
+#define MAX_PPE_SAMPLE_VALUE 0x0FFFu\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+uint16_t ACE_convert_from_mV\r
+(\r
+ ace_channel_handle_t channel_handle,\r
+ int32_t voltage\r
+)\r
+{\r
+ uint16_t sample_value;\r
+ adc_channel_id_t channel_id;\r
+ uint8_t adc_id;\r
+ uint32_t adc_voltage;\r
+ \r
+ channel_id = g_ace_channel_desc_table[channel_handle].signal_id;\r
+ adc_id = (uint8_t)channel_id >> 4u;\r
+ \r
+ if ( abps_channel_lut[channel_id] == NON_ABPS_CHANNEL )\r
+ {\r
+ if (voltage > 0)\r
+ {\r
+ adc_voltage = (uint32_t)voltage;\r
+ }\r
+ else\r
+ {\r
+ adc_voltage = 0u;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ uint8_t apbs_idx;\r
+ uint8_t gdec;\r
+ \r
+ apbs_idx = abps_idx_lut[channel_id];\r
+ gdec = g_gdec_lut[apbs_idx];\r
+ voltage = voltage + apbs_range[gdec];\r
+ if (voltage > 0)\r
+ {\r
+ adc_voltage = (uint32_t)voltage;\r
+ adc_voltage = adc_voltage / (uint8_t)apbs_gain_lut[gdec];\r
+ }\r
+ else\r
+ {\r
+ adc_voltage = 0;\r
+ }\r
+ }\r
+ \r
+ sample_value = (uint16_t)((adc_voltage * PPE_SAMPLES_RESOLUTION) / g_ace_adc_config[adc_id].va_ref);\r
+ \r
+ if (sample_value > MAX_PPE_SAMPLE_VALUE)\r
+ {\r
+ sample_value = MAX_PPE_SAMPLE_VALUE;\r
+ }\r
+ return sample_value;\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+uint16_t ACE_convert_from_mA\r
+(\r
+ ace_channel_handle_t channel_handle,\r
+ uint32_t current\r
+)\r
+{\r
+ uint16_t sample_value;\r
+ uint32_t voltage;\r
+ uint32_t resistor = 1u;\r
+ \r
+ voltage = current * 50u * resistor;\r
+ sample_value = convert_mV_to_ppe_value( channel_handle, voltage );\r
+ \r
+ if (sample_value > MAX_PPE_SAMPLE_VALUE)\r
+ {\r
+ sample_value = MAX_PPE_SAMPLE_VALUE;\r
+ }\r
+ return sample_value;\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+uint16_t ACE_convert_from_Kelvin\r
+(\r
+ ace_channel_handle_t channel_handle,\r
+ uint32_t temperature\r
+)\r
+{\r
+ uint16_t sample_value;\r
+ uint32_t voltage;\r
+ \r
+ voltage = (temperature * 25u) / 10u;\r
+ sample_value = convert_mV_to_ppe_value( channel_handle, voltage );\r
+ \r
+ if (sample_value > MAX_PPE_SAMPLE_VALUE)\r
+ {\r
+ sample_value = MAX_PPE_SAMPLE_VALUE;\r
+ }\r
+ return sample_value;\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+uint16_t ACE_convert_from_Celsius\r
+(\r
+ ace_channel_handle_t channel_handle,\r
+ int32_t temperature\r
+)\r
+{\r
+ uint16_t sample_value;\r
+ uint32_t voltage;\r
+ \r
+ temperature = temperature + 2731;\r
+ voltage = (uint32_t)temperature / 4u;\r
+ sample_value = convert_mV_to_ppe_value( channel_handle, voltage );\r
+ \r
+ if (sample_value > MAX_PPE_SAMPLE_VALUE)\r
+ {\r
+ sample_value = MAX_PPE_SAMPLE_VALUE;\r
+ }\r
+ return sample_value;\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+uint16_t ACE_convert_from_Fahrenheit\r
+(\r
+ ace_channel_handle_t channel_handle,\r
+ int32_t temperature\r
+)\r
+{\r
+ uint16_t sample_value;\r
+ uint32_t kelvin;\r
+ \r
+ temperature = temperature + 459;\r
+ kelvin = (uint32_t)temperature;\r
+ kelvin = (kelvin * 5u) / 9u;\r
+ \r
+ sample_value = ACE_convert_from_Kelvin( channel_handle, kelvin );\r
+ \r
+ if (sample_value > MAX_PPE_SAMPLE_VALUE)\r
+ {\r
+ sample_value = MAX_PPE_SAMPLE_VALUE;\r
+ }\r
+ return sample_value;\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+uint16_t ACE_translate_pdma_value\r
+(\r
+ uint32_t pdma_value,\r
+ adc_channel_id_t * channel_id\r
+)\r
+{\r
+ uint16_t ppe_value;\r
+ \r
+ ppe_value = (pdma_value >> 8u) & 0xFFFFu;\r
+ if ( channel_id != 0 )\r
+ {\r
+ *channel_id = (adc_channel_id_t)((pdma_value >> 24u) & 0xFFu);\r
+ }\r
+ \r
+ return ppe_value;\r
+}\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
--- /dev/null
+/*******************************************************************************\r
+ * (c) Copyright 2009 Actel Corporation. All rights reserved.\r
+ * \r
+ * SVN $Revision: 2840 $\r
+ * SVN $Date: 2010-07-20 17:00:32 +0100 (Tue, 20 Jul 2010) $\r
+ */\r
+#include "mss_ace.h"\r
+#include "mss_ace_configurator.h"\r
+#include "../../CMSIS/a2fxxxm3.h"\r
+#include "../../CMSIS/mss_assert.h"\r
+#include "../../drivers_config/mss_ace/ace_handles.h"\r
+#include "../../drivers_config/mss_ace/ace_config.h"\r
+#include <string.h>\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif \r
+\r
+#define MAX_FULL_FLAG_NAME_LENGTH (MAX_CHANNEL_NAME_LENGTH + MAX_FLAG_NAME_LENGTH + 1)\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ * Number of flag types supported.\r
+ * the supported flag types are:\r
+ * - BASIC_THRESHOLD_OVER\r
+ * - BASIC_THRESHOLD_UNDER\r
+ * - STATE_FILTERED_OVER\r
+ * - STATE_FILTERED_UNDER\r
+ * - DUAL_HYSTERESIS_OVER\r
+ * - DUAL_HYSTERESIS_UNDER\r
+ * - IPMI_HYSTERESIS_OVER\r
+ * - IPMI_HYSTERESIS_UNDER\r
+ */\r
+#define NB_OF_FLAG_TYPES 8\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+#define THRESHOLD_FLAG0 0u\r
+#define THRESHOLD_FLAG1 1u\r
+#define THRESHOLD_FLAG2 2u\r
+#define THRESHOLD_FLAG3 3u\r
+#define THRESHOLD_FLAG4 4u\r
+#define THRESHOLD_FLAG5 5u\r
+#define THRESHOLD_FLAG6 6u\r
+#define THRESHOLD_FLAG7 7u\r
+#define THRESHOLD_FLAG8 8u\r
+#define THRESHOLD_FLAG9 9u\r
+#define THRESHOLD_FLAG10 10u\r
+#define THRESHOLD_FLAG11 11u\r
+#define THRESHOLD_FLAG12 12u\r
+#define THRESHOLD_FLAG13 13u\r
+#define THRESHOLD_FLAG14 14u\r
+#define THRESHOLD_FLAG15 15u\r
+#define THRESHOLD_FLAG16 16u\r
+#define THRESHOLD_FLAG17 17u\r
+#define THRESHOLD_FLAG18 18u\r
+#define THRESHOLD_FLAG19 19u\r
+#define THRESHOLD_FLAG20 20u\r
+#define THRESHOLD_FLAG21 21u\r
+#define THRESHOLD_FLAG22 22u\r
+#define THRESHOLD_FLAG23 23u\r
+#define THRESHOLD_FLAG24 24u\r
+#define THRESHOLD_FLAG25 25u\r
+#define THRESHOLD_FLAG26 26u\r
+#define THRESHOLD_FLAG27 27u\r
+#define THRESHOLD_FLAG28 28u\r
+#define THRESHOLD_FLAG29 29u\r
+#define THRESHOLD_FLAG30 30u\r
+#define THRESHOLD_FLAG31 31u\r
+#define NB_OF_THRESHOLD_IRQ 32u\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+void ace_init_flags( void );\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ * Flag interrupots routines function prototypes\r
+ */\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void ACE_PPE_Flag0_IRQHandler( void );\r
+#else\r
+void ACE_PPE_Flag0_IRQHandler( void );\r
+#endif\r
+\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void ACE_PPE_Flag1_IRQHandler( void );\r
+#else\r
+void ACE_PPE_Flag1_IRQHandler( void );\r
+#endif\r
+\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void ACE_PPE_Flag2_IRQHandler( void );\r
+#else\r
+void ACE_PPE_Flag2_IRQHandler( void );\r
+#endif\r
+\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void ACE_PPE_Flag3_IRQHandler( void );\r
+#else\r
+void ACE_PPE_Flag3_IRQHandler( void );\r
+#endif\r
+\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void ACE_PPE_Flag4_IRQHandler( void );\r
+#else\r
+void ACE_PPE_Flag4_IRQHandler( void );\r
+#endif\r
+\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void ACE_PPE_Flag5_IRQHandler( void );\r
+#else\r
+void ACE_PPE_Flag5_IRQHandler( void );\r
+#endif\r
+\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void ACE_PPE_Flag6_IRQHandler( void );\r
+#else\r
+void ACE_PPE_Flag6_IRQHandler( void );\r
+#endif\r
+\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void ACE_PPE_Flag7_IRQHandler( void );\r
+#else\r
+void ACE_PPE_Flag7_IRQHandler( void );\r
+#endif\r
+\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void ACE_PPE_Flag8_IRQHandler( void );\r
+#else\r
+void ACE_PPE_Flag8_IRQHandler( void );\r
+#endif\r
+\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void ACE_PPE_Flag9_IRQHandler( void );\r
+#else\r
+void ACE_PPE_Flag9_IRQHandler( void );\r
+#endif\r
+\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void ACE_PPE_Flag10_IRQHandler( void );\r
+#else\r
+void ACE_PPE_Flag10_IRQHandler( void );\r
+#endif\r
+\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void ACE_PPE_Flag11_IRQHandler( void );\r
+#else\r
+void ACE_PPE_Flag11_IRQHandler( void );\r
+#endif\r
+\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void ACE_PPE_Flag12_IRQHandler( void );\r
+#else\r
+void ACE_PPE_Flag12_IRQHandler( void );\r
+#endif\r
+\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void ACE_PPE_Flag13_IRQHandler( void );\r
+#else\r
+void ACE_PPE_Flag13_IRQHandler( void );\r
+#endif\r
+\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void ACE_PPE_Flag14_IRQHandler( void );\r
+#else\r
+void ACE_PPE_Flag14_IRQHandler( void );\r
+#endif\r
+\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void ACE_PPE_Flag15_IRQHandler( void );\r
+#else\r
+void ACE_PPE_Flag15_IRQHandler( void );\r
+#endif\r
+\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void ACE_PPE_Flag16_IRQHandler( void );\r
+#else\r
+void ACE_PPE_Flag16_IRQHandler( void );\r
+#endif\r
+\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void ACE_PPE_Flag17_IRQHandler( void );\r
+#else\r
+void ACE_PPE_Flag17_IRQHandler( void );\r
+#endif\r
+\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void ACE_PPE_Flag18_IRQHandler( void );\r
+#else\r
+void ACE_PPE_Flag18_IRQHandler( void );\r
+#endif\r
+\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void ACE_PPE_Flag19_IRQHandler( void );\r
+#else\r
+void ACE_PPE_Flag19_IRQHandler( void );\r
+#endif\r
+\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void ACE_PPE_Flag20_IRQHandler( void );\r
+#else\r
+void ACE_PPE_Flag20_IRQHandler( void );\r
+#endif\r
+\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void ACE_PPE_Flag21_IRQHandler( void );\r
+#else\r
+void ACE_PPE_Flag21_IRQHandler( void );\r
+#endif\r
+\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void ACE_PPE_Flag22_IRQHandler( void );\r
+#else\r
+void ACE_PPE_Flag22_IRQHandler( void );\r
+#endif\r
+\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void ACE_PPE_Flag23_IRQHandler( void );\r
+#else\r
+void ACE_PPE_Flag23_IRQHandler( void );\r
+#endif\r
+\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void ACE_PPE_Flag24_IRQHandler( void );\r
+#else\r
+void ACE_PPE_Flag24_IRQHandler( void );\r
+#endif\r
+\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void ACE_PPE_Flag25_IRQHandler( void );\r
+#else\r
+void ACE_PPE_Flag25_IRQHandler( void );\r
+#endif\r
+\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void ACE_PPE_Flag26_IRQHandler( void );\r
+#else\r
+void ACE_PPE_Flag26_IRQHandler( void );\r
+#endif\r
+\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void ACE_PPE_Flag27_IRQHandler( void );\r
+#else\r
+void ACE_PPE_Flag27_IRQHandler( void );\r
+#endif\r
+\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void ACE_PPE_Flag28_IRQHandler( void );\r
+#else\r
+void ACE_PPE_Flag28_IRQHandler( void );\r
+#endif\r
+\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void ACE_PPE_Flag29_IRQHandler( void );\r
+#else\r
+void ACE_PPE_Flag29_IRQHandler( void );\r
+#endif\r
+\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void ACE_PPE_Flag30_IRQHandler( void );\r
+#else\r
+void ACE_PPE_Flag30_IRQHandler( void );\r
+#endif\r
+\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void ACE_PPE_Flag31_IRQHandler( void );\r
+#else\r
+void ACE_PPE_Flag31_IRQHandler( void );\r
+#endif\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+#if (ACE_NB_OF_PPE_FLAGS > 0)\r
+extern ppe_flag_desc_t g_ppe_flags_desc_table[ACE_NB_OF_PPE_FLAGS];\r
+#endif\r
+\r
+extern ace_channel_desc_t g_ace_channel_desc_table[ACE_NB_OF_INPUT_CHANNELS];\r
+\r
+extern ace_adc_config_t g_ace_adc_config[ACE_NB_OF_ADC];\r
+\r
+#if (ACE_NB_OF_PPE_FLAGS > 0)\r
+/*-------------------------------------------------------------------------*//**\r
+ Lookup table indexed on flag_id_t of the index of the flag's descriptor index\r
+ in the flag descriptors table g_ppe_flags_desc_table[]\r
+ */\r
+static ace_flag_handle_t g_ppe_flag_handles_lut[NB_OF_PPE_FLAGS];\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+static flag_isr_t g_ppe_flags_isr_lut[NB_OF_PPE_FLAGS];\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+static global_flag_isr_t g_ppe_global_flags_isr;\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+static channel_flag_isr_t g_ppe_channel_flags_isr_lut[ACE_NB_OF_INPUT_CHANNELS];\r
+#endif\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ Intialise the ACE driver's internal data structures used by flag control\r
+ functions.\r
+ */\r
+void ace_init_flags( void )\r
+{\r
+ /* Ensure the generated ACE configuration files are consistent. */\r
+ ASSERT(NB_OF_ACE_FLAG_HANDLES == ACE_NB_OF_PPE_FLAGS);\r
+ \r
+#if (ACE_NB_OF_PPE_FLAGS > 0) \r
+ {\r
+ uint8_t flag_idx;\r
+ uint8_t channel_idx;\r
+ \r
+ for ( flag_idx = 0u; flag_idx < (uint8_t)NB_OF_PPE_FLAGS; ++flag_idx )\r
+ {\r
+ g_ppe_flags_isr_lut[flag_idx] = 0;\r
+ g_ppe_flag_handles_lut[flag_idx] = INVALID_FLAG_HANDLE;\r
+ }\r
+ \r
+ for ( flag_idx = 0u; flag_idx < (uint8_t)ACE_NB_OF_PPE_FLAGS; ++flag_idx )\r
+ {\r
+ ASSERT( g_ppe_flags_desc_table[flag_idx].flag_id < NB_OF_PPE_FLAGS );\r
+ g_ppe_flag_handles_lut[g_ppe_flags_desc_table[flag_idx].flag_id] = (ace_flag_handle_t)flag_idx;\r
+ }\r
+ \r
+ for ( channel_idx = 0u; channel_idx < (uint8_t)ACE_NB_OF_INPUT_CHANNELS; ++channel_idx )\r
+ {\r
+ g_ppe_channel_flags_isr_lut[channel_idx] = 0;\r
+ }\r
+ \r
+ g_ppe_global_flags_isr = 0u;\r
+ }\r
+#endif\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+uint32_t ACE_is_hysteresis_flag( ace_flag_handle_t flag_handle )\r
+{\r
+ uint32_t hysteresis = 0u;\r
+ \r
+#if (ACE_NB_OF_PPE_FLAGS > 0)\r
+ ASSERT( flag_handle < NB_OF_ACE_FLAG_HANDLES );\r
+ \r
+ if ( g_ppe_flags_desc_table[flag_handle].flag_type >= DUAL_HYSTERESIS_OVER )\r
+ {\r
+ hysteresis = 1u;\r
+ }\r
+#endif\r
+ return hysteresis;\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+uint32_t ACE_is_under_flag\r
+(\r
+ ace_flag_handle_t flag_handle\r
+)\r
+{\r
+ uint32_t is_under = 0;\r
+ \r
+#if (ACE_NB_OF_PPE_FLAGS > 0)\r
+ const uint32_t flag_type_lut[NB_OF_FLAG_TYPES] =\r
+ {\r
+ 0, /* BASIC_THRESHOLD_OVER */\r
+ 1, /* BASIC_THRESHOLD_UNDER */\r
+ 0, /* STATE_FILTERED_OVER */\r
+ 1, /* STATE_FILTERED_UNDER */\r
+ 0, /* DUAL_HYSTERESIS_OVER */\r
+ 1, /* DUAL_HYSTERESIS_UNDER */\r
+ 0, /* IPMI_HYSTERESIS_OVER */\r
+ 1, /* IPMI_HYSTERESIS_UNDER */\r
+ };\r
+ \r
+ ASSERT(flag_handle < ACE_NB_OF_PPE_FLAGS);\r
+ if (flag_handle < ACE_NB_OF_PPE_FLAGS)\r
+ {\r
+ uint8_t flag_type;\r
+ flag_type = g_ppe_flags_desc_table[flag_handle].flag_type;\r
+ ASSERT(flag_type < NB_OF_FLAG_TYPES);\r
+ if (flag_type < NB_OF_FLAG_TYPES)\r
+ {\r
+ is_under = flag_type_lut[flag_type];\r
+ }\r
+ }\r
+#endif\r
+ return is_under;\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ Mask of the threshold value bits within a PPE RAM meory location holding the\r
+ threshold value for a flag.\r
+ */\r
+#define PPE_RAM_THRESHOLD_MASK 0x0000FFFFuL\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ * TODO: handle IPMI hysteresis flags\r
+ */\r
+void ACE_set_flag_threshold\r
+(\r
+ ace_flag_handle_t flag_handle,\r
+ uint16_t new_threshold\r
+)\r
+{\r
+#if (ACE_NB_OF_PPE_FLAGS > 0)\r
+ uint16_t ppe_offset;\r
+ \r
+ ASSERT( flag_handle < NB_OF_ACE_FLAG_HANDLES );\r
+ \r
+ if ( flag_handle < NB_OF_ACE_FLAG_HANDLES )\r
+ {\r
+ \r
+ ppe_offset = g_ppe_flags_desc_table[flag_handle].threshold_ppe_offset;\r
+ \r
+ if ( ACE_is_hysteresis_flag( flag_handle ) == 0u )\r
+ {\r
+ ACE->PPE_RAM_DATA[ppe_offset] = (ACE->PPE_RAM_DATA[ppe_offset] & (uint32_t)~PPE_RAM_THRESHOLD_MASK) + new_threshold;\r
+ }\r
+ else\r
+ {\r
+ uint16_t high_threshold;\r
+ uint16_t low_threshold;\r
+ ace_channel_handle_t channel_handle;\r
+ uint16_t hysteresis;\r
+ uint32_t adc_id;\r
+ uint16_t adc_resolution;\r
+ \r
+ high_threshold = (uint16_t)(ACE->PPE_RAM_DATA[ppe_offset] & PPE_RAM_THRESHOLD_MASK);\r
+ low_threshold = (uint16_t)(ACE->PPE_RAM_DATA[ppe_offset + 1u] & PPE_RAM_THRESHOLD_MASK);\r
+ ASSERT(high_threshold > low_threshold);\r
+ hysteresis = (uint16_t)(high_threshold - low_threshold) / 2u;\r
+ \r
+ channel_handle = g_ppe_flags_desc_table[flag_handle].channel_handle;\r
+ adc_id = (uint32_t)(g_ace_channel_desc_table[channel_handle].signal_id) >> 4u;\r
+ ASSERT( adc_id < (uint32_t)ACE_NB_OF_ADC );\r
+ \r
+ if ( adc_id < (uint32_t)ACE_NB_OF_ADC )\r
+ {\r
+ adc_resolution = g_ace_adc_config[adc_id].adc_resolution - 1u;\r
+ \r
+ high_threshold = new_threshold + hysteresis;\r
+ if ( high_threshold > adc_resolution )\r
+ {\r
+ high_threshold = adc_resolution;\r
+ }\r
+ \r
+ if ( hysteresis > new_threshold )\r
+ {\r
+ low_threshold = 1u;\r
+ }\r
+ else\r
+ {\r
+ low_threshold = new_threshold - hysteresis;\r
+ }\r
+ \r
+ ACE->PPE_RAM_DATA[ppe_offset] = (ACE->PPE_RAM_DATA[ppe_offset] & ~PPE_RAM_THRESHOLD_MASK) + high_threshold;\r
+ ACE->PPE_RAM_DATA[ppe_offset + 1u] = (ACE->PPE_RAM_DATA[ppe_offset + 1u] & (uint32_t)~PPE_RAM_THRESHOLD_MASK) + low_threshold;\r
+ }\r
+ }\r
+ }\r
+#endif\r
+}\r
+\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+#define FLAG_OVER_UNDER_MASK 0x01u\r
+#define FLAG_OVER 0x00u\r
+#define FLAF_UNDER 0x01\r
+\r
+void ACE_set_flag_assertion\r
+(\r
+ ace_flag_handle_t flag_handle,\r
+ uint16_t assertion_value\r
+)\r
+{\r
+#if (ACE_NB_OF_PPE_FLAGS > 0)\r
+ uint16_t ppe_offset;\r
+ \r
+ ASSERT( flag_handle < NB_OF_ACE_FLAG_HANDLES );\r
+ \r
+ if ( flag_handle < NB_OF_ACE_FLAG_HANDLES )\r
+ {\r
+ if (ACE_is_hysteresis_flag(flag_handle))\r
+ {\r
+ uint8_t flag_direction;\r
+ flag_direction = g_ppe_flags_desc_table[flag_handle].flag_type & FLAG_OVER_UNDER_MASK;\r
+ \r
+ if ( FLAG_OVER == flag_direction )\r
+ {\r
+ ppe_offset = g_ppe_flags_desc_table[flag_handle].threshold_ppe_offset;\r
+ }\r
+ else\r
+ {\r
+ ppe_offset = g_ppe_flags_desc_table[flag_handle].threshold_ppe_offset + 1u;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ ppe_offset = g_ppe_flags_desc_table[flag_handle].threshold_ppe_offset;\r
+ }\r
+ ACE->PPE_RAM_DATA[ppe_offset] = (ACE->PPE_RAM_DATA[ppe_offset] & ~PPE_RAM_THRESHOLD_MASK) + assertion_value;\r
+ }\r
+#endif\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+void ACE_set_flag_deassertion\r
+(\r
+ ace_flag_handle_t flag_handle,\r
+ uint16_t assertion_value\r
+)\r
+{\r
+#if (ACE_NB_OF_PPE_FLAGS > 0)\r
+ uint16_t ppe_offset;\r
+ \r
+ ASSERT( flag_handle < NB_OF_ACE_FLAG_HANDLES );\r
+ ASSERT(ACE_is_hysteresis_flag(flag_handle));\r
+ \r
+ if ((flag_handle < NB_OF_ACE_FLAG_HANDLES) && (ACE_is_hysteresis_flag(flag_handle)))\r
+ {\r
+ uint8_t flag_direction;\r
+ flag_direction = g_ppe_flags_desc_table[flag_handle].flag_type & FLAG_OVER_UNDER_MASK;\r
+ \r
+ if ( FLAG_OVER == flag_direction )\r
+ {\r
+ ppe_offset = g_ppe_flags_desc_table[flag_handle].threshold_ppe_offset + 1u;\r
+ }\r
+ else\r
+ {\r
+ ppe_offset = g_ppe_flags_desc_table[flag_handle].threshold_ppe_offset;\r
+ }\r
+ \r
+ ACE->PPE_RAM_DATA[ppe_offset] = (ACE->PPE_RAM_DATA[ppe_offset] & ~PPE_RAM_THRESHOLD_MASK) + assertion_value;\r
+ }\r
+#endif\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+void\r
+ACE_set_flag_hysteresis\r
+(\r
+ ace_flag_handle_t flag_handle,\r
+ uint16_t adc_hysteresis\r
+)\r
+{\r
+#if (ACE_NB_OF_PPE_FLAGS > 0)\r
+ uint16_t ppe_offset;\r
+ uint32_t high_threshold;\r
+ uint32_t low_threshold;\r
+ uint32_t nominal_threshold;\r
+ uint16_t adc_resolution;\r
+ uint32_t adc_id;\r
+ \r
+ ASSERT( flag_handle < NB_OF_ACE_FLAG_HANDLES );\r
+ ASSERT(ACE_is_hysteresis_flag(flag_handle));\r
+ \r
+ if ( ( flag_handle < NB_OF_ACE_FLAG_HANDLES ) && ( ACE_is_hysteresis_flag( flag_handle ) ) )\r
+ {\r
+ ace_channel_handle_t channel_handle;\r
+ \r
+ ppe_offset = g_ppe_flags_desc_table[flag_handle].threshold_ppe_offset;\r
+ \r
+ high_threshold = ACE->PPE_RAM_DATA[ppe_offset] & PPE_RAM_THRESHOLD_MASK;\r
+ low_threshold = ACE->PPE_RAM_DATA[ppe_offset + 1u] & PPE_RAM_THRESHOLD_MASK;\r
+ ASSERT(high_threshold > low_threshold);\r
+ nominal_threshold = (low_threshold + ((high_threshold - low_threshold) / 2u));\r
+ \r
+ channel_handle = g_ppe_flags_desc_table[flag_handle].channel_handle;\r
+ adc_id = (uint32_t)((uint32_t)g_ace_channel_desc_table[channel_handle].signal_id >> 4u);\r
+ ASSERT( adc_id < (uint32_t)ACE_NB_OF_ADC );\r
+ \r
+ if ( adc_id < (uint32_t)ACE_NB_OF_ADC )\r
+ {\r
+ adc_resolution = g_ace_adc_config[adc_id].adc_resolution;\r
+ \r
+ high_threshold = nominal_threshold + adc_hysteresis;\r
+ if ( high_threshold > adc_resolution )\r
+ {\r
+ high_threshold = (uint32_t)adc_resolution - 1u;\r
+ }\r
+ \r
+ if ( adc_hysteresis > nominal_threshold )\r
+ {\r
+ low_threshold = 1u;\r
+ }\r
+ else\r
+ {\r
+ low_threshold = nominal_threshold - adc_hysteresis;\r
+ }\r
+ \r
+ ACE->PPE_RAM_DATA[ppe_offset] = (ACE->PPE_RAM_DATA[ppe_offset] & ~PPE_RAM_THRESHOLD_MASK) + high_threshold;\r
+ ACE->PPE_RAM_DATA[ppe_offset + 1u] = (ACE->PPE_RAM_DATA[ppe_offset + 1u] & ~PPE_RAM_THRESHOLD_MASK) + low_threshold;\r
+ }\r
+ }\r
+#endif\r
+}\r
+\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+void\r
+ACE_set_channel_hysteresis\r
+(\r
+ ace_channel_handle_t channel_handle,\r
+ uint16_t adc_hysteresis\r
+)\r
+{\r
+#if (ACE_NB_OF_PPE_FLAGS > 0)\r
+ ace_flag_handle_t flag_handle;\r
+ \r
+ ASSERT( channel_handle < NB_OF_ACE_CHANNEL_HANDLES );\r
+ \r
+ if ( channel_handle < NB_OF_ACE_CHANNEL_HANDLES )\r
+ {\r
+ uint16_t i;\r
+ \r
+ for( i = 0u; i < g_ace_channel_desc_table[channel_handle].nb_of_flags; ++i )\r
+ {\r
+ flag_handle = (ace_flag_handle_t)g_ace_channel_desc_table[channel_handle].p_flags_array[i];\r
+ ACE_set_flag_hysteresis( flag_handle, adc_hysteresis );\r
+ }\r
+ }\r
+#endif\r
+}\r
+\r
+/*==============================================================================\r
+ *\r
+ */\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ Masking a flag_id with FLAG_BIT_OFFSET_MASK results in the offset of the \r
+ flag bit within a PPE__FLAGSn register.\r
+ */\r
+#define FLAG_BIT_OFFSET_MASK 0x0000001FuL\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ Shifting right a flag_id by FLAG_PPE_REG_SHIFT results in identifying the\r
+ PPE_FLAGSn or PPE_SFFLAGS the flags belongs to.\r
+ */\r
+#define FLAG_PPE_REG_SHIFT 5u\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ There is a set of 5 PPE flag registers to control and report status of the PPE\r
+ flags resulting in the PPE flags being grouped into 5 separate flag groups at\r
+ the register level. Each register provides status or control for 32 flags.\r
+ */\r
+#define NB_OF_FLAG_GROUPS 5u\r
+#define NB_OF_FLAGS_PER_GROUP 32u\r
+\r
+#if (ACE_NB_OF_PPE_FLAGS > 0)\r
+/*-------------------------------------------------------------------------*//**\r
+ Lookup table of the address PPE_FLAGSn registers for fast reading of PPE\r
+ status.\r
+ */\r
+static volatile uint32_t * const g_ppe_flags_regs_lut[NB_OF_FLAG_GROUPS] =\r
+{\r
+ &ACE->PPE_FLAGS0,\r
+ &ACE->PPE_FLAGS1,\r
+ &ACE->PPE_FLAGS2,\r
+ &ACE->PPE_FLAGS3,\r
+ &ACE->PPE_SFFLAGS\r
+};\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ Lookup table of the address of the PPE flags interrupt enable registers.\r
+ */\r
+static uint32_t volatile * const flags_irq_enable_regs_lut[NB_OF_FLAG_GROUPS] =\r
+{\r
+ &ACE->PPE_FLAGS0_IRQ_EN,\r
+ &ACE->PPE_FLAGS1_IRQ_EN,\r
+ &ACE->PPE_FLAGS2_IRQ_EN,\r
+ &ACE->PPE_FLAGS3_IRQ_EN,\r
+ &ACE->PPE_SFFLAGS_IRQ_EN\r
+};\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ Lookup table of the address of the PPE flags interrupt status registers.\r
+ */\r
+static uint32_t volatile const * const flags_irq_status_regs_lut[NB_OF_FLAG_GROUPS] =\r
+{\r
+ &ACE->PPE_FLAGS0_IRQ,\r
+ &ACE->PPE_FLAGS1_IRQ,\r
+ &ACE->PPE_FLAGS2_IRQ,\r
+ &ACE->PPE_FLAGS3_IRQ,\r
+ &ACE->PPE_SFFLAGS_IRQ\r
+};\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ Lookup table of the address of the PPE flags interrupt clearing registers.\r
+ */\r
+static uint32_t volatile * const flags_irq_clear_regs_lut[NB_OF_FLAG_GROUPS] =\r
+{\r
+ &ACE->PPE_FLAGS0_IRQ_CLR,\r
+ &ACE->PPE_FLAGS1_IRQ_CLR,\r
+ &ACE->PPE_FLAGS2_IRQ_CLR,\r
+ &ACE->PPE_FLAGS3_IRQ_CLR,\r
+ &ACE->PPE_SFFLAGS_IRQ_CLR\r
+};\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+static const IRQn_Type threshold_irqn_lut[NB_OF_THRESHOLD_IRQ] =\r
+{\r
+ ACE_PPE_Flag0_IRQn,\r
+ ACE_PPE_Flag1_IRQn,\r
+ ACE_PPE_Flag2_IRQn,\r
+ ACE_PPE_Flag3_IRQn,\r
+ ACE_PPE_Flag4_IRQn,\r
+ ACE_PPE_Flag5_IRQn,\r
+ ACE_PPE_Flag6_IRQn,\r
+ ACE_PPE_Flag7_IRQn,\r
+ ACE_PPE_Flag8_IRQn,\r
+ ACE_PPE_Flag9_IRQn,\r
+ ACE_PPE_Flag10_IRQn,\r
+ ACE_PPE_Flag11_IRQn,\r
+ ACE_PPE_Flag12_IRQn,\r
+ ACE_PPE_Flag13_IRQn,\r
+ ACE_PPE_Flag14_IRQn,\r
+ ACE_PPE_Flag15_IRQn,\r
+ ACE_PPE_Flag16_IRQn,\r
+ ACE_PPE_Flag17_IRQn,\r
+ ACE_PPE_Flag18_IRQn,\r
+ ACE_PPE_Flag19_IRQn,\r
+ ACE_PPE_Flag20_IRQn,\r
+ ACE_PPE_Flag21_IRQn,\r
+ ACE_PPE_Flag22_IRQn,\r
+ ACE_PPE_Flag23_IRQn,\r
+ ACE_PPE_Flag24_IRQn,\r
+ ACE_PPE_Flag25_IRQn,\r
+ ACE_PPE_Flag26_IRQn,\r
+ ACE_PPE_Flag27_IRQn,\r
+ ACE_PPE_Flag28_IRQn,\r
+ ACE_PPE_Flag29_IRQn,\r
+ ACE_PPE_Flag30_IRQn,\r
+ ACE_PPE_Flag31_IRQn\r
+};\r
+#endif\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ */\r
+ace_flag_handle_t\r
+ACE_get_flag_handle\r
+(\r
+ const uint8_t * p_sz_full_flag_name\r
+)\r
+{\r
+ ace_flag_handle_t flag_handle = INVALID_FLAG_HANDLE;\r
+#if (ACE_NB_OF_PPE_FLAGS > 0)\r
+ ace_flag_handle_t flag_idx;\r
+ \r
+ for ( flag_idx = (ace_flag_handle_t)0; flag_idx < NB_OF_ACE_FLAG_HANDLES; ++flag_idx )\r
+ {\r
+ if ( g_ppe_flags_desc_table[flag_idx].p_sz_flag_name != 0 )\r
+ {\r
+ int32_t diff;\r
+ diff = strncmp( (const char *)p_sz_full_flag_name, (const char *)g_ppe_flags_desc_table[flag_idx].p_sz_flag_name, (size_t)MAX_FULL_FLAG_NAME_LENGTH );\r
+ if ( 0 == diff )\r
+ {\r
+ /* flag name found. */\r
+ flag_handle = (ace_flag_handle_t)flag_idx;\r
+ break;\r
+ }\r
+ }\r
+ }\r
+#endif\r
+ return flag_handle;\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ */\r
+int32_t\r
+ACE_get_flag_status\r
+(\r
+ ace_flag_handle_t flag_handle\r
+)\r
+{\r
+ int32_t flag_state = UNKNOWN_FLAG;\r
+#if (ACE_NB_OF_PPE_FLAGS > 0) \r
+ ppe_flag_id_t flag_id;\r
+ \r
+ ASSERT( flag_handle < NB_OF_ACE_FLAG_HANDLES );\r
+ \r
+ if ( flag_handle < NB_OF_ACE_FLAG_HANDLES )\r
+ {\r
+ uint32_t flag_bit_offset;\r
+ uint32_t ppe_flag_group;\r
+ uint32_t flag_id_mask;\r
+ uint32_t flag_status;\r
+\r
+ flag_id = g_ppe_flags_desc_table[flag_handle].flag_id;\r
+ \r
+ if ( flag_id < NB_OF_PPE_FLAGS )\r
+ {\r
+ flag_bit_offset = ((uint32_t)flag_id & FLAG_BIT_OFFSET_MASK);\r
+ ppe_flag_group = ((uint32_t)flag_id >> FLAG_PPE_REG_SHIFT);\r
+ flag_id_mask = 1uL << flag_bit_offset;\r
+ flag_status = *(g_ppe_flags_regs_lut[ppe_flag_group]) & flag_id_mask;\r
+ if ( flag_status > 0u )\r
+ {\r
+ flag_state = FLAG_ASSERTED;\r
+ }\r
+ else\r
+ {\r
+ flag_state = FLAG_NOT_ASSERTED;\r
+ }\r
+ }\r
+\r
+ }\r
+#endif\r
+ return flag_state;\r
+}\r
+\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ */\r
+const uint8_t *\r
+ACE_get_flag_name\r
+(\r
+ ace_flag_handle_t flag_handle\r
+)\r
+{\r
+ const uint8_t * psz_flag_name = 0;\r
+#if (ACE_NB_OF_PPE_FLAGS > 0) \r
+ ASSERT( flag_handle < NB_OF_ACE_FLAG_HANDLES );\r
+ \r
+ if ( flag_handle < NB_OF_ACE_FLAG_HANDLES )\r
+ {\r
+ psz_flag_name = g_ppe_flags_desc_table[flag_handle].p_sz_flag_name;\r
+ }\r
+#endif\r
+ return psz_flag_name;\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ */\r
+ace_channel_handle_t\r
+ACE_get_flag_channel\r
+(\r
+ ace_flag_handle_t flag_handle\r
+)\r
+{\r
+ ace_channel_handle_t channel_handle = INVALID_CHANNEL_HANDLE;\r
+#if (ACE_NB_OF_PPE_FLAGS > 0)\r
+ ASSERT( flag_handle < NB_OF_ACE_FLAG_HANDLES );\r
+ \r
+ if ( flag_handle < NB_OF_ACE_FLAG_HANDLES )\r
+ {\r
+ channel_handle = g_ppe_flags_desc_table[flag_handle].channel_handle;\r
+ }\r
+#endif\r
+ return channel_handle;\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ */\r
+uint32_t\r
+ACE_get_channel_flag_count\r
+(\r
+ ace_channel_handle_t channel_handle\r
+)\r
+{\r
+ uint32_t flag_count = 0;\r
+#if (ACE_NB_OF_PPE_FLAGS > 0)\r
+ ASSERT( channel_handle < ACE_NB_OF_INPUT_CHANNELS );\r
+ if (channel_handle < ACE_NB_OF_INPUT_CHANNELS)\r
+ {\r
+ flag_count = g_ace_channel_desc_table[channel_handle].nb_of_flags;\r
+ }\r
+#endif\r
+ return flag_count;\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ \r
+ */\r
+ace_flag_handle_t\r
+ACE_get_channel_first_flag\r
+(\r
+ ace_channel_handle_t channel_handle,\r
+ uint16_t * iterator\r
+)\r
+{\r
+ ace_flag_handle_t flag_handle = INVALID_FLAG_HANDLE;\r
+#if (ACE_NB_OF_PPE_FLAGS > 0)\r
+ ASSERT( channel_handle < NB_OF_ACE_CHANNEL_HANDLES);\r
+ \r
+ *iterator = 0u;\r
+ \r
+ if ( channel_handle < NB_OF_ACE_CHANNEL_HANDLES)\r
+ {\r
+ if ( g_ace_channel_desc_table[channel_handle].nb_of_flags > 0u )\r
+ {\r
+ flag_handle = (ace_flag_handle_t)g_ace_channel_desc_table[channel_handle].p_flags_array[*iterator];\r
+ }\r
+ }\r
+#endif \r
+ return flag_handle;\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ \r
+ */\r
+ace_flag_handle_t\r
+ACE_get_channel_next_flag\r
+(\r
+ ace_channel_handle_t channel_handle,\r
+ uint16_t * iterator\r
+)\r
+{\r
+ ace_flag_handle_t flag_handle = INVALID_FLAG_HANDLE;\r
+#if (ACE_NB_OF_PPE_FLAGS > 0) \r
+ ASSERT( channel_handle < NB_OF_ACE_CHANNEL_HANDLES);\r
+\r
+ if ( channel_handle < NB_OF_ACE_CHANNEL_HANDLES)\r
+ {\r
+ ++(*iterator);\r
+ \r
+ if ( *iterator >= g_ace_channel_desc_table[channel_handle].nb_of_flags )\r
+ {\r
+ *iterator = 0u;\r
+ }\r
+ \r
+ if ( g_ace_channel_desc_table[channel_handle].nb_of_flags > 0u )\r
+ {\r
+ flag_handle = (ace_flag_handle_t)g_ace_channel_desc_table[channel_handle].p_flags_array[*iterator];\r
+ }\r
+ }\r
+#endif\r
+ return flag_handle;\r
+}\r
+\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+void ACE_enable_channel_flags_irq\r
+(\r
+ ace_channel_handle_t channel_handle\r
+)\r
+{\r
+#if (ACE_NB_OF_PPE_FLAGS > 0)\r
+ uint32_t flag_idx;\r
+ ace_flag_handle_t flag_handle;\r
+ \r
+ ASSERT( channel_handle < NB_OF_ACE_CHANNEL_HANDLES );\r
+ \r
+ if ( channel_handle < NB_OF_ACE_CHANNEL_HANDLES )\r
+ {\r
+ for ( flag_idx = 0u; flag_idx < g_ace_channel_desc_table[channel_handle].nb_of_flags; ++flag_idx )\r
+ {\r
+ flag_handle = (ace_flag_handle_t)g_ace_channel_desc_table[channel_handle].p_flags_array[flag_idx];\r
+ ACE_enable_flag_irq( flag_handle );\r
+ }\r
+ }\r
+#endif\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+void ACE_disable_channel_flags_irq\r
+(\r
+ ace_channel_handle_t channel_handle\r
+)\r
+{\r
+#if (ACE_NB_OF_PPE_FLAGS > 0)\r
+ uint32_t flag_idx;\r
+ ace_flag_handle_t flag_handle;\r
+ \r
+ ASSERT( channel_handle < NB_OF_ACE_CHANNEL_HANDLES );\r
+ \r
+ if ( channel_handle < NB_OF_ACE_CHANNEL_HANDLES )\r
+ {\r
+ for ( flag_idx = 0u; flag_idx < g_ace_channel_desc_table[channel_handle].nb_of_flags; ++flag_idx )\r
+ {\r
+ flag_handle = (ace_flag_handle_t)g_ace_channel_desc_table[channel_handle].p_flags_array[flag_idx];\r
+ ACE_disable_flag_irq( flag_handle );\r
+ }\r
+ }\r
+#endif\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+void ACE_clear_channel_flags_irq\r
+(\r
+ ace_channel_handle_t channel_handle\r
+)\r
+{\r
+#if (ACE_NB_OF_PPE_FLAGS > 0)\r
+ uint32_t flag_idx;\r
+ ace_flag_handle_t flag_handle;\r
+ \r
+ ASSERT( channel_handle < NB_OF_ACE_CHANNEL_HANDLES );\r
+ \r
+ if ( channel_handle < NB_OF_ACE_CHANNEL_HANDLES )\r
+ {\r
+ for ( flag_idx = 0u; flag_idx < g_ace_channel_desc_table[channel_handle].nb_of_flags; ++flag_idx )\r
+ {\r
+ flag_handle = (ace_flag_handle_t)g_ace_channel_desc_table[channel_handle].p_flags_array[flag_idx];\r
+ ACE_clear_flag_irq( flag_handle );\r
+ }\r
+ }\r
+#endif\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+void ACE_enable_flag_irq\r
+(\r
+ ace_flag_handle_t flag_handle\r
+)\r
+{\r
+#if (ACE_NB_OF_PPE_FLAGS > 0)\r
+ ASSERT( flag_handle < NB_OF_ACE_FLAG_HANDLES );\r
+ \r
+ if ( flag_handle < NB_OF_ACE_FLAG_HANDLES )\r
+ {\r
+ ppe_flag_id_t flag_id;\r
+ uint32_t flag_bit_offset;\r
+ uint32_t ppe_flag_group;\r
+ uint32_t flag_id_mask;\r
+ \r
+ flag_id = g_ppe_flags_desc_table[flag_handle].flag_id;\r
+ \r
+ ASSERT( flag_id < NB_OF_PPE_FLAGS );\r
+ \r
+ flag_bit_offset = ((uint32_t)flag_id & FLAG_BIT_OFFSET_MASK);\r
+ ppe_flag_group = ((uint32_t)flag_id >> FLAG_PPE_REG_SHIFT);\r
+ flag_id_mask = 1uL << flag_bit_offset;\r
+ \r
+ ASSERT( ppe_flag_group < NB_OF_FLAG_GROUPS );\r
+ \r
+ if ( ppe_flag_group < NB_OF_FLAG_GROUPS )\r
+ {\r
+ *(flags_irq_enable_regs_lut[ppe_flag_group]) |= flag_id_mask;\r
+ }\r
+ \r
+ NVIC_EnableIRQ( threshold_irqn_lut[flag_bit_offset] );\r
+ }\r
+#endif\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+void ACE_disable_flag_irq\r
+(\r
+ ace_flag_handle_t flag_handle\r
+)\r
+{\r
+#if (ACE_NB_OF_PPE_FLAGS > 0)\r
+ ASSERT( flag_handle < NB_OF_ACE_FLAG_HANDLES );\r
+ \r
+ if ( flag_handle < NB_OF_ACE_FLAG_HANDLES )\r
+ {\r
+ ppe_flag_id_t flag_id;\r
+ uint32_t flag_bit_offset;\r
+ uint32_t ppe_flag_group;\r
+ uint32_t flag_id_mask;\r
+ \r
+ flag_id = g_ppe_flags_desc_table[flag_handle].flag_id;\r
+ \r
+ ASSERT( flag_id < NB_OF_PPE_FLAGS );\r
+ \r
+ flag_bit_offset = ((uint32_t)flag_id & FLAG_BIT_OFFSET_MASK);\r
+ ppe_flag_group = ((uint32_t)flag_id >> FLAG_PPE_REG_SHIFT);\r
+ flag_id_mask = 1uL << flag_bit_offset;\r
+ \r
+ ASSERT( ppe_flag_group < NB_OF_FLAG_GROUPS );\r
+ \r
+ if ( ppe_flag_group < NB_OF_FLAG_GROUPS )\r
+ {\r
+ *(flags_irq_enable_regs_lut[ppe_flag_group]) &= (uint32_t)~flag_id_mask;\r
+ }\r
+ }\r
+#endif\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+void ACE_clear_flag_irq\r
+(\r
+ ace_flag_handle_t flag_handle\r
+)\r
+{\r
+#if (ACE_NB_OF_PPE_FLAGS > 0)\r
+ ASSERT( flag_handle < NB_OF_ACE_FLAG_HANDLES );\r
+ \r
+ if ( flag_handle < NB_OF_ACE_FLAG_HANDLES )\r
+ {\r
+ ppe_flag_id_t flag_id;\r
+ uint32_t flag_bit_offset;\r
+ uint32_t ppe_flag_group;\r
+ uint32_t flag_id_mask;\r
+ \r
+ flag_id = g_ppe_flags_desc_table[flag_handle].flag_id;\r
+ \r
+ ASSERT( flag_id < NB_OF_PPE_FLAGS );\r
+ \r
+ flag_bit_offset = ((uint32_t)flag_id & FLAG_BIT_OFFSET_MASK);\r
+ ppe_flag_group = ((uint32_t)flag_id >> FLAG_PPE_REG_SHIFT);\r
+ flag_id_mask = 1uL << flag_bit_offset;\r
+ \r
+ ASSERT( ppe_flag_group < NB_OF_FLAG_GROUPS );\r
+ \r
+ if ( ppe_flag_group < NB_OF_FLAG_GROUPS )\r
+ {\r
+ *(flags_irq_clear_regs_lut[ppe_flag_group]) |= flag_id_mask;\r
+ }\r
+ }\r
+#endif\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+void ACE_register_flag_isr\r
+(\r
+ ace_flag_handle_t flag_handle,\r
+ flag_isr_t flag_isr\r
+)\r
+{\r
+#if (ACE_NB_OF_PPE_FLAGS > 0)\r
+ ppe_flag_id_t flag_id;\r
+ \r
+ ASSERT( flag_handle < NB_OF_ACE_FLAG_HANDLES );\r
+ \r
+ if ( flag_handle < NB_OF_ACE_FLAG_HANDLES )\r
+ {\r
+ flag_id = g_ppe_flags_desc_table[flag_handle].flag_id;\r
+ \r
+ ASSERT( flag_id < NB_OF_PPE_FLAGS );\r
+ \r
+ if ( flag_id < NB_OF_PPE_FLAGS )\r
+ {\r
+ g_ppe_flags_isr_lut[flag_id] = flag_isr;\r
+ }\r
+ }\r
+#endif\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+void ACE_register_channel_flags_isr\r
+(\r
+ ace_channel_handle_t channel_handle,\r
+ channel_flag_isr_t channel_flag_isr\r
+)\r
+{\r
+#if (ACE_NB_OF_PPE_FLAGS > 0)\r
+ ASSERT( channel_handle < NB_OF_ACE_CHANNEL_HANDLES );\r
+ \r
+ if ( channel_handle < NB_OF_ACE_CHANNEL_HANDLES )\r
+ {\r
+ g_ppe_channel_flags_isr_lut[channel_handle] = channel_flag_isr;\r
+ }\r
+#endif\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+void ACE_register_global_flags_isr\r
+(\r
+ global_flag_isr_t global_flag_isr\r
+)\r
+{\r
+#if (ACE_NB_OF_PPE_FLAGS > 0)\r
+ g_ppe_global_flags_isr = global_flag_isr;\r
+#endif\r
+}\r
+\r
+\r
+/*==============================================================================\r
+ *\r
+ */\r
+ \r
+/*-------------------------------------------------------------------------*//**\r
+ * Actual PPE flag interrupt service routines:\r
+ */\r
+\r
+static void process_flag_irq( uint8_t threshold_flag_id )\r
+{\r
+#if (ACE_NB_OF_PPE_FLAGS > 0)\r
+ uint8_t flag_group;\r
+ uint32_t threshold_flag_mask;\r
+ ppe_flag_id_t flag_id;\r
+ uint32_t irq_enable_reg;\r
+ uint32_t irq_status_reg;\r
+ uint32_t irq_active;\r
+ \r
+ threshold_flag_mask = 1uL << threshold_flag_id;\r
+ \r
+ \r
+ for ( flag_group = 0u; flag_group < NB_OF_FLAG_GROUPS; ++flag_group )\r
+ {\r
+ irq_enable_reg = *flags_irq_enable_regs_lut[flag_group];\r
+ irq_status_reg = *flags_irq_status_regs_lut[flag_group];\r
+ irq_active = threshold_flag_mask & irq_enable_reg & irq_status_reg;\r
+ \r
+ if ( irq_active )\r
+ {\r
+ ace_flag_handle_t flag_handle;\r
+ ace_channel_handle_t channel_handle;\r
+ \r
+ flag_id = (ppe_flag_id_t)((flag_group * NB_OF_FLAGS_PER_GROUP) + threshold_flag_id);\r
+ flag_handle = g_ppe_flag_handles_lut[flag_id];\r
+ \r
+ /* Call individual flag handler */\r
+ if ( g_ppe_flags_isr_lut[flag_id] != 0 ) \r
+ {\r
+ g_ppe_flags_isr_lut[flag_id]( flag_handle );\r
+ }\r
+ \r
+ /* Call the channel flag handler. */\r
+ channel_handle = g_ppe_flags_desc_table[flag_handle].channel_handle;\r
+ if ( channel_handle < NB_OF_ACE_CHANNEL_HANDLES )\r
+ {\r
+ if ( g_ppe_channel_flags_isr_lut[channel_handle] != 0 )\r
+ {\r
+ g_ppe_channel_flags_isr_lut[channel_handle]( flag_handle );\r
+ }\r
+ }\r
+ \r
+ /* Call the global flag handler. */\r
+ if ( g_ppe_global_flags_isr != 0 )\r
+ {\r
+ g_ppe_global_flags_isr( flag_handle, channel_handle );\r
+ }\r
+ \r
+ /* Clear the flag interrupt */\r
+ *flags_irq_clear_regs_lut[flag_group] |= threshold_flag_mask;\r
+ }\r
+ }\r
+#endif\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void ACE_PPE_Flag0_IRQHandler( void )\r
+#else\r
+void ACE_PPE_Flag0_IRQHandler( void )\r
+#endif\r
+{\r
+ process_flag_irq( THRESHOLD_FLAG0 );\r
+ NVIC_ClearPendingIRQ( ACE_PPE_Flag0_IRQn );\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void ACE_PPE_Flag1_IRQHandler( void )\r
+#else\r
+void ACE_PPE_Flag1_IRQHandler( void )\r
+#endif\r
+{\r
+ process_flag_irq( THRESHOLD_FLAG1 );\r
+ NVIC_ClearPendingIRQ( ACE_PPE_Flag1_IRQn );\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void ACE_PPE_Flag2_IRQHandler( void )\r
+#else\r
+void ACE_PPE_Flag2_IRQHandler( void )\r
+#endif\r
+{\r
+ process_flag_irq( THRESHOLD_FLAG2 );\r
+ NVIC_ClearPendingIRQ( ACE_PPE_Flag2_IRQn );\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void ACE_PPE_Flag3_IRQHandler( void )\r
+#else\r
+void ACE_PPE_Flag3_IRQHandler( void )\r
+#endif\r
+{\r
+ process_flag_irq( THRESHOLD_FLAG3 );\r
+ NVIC_ClearPendingIRQ( ACE_PPE_Flag3_IRQn );\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void ACE_PPE_Flag4_IRQHandler( void )\r
+#else\r
+void ACE_PPE_Flag4_IRQHandler( void )\r
+#endif\r
+{\r
+ process_flag_irq( THRESHOLD_FLAG4 );\r
+ NVIC_ClearPendingIRQ( ACE_PPE_Flag4_IRQn );\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void ACE_PPE_Flag5_IRQHandler( void )\r
+#else\r
+void ACE_PPE_Flag5_IRQHandler( void )\r
+#endif\r
+{\r
+ process_flag_irq( THRESHOLD_FLAG5 );\r
+ NVIC_ClearPendingIRQ( ACE_PPE_Flag5_IRQn );\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void ACE_PPE_Flag6_IRQHandler( void )\r
+#else\r
+void ACE_PPE_Flag6_IRQHandler( void )\r
+#endif\r
+{\r
+ process_flag_irq( THRESHOLD_FLAG6 );\r
+ NVIC_ClearPendingIRQ( ACE_PPE_Flag6_IRQn );\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void ACE_PPE_Flag7_IRQHandler( void )\r
+#else\r
+void ACE_PPE_Flag7_IRQHandler( void )\r
+#endif\r
+{\r
+ process_flag_irq( THRESHOLD_FLAG7 );\r
+ NVIC_ClearPendingIRQ( ACE_PPE_Flag7_IRQn );\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void ACE_PPE_Flag8_IRQHandler( void )\r
+#else\r
+void ACE_PPE_Flag8_IRQHandler( void )\r
+#endif\r
+{\r
+ process_flag_irq( THRESHOLD_FLAG8 );\r
+ NVIC_ClearPendingIRQ( ACE_PPE_Flag8_IRQn );\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void ACE_PPE_Flag9_IRQHandler( void )\r
+#else\r
+void ACE_PPE_Flag9_IRQHandler( void )\r
+#endif\r
+{\r
+ process_flag_irq( THRESHOLD_FLAG9 );\r
+ NVIC_ClearPendingIRQ( ACE_PPE_Flag9_IRQn );\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void ACE_PPE_Flag10_IRQHandler( void )\r
+#else\r
+void ACE_PPE_Flag10_IRQHandler( void )\r
+#endif\r
+{\r
+ process_flag_irq( THRESHOLD_FLAG10 );\r
+ NVIC_ClearPendingIRQ( ACE_PPE_Flag10_IRQn );\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void ACE_PPE_Flag11_IRQHandler( void )\r
+#else\r
+void ACE_PPE_Flag11_IRQHandler( void )\r
+#endif\r
+{\r
+ process_flag_irq( THRESHOLD_FLAG11 );\r
+ NVIC_ClearPendingIRQ( ACE_PPE_Flag11_IRQn );\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void ACE_PPE_Flag12_IRQHandler( void )\r
+#else\r
+void ACE_PPE_Flag12_IRQHandler( void )\r
+#endif\r
+{\r
+ process_flag_irq( THRESHOLD_FLAG12 );\r
+ NVIC_ClearPendingIRQ( ACE_PPE_Flag12_IRQn );\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void ACE_PPE_Flag13_IRQHandler( void )\r
+#else\r
+void ACE_PPE_Flag13_IRQHandler( void )\r
+#endif\r
+{\r
+ process_flag_irq( THRESHOLD_FLAG13 );\r
+ NVIC_ClearPendingIRQ( ACE_PPE_Flag13_IRQn );\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void ACE_PPE_Flag14_IRQHandler( void )\r
+#else\r
+void ACE_PPE_Flag14_IRQHandler( void )\r
+#endif\r
+{\r
+ process_flag_irq( THRESHOLD_FLAG14 );\r
+ NVIC_ClearPendingIRQ( ACE_PPE_Flag14_IRQn );\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void ACE_PPE_Flag15_IRQHandler( void )\r
+#else\r
+void ACE_PPE_Flag15_IRQHandler( void )\r
+#endif\r
+{\r
+ process_flag_irq( THRESHOLD_FLAG15 );\r
+ NVIC_ClearPendingIRQ( ACE_PPE_Flag15_IRQn );\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void ACE_PPE_Flag16_IRQHandler( void )\r
+#else\r
+void ACE_PPE_Flag16_IRQHandler( void )\r
+#endif\r
+{\r
+ process_flag_irq( THRESHOLD_FLAG16 );\r
+ NVIC_ClearPendingIRQ( ACE_PPE_Flag16_IRQn );\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void ACE_PPE_Flag17_IRQHandler( void )\r
+#else\r
+void ACE_PPE_Flag17_IRQHandler( void )\r
+#endif\r
+{\r
+ process_flag_irq( THRESHOLD_FLAG17 );\r
+ NVIC_ClearPendingIRQ( ACE_PPE_Flag17_IRQn );\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void ACE_PPE_Flag18_IRQHandler( void )\r
+#else\r
+void ACE_PPE_Flag18_IRQHandler( void )\r
+#endif\r
+{\r
+ process_flag_irq( THRESHOLD_FLAG18 );\r
+ NVIC_ClearPendingIRQ( ACE_PPE_Flag18_IRQn );\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void ACE_PPE_Flag19_IRQHandler( void )\r
+#else\r
+void ACE_PPE_Flag19_IRQHandler( void )\r
+#endif\r
+{\r
+ process_flag_irq( THRESHOLD_FLAG19 );\r
+ NVIC_ClearPendingIRQ( ACE_PPE_Flag19_IRQn );\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void ACE_PPE_Flag20_IRQHandler( void )\r
+#else\r
+void ACE_PPE_Flag20_IRQHandler( void )\r
+#endif\r
+{\r
+ process_flag_irq( THRESHOLD_FLAG20 );\r
+ NVIC_ClearPendingIRQ( ACE_PPE_Flag20_IRQn );\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void ACE_PPE_Flag21_IRQHandler( void )\r
+#else\r
+void ACE_PPE_Flag21_IRQHandler( void )\r
+#endif\r
+{\r
+ process_flag_irq( THRESHOLD_FLAG21 );\r
+ NVIC_ClearPendingIRQ( ACE_PPE_Flag21_IRQn );\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void ACE_PPE_Flag22_IRQHandler( void )\r
+#else\r
+void ACE_PPE_Flag22_IRQHandler( void )\r
+#endif\r
+{\r
+ process_flag_irq( THRESHOLD_FLAG22 );\r
+ NVIC_ClearPendingIRQ( ACE_PPE_Flag22_IRQn );\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void ACE_PPE_Flag23_IRQHandler( void )\r
+#else\r
+void ACE_PPE_Flag23_IRQHandler( void )\r
+#endif\r
+{\r
+ process_flag_irq( THRESHOLD_FLAG23 );\r
+ NVIC_ClearPendingIRQ( ACE_PPE_Flag23_IRQn );\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void ACE_PPE_Flag24_IRQHandler( void )\r
+#else\r
+void ACE_PPE_Flag24_IRQHandler( void )\r
+#endif\r
+{\r
+ process_flag_irq( THRESHOLD_FLAG24 );\r
+ NVIC_ClearPendingIRQ( ACE_PPE_Flag24_IRQn );\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void ACE_PPE_Flag25_IRQHandler( void )\r
+#else\r
+void ACE_PPE_Flag25_IRQHandler( void )\r
+#endif\r
+{\r
+ process_flag_irq( THRESHOLD_FLAG25 );\r
+ NVIC_ClearPendingIRQ( ACE_PPE_Flag25_IRQn );\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void ACE_PPE_Flag26_IRQHandler( void )\r
+#else\r
+void ACE_PPE_Flag26_IRQHandler( void )\r
+#endif\r
+{\r
+ process_flag_irq( THRESHOLD_FLAG26 );\r
+ NVIC_ClearPendingIRQ( ACE_PPE_Flag26_IRQn );\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void ACE_PPE_Flag27_IRQHandler( void )\r
+#else\r
+void ACE_PPE_Flag27_IRQHandler( void )\r
+#endif\r
+{\r
+ process_flag_irq( THRESHOLD_FLAG27 );\r
+ NVIC_ClearPendingIRQ( ACE_PPE_Flag27_IRQn );\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void ACE_PPE_Flag28_IRQHandler( void )\r
+#else\r
+void ACE_PPE_Flag28_IRQHandler( void )\r
+#endif\r
+{\r
+ process_flag_irq( THRESHOLD_FLAG28 );\r
+ NVIC_ClearPendingIRQ( ACE_PPE_Flag28_IRQn );\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void ACE_PPE_Flag29_IRQHandler( void )\r
+#else\r
+void ACE_PPE_Flag29_IRQHandler( void )\r
+#endif\r
+{\r
+ process_flag_irq( THRESHOLD_FLAG29 );\r
+ NVIC_ClearPendingIRQ( ACE_PPE_Flag29_IRQn );\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void ACE_PPE_Flag30_IRQHandler( void )\r
+#else\r
+void ACE_PPE_Flag30_IRQHandler( void )\r
+#endif\r
+{\r
+ process_flag_irq( THRESHOLD_FLAG30 );\r
+ NVIC_ClearPendingIRQ( ACE_PPE_Flag30_IRQn );\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void ACE_PPE_Flag31_IRQHandler( void )\r
+#else\r
+void ACE_PPE_Flag31_IRQHandler( void )\r
+#endif\r
+{\r
+ process_flag_irq( THRESHOLD_FLAG31 );\r
+ NVIC_ClearPendingIRQ( ACE_PPE_Flag31_IRQn );\r
+}\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
--- /dev/null
+/*******************************************************************************\r
+ * (c) Copyright 2009 Actel Corporation. All rights reserved.\r
+ * \r
+ * SVN $Revision: 2905 $\r
+ * SVN $Date: 2010-08-20 14:03:28 +0100 (Fri, 20 Aug 2010) $\r
+ */\r
+#include "mss_ace.h"\r
+#include "mss_ace_configurator.h"\r
+#include "../../drivers_config/mss_ace/ace_handles.h"\r
+#include "../../drivers_config/mss_ace/ace_config.h"\r
+\r
+#include "../../CMSIS/a2fxxxm3.h"\r
+#include "../../CMSIS/mss_assert.h"\r
+#include <string.h>\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif \r
+\r
+#define SSE_START 1uL\r
+#define SSE_STOP 0uL\r
+\r
+#define NB_OF_ANALOG_BLOCKS 3u\r
+#define SEE_RAM_WORD_SIZE 512\r
+\r
+#define TS_ENABLE_MASK 0x01u\r
+#define PPE_ENABLE_MASK 0x01u\r
+#define ADC_RESET_MASK 0x10u\r
+#define ADC_FIFO_CLR_MASK 0x04u\r
+#define PDMA_DATAOUT_CLR_MASK 0x04u\r
+\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+extern ace_procedure_desc_t g_sse_sequences_desc_table[ACE_NB_OF_SSE_PROCEDURES];\r
+ \r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+sse_sequence_handle_t\r
+ACE_get_sse_seq_handle\r
+(\r
+ const uint8_t * p_sz_sequence_name\r
+)\r
+{\r
+ uint16_t seq_idx;\r
+ sse_sequence_handle_t handle = INVALID_SSE_SEQ_HANDLE;\r
+ \r
+ for ( seq_idx = 0u; seq_idx < (uint32_t)ACE_NB_OF_SSE_PROCEDURES; ++seq_idx )\r
+ {\r
+ if ( g_sse_sequences_desc_table[seq_idx].p_sz_proc_name != 0 )\r
+ {\r
+ int32_t diff;\r
+ diff = strncmp( (const char *)p_sz_sequence_name, (const char *)g_sse_sequences_desc_table[seq_idx].p_sz_proc_name, MAX_PROCEDURE_NAME_LENGTH );\r
+ if ( 0 == diff )\r
+ {\r
+ /* channel name found. */\r
+ handle = seq_idx;\r
+ break;\r
+ }\r
+ }\r
+ }\r
+ return handle;\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+static uint32_t volatile * const sse_pc_ctrl_lut[NB_OF_ANALOG_BLOCKS] =\r
+{\r
+ &ACE->PC0_CTRL,\r
+ &ACE->PC1_CTRL,\r
+ &ACE->PC2_CTRL\r
+};\r
+\r
+static uint32_t volatile * const sse_pc_lo_lut[NB_OF_ANALOG_BLOCKS] =\r
+{\r
+ &ACE->PC0_LO,\r
+ &ACE->PC1_LO,\r
+ &ACE->PC2_LO\r
+};\r
+\r
+static uint32_t volatile * const sse_pc_hi_lut[NB_OF_ANALOG_BLOCKS] =\r
+{\r
+ &ACE->PC0_HI,\r
+ &ACE->PC1_HI,\r
+ &ACE->PC2_HI\r
+};\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+void ACE_load_sse\r
+(\r
+ sse_sequence_handle_t sequence\r
+)\r
+{\r
+ ASSERT( sequence < (sse_sequence_handle_t)ACE_NB_OF_SSE_PROCEDURES );\r
+ \r
+ if ( sequence < (sse_sequence_handle_t)ACE_NB_OF_SSE_PROCEDURES )\r
+ {\r
+ uint16_t i;\r
+ uint16_t offset;\r
+ const uint16_t * p_ucode;\r
+ \r
+ ASSERT( g_sse_sequences_desc_table[sequence].sse_pc_id < NB_OF_ANALOG_BLOCKS );\r
+ \r
+ if ( g_sse_sequences_desc_table[sequence].sse_pc_id < NB_OF_ANALOG_BLOCKS )\r
+ {\r
+ /* Stop relevant program counter. */\r
+ *sse_pc_ctrl_lut[g_sse_sequences_desc_table[sequence].sse_pc_id] = SSE_STOP;\r
+ \r
+ /* Load microcode into SEE RAM.*/\r
+ p_ucode = g_sse_sequences_desc_table[sequence].sse_ucode;\r
+ offset = g_sse_sequences_desc_table[sequence].sse_load_offset;\r
+ \r
+ for ( i = 0u; i < g_sse_sequences_desc_table[sequence].sse_ucode_length; ++i )\r
+ {\r
+ ACE->SSE_RAM_DATA[offset + i] = (uint32_t)*p_ucode;\r
+ ++p_ucode;\r
+ }\r
+ }\r
+ }\r
+}\r
+\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+void ACE_start_sse\r
+(\r
+ sse_sequence_handle_t sequence\r
+)\r
+{\r
+ ASSERT( sequence < (sse_sequence_handle_t)ACE_NB_OF_SSE_PROCEDURES );\r
+ \r
+ if ( sequence < (sse_sequence_handle_t)ACE_NB_OF_SSE_PROCEDURES )\r
+ {\r
+ uint16_t pc;\r
+ \r
+ ASSERT( g_sse_sequences_desc_table[sequence].sse_pc_id < NB_OF_ANALOG_BLOCKS );\r
+ ASSERT( g_sse_sequences_desc_table[sequence].sse_load_offset < SEE_RAM_WORD_SIZE );\r
+ \r
+ pc = g_sse_sequences_desc_table[sequence].sse_load_offset;\r
+ \r
+ if ( pc < 256u )\r
+ {\r
+ *sse_pc_lo_lut[g_sse_sequences_desc_table[sequence].sse_pc_id] = pc;\r
+ }\r
+ else\r
+ {\r
+ *sse_pc_hi_lut[g_sse_sequences_desc_table[sequence].sse_pc_id] = pc - 256;\r
+ }\r
+ \r
+ *sse_pc_ctrl_lut[g_sse_sequences_desc_table[sequence].sse_pc_id] = SSE_START;\r
+ \r
+ /* Enable Sample Sequencing Engine in case it was not done as part of\r
+ * system boot. */\r
+ ACE->SSE_TS_CTRL |= TS_ENABLE_MASK;\r
+ }\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+void ACE_restart_sse\r
+(\r
+ sse_sequence_handle_t sequence\r
+)\r
+{\r
+ ASSERT( sequence < ACE_NB_OF_SSE_PROCEDURES );\r
+ ASSERT( g_sse_sequences_desc_table[sequence].sse_pc_id < NB_OF_ANALOG_BLOCKS );\r
+ ASSERT( g_sse_sequences_desc_table[sequence].sse_load_offset < SEE_RAM_WORD_SIZE );\r
+ \r
+ if ( sequence < (sse_sequence_handle_t)ACE_NB_OF_SSE_PROCEDURES )\r
+ {\r
+ uint16_t pc;\r
+ \r
+ pc = g_sse_sequences_desc_table[sequence].sse_loop_pc;\r
+ \r
+ if ( pc < 256u )\r
+ {\r
+ *sse_pc_lo_lut[g_sse_sequences_desc_table[sequence].sse_pc_id] = pc;\r
+ }\r
+ else\r
+ {\r
+ *sse_pc_hi_lut[g_sse_sequences_desc_table[sequence].sse_pc_id] = pc - 256;\r
+ }\r
+ \r
+ *sse_pc_ctrl_lut[g_sse_sequences_desc_table[sequence].sse_pc_id] = SSE_START;\r
+ }\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+void ACE_stop_sse\r
+(\r
+ sse_sequence_handle_t sequence\r
+)\r
+{\r
+ ASSERT( sequence < ACE_NB_OF_SSE_PROCEDURES );\r
+ \r
+ if ( sequence < (sse_sequence_handle_t)ACE_NB_OF_SSE_PROCEDURES )\r
+ {\r
+ /* Stop relevant program counter. */\r
+ *sse_pc_ctrl_lut[g_sse_sequences_desc_table[sequence].sse_pc_id] = SSE_STOP;\r
+ }\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+void ACE_resume_sse\r
+(\r
+ sse_sequence_handle_t sequence\r
+)\r
+{\r
+ ASSERT( sequence < ACE_NB_OF_SSE_PROCEDURES );\r
+ \r
+ if ( sequence < (sse_sequence_handle_t)ACE_NB_OF_SSE_PROCEDURES )\r
+ {\r
+ *sse_pc_ctrl_lut[g_sse_sequences_desc_table[sequence].sse_pc_id] = SSE_START;\r
+ }\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+void ACE_enable_sse_irq\r
+(\r
+ sse_irq_id_t sse_irq_id\r
+)\r
+{\r
+ ASSERT( sse_irq_id < NB_OF_SSE_FLAG_IRQS );\r
+ \r
+ ACE->SSE_IRQ_EN |= 1uL << (uint32_t)sse_irq_id;\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+void ACE_disable_sse_irq\r
+(\r
+ sse_irq_id_t sse_irq_id\r
+)\r
+{\r
+ ASSERT( sse_irq_id < NB_OF_SSE_FLAG_IRQS );\r
+ \r
+ ACE->SSE_IRQ_EN &= (uint32_t)~(1uL << (uint32_t)sse_irq_id);\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+void ACE_clear_sse_irq\r
+(\r
+ sse_irq_id_t sse_irq_id\r
+)\r
+{\r
+ ASSERT( sse_irq_id < NB_OF_SSE_FLAG_IRQS );\r
+ \r
+ ACE->SSE_IRQ_CLR |= 1uL << (uint32_t)sse_irq_id;\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+void ACE_clear_sample_pipeline(void)\r
+{\r
+ uint32_t saved_sse_ctrl;\r
+ uint32_t saved_ppe_ctrl;\r
+ \r
+ /* Pause the Sample Sequencing Engine. */\r
+ saved_sse_ctrl = ACE->SSE_TS_CTRL;\r
+ ACE->SSE_TS_CTRL = ACE->SSE_TS_CTRL & ~((uint32_t)TS_ENABLE_MASK);\r
+ \r
+ /* Pause the Post Processing Engine. */\r
+ saved_ppe_ctrl = ACE->PPE_CTRL;\r
+ ACE->PPE_CTRL = ACE->PPE_CTRL & ~((uint32_t)PPE_ENABLE_MASK);\r
+ \r
+ /* Reset the ADCs */\r
+ ACE->ADC0_MISC_CTRL |= ADC_RESET_MASK;\r
+ ACE->ADC1_MISC_CTRL |= ADC_RESET_MASK;\r
+ ACE->ADC2_MISC_CTRL |= ADC_RESET_MASK;\r
+ \r
+ /* Clear ADC FIFOs */\r
+ ACE->ADC0_FIFO_CTRL |= ADC_FIFO_CLR_MASK;\r
+ ACE->ADC1_FIFO_CTRL |= ADC_FIFO_CLR_MASK;\r
+ ACE->ADC2_FIFO_CTRL |= ADC_FIFO_CLR_MASK;\r
+ \r
+ /* clear DMA FIFOs */\r
+ ACE->PPE_PDMA_CTRL |= PDMA_DATAOUT_CLR_MASK;\r
+ \r
+ /* Unpause the Post Processing Engine. */\r
+ ACE->PPE_CTRL = saved_ppe_ctrl;\r
+ \r
+ /* Unpause the Sample Sequencing Engine. */\r
+ ACE->SSE_TS_CTRL = saved_sse_ctrl;\r
+}\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
--- /dev/null
+/*******************************************************************************\r
+ * (c) Copyright 2010 Actel Corporation. All rights reserved.\r
+ *\r
+ * This file contains the implementation of the functions used to dynamically\r
+ * control the linear transforms applied by the ACE post processing engine to\r
+ * the samples read from the SSE.\r
+ *\r
+ * SVN $Revision: 2908 $\r
+ * SVN $Date: 2010-08-20 16:01:28 +0100 (Fri, 20 Aug 2010) $\r
+ */\r
+\r
+#include "mss_ace.h"\r
+#include "mss_ace_configurator.h"\r
+#include "mtd_data.h"\r
+#include "envm_layout.h"\r
+#include "../../CMSIS/a2fxxxm3.h"\r
+#include "../../CMSIS/mss_assert.h"\r
+#include "../../drivers_config/mss_ace/ace_config.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif \r
+\r
+/*\r
+ * The ACE_set_linear_transform() is only available when using ACE configuration\r
+ * files generated by Libero 9.1 or later.\r
+ */\r
+#ifdef ACE_CFG_DATA_FORMAT_VERSION\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Masks ans shift values used to derive the ABPS ranges from the analog block\r
+ * configuration.\r
+ */\r
+#define ABPS1_CFG_BITS_MASK (uint32_t)0x06\r
+#define ABPS1_CFG_BITS_SHIFT (uint32_t)1\r
+\r
+#define ABPS2_CFG_BITS_MASK (uint32_t)0x60\r
+#define ABPS2_CFG_BITS_SHIFT (uint32_t)5\r
+\r
+/*------------------------------------------------------------------------------\r
+ * One Bit DAC definitions.\r
+ */\r
+#define OBD_CURRENT (uint32_t)1\r
+#define OBD_VOLTAGE (uint32_t)0\r
+\r
+#define OBD_MODE_MASK (uint32_t)0x01\r
+#define OBD_CHOPPING_MASK (uint32_t)0x02\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ Neutral factor and offset for m*x + c trnasform.\r
+ */\r
+#define NEUTRAL_M_FACTOR 0x4000\r
+#define NEUTRAL_C_OFFSET 0x0000\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ Enumearation of the various input channel types. This is used to differentiate\r
+ between channel types in order to extract the relevant factory calibration\r
+ data(m1 and c1).\r
+ */\r
+typedef enum channel_type\r
+{\r
+ ABPS1_CHAN = 0,\r
+ ABPS2_CHAN,\r
+ CMB_CHAN,\r
+ TMB_CHAN,\r
+ DIRECT_ADC_INPUT_CHAN,\r
+ OBDOUT_CHAN,\r
+ FLOATING_CHAN\r
+} cal_channel_type_t;\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ This data structure is used to store factory calibration data for a specific\r
+ analog input.\r
+ */\r
+typedef struct __channel_calibration_t\r
+{\r
+ uint16_t mext;\r
+ uint16_t m1;\r
+ uint16_t c1;\r
+} channel_calibration_t;\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ Local functions\r
+ */\r
+int32_t extend_sign\r
+(\r
+ uint16_t x\r
+);\r
+\r
+uint32_t adjust_to_24bit_ace_format\r
+(\r
+ int64_t signed48\r
+);\r
+\r
+uint32_t adjust_to_16bit_ace_format\r
+(\r
+ int64_t signed48\r
+);\r
+\r
+void get_calibration\r
+(\r
+ adc_channel_id_t channel_id,\r
+ channel_calibration_t * p_calibration\r
+);\r
+\r
+void write_transform_coefficients\r
+(\r
+ ace_channel_handle_t channel_handle,\r
+ uint32_t m,\r
+ uint32_t c\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ \r
+ */\r
+extern const uint8_t g_ace_external_varef_used[ACE_NB_OF_ADC];\r
+\r
+extern ace_channel_desc_t g_ace_channel_desc_table[ACE_NB_OF_INPUT_CHANNELS];\r
+\r
+extern const ppe_transforms_desc_t g_ace_ppe_transforms_desc_table[ACE_NB_OF_INPUT_CHANNELS];\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Pointer to the manufacturing test data containing trimming information\r
+ * generated during manufacturing.\r
+ */\r
+static const mtd_data_t * const p_mtd_data = (mtd_data_t *)MTD_ADDRESS;\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ See "mss_ace.h" for details of how to use this function.\r
+ */\r
+int16_t ACE_get_default_m_factor\r
+(\r
+ ace_channel_handle_t channel_handle\r
+)\r
+{\r
+ ASSERT( channel_handle < NB_OF_ACE_CHANNEL_HANDLES );\r
+ \r
+ return g_ace_ppe_transforms_desc_table[channel_handle].m_ppe_offset;\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ See "mss_ace.h" for details of how to use this function.\r
+ */\r
+int16_t ACE_get_default_c_offset\r
+(\r
+ ace_channel_handle_t channel_handle\r
+)\r
+{\r
+ ASSERT( channel_handle < NB_OF_ACE_CHANNEL_HANDLES );\r
+ \r
+ return g_ace_ppe_transforms_desc_table[channel_handle].c_ppe_offset;\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ See "mss_ace.h" for details of how to use this function.\r
+ \r
+ m = m2 * m1 * mext\r
+ c = (m2 * c1 * mext) + (c2 * mext)\r
+ */\r
+void ACE_set_linear_transform\r
+(\r
+ ace_channel_handle_t channel_handle,\r
+ int16_t m2,\r
+ int16_t c2\r
+)\r
+{\r
+ adc_channel_id_t channel_id;\r
+ uint32_t m;\r
+ uint32_t c;\r
+ int32_t m32;\r
+ int64_t m64;\r
+ int32_t c32;\r
+ int64_t c64_1;\r
+ int64_t c64_2;\r
+ uint16_t m1;\r
+ uint16_t c1;\r
+ uint16_t mext;\r
+ \r
+ channel_calibration_t calibration;\r
+ \r
+ ASSERT( channel_handle < NB_OF_ACE_CHANNEL_HANDLES );\r
+ \r
+ if(channel_handle < NB_OF_ACE_CHANNEL_HANDLES)\r
+ {\r
+ channel_id = g_ace_channel_desc_table[channel_handle].signal_id;\r
+ \r
+ get_calibration(channel_id, &calibration);\r
+ \r
+ m1 = calibration.m1;\r
+ c1 = calibration.c1;\r
+ \r
+ mext = calibration.mext;\r
+\r
+ /* \r
+ * m = m2 * m1 * mext\r
+ */\r
+ m32 = extend_sign(m2) * extend_sign(m1);\r
+ m64 = (int64_t)m32 * extend_sign(mext);\r
+ \r
+ /* Convert 48-bit result to 32-bit ACE format result. */\r
+ m = adjust_to_16bit_ace_format(m64);\r
+\r
+ /*\r
+ * c = (m2 * c1 * mext) + (c2 * mext)\r
+ */\r
+ c32 = extend_sign(m2) * extend_sign(c1);\r
+ c64_1 = (int64_t)c32 * extend_sign(mext);\r
+\r
+ c64_2 = ((int64_t)(extend_sign(c2) * extend_sign(mext))) << 14;\r
+ \r
+ c = adjust_to_24bit_ace_format(c64_1 + c64_2);\r
+ \r
+ write_transform_coefficients(channel_handle, m, c);\r
+ }\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ Extend 16-bit signed number to 32-bit signed number.\r
+ */\r
+int32_t extend_sign\r
+(\r
+ uint16_t x\r
+)\r
+{\r
+ int32_t y;\r
+ const uint32_t sign_bit_mask = 0x00008000u;\r
+ \r
+ y = (x ^ sign_bit_mask) - sign_bit_mask;\r
+ \r
+ return y;\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ Take a 48-bit signed number, adjust it for saturation in the range -8 to\r
+ +7.999, translate into 24-bit ACE format.\r
+ */\r
+uint32_t adjust_to_24bit_ace_format\r
+(\r
+ int64_t signed48\r
+)\r
+{\r
+ int32_t ace24_format;\r
+ const int64_t MAX_POSITIVE = 0x00001FFFFFFFFFFFuLL; /* +7.9999 */\r
+ const int64_t MIN_NEGATIVE = 0xFFFF200000000000uLL; /* -8 */\r
+ \r
+ /* Check saturation. */\r
+ if(signed48 > MAX_POSITIVE)\r
+ {\r
+ signed48 = MAX_POSITIVE;\r
+ }\r
+ else if(signed48 < MIN_NEGATIVE)\r
+ {\r
+ signed48 = MIN_NEGATIVE;\r
+ }\r
+ \r
+ /* Adjust to 24-bit ACE format. */\r
+ ace24_format = (uint32_t)(signed48 >> 14);\r
+ \r
+ return ace24_format;\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ Take a 48-bit signed number, adjust it for saturation in the range -8 to\r
+ +7.999, translate into 16-bit ACE format.\r
+ */\r
+uint32_t adjust_to_16bit_ace_format\r
+(\r
+ int64_t signed48\r
+)\r
+{\r
+ int32_t ace24_format;\r
+ const int64_t MAX_POSITIVE = 0x00001FFFFFFFFFFFuLL; /* +7.9999 */\r
+ const int64_t MIN_NEGATIVE = 0xFFFF200000000000uLL; /* -8 */\r
+ \r
+ /* Check saturation. */\r
+ if(signed48 > MAX_POSITIVE)\r
+ {\r
+ signed48 = MAX_POSITIVE;\r
+ }\r
+ else if(signed48 < MIN_NEGATIVE)\r
+ {\r
+ signed48 = MIN_NEGATIVE;\r
+ }\r
+ \r
+ /* Adjust to 24-bit ACE format. */\r
+ ace24_format = (uint32_t)(signed48 >> 20);\r
+ \r
+ return ace24_format;\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ \r
+ */\r
+void get_calibration\r
+(\r
+ adc_channel_id_t channel_id,\r
+ channel_calibration_t * p_calibration\r
+)\r
+{\r
+ const uint32_t channel_mask = 0x0000000F;\r
+ const uint32_t CMB_MUX_SEL_MASK = 0x01;\r
+ const uint32_t TMB_MUX_SEL_MASK = 0x01;\r
+ \r
+ const cal_channel_type_t channel_type_lut[16] =\r
+ {\r
+ FLOATING_CHAN,\r
+ ABPS1_CHAN,\r
+ ABPS2_CHAN,\r
+ CMB_CHAN,\r
+ TMB_CHAN,\r
+ ABPS1_CHAN,\r
+ ABPS2_CHAN,\r
+ CMB_CHAN,\r
+ TMB_CHAN,\r
+ DIRECT_ADC_INPUT_CHAN,\r
+ DIRECT_ADC_INPUT_CHAN,\r
+ DIRECT_ADC_INPUT_CHAN,\r
+ DIRECT_ADC_INPUT_CHAN,\r
+ FLOATING_CHAN,\r
+ FLOATING_CHAN,\r
+ OBDOUT_CHAN\r
+ };\r
+ \r
+ cal_channel_type_t channel_type;\r
+ uint32_t channel_nb;\r
+ uint32_t adc_nb;\r
+ uint32_t range;\r
+ uint32_t quad_id;\r
+ mtd_calibration_mc_t const * p_mc_coeff = 0;\r
+ \r
+ channel_nb = channel_id & channel_mask;\r
+ channel_type = channel_type_lut[channel_nb];\r
+ adc_nb = ((uint32_t)channel_id & 0x30u) >> 4u;\r
+ \r
+ quad_id = adc_nb * 2;\r
+ \r
+ if ( (channel_nb > 4) && (channel_nb < 9) ) { ++quad_id; }\r
+ \r
+ switch ( channel_type )\r
+ {\r
+ case ABPS1_CHAN:\r
+ range = (ACE->ACB_DATA[quad_id].b8 & ABPS1_CFG_BITS_MASK) >> ABPS1_CFG_BITS_SHIFT;\r
+ p_mc_coeff = &p_mtd_data->abps_calibration[quad_id][0][range];\r
+ break;\r
+ \r
+ case ABPS2_CHAN:\r
+ range = (ACE->ACB_DATA[quad_id].b8 & ABPS2_CFG_BITS_MASK) >> ABPS2_CFG_BITS_SHIFT;\r
+ p_mc_coeff = &p_mtd_data->abps_calibration[quad_id][1][range];\r
+ break;\r
+ \r
+ case CMB_CHAN:\r
+ {\r
+ uint32_t cmb_mux_sel = (uint32_t)ACE->ACB_DATA[quad_id].b9 & CMB_MUX_SEL_MASK;\r
+ if ( cmb_mux_sel == 0 )\r
+ { /* current monitor */\r
+ p_mc_coeff = &p_mtd_data->cm_calibration[quad_id];\r
+ }\r
+ else\r
+ { /* direct input */\r
+ p_mc_coeff = &p_mtd_data->quads_direct_input_cal[quad_id][0];\r
+ }\r
+ }\r
+ break;\r
+ \r
+ case TMB_CHAN:\r
+ {\r
+ uint32_t tmb_mux_sel = (uint32_t)ACE->ACB_DATA[quad_id].b10 & TMB_MUX_SEL_MASK;\r
+ if ( tmb_mux_sel == 0 )\r
+ { /* temperature monitor */\r
+ p_mc_coeff = &p_mtd_data->tm_calibration[quad_id];\r
+ }\r
+ else\r
+ { /* direct input */\r
+ p_mc_coeff = &p_mtd_data->quads_direct_input_cal[quad_id][1];\r
+ }\r
+ }\r
+ break;\r
+ \r
+ case DIRECT_ADC_INPUT_CHAN:\r
+ {\r
+ const uint32_t channel_to_direct_in_lut[16]\r
+ = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 0, 0, 0};\r
+ uint32_t direct_in_id;\r
+ \r
+ direct_in_id = channel_to_direct_in_lut[channel_id & channel_mask];\r
+ p_mc_coeff = &p_mtd_data->adc_direct_input_cal[adc_nb][direct_in_id];\r
+ }\r
+ break;\r
+ \r
+ case OBDOUT_CHAN:\r
+ {\r
+ uint32_t obd_mode = (uint32_t)ACE->ACB_DATA[quad_id].b6 & OBD_MODE_MASK;\r
+ uint32_t chopping_option = (uint32_t)ACE->ACB_DATA[quad_id].b6 & OBD_CHOPPING_MASK;\r
+ if (obd_mode > 0)\r
+ {\r
+ obd_mode = 1;\r
+ }\r
+ if (chopping_option > 0)\r
+ {\r
+ chopping_option = 1;\r
+ }\r
+ p_mc_coeff = &p_mtd_data->obd_calibration[adc_nb][obd_mode][chopping_option];\r
+ }\r
+ break;\r
+ \r
+ case FLOATING_CHAN:\r
+ default:\r
+ /* Give neutral values is invalid channel. */\r
+ p_calibration->m1 = NEUTRAL_M_FACTOR;\r
+ p_calibration->c1 = NEUTRAL_C_OFFSET;\r
+ break;\r
+ }\r
+ \r
+ if (p_mc_coeff != 0)\r
+ {\r
+ p_calibration->m1 = p_mc_coeff->m;\r
+ p_calibration->c1 = p_mc_coeff->c;\r
+ \r
+ }\r
+ \r
+ /*--------------------------------------------------------------------------\r
+ Retrieve the value of the mext factor. This depends if external VAREF is\r
+ used by the ADC sampling the analog input channel.\r
+ */\r
+ if (g_ace_external_varef_used[adc_nb])\r
+ {\r
+ p_calibration->mext = p_mtd_data->global_settings.varef_m;\r
+ }\r
+ else\r
+ {\r
+ p_calibration->mext = NEUTRAL_M_FACTOR;\r
+ }\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ Write new m and c transform factors into the PPE RAM. The m and c factors\r
+ should be in 32-bit ACE number format. The factors will be merged with\r
+ relevant PE opcode into PPE RAM. The 32-bit factors are shifted right by one\r
+ byte giving a 24-bit ACE number which is then merged with an 8-bit PPE opcode\r
+ located in the most significant byte of the PPE RAM location.\r
+ */\r
+void write_transform_coefficients\r
+(\r
+ ace_channel_handle_t channel_handle,\r
+ uint32_t m,\r
+ uint32_t c\r
+)\r
+{\r
+ uint16_t m_ppe_offset;\r
+ uint16_t c_ppe_offset;\r
+ const uint32_t PPE_OPCODE_MASK = 0xFF000000u;\r
+ \r
+ m_ppe_offset = g_ace_ppe_transforms_desc_table[channel_handle].m_ppe_offset;\r
+ c_ppe_offset = g_ace_ppe_transforms_desc_table[channel_handle].c_ppe_offset;\r
+ \r
+ ACE->PPE_RAM_DATA[m_ppe_offset]\r
+ = (ACE->PPE_RAM_DATA[m_ppe_offset] & PPE_OPCODE_MASK) | (m >> 8u);\r
+ \r
+ ACE->PPE_RAM_DATA[c_ppe_offset]\r
+ = (ACE->PPE_RAM_DATA[c_ppe_offset] & PPE_OPCODE_MASK) | (c >> 8u);\r
+}\r
+\r
+#endif /* ACE_CFG_DATA_FORMAT_VERSION */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
--- /dev/null
+/*******************************************************************************\r
+ * (c) Copyright 2009 Actel Corporation. All rights reserved.\r
+ * \r
+ * This file contains the addresses and size of the various blocks of data\r
+ * stored in eNVM.\r
+ *\r
+ * SVN $Revision: 1113 $\r
+ * SVN $Date: 2009-07-01 11:11:29 +0100 (Wed, 01 Jul 2009) $\r
+ */\r
+#ifndef ENVM_LAYOUT_HEADER\r
+#define ENVM_LAYOUT_HEADER\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif \r
+\r
+/*==============================================================================\r
+ * Address of the manufacturing test data.\r
+ */\r
+#define MTD_ADDRESS 0x60080010\r
+\r
+/*==============================================================================\r
+ * MSS configuration location.\r
+ */\r
+#define MSS_CONFIG_ADDRESS 0x60081618\r
+\r
+/*==============================================================================\r
+ * Analog configuration location and size.\r
+ */\r
+#define ANALOG_CONFIG_ADDRESS 0x60081600\r
+#define ANALOG_CONFIG_BYTE_SIZE 24\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* ENVM_LAYOUT_HEADER */\r
--- /dev/null
+/*******************************************************************************\r
+ * (c) Copyright 2009 Actel Corporation. All rights reserved.\r
+ * \r
+ * SVN $Revision: 2905 $\r
+ * SVN $Date: 2010-08-20 14:03:28 +0100 (Fri, 20 Aug 2010) $\r
+ */\r
+\r
+#include "mss_ace.h"\r
+#include "mtd_data.h"\r
+#include "envm_layout.h"\r
+#include "mss_ace_configurator.h"\r
+#include "../../CMSIS/a2fxxxm3.h"\r
+#include "../../CMSIS/mss_assert.h"\r
+#include "../../drivers_config/mss_ace/ace_config.h"\r
+#include <string.h>\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif \r
+\r
+#define START_ADC_CONVERSION 0x80uL\r
+\r
+\r
+/**/\r
+void ace_init_flags( void );\r
+void ace_init_convert(void);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ See "mss_ace.h" for details of how to use this function.\r
+ */\r
+void ACE_init( void )\r
+{\r
+ /* Initialize driver's internal data. */\r
+ ace_init_flags();\r
+ \r
+ /* Initialize the data structures used by conversion functions. */\r
+ ace_init_convert();\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ See "mss_ace.h" for details of how to use this function.\r
+ */\r
+void ACE_start_adc\r
+(\r
+ adc_channel_id_t channel_id\r
+)\r
+{\r
+ ACE->ADC0_CONV_CTRL = (uint32_t)channel_id | START_ADC_CONVERSION;\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ See "mss_ace.h" for details of how to use this function.\r
+ */\r
+#define ADC_DATAVALID_MASK 0x00001000uL\r
+#define ADC_RESULT_MASK 0x00000FFFuL\r
+\r
+static const uint32_t volatile * const adc_status_reg_lut[NB_OF_ANALOG_MODULES] =\r
+{\r
+ &ACE->ADC0_STATUS,\r
+ &ACE->ADC1_STATUS,\r
+ &ACE->ADC2_STATUS\r
+};\r
+\r
+uint16_t ACE_get_adc_result\r
+(\r
+ uint8_t adc_id\r
+)\r
+{\r
+ uint16_t result = 0u;\r
+ uint32_t data_valid;\r
+\r
+ ASSERT( adc_id < NB_OF_ANALOG_MODULES );\r
+ \r
+ if ( adc_id < (uint8_t)NB_OF_ANALOG_MODULES )\r
+ {\r
+ do {\r
+ data_valid = *adc_status_reg_lut[adc_id] & ADC_DATAVALID_MASK;\r
+ } while ( !data_valid );\r
+ \r
+ result = (uint16_t)(*adc_status_reg_lut[adc_id] & ADC_RESULT_MASK);\r
+ }\r
+ return result;\r
+}\r
+\r
+/*==============================================================================\r
+ =========== Sigma Delta Digital to Analog Converters (SDD) Control ============\r
+ =============================================================================*/\r
+\r
+#define SDD_ENABLE_MASK 0x20uL\r
+#define SDD_REG_SEL_MASK 0x40uL\r
+ \r
+#define DAC0_SYNC_EN_MASK 0x10uL\r
+#define DAC1_SYNC_EN_MASK 0x20uL\r
+#define DAC2_SYNC_EN_MASK 0x40uL\r
+\r
+#define DAC0_SYNC_UPDATE 0x01uL\r
+#define DAC1_SYNC_UPDATE 0x02uL\r
+#define DAC2_SYNC_UPDATE 0x04uL\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+static volatile uint32_t * const dac_ctrl_reg_lut[NB_OF_ANALOG_MODULES] =\r
+{\r
+ &ACE->DAC0_CTRL,\r
+ &ACE->DAC1_CTRL,\r
+ &ACE->DAC1_CTRL\r
+};\r
+\r
+static const uint32_t dac_enable_masks_lut[NB_OF_ANALOG_MODULES] =\r
+{\r
+ DAC0_SYNC_EN_MASK,\r
+ DAC1_SYNC_EN_MASK,\r
+ DAC2_SYNC_EN_MASK\r
+};\r
+\r
+static volatile uint32_t * const dac_byte01_reg_lut[NB_OF_ANALOG_MODULES] =\r
+{\r
+ &ACE->SSE_DAC0_BYTES01,\r
+ &ACE->SSE_DAC1_BYTES01,\r
+ &ACE->SSE_DAC2_BYTES01,\r
+};\r
+\r
+static volatile uint32_t * const dac_byte2_reg_lut[NB_OF_ANALOG_MODULES] =\r
+{\r
+ &ACE->DAC0_BYTE2,\r
+ &ACE->DAC1_BYTE2,\r
+ &ACE->DAC2_BYTE2\r
+};\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Pointer to the manufacturing test data containing trimming information\r
+ * generated during manufacturing.\r
+ */\r
+static const mtd_data_t * const p_mtd_data = (mtd_data_t *)MTD_ADDRESS;\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ See "mss_ace.h" for details of how to use this function.\r
+ */\r
+#define OBD_MODE_MASK (uint8_t)0x01\r
+#define OBD_CHOPPING_MASK (uint8_t)0x02\r
+\r
+void ACE_configure_sdd\r
+(\r
+ sdd_id_t sdd_id,\r
+ sdd_resolution_t resolution,\r
+ uint8_t mode,\r
+ sdd_update_method_t sync_update\r
+)\r
+{\r
+ ASSERT( sdd_id < NB_OF_SDD );\r
+ \r
+ if ( sdd_id < NB_OF_SDD )\r
+ {\r
+ const uint8_t sdd_2_quad_lut[NB_OF_SDD] = {0u, 2u, 4u};\r
+ uint8_t quad_id;\r
+ uint8_t obd_mode_idx = 1u;\r
+ uint8_t chopping_mode_idx = 0u;\r
+ uint32_t saved_pc2_ctrl;\r
+ \r
+ quad_id = sdd_2_quad_lut[sdd_id];\r
+ \r
+ /* Pause the SSE PC2 while accesses to ACB from APB3 are taking place. */\r
+ saved_pc2_ctrl = ACE->PC2_CTRL;\r
+ ACE->PC2_CTRL = 0u;\r
+ \r
+ /* Select between voltage/current and RTZ modes.*/\r
+ ACE->ACB_DATA[quad_id].b6 = mode;\r
+ \r
+ /* Load manufacturing generated trim value. */\r
+ if ( (mode & OBD_MODE_MASK) > 0u )\r
+ {\r
+ obd_mode_idx = 0u;\r
+ }\r
+ if ( (mode & OBD_CHOPPING_MASK) > 0u )\r
+ {\r
+ chopping_mode_idx = 1u;\r
+ }\r
+ ACE->ACB_DATA[quad_id].b4\r
+ = p_mtd_data->odb_trimming[sdd_id][obd_mode_idx][chopping_mode_idx];\r
+ \r
+ /* Restore SSE PC2 operations since no ACB accesses should take place\r
+ * beyond this point. */\r
+ ACE->PC2_CTRL = saved_pc2_ctrl;\r
+ \r
+ /* Set SDD resolution. */\r
+ *dac_ctrl_reg_lut[sdd_id] = (uint32_t)resolution;\r
+ \r
+ /* Update SDD value through SSE_DACn_BYTES01. */\r
+ *dac_ctrl_reg_lut[sdd_id] |= SDD_REG_SEL_MASK;\r
+ \r
+ /* Synchronous or individual SDD update. */\r
+ if ( INDIVIDUAL_UPDATE == sync_update )\r
+ {\r
+ ACE->DAC_SYNC_CTRL &= ~dac_enable_masks_lut[sdd_id];\r
+ }\r
+ else\r
+ {\r
+ ACE->DAC_SYNC_CTRL |= dac_enable_masks_lut[sdd_id];\r
+ }\r
+ }\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ See "mss_ace.h" for details of how to use this function.\r
+ */\r
+void ACE_enable_sdd\r
+(\r
+ sdd_id_t sdd_id\r
+)\r
+{\r
+ ASSERT( sdd_id < NB_OF_SDD );\r
+ \r
+ if ( sdd_id < NB_OF_SDD )\r
+ {\r
+ *dac_ctrl_reg_lut[sdd_id] |= SDD_ENABLE_MASK;\r
+ }\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ See "mss_ace.h" for details of how to use this function.\r
+ */\r
+void ACE_disable_sdd\r
+(\r
+ sdd_id_t sdd_id\r
+)\r
+{\r
+ ASSERT( sdd_id < NB_OF_SDD );\r
+ \r
+ if ( sdd_id < NB_OF_SDD )\r
+ {\r
+ *dac_ctrl_reg_lut[sdd_id] &= ~SDD_ENABLE_MASK;\r
+ }\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ See "mss_ace.h" for details of how to use this function.\r
+ */\r
+void ACE_set_sdd_value\r
+(\r
+ sdd_id_t sdd_id,\r
+ uint32_t sdd_value\r
+)\r
+{\r
+ ASSERT( sdd_id < NB_OF_SDD );\r
+ \r
+ if ( sdd_id < NB_OF_SDD )\r
+ {\r
+ *dac_byte2_reg_lut[sdd_id] = sdd_value >> 16;\r
+ *dac_byte01_reg_lut[sdd_id] = sdd_value;\r
+ }\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ See "mss_ace.h" for details of how to use this function.\r
+ */\r
+void ACE_set_sdd_value_sync\r
+(\r
+ uint32_t sdd0_value,\r
+ uint32_t sdd1_value,\r
+ uint32_t sdd2_value\r
+)\r
+{\r
+ uint32_t dac_sync_ctrl;\r
+ \r
+ dac_sync_ctrl = ACE->DAC_SYNC_CTRL;\r
+ \r
+ if ( SDD_NO_UPDATE != sdd0_value )\r
+ {\r
+ ACE->DAC0_BYTE2 = sdd0_value >> 16;\r
+ ACE->SSE_DAC0_BYTES01 = sdd0_value;\r
+ dac_sync_ctrl |= DAC0_SYNC_UPDATE;\r
+ }\r
+\r
+ if ( SDD_NO_UPDATE != sdd1_value )\r
+ {\r
+ ACE->DAC1_BYTE2 = sdd1_value >> 16;\r
+ ACE->SSE_DAC1_BYTES01 = sdd1_value;\r
+ dac_sync_ctrl |= DAC1_SYNC_UPDATE;\r
+ }\r
+\r
+ if ( SDD_NO_UPDATE != sdd2_value )\r
+ {\r
+ ACE->DAC2_BYTE2 = sdd2_value >> 16;\r
+ ACE->DAC2_BYTE1 = sdd2_value >> 8;\r
+ ACE->SSE_DAC2_BYTES01 = sdd2_value;\r
+ dac_sync_ctrl |= DAC2_SYNC_UPDATE;\r
+ }\r
+ \r
+ ACE->DAC_SYNC_CTRL = dac_sync_ctrl;\r
+}\r
+\r
+/*==============================================================================\r
+ ============================ Comparators Control ==============================\r
+ =============================================================================*/\r
+\r
+ /*\r
+ * SDD Analog switch mask. ACB byte 10.\r
+ * 0: TMB comparator reference voltage is an ADC direct input\r
+ * 1: TMB comparator reference voltage is one of the SDD outputs as\r
+ * selected by DAC_MUXSEL[1:0]\r
+ */\r
+#define B10_COMP_VREF_SW_MASK 0x20u\r
+\r
+/*\r
+ * Comparator reference voltage multiplexer.\r
+ * Used to select which SDD output will be used as reference voltage for TMB\r
+ * comparator. These bits are only meaningful when COMP_VREF_SW is set to 1.\r
+ */\r
+#define B11_DAC_MUXSEL_MASK 0x03u\r
+\r
+/*\r
+ * Number of bits to shift a value of type comp_hysteresis_t to get the\r
+ * hysteresis to program into ACB b9 or b10.\r
+ */\r
+#define HYSTERESIS_SHIFT 6u\r
+\r
+/*\r
+ * Mask of hysteresis bits within ACB b9 or b10.\r
+ */\r
+#define HYSTERESIS_MASK 0xC0u\r
+\r
+/*\r
+ * Mask of the comparator enable bit within ACB b9 and b10.\r
+ */\r
+#define COMPARATOR_ENABLE_MASK 0x10u\r
+\r
+/*\r
+ * Comparator ID to Signal Conditioning Block (SCB) lookup table.\r
+ * USe to find which SCB a comparator belongs to.\r
+ */\r
+const uint8_t comp_id_2_scb_lut[NB_OF_COMPARATORS] =\r
+{\r
+ 0u, /* CMP0 */\r
+ 0u, /* CMP1 */\r
+ 1u, /* CMP2 */\r
+ 1u, /* CMP3 */\r
+ 2u, /* CMP4 */\r
+ 2u, /* CMP5 */\r
+ 3u, /* CMP6 */\r
+ 3u, /* CMP7 */\r
+ 4u, /* CMP8 */\r
+ 4u, /* CMP9 */\r
+ 5u, /* CMP10 */\r
+ 5u /* CMP11 */\r
+};\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ * This function is requred to configure comparators included in temperature\r
+ * monitor blocks.\r
+ */\r
+void ACE_set_comp_reference\r
+(\r
+ comparator_id_t comp_id,\r
+ comp_reference_t reference\r
+)\r
+{\r
+ uint8_t scb_id;\r
+ uint32_t odd;\r
+ \r
+ odd = (uint32_t)comp_id & 0x01uL;\r
+ \r
+ ASSERT( comp_id < NB_OF_COMPARATORS );\r
+ ASSERT( reference < NB_OF_COMP_REF );\r
+ ASSERT( odd ); /* Only Temperature block comparators have configurable reference input. */\r
+ \r
+ if ( (comp_id < NB_OF_COMPARATORS) && (reference < NB_OF_COMP_REF) && (odd) )\r
+ {\r
+ uint32_t saved_pc2_ctrl;\r
+ \r
+ scb_id = comp_id_2_scb_lut[comp_id];\r
+ \r
+ /* Pause the SSE PC2 while accesses to ACB from APB3 are taking place. */\r
+ saved_pc2_ctrl = ACE->PC2_CTRL;\r
+ ACE->PC2_CTRL = 0u;\r
+ \r
+ if ( ADC_IN_COMP_REF == reference )\r
+ {\r
+ ACE->ACB_DATA[scb_id].b10 &= (uint8_t)~B10_COMP_VREF_SW_MASK;\r
+ ACE->ACB_DATA[scb_id].b11 &= (uint8_t)~B11_DAC_MUXSEL_MASK;\r
+ }\r
+ else\r
+ {\r
+ ACE->ACB_DATA[scb_id].b10 &= (uint8_t)~B10_COMP_VREF_SW_MASK;\r
+ ACE->ACB_DATA[scb_id].b11 = (ACE->ACB_DATA[scb_id].b11 & (uint8_t)~B11_DAC_MUXSEL_MASK) + (uint8_t)reference;\r
+ }\r
+ \r
+ /* Restore SSE PC2 operations since no ACB accesses should take place\r
+ * beyond this point. */\r
+ ACE->PC2_CTRL = saved_pc2_ctrl;\r
+ }\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ * Set analog block comparators hysteresis.\r
+ */\r
+void ACE_set_comp_hysteresis\r
+(\r
+ comparator_id_t comp_id,\r
+ comp_hysteresis_t hysteresis\r
+)\r
+{\r
+ uint8_t scb_id;\r
+ \r
+ ASSERT( comp_id < NB_OF_COMPARATORS );\r
+ ASSERT( hysteresis < NB_OF_HYSTERESIS );\r
+ \r
+ if ( (comp_id < NB_OF_COMPARATORS) && (hysteresis < NB_OF_HYSTERESIS) )\r
+ {\r
+ uint32_t odd;\r
+ uint32_t saved_pc2_ctrl;\r
+ \r
+ scb_id = comp_id_2_scb_lut[comp_id];\r
+ odd = (uint32_t)comp_id & 0x01uL;\r
+ \r
+ /* Pause the SSE PC2 while accesses to ACB from APB3 are taking place. */\r
+ saved_pc2_ctrl = ACE->PC2_CTRL;\r
+ ACE->PC2_CTRL = 0u;\r
+ \r
+ if ( odd )\r
+ {\r
+ /* Temperature monitor block comparator. */\r
+ ACE->ACB_DATA[scb_id].b10 = (ACE->ACB_DATA[scb_id].b10 & HYSTERESIS_MASK) | (uint8_t)((uint8_t)hysteresis << HYSTERESIS_SHIFT);\r
+ }\r
+ else\r
+ {\r
+ /* Current monitor block comparator. */\r
+ ACE->ACB_DATA[scb_id].b9 = (ACE->ACB_DATA[scb_id].b9 & HYSTERESIS_MASK) | (uint8_t)((uint8_t)hysteresis << HYSTERESIS_SHIFT);\r
+ }\r
+ \r
+ /* Restore SSE PC2 operations since no ACB accesses should take place\r
+ * beyond this point. */\r
+ ACE->PC2_CTRL = saved_pc2_ctrl;\r
+ }\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ \r
+ */\r
+void ACE_enable_comp\r
+(\r
+ comparator_id_t comp_id\r
+)\r
+{\r
+ uint8_t scb_id;\r
+ \r
+ ASSERT( comp_id < NB_OF_COMPARATORS );\r
+ \r
+ if ( comp_id < NB_OF_COMPARATORS )\r
+ {\r
+ uint32_t odd;\r
+ uint32_t saved_pc2_ctrl;\r
+ \r
+ scb_id = comp_id_2_scb_lut[comp_id];\r
+ odd = (uint32_t)comp_id & 0x01uL;\r
+ \r
+ /* Pause the SSE PC2 while accesses to ACB from APB3 are taking place. */\r
+ saved_pc2_ctrl = ACE->PC2_CTRL;\r
+ ACE->PC2_CTRL = 0u;\r
+ \r
+ if ( odd )\r
+ {\r
+ /* Temperature monitor block comparator. */\r
+ ACE->ACB_DATA[scb_id].b10 |= COMPARATOR_ENABLE_MASK;\r
+ }\r
+ else\r
+ {\r
+ /* Current monitor block comparator. */\r
+ ACE->ACB_DATA[scb_id].b9 |= COMPARATOR_ENABLE_MASK;\r
+ }\r
+ \r
+ /* Restore SSE PC2 operations since no ACB accesses should take place\r
+ * beyond this point. */\r
+ ACE->PC2_CTRL = saved_pc2_ctrl;\r
+ }\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+void ACE_disable_comp\r
+(\r
+ comparator_id_t comp_id\r
+)\r
+{\r
+ uint8_t scb_id;\r
+ \r
+ ASSERT( comp_id < NB_OF_COMPARATORS );\r
+ \r
+ if ( comp_id < NB_OF_COMPARATORS )\r
+ {\r
+ uint32_t odd;\r
+ uint32_t saved_pc2_ctrl;\r
+ \r
+ scb_id = comp_id_2_scb_lut[comp_id];\r
+ odd = (uint32_t)comp_id & 0x01uL;\r
+ \r
+ /* Pause the SSE PC2 while accesses to ACB from APB3 are taking place. */\r
+ saved_pc2_ctrl = ACE->PC2_CTRL;\r
+ ACE->PC2_CTRL = 0u;\r
+ \r
+ if ( odd )\r
+ {\r
+ /* Temperature monitor block comparator. */\r
+ ACE->ACB_DATA[scb_id].b10 &= (uint8_t)~COMPARATOR_ENABLE_MASK;\r
+ }\r
+ else\r
+ {\r
+ /* Current monitor block comparator. */\r
+ ACE->ACB_DATA[scb_id].b9 &= (uint8_t)~COMPARATOR_ENABLE_MASK;\r
+ }\r
+ \r
+ /* Restore SSE PC2 operations since no ACB accesses should take place\r
+ * beyond this point. */\r
+ ACE->PC2_CTRL = saved_pc2_ctrl;\r
+ }\r
+}\r
+\r
+/*\r
+ * Bit mask of comparator 0 rise interrupt bit.\r
+ * Shift this value left by the value of the comparator ID to obtain the bit\r
+ * mask used enable/disable/clear rise interrupts from that comparator.\r
+ */\r
+#define FIRST_RISE_IRQ_MASK 0x00000800uL\r
+\r
+/*\r
+ * Bit mask of comparator 0 fall interrupt bit.\r
+ * Shift this value left by the value of the comparator ID to obtain the bit\r
+ * mask used enable/disable/clear fall interrupts from that comparator.\r
+ */\r
+#define FIRST_FALL_IRQ_MASK 0x00000001uL\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ See "mss_ace.h" for details of how to use this function.\r
+ */\r
+void ACE_enable_comp_rise_irq\r
+(\r
+ comparator_id_t comp_id\r
+)\r
+{\r
+ ASSERT( comp_id < NB_OF_COMPARATORS );\r
+ \r
+ ACE->COMP_IRQ_EN |= (FIRST_RISE_IRQ_MASK << (uint32_t)comp_id);\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ See "mss_ace.h" for details of how to use this function.\r
+ */\r
+void ACE_disable_comp_rise_irq\r
+(\r
+ comparator_id_t comp_id\r
+)\r
+{\r
+ ASSERT( comp_id < NB_OF_COMPARATORS );\r
+ \r
+ ACE->COMP_IRQ_EN &= ~(FIRST_RISE_IRQ_MASK << (uint32_t)comp_id);\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ See "mss_ace.h" for details of how to use this function.\r
+ */\r
+void ACE_clear_comp_rise_irq\r
+(\r
+ comparator_id_t comp_id\r
+)\r
+{\r
+ ASSERT( comp_id < NB_OF_COMPARATORS );\r
+ \r
+ ACE->COMP_IRQ_CLR |= (FIRST_RISE_IRQ_MASK << (uint32_t)comp_id);\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ See "mss_ace.h" for details of how to use this function.\r
+ */\r
+void ACE_enable_comp_fall_irq\r
+(\r
+ comparator_id_t comp_id\r
+)\r
+{\r
+ ASSERT( comp_id < NB_OF_COMPARATORS );\r
+ \r
+ ACE->COMP_IRQ_EN |= (FIRST_FALL_IRQ_MASK << (uint32_t)comp_id);\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ See "mss_ace.h" for details of how to use this function.\r
+ */\r
+void ACE_disable_comp_fall_irq\r
+(\r
+ comparator_id_t comp_id\r
+)\r
+{\r
+ ASSERT( comp_id < NB_OF_COMPARATORS );\r
+ \r
+ ACE->COMP_IRQ_EN &= ~(FIRST_FALL_IRQ_MASK << (uint32_t)comp_id);\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ See "mss_ace.h" for details of how to use this function.\r
+ */\r
+void ACE_clear_comp_fall_irq\r
+(\r
+ comparator_id_t comp_id\r
+)\r
+{\r
+ ASSERT( comp_id < NB_OF_COMPARATORS );\r
+ \r
+ ACE->COMP_IRQ_CLR |= (FIRST_FALL_IRQ_MASK << (uint32_t)comp_id);\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ * Returns the raw analog quad comparator status.\r
+ */\r
+uint32_t ACE_get_comp_status( void )\r
+{\r
+ return ACE->COMP_IRQ;\r
+}\r
+\r
+/*==============================================================================\r
+ ============ Reading Samples from post processing engine (PPE) ================\r
+ =============================================================================*/\r
+extern ace_channel_desc_t g_ace_channel_desc_table[ACE_NB_OF_INPUT_CHANNELS];\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ See "mss_ace.h" for details of how to use this function.\r
+ */\r
+uint32_t\r
+ACE_get_channel_count\r
+(\r
+ void\r
+)\r
+{\r
+ return (uint32_t)ACE_NB_OF_INPUT_CHANNELS;\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ See "mss_ace.h" for details of how to use this function.\r
+ */\r
+ace_channel_handle_t\r
+ACE_get_first_channel\r
+(\r
+ void\r
+)\r
+{\r
+ ace_channel_handle_t channel_handle;\r
+ \r
+ channel_handle = (ace_channel_handle_t)0;\r
+ \r
+ return channel_handle;\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ See "mss_ace.h" for details of how to use this function.\r
+ */\r
+ace_channel_handle_t\r
+ACE_get_next_channel\r
+(\r
+ ace_channel_handle_t channel_handle\r
+)\r
+{\r
+ ++channel_handle;\r
+ \r
+ if ( channel_handle >= NB_OF_ACE_CHANNEL_HANDLES )\r
+ {\r
+ channel_handle = (ace_channel_handle_t)0;\r
+ }\r
+ \r
+ return channel_handle;\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ See "mss_ace.h" for details of how to use this function.\r
+ */\r
+ace_channel_handle_t\r
+ACE_get_channel_handle\r
+(\r
+ const uint8_t * p_sz_channel_name\r
+)\r
+{\r
+ uint16_t channel_idx;\r
+ ace_channel_handle_t channel_handle = INVALID_CHANNEL_HANDLE;\r
+ \r
+ for ( channel_idx = 0u; channel_idx < (uint16_t)ACE_NB_OF_INPUT_CHANNELS; ++channel_idx )\r
+ {\r
+ if ( g_ace_channel_desc_table[channel_idx].p_sz_channel_name != 0 )\r
+ {\r
+ int32_t diff;\r
+ diff = strncmp( (const char*)p_sz_channel_name, (const char*)g_ace_channel_desc_table[channel_idx].p_sz_channel_name, MAX_CHANNEL_NAME_LENGTH );\r
+ if ( 0 == diff )\r
+ {\r
+ /* channel name found. */\r
+ channel_handle = (ace_channel_handle_t)channel_idx;\r
+ break;\r
+ }\r
+ }\r
+ }\r
+ return channel_handle;\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ See "mss_ace.h" for details of how to use this function.\r
+ */\r
+ace_channel_handle_t\r
+ACE_get_input_channel_handle\r
+(\r
+ adc_channel_id_t channel_id\r
+)\r
+{\r
+ uint16_t channel_idx;\r
+ ace_channel_handle_t channel_handle = INVALID_CHANNEL_HANDLE;\r
+ \r
+ for ( channel_idx = 0u; channel_idx < (uint16_t)ACE_NB_OF_INPUT_CHANNELS; ++channel_idx )\r
+ {\r
+ if ( g_ace_channel_desc_table[channel_idx].signal_id == channel_id )\r
+ {\r
+ /* channel ID found. */\r
+ channel_handle = (ace_channel_handle_t)channel_idx;\r
+ break;\r
+ }\r
+ }\r
+ return channel_handle;\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ See "mss_ace.h" for details of how to use this function.\r
+ */\r
+uint16_t\r
+ACE_get_ppe_sample\r
+(\r
+ ace_channel_handle_t channel_handle\r
+)\r
+{\r
+ uint16_t sample;\r
+ uint16_t ppe_offset;\r
+ \r
+ ppe_offset = g_ace_channel_desc_table[channel_handle].signal_ppe_offset;\r
+ sample = (uint16_t)(ACE->PPE_RAM_DATA[ppe_offset] >> 16u);\r
+ \r
+ return sample;\r
+}\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
--- /dev/null
+/*******************************************************************************\r
+ * (c) Copyright 2009 Actel Corporation. All rights reserved.\r
+ * \r
+ * SmartFusion ACE driver public API.\r
+ *\r
+ * SVN $Revision: 2884 $\r
+ * SVN $Date: 2010-08-13 16:16:59 +0100 (Fri, 13 Aug 2010) $\r
+ */\r
+\r
+/*=========================================================================*//**\r
+ @mainpage SmartFusion Analog Compute Engine driver public API.\r
+\r
+ @section intro_sec Introduction\r
+ The SmartFusion\99 microcontroller subsystem (MSS) includes the Analog Compute\r
+ Engine (ACE) which provides access to the analog capabilities of SmartFusion\r
+ from the Cortex\99-M3 microcontroller. This driver provides a set of functions\r
+ for controlling the MSS ACE as part of a bare metal system where no operating\r
+ system is available. These drivers can be adapted for use as part of an\r
+ operating system, but the implementation of the adaptation layer between this\r
+ driver and the operating system's driver model is outside the scope of this\r
+ driver. The ACE includes:\r
+ \95 A Sample Sequencing Engine (SSE) controlling the operations of up to\r
+ three analog to digital converters (ADC)\r
+ \95 A Post Processing Engine (PPE) processing the analog inputs samples\r
+ generated as a result of the SSE operations\r
+ \95 An interface for controlling Sigma Delta DACs (SDD)\r
+ \95 An interface for controlling high speed comparators\r
+\r
+ The Sample Sequencing Engine controls the sampling of the various analog\r
+ inputs based on a predefined sampling sequence without requiring intervention\r
+ from the Cortex-M3. The sampling sequence is defined using the ACE Configurator\r
+ provided as part of the MSS Configurator software tool.\r
+ Available analog inputs are:\r
+ \95 Active bipolar prescaler inputs (ABPS) allowing to measure voltages within\r
+ four possible ranges:\r
+ o -15V to +15V\r
+ o -10V to +10V\r
+ o -5V to +5V\r
+ o -2.5V to +2.5V\r
+ \95 Current inputs\r
+ \95 Temperature inputs\r
+ \95 Direct ADC inputs allowing to measure a voltage between zero volts and\r
+ the ADC\92s reference voltage (VAREF)\r
+ Please refer to the Analog Front End section of the SmartFusion datasheet for\r
+ further details about analog inputs.\r
+\r
+ The Post Processing Engine can perform the following operations on the analog\r
+ input samples generated as a result of the SSE operations:\r
+ \95 Calibration adjustment\r
+ \95 Averaging\r
+ \95 Threshold detection\r
+ \95 DMA transfer of most recent sample result to RAM or FPGA fabric\r
+ The result of analog input sampling is read from the PPE rather than directly\r
+ from the ADC. This ensures more accurate sample results thought the factory\r
+ calibration adjustment performed by the PPE.\r
+ The PPE can be set to generate interrupts when specific threshold values are\r
+ reached on analog inputs through the ACE Configurator software tool. These\r
+ thresholds can also be dynamically adjusted through the ACE driver.\r
+\r
+ The ACE provides an interface to the Sigma Delta DACs included within the\r
+ Analog Front End (AFE). This interface allows control of the DAC\92s output\r
+ value. Dynamic configuration of the DAC is also possible.\r
+\r
+ The ACE provides an interface to the high speed comparators included within\r
+ the Analog Front End. This interface allows dynamic configuration of the\r
+ comparators and controlling interrupts based on the comparators\92 state.\r
+\r
+ @section theory_op Theory of Operation\r
+ The configuration of the ACE is set though the use of the ACE Configurator\r
+ included in the SmartFusion MSS Configurator software tool provided as part of\r
+ the Libero Integrated Design Environment tool suite. The ACE Configurator\r
+ offers an easy to use graphical method of selecting the configuration of the\r
+ following ACE characteristics:\r
+ \95 Analog input channels configuration\r
+ \95 ADC configuration\r
+ \95 Analog input channels sampling sequence\r
+ \95 Filtering applied to analog input samples\r
+ \95 Threshold flags configuration including hysteresis or state filtering properties\r
+ \95 Selection of post processing results transferred though DMA\r
+ \95 Sigma Delta DACs configuration\r
+ \95 Analog comparators configuration\r
+ The selected configuration hardware settings, SSE microcode and PPE microcode\r
+ are stored in the SmartFusion eNVM. This configuration data is used by the\r
+ system boot to configure the ACE after the system come out of reset and before\r
+ control is passed to the application. This results in the ACE being fully\r
+ operational by the time the application starts executing.\r
+ The ACE Configurator also generates a set of C files containing information\r
+ about the ACE\92s configuration. These C files must be copied into the\r
+ drivers_config/mss_ace folder of you r software project for consumption by the\r
+ ACE driver. The ACE driver uses the content of these configuration files to\r
+ interact with the configured ACE hardware.\r
+\r
+ The ACE driver functions are grouped into the following categories:\r
+ \95 Initialization\r
+ \95 Reading analog input channels values and properties\r
+ \95 Post Processing Engine flags\r
+ \95 Conversion functions between sample value and real world units\r
+ \95 Sample Sequencing Engine control\r
+ \95 Sample Sequencing Engine Interrupts Control\r
+ \95 Comparators control\r
+ \95 Sigma Delta Digital to Analog Converters (SDD) control\r
+ \95 Direct analog block configuration and usage\r
+\r
+ \r
+ Initialization\r
+ The ACE driver is initialized through a call to the ACE_init() function. The\r
+ ACE_init() function must be called before any other ACE driver functions can\r
+ be called. It initializes the ACE\92s internal data.\r
+\r
+ \r
+ Reading analog input channels values and properties\r
+ The ACE driver allows retrieving the most recent post processed sample value\r
+ for each analog input. It also allows retrieving the name of the analog input\r
+ channel assigned in the ACE Configurator and whether the input channel samples\r
+ a voltage, current or temperature.\r
+ Each individual analog input channel is identified using a channel handle which\r
+ is passed as parameter to the ACE input channel driver functions. The channel\r
+ handles are design specific. The list of channel handles is generated by the\r
+ ACE Configurator based on the names given to the input signals. The channel\r
+ handles can be found in the drivers_config\mss_ace\ace_handles.h file. The\r
+ channel handle can be obtained from the channel name using the ACE_get_channel_handle()\r
+ function. It is also possible to iterate through all the channels using the\r
+ ACE_get_first_channel() and ACE_get_next_channel() functions.\r
+\r
+ Reading analog input samples from the post processing engine is done the following function:\r
+ \95 uint16_t ACE_get_ppe_sample( ace_channel_handle_t channel_handle )\r
+\r
+ Information about an input channel can be retrieved using the following functions:\r
+ \95 const uint8_t * ACE_get_channel_name( ace_channel_handle_t channel_handle )\r
+ \95 channel_type_t ACE_get_channel_type( ace_channel_handle_t channel_handle )\r
+\r
+ \r
+ Post Processing Engine flags\r
+ The SmartFusion ACE Post Processing Engine (PPE) provides the ability to monitor\r
+ the state of analog input channels and detect when certain threshold values are\r
+ crossed. Flags are raised by the PPE when these thresholds are crossed. Interrupts\r
+ can optionally be generated when flags are raised.\r
+ The flags are defined using the ACE Configurator software tool. The flag\92s name,\r
+ threshold value and hysteresis settings are specified in the ACE Configurator.\r
+ The ACE Configurator generates microcode based on the selected configuration which\r
+ is executed at system run time by the PPE. The PPE microcode is loaded into the\r
+ ACE at chip boot time by the Actel provided system boot code. No ACE driver\r
+ intervention is required to load up the PPE microcode.\r
+ The ACE driver allows:\r
+ \95 Retrieving the current state of the post processing engine flags\r
+ \95 Assigning a handler function to individual flag assertions\r
+ \95 Assigning a handler function to flags generated based on the value of a\r
+ specific channel\r
+ \95 Controlling flag interrupts\r
+ \95 Dynamically modify a flag\92s threshold value\r
+ \95 Dynamically modify a flag\92s hysteresis\r
+\r
+ Each individual flag is identified using a flag handle which is passed as parameter\r
+ to the ACE driver functions controlling the flags. The flag handles are design\r
+ specific. They are defined in the drivers_config\mss_ace\ace_handles.h file which\r
+ is generated by the ACE Configurator based on the names selected for the signal\r
+ and flag names. A flag handle can be obtained from the driver using the name of\r
+ the flag entered in the ACE Configurator software when the flag was created. A\r
+ flag handle can also be obtained using the functions ACE_get_channel_first_flag()\r
+ and ACE_get_channel_next_flag() when iterating through the flags associated with\r
+ an analog input channel. The functions available for retrieving flag handles are:\r
+ \95 ace_flag_handle_t ACE_get_flag_handle (const uint8_t *p_sz_full_flag_name)\r
+ \95 ace_flag_handle_t ACE_get_channel_first_flag (ace_channel_handle_t channel_handle, uint16_t *iterator)\r
+ \95 ace_flag_handle_t ACE_get_channel_next_flag (ace_channel_handle_t channel_handle, uint16_t *iterator)\r
+ \r
+ The current status of a flag can be polled using the following function:\r
+ \95 int32_t ACE_get_flag_status (ace_flag_handle_t flag_handle)\r
+\r
+ Interrupt handlers can be registered with the ACE driver to handle individual\r
+ flags. These interrupt handlers will be called by the ACE driver when a specific\r
+ flag is raised. The flag interrupt control functions are:\r
+ \95 void ACE_register_flag_isr (ace_flag_handle_t flag_handle, flag_isr_t flag_isr)\r
+ \95 void ACE_enable_flag_irq (ace_flag_handle_t flag_handle)\r
+ \95 void ACE_disable_flag_irq (ace_flag_handle_t flag_handle)\r
+ \95 void ACE_clear_flag_irq (ace_flag_handle_t flag_handle)\r
+\r
+ Interrupt handlers can be registered with the ACE driver to handle all flags\r
+ associated with one specific analog input channel. These interrupt handlers will\r
+ be called by the ACE driver when one of the flags, generated based on the state of\r
+ the specified analog input channel, is raised. The channel flag interrupt control\r
+ functions are:\r
+ \95 void ACE_register_channel_flags_isr (ace_channel_handle_t channel_handle, channel_flag_isr_t channel_flag_isr)\r
+ \95 void ACE_enable_channel_flags_irq (ace_channel_handle_t channel_handle)\r
+ \95 void ACE_disable_channel_flags_irq (ace_channel_handle_t channel_handle)\r
+ \95 void ACE_clear_channel_flags_irq (ace_channel_handle_t channel_handle)\r
+\r
+ A single global interrupt handler can be registered with the ACE driver. The global\r
+ flag interrupt handler function will be called by the ACE driver when any of the\r
+ interrupt enabled flag is raised. The handle of the flag causing the interrupt and\r
+ the handle of the associated analog input channel is passed as parameter to the\r
+ registered global flag handler.\r
+ \95 void ACE_register_global_flags_isr (global_flag_isr_t global_flag_isr)\r
+\r
+ The configuration of a flag can be dynamically modified using the following functions:\r
+ \95 void ACE_set_flag_threshold (ace_flag_handle_t flag_handle, uint16_t new_threshold)\r
+ \95 void ACE_set_flag_hysteresis (ace_flag_handle_t flag_handle, uint16_t adc_hysteresis)\r
+ \95 void ACE_set_channel_hysteresis (ace_channel_handle_t channel_handle, uint16_t adc_hysteresis)\r
+ \95 void ACE_set_flag_assertion( ace_flag_handle_t flag_handle, uint16_t assertion_value )\r
+ \95 void ACE_set_flag_deassertion( ace_flag_handle_t flag_handle, uint16_t assertion_value )\r
+\r
+ Information about a flag can be retrieved using the following functions once\r
+ the flag handle is known:\r
+ \95 const uint8_t * ACE_get_flag_name (ace_flag_handle_t flag_handle)\r
+ \95 ace_channel_handle_t ACE_get_flag_channel (ace_flag_handle_t flag_handle)\r
+\r
+ \r
+ Conversion to and from real world units\r
+ The ACE driver provides a set of conversion functions to convert sample values\r
+ read from the post processing engine into real world units:\r
+ \95 millivolts\r
+ \95 milliamps\r
+ \95 Degrees Kelvin\r
+ \95 Degrees Celsius\r
+ \95 Degrees Fahrenheit\r
+ Conversion functions are also available to convert from real world units into\r
+ PPE sample values. These functions are typically used for dynamically adjusting\r
+ flags threshold values.\r
+\r
+ \r
+ Sample Sequencing Engine control\r
+ The ACE driver provides a set of functions for dynamically controlling the\r
+ Sample Sequencing Engine. These functions are only required for managing multiple\r
+ sampling sequences. The use of these functions is not required for most applications\r
+ since the SSE is already configured and running by the time the application starts.\r
+\r
+ \r
+ Sample Sequencing Engine Interrupts Control\r
+ The ACE driver provides a set of functions for managing interrupts generated by\r
+ the Sample Sequencing Engine. These functions allow enabling, disabling and clearing\r
+ interrupt defined as part of the sampling sequence. These functions also allow\r
+ controlling interrupts generated by the ADCs.\r
+\r
+ \r
+ Comparators control\r
+ The ACE driver provides a set of functions for managing interrupts generated based\r
+ on the change of state of the high speed comparators. Functions are also provided\r
+ to dynamically modify the comparators configuration.\r
+\r
+ \r
+ Sigma Delta Digital to Analog Converters (SDD) control\r
+ The ACE driver provides functions for controlling the output value of the Sigma\r
+ Delta DACs (SDD). Functions are also provided for dynamically adjusting the\r
+ configuration of the SDDs.\r
+\r
+ *//*=========================================================================*/\r
+#ifndef __MSS_ACE_H_\r
+#define __MSS_ACE_H_\r
+\r
+#include <stdint.h>\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif \r
+\r
+#include "../../drivers_config/mss_ace/ace_handles.h"\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ Analog to Digital Converter channel IDs.\r
+ This enumeration is used to identify the ADC's analog inputs. It caters for up\r
+ to three ADCs/Analog Modules as can be found on the larger parts of the\r
+ SmartFusion family. The channel ID numbering is designed to allow easy\r
+ extraction of the ADC number and also the individual ADC input number by simple\r
+ shifting and masking. This enumeration is used as parameter to the\r
+ ACE_get_input_channel_handle() function retrieving the channel handle associated\r
+ with a specific analog input signal.\r
+ */\r
+typedef enum\r
+{\r
+ ADC0_1P5V = 0, /*!< Analog Module 0, 1.5V/GND */\r
+ ABPS0 = 1, /*!< Analog Module 0, Quad0 Active Bipolar Pre-Scaler input 1 */\r
+ ABPS1 = 2, /*!< Analog Module 0, Quad0 Active Bipolar Pre-Scaler input 2 */\r
+ CM0 = 3, /*!< Analog Module 0, Quad0 Current Monitor Block */\r
+ TM0 = 4, /*!< Analog Module 0, Quad0 Temperature Monitor Block */\r
+ ABPS2 = 5, /*!< Analog Module 0, Quad1 Active Bipolar Pre-Scaler input 1 */\r
+ ABPS3 = 6, /*!< Analog Module 0, Quad1 Active Bipolar Pre-Scaler input 2 */\r
+ CM1 = 7, /*!< Analog Module 0, Quad1 Current Monitor Block */\r
+ TM1 = 8, /*!< Analog Module 0, Quad1 Temperature Monitor Block */\r
+ ADC0 = 9, /*!< Analog Module 0 Direct Input 0 */\r
+ ADC1 = 10, /*!< Analog Module 0 Direct Input 1 */\r
+ ADC2 = 11, /*!< Analog Module 0 Direct Input 2 */\r
+ ADC3 = 12, /*!< Analog Module 0 Direct Input 3 */\r
+ SDD0_IN = 15, /*!< Analog Module 0 Sigma-Delta DAC output */\r
+\r
+ ADC1_1P5V = 16, /*!< Analog Module 1, 1.5V/GND */\r
+ ABPS4 = 17, /*!< Analog Module 1, Quad0 Active Bipolar Pre-Scaler input 1 */\r
+ ABPS5 = 18, /*!< Analog Module 1, Quad0 Active Bipolar Pre-Scaler input 2 */\r
+ CM2 = 19, /*!< Analog Module 1, Quad0 Current Monitor Block */\r
+ TM2 = 20, /*!< Analog Module 1, Quad0 Temperature Monitor Block */\r
+ ABPS6 = 21, /*!< Analog Module 1, Quad1 Active Bipolar Pre-Scaler input 1 */\r
+ ABPS7 = 22, /*!< Analog Module 1, Quad1 Active Bipolar Pre-Scaler input 2 */\r
+ CM3 = 23, /*!< Analog Module 1, Quad1 Current Monitor Block */\r
+ TM3 = 24, /*!< Analog Module 1, Quad1 Temperature Monitor Block */\r
+ ADC4 = 25, /*!< Analog Module 1 Direct Input 0 */\r
+ ADC5 = 26, /*!< Analog Module 1 Direct Input 1 */\r
+ ADC6 = 27, /*!< Analog Module 1 Direct Input 2 */\r
+ ADC7 = 28, /*!< Analog Module 1 Direct Input 3 */\r
+ SDD1_IN = 31, /*!< Analog Module 1 Sigma-Delta DAC output */\r
+\r
+ ADC2_1P5V = 32, /*!< Analog Module 2, 1.5V/GND */\r
+ ABPS8 = 33, /*!< Analog Module 2, Quad0 Active Bipolar Pre-Scaler input 1 */\r
+ ABPS9 = 34, /*!< Analog Module 2, Quad0 Active Bipolar Pre-Scaler input 2 */\r
+ CM4 = 35, /*!< Analog Module 2, Quad0 Current Monitor Block */\r
+ TM4 = 36, /*!< Analog Module 2, Quad0 Temperature Monitor Block */\r
+ ABPS10 = 37, /*!< Analog Module 2, Quad1 Active Bipolar Pre-Scaler input 1 */\r
+ ABPS11 = 38, /*!< Analog Module 2, Quad1 Active Bipolar Pre-Scaler input 2 */\r
+ CM5 = 39, /*!< Analog Module 2, Quad1 Current Monitor Block */\r
+ TM5 = 40, /*!< Analog Module 2, Quad1 Temperature Monitor Block */\r
+ ADC8 = 41, /*!< Analog Module 2 Direct Input 0 */\r
+ ADC9 = 42, /*!< Analog Module 2 Direct Input 1 */\r
+ ADC10 = 43, /*!< Analog Module 2 Direct Input 2 */\r
+ ADC11 = 44, /*!< Analog Module 2 Direct Input 3 */\r
+ SDD2_IN = 47, /*!< Analog Module 2 Sigma-Delta DAC output */\r
+ INVALID_CHANNEL = 255 /*!< Used to indicate errors */\r
+} adc_channel_id_t;\r
+\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ACE_init() function initializes the SmartFusion MSS ACE driver. It\r
+ initializes the ACE driver\92s internal data structures. The ACE_init() function\r
+ must be called before any other MSS ACE driver functions can be called.\r
+ */\r
+void ACE_init( void );\r
+\r
+\r
+/*==============================================================================\r
+ ============== Direct Analog Block Configuration and Usage ====================\r
+ =============================================================================*/\r
+ \r
+/*=========================================================================*//**\r
+ @defgroup group1 Direct Analog Block Configuration and Usage\r
+ These functions are intended for using the SmartFusion analog block hardware\r
+ without relying on the Sampling Sequence Engine or Post Processing engine.\r
+ @{\r
+ *//*=========================================================================*/\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ACE_start_adc() function initiates the sampling of the analog input\r
+ channel identified by the channel_id parameter. This function is provided for\r
+ test purposes. It must not be used while the Sample Sequencing Engine is\r
+ running.\r
+ \r
+ @param channel_id\r
+ The channel_id parameter identifies the analog input channel to sample.\r
+ \r
+ @return\r
+ This function does not return a value.\r
+ */\r
+void ACE_start_adc\r
+(\r
+ adc_channel_id_t channel_id\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ACE_get_adc_result () function reads the result of the last input channel\r
+ sampling performed by the ADC identified as parameter.\r
+ \r
+ @param adc_id\r
+ The adc_id parameter identifies which of the possible three ADC to read the\r
+ sample result from.\r
+ \r
+ @return\r
+ The ACE_start_adc_sync() function returns the ADC result from the ADC\r
+ specified as parameter.\r
+ */\r
+uint16_t ACE_get_adc_result\r
+(\r
+ uint8_t adc_id\r
+);\r
+\r
+/** @} */\r
+\r
+/*==============================================================================\r
+ =========== Sigma Delta Digital to Analog Converters (SDD) Control ============\r
+ =============================================================================*/\r
+/*=========================================================================*//**\r
+ @defgroup group2 Sigma Delta Digital to Analog Converters (SDD) Control\r
+ The following functions are used to control the Sigma Delta DACs included\r
+ within the SmartFusion analog block.\r
+ @{\r
+ *//*=========================================================================*/\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The sdd_id_t enumeration is used to identify the Sigma Delta DACs to the SDD\r
+ control functions, ACE_configure_sdd(), ACE_enable_sdd(), ACE_disable_sdd()\r
+ and ACE_set_sdd_value(). There is one SDD per analog module. \r
+ */\r
+typedef enum\r
+{\r
+ SDD0_OUT = 0, /*!< Analog Module 0 Sigma Delta DAC */\r
+ SDD1_OUT = 1, /*!< Analog Module 1 Sigma Delta DAC */\r
+ SDD2_OUT = 2, /*!< Analog Module 2 Sigma Delta DAC */\r
+ NB_OF_SDD = 3\r
+} sdd_id_t;\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The sdd_resolution_t enumeration is used as a parameter to the\r
+ ACE_configure_sdd() function to specify DAC resolution of the Sigma Delta DAC. \r
+ */\r
+typedef enum\r
+{\r
+ SDD_8_BITS = 0,\r
+ SDD_16_BITS = 4,\r
+ SDD_24_BITS = 8\r
+} sdd_resolution_t;\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ These constant definitions are used as an argument to the ACE_configure_sdd()\r
+ function to specify operating mode of the Sigma Delta DAC.\r
+ */\r
+#define SDD_CURRENT_MODE 1\r
+#define SDD_VOLTAGE_MODE 0\r
+#define SDD_RETURN_TO_ZERO 0\r
+#define SDD_NON_RTZ 2\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The sdd_update_method_t enumeration is used as a parameter to the\r
+ ACE_configure_sdd() function to specify individual or synchronous updating of\r
+ the Sigma Delta DACs.\r
+ */\r
+typedef enum\r
+{\r
+ INDIVIDUAL_UPDATE = 0,\r
+ SYNC_UPDATE = 1\r
+} sdd_update_method_t;\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ACE_configure_sdd() function is used to configure the operating mode of\r
+ the Sigma Delta DAC (SDD) specified as parameter. It allows selecting whether the\r
+ SDD will output a voltage or a current. A current between 0 and 256uA is\r
+ generated in current mode. A voltage between 0 and 2.56V is generated in\r
+ voltage mode.\r
+ This function also allows selecting whether Return To Zero (RTZ) mode is\r
+ enabled or not. Enabling Return To Zero mode improves linearity of the SDD\r
+ output at the detriment of accuracy. This mode should be used if linearity is\r
+ more important than accuracy.\r
+ A call to this function is not required if relying on the configuration\r
+ selected in the ACE configurator being loaded after reset by the system boot.\r
+ \r
+ @param sdd_id\r
+ The sdd_id parameter specifies which Sigma Delta DAC is configured by this\r
+ function. Allowed values are:\r
+ - SDD0_OUT\r
+ - SDD1_OUT\r
+ - SDD2_OUT\r
+ \r
+ @param resolution\r
+ The resolution parameter specifies the desired resolution of the Sigma Delta DAC.\r
+ Allowed values are:\r
+ - SDD_8_BITS\r
+ - SDD_16_BITS\r
+ - SDD_24_BITS\r
+ \r
+ @param mode\r
+ The mode parameter specifies the operating mode of the Sigma Delta DAC. It\r
+ specifies whether a current or voltage should be generated and whether\r
+ Return to Zero mode should be used. It is a logical OR of the following\r
+ defines:\r
+ - SDD_CURRENT_MODE\r
+ - SDD_VOLTAGE_MODE\r
+ - SDD_RETURN_TO_ZERO\r
+ - SDD_NON_RTZ\r
+ \r
+ @param sync_update\r
+ The sync_update parameter specifies whether the SDD output will be updated\r
+ individually though a call to ACE_set_sdd_value() or synchronously with one\r
+ or more other SDD outputs via a call to ACE_set_sdd_value_sync().\r
+\r
+ Example\r
+ @code\r
+ ACE_configure_sdd\r
+ (\r
+ SDD1_OUT,\r
+ SDD_24_BITS,\r
+ SDD_VOLTAGE_MODE | SDD_RETURN_TO_ZERO,\r
+ INDIVIDUAL_UPDATE\r
+ );\r
+ @endcode\r
+ */\r
+void ACE_configure_sdd\r
+(\r
+ sdd_id_t sdd_id,\r
+ sdd_resolution_t resolution,\r
+ uint8_t mode,\r
+ sdd_update_method_t sync_update\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ACE_enable_sdd() function is used to enable a Sigma Delta DAC. \r
+ \r
+ @param sdd_id\r
+ The sdd_id parameter specifies the Sigma Delta DAC to enable.\r
+ */\r
+void ACE_enable_sdd\r
+(\r
+ sdd_id_t sdd_id\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ACE_disable_sdd() function is used to disable a Sigma Delta DAC.\r
+ \r
+ @param sdd_id\r
+ The sdd_id parameter specifies the Sigma Delta DAC to disable.\r
+ */\r
+void ACE_disable_sdd\r
+(\r
+ sdd_id_t sdd_id\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ACE_set_sdd_value() function is used to set the value of the output of\r
+ a Sigma Delta DAC. It uses the ACE's phase accumulator to generate the one bit\r
+ input bit stream into the SDD which will in turn define the voltage or\r
+ current generated at the SDD output.\r
+ The SDD output is proportional to the sdd_value passed to this function taking\r
+ the SDD resolution into account. A maximum voltage of 2.56V or a maximum\r
+ current of 256uA will be generated when the sdd_value is set the maximum value\r
+ allowed by the SDD resolution\r
+ \r
+ @param sdd_id\r
+ The sdd_id parameter specifies which Sigma Delta DAC is being set.\r
+ \r
+ @param sdd_value\r
+ The sdd_value parameter specifies the value of the Sigma Delta DAC output.\r
+ It is a fraction of SDD resolution. The voltage/current value generated from\r
+ the sdd_value paramenter can be determined using the following equation where\r
+ sdd_resolution is the resolution of the SDD as set through function\r
+ ACE_configure_sdd() and sdd_rangSDD configuration:\r
+ sdd_output = (sdd_value / sdd_resolution) * sdd_range\r
+ */\r
+void ACE_set_sdd_value\r
+(\r
+ sdd_id_t sdd_id,\r
+ uint32_t sdd_value\r
+);\r
+\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ This constant definition is used as an argument to the ACE_set_sdd_value_sync()\r
+ function to specify that the output value of SDD0, or SDD1, or SDD2 should not\r
+ be modified.\r
+ */\r
+#define SDD_NO_UPDATE 0xFFFFFFFF\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ACE_set_sdd_value_sync() function is used to synchronize the update of\r
+ multiple Sigma Delta DAC outputs.\r
+\r
+ @param sdd0_value\r
+ The sdd0_value parameter specifies the value that will be used to set the\r
+ output of SDD0.\r
+ The define SDD_NO_UPDATE can be used to specify that the output value of\r
+ SDD0 should not be modified.\r
+\r
+ @param sdd1_value\r
+ The sdd1_value parameter specifies the value that will be used to set the\r
+ output of SDD1.\r
+ The define SDD_NO_UPDATE can be used to specify that the output value of\r
+ SDD1 should not be modified.\r
+\r
+ @param sdd2_value\r
+ The sdd2_value parameter specifies the value that will be used to set the\r
+ output of SDD2.\r
+ The define SDD_NO_UPDATE can be used to specify that the output value of\r
+ SDD2 should not be modified.\r
+\r
+ For example the code below will change the output value of SDD0 and SDD2 so\r
+ that the voltage/current generate by SDD0 and ADD2 will change at the same\r
+ time. This function call will not affect the output value of SDD1.\r
+ @code\r
+ uint32_t sdd0_value = 0x1234;\r
+ uint32_t sdd2_value = 0x5678;\r
+ ACE_set_sdd_value_sync( sdd0_value, SDD_NO_UPDATE, sdd2_value );\r
+ @endcode\r
+ */\r
+\r
+void ACE_set_sdd_value_sync\r
+(\r
+ uint32_t sdd0_value,\r
+ uint32_t sdd1_value,\r
+ uint32_t sdd2_value\r
+);\r
+\r
+/** @} */\r
+\r
+/*==============================================================================\r
+ ============ Reading Samples from post processing engine (PPE) ================\r
+ =============================================================================*/\r
+/*=========================================================================*//**\r
+ @defgroup group9 Reading Analog Input Channels Values and Properties\r
+ The following functions are used to access analog input channels properties\r
+ and sampled values.\r
+ @{\r
+ *//*=========================================================================*/\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ This constant returned by the ACE_get_flag_channel(), ACE_get_channel_handle()\r
+ and ACE_get_input_channel_handle() functions when the driver can\92t find a\r
+ valid handle for the ADC input channel.\r
+ */\r
+#define INVALID_CHANNEL_HANDLE NB_OF_ACE_CHANNEL_HANDLES\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ACE_get_channel_handle() function returns the channel handle associated\r
+ with an analog input channel name. The retrieved channel handle will be\r
+ subsequently used as parameter to function ACE_get_ppe_sample() used to read\r
+ the most recent post processed sample for the analog input identified through\r
+ the channel/service name passed as argument to this function.\r
+ \r
+ @param p_sz_channel_name\r
+ The p_sz_channel_name parameter is a zero-terminated string containing the\r
+ name of the channel/service as entered in the ACE configurator.\r
+ \r
+ @return\r
+ This function returns a channel handle. This channel handle is required as\r
+ parameter to function ACE_get_ppe_sample().\r
+ It will return INVALID_CHANNEL_HANDLE if the channel/service name is not\r
+ recognized.\r
+ \r
+ @code\r
+ uint16_t adc_result;\r
+ ace_channel_handle_t at0;\r
+ at0 = ACE_get_channel_handle("VoltageMonitorAT0");\r
+ adc_result = ACE_get_ppe_sample( at0 );\r
+ @endcode\r
+ */\r
+ace_channel_handle_t\r
+ACE_get_channel_handle\r
+(\r
+ const uint8_t * p_sz_channel_name\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ACE_get_input_channel_handle() function returns the channel handle for\r
+ the hardware analog input channel specified as parameter.\r
+ \r
+ @param channel_id\r
+ The channel_id parameter identifies a hardware analog input of the ACE.\r
+ \r
+ @return\r
+ This function returns a channel handle. This channel handle is required as\r
+ parameter to other ACE driver functions dealing with analog inputs.\r
+ It will return INVALID_CHANNEL_HANDLE if the channel ID passed as parameter\r
+ is invalid.\r
+ */\r
+ace_channel_handle_t\r
+ACE_get_input_channel_handle\r
+(\r
+ adc_channel_id_t channel_id\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ACE_get_ppe_sample() function is used to read the most recent post\r
+ processed sample for the analog input channel associated with the channel\r
+ handle passed as parameter.\r
+ \r
+ @param channel_handle\r
+ The channel_handle parameter identifies the analog input channel for which\r
+ this function will return the most recent ADC conversion result adjusted for\r
+ calibration and user provided coefficients as provided through the ACE\r
+ configurator. The available channel handle values can be found in the\r
+ ace_handles.h file located in the ./drivers_config/mss_ace subdirectory. The\r
+ channel handle value can also be retrieved through a call to\r
+ ACE_get_channel_handle() when the name of the channel is known, or by\r
+ iterating though all analog input channel using the ACE_get_first_channel()\r
+ and ACE_get_next_channel().\r
+ \r
+ @return\r
+ This function returns a 16 bit value representing the adjusted value of the\r
+ ADC conversion result for the analog input channel identified by the channel\r
+ handle passed as parameter. The return value is actually a 12, 10 or 8 bits\r
+ number depending on the configuration of the ADC.\r
+ \r
+ @code\r
+ uint16_t adc_result;\r
+ ace_channel_handle_t at0;\r
+ at0 = ACE_get_channel_handle("VoltageMonitorAT0");\r
+ adc_result = ACE_get_ppe_sample( at0 );\r
+ @endcode\r
+ */\r
+uint16_t\r
+ACE_get_ppe_sample\r
+(\r
+ ace_channel_handle_t channel_handle\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ACE_get_channel_name() function provides the name of the channel\r
+ associated with the channel handle passed as parameter. The channel name is\r
+ the name used in the ACE configurator software tool when adding a service to\r
+ the ACE.\r
+ \r
+ @param channel_handle\r
+ The channel_handle parameter identifies the analog input channel for which\r
+ we want to retrieve the channel name. The available channel handle values can\r
+ be found in the ace_handles.h file located in the ./drivers_config/mss_ace\r
+ subdirectory. The channel handle value can also be retrieved through a call\r
+ to ACE_get_channel_handle() when the name of the channel is known, or by\r
+ iterating though all analog input channel using the ACE_get_first_channel()\r
+ and ACE_get_next_channel().\r
+ \r
+ @return\r
+ This function returns a pointer to a zero-terminated string containing the\r
+ name of the channel. It returns 0 if the channel handle passed as parameter\r
+ is not recognized.\r
+ */\r
+const uint8_t * ACE_get_channel_name\r
+(\r
+ ace_channel_handle_t channel_handle\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The channel_type_t enumeration is used to identify the type of quantity\r
+ measured by an analog input channel. It is typically used to figure out the\r
+ type of conversion that must be applied to the ADC value generated from\r
+ sampling a channel in order to yield real world units such millivolts,\r
+ milliamps or degrees.\r
+ */\r
+typedef enum\r
+{\r
+ VOLTAGE,\r
+ CURRENT,\r
+ TEMPERATURE\r
+} channel_type_t;\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ACE_get_channel_type() function returns the type of input channel of the\r
+ analog input channel identified by the channel handle passed as parameter.\r
+ This function allows determining whether the quantity measured through the ADC\r
+ is a voltage, current or temperature.\r
+ \r
+ @param channel_handle\r
+ The channel_handle parameter identifies one of the analog input channels\r
+ monitored by the ACE. The available channel handle values can be found in the\r
+ ace_handles.h file located in the .\drivers_config\mss_ace subdirectory. The\r
+ channel handle value can also be retrieved through a call to\r
+ ACE_get_channel_handle() when the name of the channel is known, or by\r
+ iterating though all analog input channel using the ACE_get_first_channel()\r
+ and ACE_get_next_channel().\r
+ \r
+ @return\r
+ This function returns one of the following values to report the type of\r
+ quantity measure throught the channel:\r
+ - VOLTAGE\r
+ - CURRENT\r
+ - TEMPERATURE\r
+ */\r
+channel_type_t\r
+ACE_get_channel_type\r
+(\r
+ ace_channel_handle_t channel_handle\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ACE_get_channel_count() function returns the total number of configured\r
+ analog input channels. It is the number of channels available for use as\r
+ opposed to the theorical number of physical channels supported by the device.\r
+ \r
+ @return\r
+ The ACE_get_channel_count() function returns the total number of input\r
+ channels that were configured in the ACE configurator.\r
+ The ACE_get_channel_count() function returns 0 if no input channels were\r
+ configured.\r
+ \r
+ @code\r
+ uint32_t inc;\r
+ uint32_t nb_of_channels;\r
+ ace_channel_handle_t current_channel;\r
+ \r
+ nb_of_channels = ACE_get_channel_count();\r
+ current_channel = ACE_get_first_channel();\r
+ \r
+ for (inc = 0; inc < nb_of_channels; ++inc)\r
+ {\r
+ adc_result = ACE_get_ppe_sample( current_channel );\r
+ display_value( current_channel, adc_result );\r
+ current_channel = ACE_get_next_channel( current_channel );\r
+ }\r
+ @endcode\r
+ */\r
+uint32_t\r
+ACE_get_channel_count\r
+(\r
+ void\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ACE_get_first_channel() function returns the channel handle of one of the\r
+ channel controlled by the ACE. This function is used to start iterating though\r
+ the list of analog input channels handled by the ACE.\r
+ \r
+ @return\r
+ The ACE_get_first_channel() function returns the first channel handle found\r
+ in the ACE driver's internal channel handles list or INVALID_CHANNEL_HANDLE\r
+ if there are no channels defined in the ACE configuration.\r
+ \r
+ @code\r
+ uint32_t inc;\r
+ uint32_t nb_of_channels;\r
+ ace_channel_handle_t current_channel;\r
+ \r
+ nb_of_channels = ACE_get_channel_count();\r
+ current_channel = ACE_get_first_channel();\r
+ \r
+ for (inc = 0; inc < nb_of_channels; ++inc)\r
+ {\r
+ adc_result = ACE_get_ppe_sample( current_channel );\r
+ display_value( current_channel, adc_result );\r
+ current_channel = ACE_get_next_channel( current_channel );\r
+ }\r
+ @endcode\r
+ */\r
+ace_channel_handle_t\r
+ACE_get_first_channel\r
+(\r
+ void\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ACE_get_next_channel() returns the channel handle of the channel following\r
+ the one passed as parameter. This function is used to iterate through the list\r
+ of analog input channels handled by the ACE.\r
+ \r
+ @param channel_handle\r
+ The channel_handle parameter identifies from which channel the driver should\r
+ look in its channel handle list to return the next channel handle. The\r
+ channel_handle parameter would typically be the channel handle returned by a\r
+ call to ACE_get_first_channel() or a previous call to ACE_get_next_channel().\r
+ Note:\r
+ The first call to ACE_get_next_channel() would typically use the\r
+ channel_handle returned by a previous call to ACE_get_first_channel(). The\r
+ second and subsequent calls to ACE_get_next_channel() would typically use\r
+ the channel_handle returned by a previous call to ACE_get_next_channel().\r
+ \r
+ @return\r
+ The ACE_get_next_channel() function returns the channel handle of the channel\r
+ following the one passed as parameter or INVALID_CHANNEL_HANDLE if the end of\r
+ the channels list has been reached.\r
+ \r
+ @code\r
+ uint32_t inc;\r
+ uint32_t nb_of_channels;\r
+ ace_channel_handle_t current_channel;\r
+ \r
+ nb_of_channels = ACE_get_channel_count();\r
+ current_channel = ACE_get_first_channel();\r
+ \r
+ for (inc = 0; inc < nb_of_channels; ++inc)\r
+ {\r
+ adc_result = ACE_get_ppe_sample( current_channel );\r
+ display_value( current_channel, adc_result );\r
+ current_channel = ACE_get_next_channel( current_channel );\r
+ }\r
+ @endcode\r
+ */\r
+ace_channel_handle_t\r
+ACE_get_next_channel\r
+(\r
+ ace_channel_handle_t channel_handle\r
+);\r
+\r
+ /** @} */\r
+\r
+/*==============================================================================\r
+ =============================== SSE Control ==================================\r
+ =============================================================================*/\r
+/*=========================================================================*//**\r
+ @defgroup group3 Sample Sequencing Engine Control\r
+ Sample Sequencing Engine control.\r
+ @{\r
+ *//*=========================================================================*/\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The Sample Sequencing Engine control functions use a parameter of this type as\r
+ a handle to identify the Sample Sequencing Engine (SSE) sequences configured\r
+ using the ACE configurator. The ACE_get_sse_seq_handle() function retrieves the\r
+ handle of the SSE sequence identified by the sequence name passed as parameter.\r
+ Note: The ACE configurator generates ACE driver configuration files into the\r
+ .\drivers_config\mss_ace folder of the firmware project. These files\r
+ contain the details of the SSE sequence handles for your ACE configuration.\r
+ The ACE driver automatically includes these files when the\r
+ .\drivers_config\mss_ace folder is present in the firmware project.\r
+ */\r
+typedef uint16_t sse_sequence_handle_t;\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ This constant is returned by the ACE_get_sse_seq_handle() function when the\r
+ driver can\92t find a valid handle for the Sample Sequencing Engine (SSE) sequence.\r
+*/\r
+#define INVALID_SSE_SEQ_HANDLE 0xFFFFu\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ACE_get_sse_seq_handle() function retrieves the handle of the Sample\r
+ Sequencing Engine sequence identified by the sequence name passed as parameter.\r
+ The sequence handler can then be used as parameter to other SSE sequence control\r
+ functions to identify the sequence to control.\r
+ \r
+ @param p_sz_sequence_name\r
+ The p_sz_sequence_name parameter is a pointer to a zero-terminated string\r
+ containing the name of the sampling sequence for which we want to retrieve\r
+ the handle.\r
+ \r
+ @return\r
+ The ACE_get_sse_seq_handle() function returns the handle used to identify\r
+ the sequence passed as parameter with other ACE driver sampling sequence\r
+ control functions. It returns INVALID_SSE_SEQ_HANDLE if the sequence name\r
+ passed as parameter is not recognized.\r
+ \r
+ @code\r
+ sse_sequence_handle_t sse_seq_handle;\r
+ sse_seq_handle = ACE_get_sse_seq_handle("ProcedureA");\r
+ if ( sse_seq_handle != INVALID_SSE_SEQ_HANDLE )\r
+ {\r
+ ACE_load_sse( sse_seq_handle );\r
+ ACE_start_sse( sse_seq_handle );\r
+ }\r
+ @endcode\r
+ */\r
+sse_sequence_handle_t\r
+ACE_get_sse_seq_handle\r
+(\r
+ const uint8_t * p_sz_sequence_name\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ACE_load_sse() function loads the ACE Sample Sequencing Engine (SSE) RAM\r
+ with the microcode implementing the sampling sequence identified by the SSE\r
+ sequence handler passed as parameter.\r
+ \r
+ @param sequence\r
+ The sequence parameter is the SSE sequence handler identifying the sampling\r
+ sequence to load into the ACE SSE. The value for this handler is retrieved\r
+ through a call to function ACE_get_sse_seq_handle().\r
+ */\r
+void ACE_load_sse\r
+(\r
+ sse_sequence_handle_t sequence\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ACE_start_sse() function causes the Sampling Sequence Engine (SSE) to start\r
+ executing the sequence identified by the sequence handler passed as parameter.\r
+ It causes the initiailization part of the sampling sequence to be executed\r
+ before the loop part of the sequence is started.\r
+ You must ensure that the sampling sequence has been loaded into the ACE's SSE\r
+ before calling this function.\r
+ \r
+ @param sequence\r
+ The sequence parameter is the SSE sequence handler identifying the sampling\r
+ sequence to load into the ACE SSE. The value for this handler is retrieved\r
+ through a call to function ACE_get_sse_seq_handle().\r
+ */\r
+void ACE_start_sse\r
+(\r
+ sse_sequence_handle_t sequence\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ACE_restart_sse() function restarts the loop part of the sampling sequence\r
+ loaded into the ACE's Sampling Sequence Engine (SSE). The sampling sequence\r
+ will be restarted from the beginning of the sequence but omiting the\r
+ intialization phase of the sequence.\r
+ This function would typically be called after stopping the sampling sequence\r
+ using the ACE_stop_see() function or with non-repeating sequences.\r
+ \r
+ @param sequence\r
+ The sequence parameter is the SSE sequence handler identifying the sampling\r
+ sequence to load into the ACE SSE. The value for this handler is retrieved\r
+ through a call to function ACE_get_sse_seq_handle().\r
+ */\r
+void ACE_restart_sse\r
+(\r
+ sse_sequence_handle_t sequence\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ACE_stop_sse() function stops execution of the Sample Sequencing Engine\r
+ (SSE) sequence indentified by the sequence handle passed as parameter.\r
+ \r
+ @param sequence\r
+ The sequence parameter is the SSE sequence handle identifying the sampling\r
+ sequence to load into the ACE SSE. The value for this handler is retrieved\r
+ through a call to function ACE_get_sse_seq_handle().\r
+ */\r
+void ACE_stop_sse\r
+(\r
+ sse_sequence_handle_t sequence\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ACE_resume_sse() function causes the Sampling Sequencing Engine (SSE)\r
+ sampling sequence identified by the sequence handle passed as parameter to\r
+ resume execution. This function is typically used to restart execution of\r
+ a sequence at the point where it was stopped through a call to ACE_stop_sse().\r
+ \r
+ @param sequence\r
+ The sequence parameter is the SSE sequence handler identifying the sampling\r
+ sequence to load into the ACE SSE. The value for this handler is retrieved\r
+ through a call to function ACE_get_sse_seq_handle().\r
+ */\r
+void ACE_resume_sse\r
+(\r
+ sse_sequence_handle_t sequence\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ACE_clear_sample_pipeline() function clears the ACE hardware of samples\r
+ being processed. It clear the various stages involved in the production of\r
+ post processed samples within the ACE hardware. It is intended for use when\r
+ switching between sampling sequences and using peripheral DMA. It avoids\r
+ receiving stale samples generated as a result of a previous sampling sequence.\r
+ \r
+ The example below shows how this function can be used to ensure that no sample\r
+ generated as a result of sampling sequence sequence_a will be generated once\r
+ sampling sequence_b is started. Please note that it is important to stop the\r
+ SSE using function ACE_stop_sse() before calling ACE_clear_sample_pipeline()\r
+ to ensure sequence_a is not restarted after the sample pipeline is cleared.\r
+ @code\r
+ ACE_stop_sse(sequence_a);\r
+ ACE_clear_sample_pipeline();\r
+ ACE_start_sse(sequence_b);\r
+ @endcode\r
+ \r
+ The example below shows how to ensure that the first sample read through PDMA\r
+ will be from the first channel in the sampling sequence.\r
+ @code\r
+ ACE_stop_sse(sequence_a);\r
+ ACE_clear_sample_pipeline();\r
+ ACE_restart_sse(sequence_a);\r
+ PDMA_start\r
+ (\r
+ PDMA_CHANNEL_0, \r
+ PDMA_ACE_PPE_DATAOUT, \r
+ (uint32_t)g_samples_buffer[g_pdma_buffer_idx], \r
+ SAMPLES_BUFFER_SIZE\r
+ );\r
+ @endcode\r
+ */\r
+void ACE_clear_sample_pipeline(void);\r
+\r
+/** @} */\r
+/*==============================================================================\r
+ ======================== SSE Interrupts Control ===============================\r
+ =============================================================================*/\r
+/*=========================================================================*//**\r
+ @defgroup group4 Sample Sequencing Engine Interrupts Control\r
+ The following functions are used to control interrupts generated from the\r
+ ACE's Sample Sequencing Engine. These interrupts would typically be used to\r
+ detect when valid data is available from the ADCs controlled by the SSE or to\r
+ detect the complete or partial completion of the sampling sequence through the\r
+ insertion of SSE program counter general purpose interrupt assertion as part\r
+ of the sequence.\r
+ @{\r
+ *//*=========================================================================*/\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The sse_irq_id_t enumeration is used to identify the Sample Sequencing Engine\r
+ (SSE) interrupt sources to the SSE interrupt control functions.\r
+ */\r
+typedef enum\r
+{\r
+ PC0_FLAG0 = 0,\r
+ PC0_FLAG1 = 1,\r
+ PC0_FLAG2 = 2,\r
+ PC0_FLAG3 = 3,\r
+ PC1_FLAG0 = 4,\r
+ PC1_FLAG1 = 5,\r
+ PC1_FLAG2 = 6,\r
+ PC1_FLAG3 = 7,\r
+ PC2_FLAG0 = 8,\r
+ PC2_FLAG1 = 9,\r
+ PC2_FLAG2 = 10,\r
+ PC2_FLAG3 = 11,\r
+ ADC0_DATAVALID = 12,\r
+ ADC1_DATAVALID = 13,\r
+ ADC2_DATAVALID = 14,\r
+ ADC0_CALIBRATION_COMPLETE = 15,\r
+ ADC1_CALIBRATION_COMPLETE = 16,\r
+ ADC2_CALIBRATION_COMPLETE = 17,\r
+ ADC0_CALIBRATION_START = 18,\r
+ ADC1_CALIBRATION_START = 19,\r
+ ADC2_CALIBRATION_START = 20,\r
+ NB_OF_SSE_FLAG_IRQS = 21\r
+} sse_irq_id_t;\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ACE_enable_sse_irq() function enables the Sample Sequencing Engine (SSE)\r
+ interrupt source specified as parameter to generate interrupts.\r
+ \r
+ @param sse_irq_id\r
+ The sse_irq_id parameter identifies the SSE interrupt source controlled by\r
+ this function.\r
+ */\r
+void ACE_enable_sse_irq\r
+(\r
+ sse_irq_id_t sse_irq_id\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ACE_disable_sse_irq() function disables the Sample Sequencing Engine\r
+ (SSE) interrupt source specified as parameter from generating interrupts.\r
+ \r
+ @param sse_irq_id\r
+ The sse_irq_id parameter identifies the SSE interrupt source controlled by\r
+ this function.\r
+ */\r
+void ACE_disable_sse_irq\r
+(\r
+ sse_irq_id_t sse_irq_id\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ACE_clear_sse_irq() function clears the Sampling Sequencing Engine (SSE)\r
+ interrupt specified as parameter.\r
+ \r
+ @param sse_irq_id\r
+ The sse_irq_id parameter identifies the SSE interrupt source controlled by\r
+ this function.\r
+ */\r
+void ACE_clear_sse_irq\r
+(\r
+ sse_irq_id_t sse_irq_id\r
+);\r
+\r
+/** @} */\r
+/*==============================================================================\r
+ ============================ Comparators Control ==============================\r
+ =============================================================================*/\r
+/*=========================================================================*//**\r
+ @defgroup group5 Comparators Control\r
+ The following functions are used to control the analog comparators included\r
+ in the SmartFusion analog block.\r
+ The comparator configuration functions can be used to directly configure the\r
+ comparators. Their use is only required when the ACE is not configured using\r
+ the ACE configurator software tool.\r
+ The comparator interrupt control functions are used regardless of the way the\r
+ ACE was configured to enable, disable and clear interrupts generated when the\r
+ positive input of a comparator rises above or falls below the negative input.\r
+ @{\r
+ *//*=========================================================================*/\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The comparator_id_t enumeration is used by the comparator control functions\r
+ to identify the analog comparators included in the SmartFusion analog block.\r
+ */\r
+typedef enum\r
+{\r
+ CMP0 = 0, /*!< Analog module 0, Quad 0, CMB comparator */\r
+ CMP1 = 1, /*!< Analog module 0, Quad 0, TMB comparator */\r
+ CMP2 = 2, /*!< Analog module 0, Quad 1, CMB comparator */\r
+ CMP3 = 3, /*!< Analog module 0, Quad 1, TMB comparator */\r
+ CMP4 = 4, /*!< Analog module 1, Quad 0, CMB comparator */\r
+ CMP5 = 5, /*!< Analog module 1, Quad 0, TMB comparator */\r
+ CMP6 = 6, /*!< Analog module 1, Quad 1, CMB comparator */\r
+ CMP7 = 7, /*!< Analog module 1, Quad 1, TMB comparator */\r
+ CMP8 = 8, /*!< Analog module 2, Quad 0, CMB comparator */\r
+ CMP9 = 9, /*!< Analog module 2, Quad 0, TMB comparator */\r
+ CMP10 = 10, /*!< Analog module 2, Quad 1, CMB comparator */\r
+ CMP11 = 11, /*!< Analog module 2, Quad 1, TMB comparator */\r
+ NB_OF_COMPARATORS = 12\r
+} comparator_id_t;\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The comp_hysteresis_t enumeration is used by the ACE_set_comp_hysteresis()\r
+ function to set the hysteresis of the analog comparators included in the\r
+ SmartFusion analog block. This enumeration provides the allowed values of the\r
+ hysteresis parameter of the ACE_set_comp_hysteresis() function.\r
+ */\r
+typedef enum\r
+{\r
+ NO_HYSTERESIS = 0,\r
+ HYSTERESIS_10_MV = 1,\r
+ HYSTERESIS_30_MV = 2,\r
+ HYSTERESIS_100_MV = 3,\r
+ NB_OF_HYSTERESIS = 4\r
+} comp_hysteresis_t ;\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The comp_reference_t enumeration is used by the ACE_set_comp_reference()\r
+ function to select the reference input of the odd numbered analog comparators\r
+ included in the SmartFusion analog block. This enumeration provides the allowed\r
+ values of the reference parameter of the ACE_set_comp_reference () function.\r
+ */\r
+typedef enum\r
+{\r
+ SDD0_COMP_REF = 0,\r
+ SDD1_COMP_REF = 1,\r
+ SDD2_COMP_REF = 2,\r
+ ADC_IN_COMP_REF = 3,\r
+ NB_OF_COMP_REF = 4\r
+} comp_reference_t;\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ACE_set_comp_reference() function is used to select the reference input\r
+ of a temperature monitor block comparator. The reference input of a temperature\r
+ monitor can be an ADC direct input or one of the SDD's output.\r
+ \r
+ @param comp_id\r
+ The comp_id parameter specifies the comparator for which to select the\r
+ reference input. Since only temperature monitor block comparators have a \r
+ selectable reference input, allowed values are:\r
+ - CMP1\r
+ - CMP3\r
+ - CMP5\r
+ - CMP7\r
+ - CMP9\r
+ - CMP11\r
+ \r
+ @param reference\r
+ The reference parameter specify the signal that will be used as reference\r
+ by the comparator. Allowed values are:\r
+ - SDD0_COMP_REF\r
+ - SDD1_COMP_REF\r
+ - SDD2_COMP_REF\r
+ - ADC_IN_COMP_REF\r
+ */\r
+void ACE_set_comp_reference\r
+(\r
+ comparator_id_t comp_id,\r
+ comp_reference_t reference\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ACE_set_comp_hysteresis() function is used to set the hysteresis of a\r
+ comparator. There are four possible hystereris settings: no hysteresis,\r
+ +/-10mV, +/-30mV or +/-100mV.\r
+ \r
+ @param comp_id\r
+ The comp_id parameter specifies the comparator for which this function will\r
+ set the hyteresis.\r
+ \r
+ @param hysteresis\r
+ The hysteresis parameter specifies the hysteresis that will be applied to \r
+ the comparator's input. Allowed values are:\r
+ - NO_HYSTERESIS\r
+ - HYSTERESIS_10_MV\r
+ - HYSTERESIS_30_MV\r
+ - HYSTERESIS_100_MV\r
+ \r
+ */\r
+void ACE_set_comp_hysteresis\r
+(\r
+ comparator_id_t comp_id,\r
+ comp_hysteresis_t hysteresis\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ACE_enable_comp() function is used to enable the comparator specified as\r
+ parameter.\r
+ \r
+ @param comp_id\r
+ The comp_id parameter specifies which comparator will be enabled by a call\r
+ to this function.\r
+ */\r
+void ACE_enable_comp\r
+(\r
+ comparator_id_t comp_id\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ACE_disable_comp() function is used to disable the comparator specified as\r
+ parameter.\r
+ \r
+ @param comp_id\r
+ The comp_id parameter specifies which comparator will be disabled by a call\r
+ to this function.\r
+ */\r
+void ACE_disable_comp\r
+(\r
+ comparator_id_t comp_id\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ACE_enable_comp_rise_irq() function is used to enable interrupts to be\r
+ generated when the positive input of the comparator specified as parameter\r
+ rises above the negative input of the comparator.\r
+ The function prototypes for the comparator rise interrupt service routines are:\r
+ - void ACE_Comp0_Rise_IRQHandler( void );\r
+ - void ACE_Comp1_Rise_IRQHandler( void );\r
+ - void ACE_Comp2_Rise_IRQHandler( void );\r
+ - void ACE_Comp3_Rise_IRQHandler( void );\r
+ - void ACE_Comp4_Rise_IRQHandler( void );\r
+ - void ACE_Comp5_Rise_IRQHandler( void );\r
+ - void ACE_Comp6_Rise_IRQHandler( void );\r
+ - void ACE_Comp7_Rise_IRQHandler( void );\r
+ - void ACE_Comp8_Rise_IRQHandler( void );\r
+ - void ACE_Comp9_Rise_IRQHandler( void );\r
+ - void ACE_Comp10_Rise_IRQHandler( void );\r
+ - void ACE_Comp11_Rise_IRQHandler( void );\r
+ \r
+ @param comp_id\r
+ The comp_id parameter specifies which comparator will be enabled to generate\r
+ rising interrupts.\r
+ */\r
+void ACE_enable_comp_rise_irq\r
+(\r
+ comparator_id_t comp_id\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ACE_disable_comp_rise_irq() function is used to disable interrupts from\r
+ being generated when the positive input of the comparator specified as parameter\r
+ rises above the negative input of the comparator.\r
+ \r
+ @param comp_id\r
+ The comp_id parameter specifies which comparator will be disabled from\r
+ generating rising interrupts.\r
+ */\r
+void ACE_disable_comp_rise_irq\r
+(\r
+ comparator_id_t comp_id\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ACE_clear_comp_rise_irq() function is used to clear rise interrupts. This\r
+ function is typically called as part of the rise interrupt service routine.\r
+ \r
+ @param comp_id\r
+ The comp_id parameter specifies the comparator for which to clear the rise\r
+ interrupt.\r
+ \r
+ Example:\r
+ @code\r
+ void ACE_Comp1_Rise_IRQHandler( void )\r
+ {\r
+ process_rise_irq();\r
+ ACE_clear_comp_rise_irq( CMP1 );\r
+ NVIC_ClearPendingIRQ( ACE_Comp1_Rise_IRQn );\r
+ }\r
+ @endcode\r
+ */\r
+void ACE_clear_comp_rise_irq\r
+(\r
+ comparator_id_t comp_id\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ACE_enable_comp_fall_irq() function is used to enable interrupts to be\r
+ generated when the positive input of the comparator specified as parameter\r
+ falls below the negative input of the comparator.\r
+ The function prototypes for the comparator fall interrupt service routines are:\r
+ - void ACE_Comp0_Fall_IRQHandler( void );\r
+ - void ACE_Comp1_Fall_IRQHandler( void );\r
+ - void ACE_Comp2_Fall_IRQHandler( void );\r
+ - void ACE_Comp3_Fall_IRQHandler( void );\r
+ - void ACE_Comp4_Fall_IRQHandler( void );\r
+ - void ACE_Comp5_Fall_IRQHandler( void );\r
+ - void ACE_Comp6_Fall_IRQHandler( void );\r
+ - void ACE_Comp7_Fall_IRQHandler( void );\r
+ - void ACE_Comp8_Fall_IRQHandler( void );\r
+ - void ACE_Comp9_Fall_IRQHandler( void );\r
+ - void ACE_Comp10_Fall_IRQHandler( void );\r
+ - void ACE_Comp11_Fall_IRQHandler( void );\r
+ \r
+ @param comp_id\r
+ The comp_id parameter specifies which comparator will be enabled to generate\r
+ fall interrupts.\r
+ */\r
+void ACE_enable_comp_fall_irq\r
+(\r
+ comparator_id_t comp_id\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ACE_disable_comp_fall_irq() function is used to disable interrupts from\r
+ being generated when the positive input of the comparator specified as parameter\r
+ falls below the negative input of the comparator.\r
+ \r
+ @param comp_id\r
+ The comp_id parameter specifies which comparator will be disabled from\r
+ generating fall interrupts.\r
+ */\r
+void ACE_disable_comp_fall_irq\r
+(\r
+ comparator_id_t comp_id\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ACE_clear_comp_fall_irq() function is used to clear fall interrupts. This\r
+ function is typically called as part of the fall interrupt service routine.\r
+ \r
+ @param comp_id\r
+ The comp_id parameter specifies the comparator for which to clear the fall\r
+ interrupt.\r
+ \r
+ Example:\r
+ @code\r
+ void ACE_Comp1_Fall_IRQHandler( void )\r
+ {\r
+ process_fall_irq();\r
+ ACE_clear_comp_fall_irq( CMP1 );\r
+ NVIC_ClearPendingIRQ( ACE_Comp1_Fall_IRQn );\r
+ }\r
+ @endcode\r
+ */\r
+void ACE_clear_comp_fall_irq\r
+(\r
+ comparator_id_t comp_id\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ACE_get_comp_status() function returns the current comparator interrupt\r
+ status. It returns a 32 bit value indicating which comparators experienced a\r
+ fall and/or rise event. These status bits can be cleared using the\r
+ ACE_clear_comp_rise_irq() and ACE_clear_comp_fall_irq() functions.\r
+ \r
+ @return\r
+ The return value is a 32 bit numnber where bits 0 to 11 indicate which\r
+ comparator experienced a fall event and bits 21 to 23 indicate which\r
+ comparator experienced a rise event.\r
+ */\r
+uint32_t ACE_get_comp_status( void );\r
+\r
+/** @} */\r
+\r
+/*==============================================================================\r
+ ========================== Controlling Thresholds =============================\r
+ =============================================================================*/\r
+/*=========================================================================*//**\r
+ @defgroup group8 Controlling Flags Thresholds\r
+ The following functions are used to dynamically control Post Processing Engine\r
+ (PPE) flags threshholds.\r
+ @{\r
+ *//*=========================================================================*/\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ACE_is_hysteresis_flag() function indicates if an hysteresis is applied\r
+ to the analog input sample value when determining the state of the flag\r
+ identified as parameter.\r
+ \r
+ @param flag_handle\r
+ The flag_handle parameter identifies one of the flags generated based on the\r
+ value of an analog input channel. The available flag handle values can be\r
+ found in the ace_handles.h file located in the .\drivers_config\mss_ace\r
+ subdirectory. The flag handle value can also be retrieved through a call to\r
+ ACE_get_flag_handle() when the name of the flag is known, or by iterating\r
+ though all flags associated with an analog input channel using the\r
+ ACE_get_channel_first_flag() and ACE_get_channel_next_flag().\r
+ \r
+ @return\r
+ This function returns the value one if a hysteresis is applied to the channel\r
+ sample values as part of determining the state of the flag identified as\r
+ parameter. It returns zero if no hysteresis is applied.\r
+ */\r
+uint32_t ACE_is_hysteresis_flag\r
+(\r
+ ace_flag_handle_t flag_handle\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ACE_is_under_flag() function indicates whether a flag is triggered when the\r
+ monitored analog input falls below the flag's threshold level or above the\r
+ flag's threshold level.\r
+ \r
+ @param flag_handle\r
+ The flag_handle parameter identifies one of the flags generated based on the\r
+ value of an analog input channel. The available flag handle values can be\r
+ found in the ace_handles.h file located in the .\drivers_config\mss_ace\r
+ subdirectory. The flag handle value can also be retrieved through a call to\r
+ ACE_get_flag_handle() when the name of the flag is known, or by iterating\r
+ though all flags associated with an analog input channel using the\r
+ ACE_get_channel_first_flag() and ACE_get_channel_next_flag().\r
+ \r
+ @return\r
+ This function returns the value one if the flag identified as parameter\r
+ triggers as a result of the monitored input falling below the flag's\r
+ threshold value.\r
+ It returns zero if the flag triggers as a result of the monitored input\r
+ exceeding the flag's threshold value.\r
+ */\r
+uint32_t ACE_is_under_flag\r
+(\r
+ ace_flag_handle_t flag_handle\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ACE_set_flag_threshold() function is used to adjust the threshold for a\r
+ specific post processing engine generated flag. The flag is identified through\r
+ the name selected in the ACE configurator software tool.\r
+ This function will set a new flag\92s threshold value while preserving the\r
+ hysteresis specified at configuration time or through a call to\r
+ ACE_set_flag_hysteresis(). For example, requesting a 1 volt threshold for an\r
+ over flag configured with a 100 millivolts hysteresis will result in the flag\r
+ being asserted when the voltage reaches 1.1 volts and deasserted when the\r
+ voltage falls below 0.9 volt.\r
+ \r
+ @param flag_handle\r
+ The flag_handle parameter identifies one of the flags generated based on the\r
+ value of an analog input channel. The available flag handle values can be\r
+ found in the ace_handles.h file located in the ./drivers_config/mss_ace\r
+ subdirectory. The flag handle value can also be retrieved through a call to\r
+ ACE_get_flag_handle() when the name of the flag is known, or by iterating\r
+ though all flags associated with an analog input channel using the\r
+ ACE_get_channel_first_flag() and ACE_get_channel_next_flag().\r
+ \r
+ @param new_threshold\r
+ The new_threshold parameter specifies the new threshold level that must be\r
+ reached in order for the flag to be raised. The value of this parameter is\r
+ the sample value resulting from a post processing engine conversion of the\r
+ desired analog input threshold level.\r
+ \r
+ Example:\r
+ The function below sets the threshold of the flag specified as parameter to\r
+ 1 volt.\r
+ @code\r
+ void set_threshold_to_1V\r
+ (\r
+ ace_flag_handle_t flag_handle\r
+ )\r
+ {\r
+ uint16_t new_threshold;\r
+ ace_channel_handle_t channel_handle;\r
+ \r
+ channel_handle = ACE_get_flag_channel(flag_handle);\r
+ new_threshold = ACE_convert_from_mV(channel_handle, 1000);\r
+ ACE_set_flag_threshold(flag_handle, new_threshold);\r
+ }\r
+ @endcode\r
+ */\r
+void ACE_set_flag_threshold\r
+(\r
+ ace_flag_handle_t flag_handle,\r
+ uint16_t new_threshold\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ACE_set_flag_hysteresis() function modifies the hysteresis applied to the\r
+ analog input channel sample values used to generate the flag specified as\r
+ parameter.\r
+\r
+ @param flag_handle\r
+ The flag_handle parameter identifies one of the flags generated based on the\r
+ value of an analog input channel. The available flag handle values can be\r
+ found in the ace_handles.h file located in the .\drivers_config\mss_ace\r
+ subdirectory. The flag handle value can also be retrieved through a call to\r
+ ACE_get_flag_handle() when the name of the flag is known, or by iterating\r
+ though all flags associated with an analog input channel using the\r
+ ACE_get_channel_first_flag() and ACE_get_channel_next_flag().\r
+ \r
+ @param adc_hysteresis\r
+ The adc_hysteresis parameter is the value to add and subtract to the\r
+ threshold value to obtain the hysteresis high and low limits triggering flag\r
+ assertion and deassertion. The adc_hysteresis parameter is a PPE conversion\r
+ result offset.\r
+\r
+ Example\r
+ The example below demonstrates the use of the ACE_set_flag_hysteresis()\r
+ function to set a 100mV hysteresis on the OVER_1V flag of the VoltageMonitor\r
+ input channel. VoltageMonitor and OVER_1V are names selected in the ACE\r
+ configurator for one of the analog inputs and one of the flags associated\r
+ with that input.\r
+ The method used to compute the adc_hysteresis value will work for all\r
+ input types including ABPS inputs where zero Volts is not equivalent to a \r
+ PPE sample value of zero.\r
+ \r
+ @code\r
+ ace_channel_handle_t channel_handle;\r
+ ace_flag_handle_t flag_handle;\r
+ uint16_t adc_hysteresis;\r
+ uint16_t upper_limit;\r
+ uint16_t lower_limit;\r
+ \r
+ channel_handle = VoltageMonitor;\r
+ flag_handle = VoltageMonitor_OVER_1V;\r
+ \r
+ upper_limit = ACE_convert_from_mV(channel_handle, 100);\r
+ lower_limit = ACE_convert_from_mV(channel_handle, 0);\r
+ \r
+ if (upper_limit > lower_limit)\r
+ {\r
+ adc_hysteresis = upper_limit - lower_limit;\r
+ }\r
+ else\r
+ {\r
+ adc_hysteresis = lower_limit - upper_limit;\r
+ }\r
+ \r
+ ACE_set_flag_hysteresis(flag_handle, adc_hysteresis);\r
+ @endcode\r
+ */\r
+void\r
+ACE_set_flag_hysteresis\r
+(\r
+ ace_flag_handle_t flag_handle,\r
+ uint16_t adc_hysteresis\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ACE_set_flag_assertion() function sets the PPE sample value that must be\r
+ reached in order for the flag specified as parameter to become asserted. It is\r
+ used in conjunction with the ACE_set_flag_deassertion() function as an\r
+ alternative to the ACE_set_flag_threshold() and ACE_set_flag_hysteresis()\r
+ functions to set the hysteresis window of an hysteresis flag.\r
+ The ACE_set_flag_assertion() and ACE_set_flag_deassertion() functions are\r
+ intended to be used where the threshold value is not centered within the\r
+ hysteresis window. They allow specifying the actual threshold values at which\r
+ the flag will be asserted and deasserted.\r
+\r
+ @param flag_handle\r
+ The flag_handle parameter identifies one of the flags generated based on the\r
+ value of an analog input channel. The available flag handle values can be\r
+ found in the ace_handles.h file located in the .\drivers_config\mss_ace\r
+ subdirectory. The flag handle value can also be retrieved through a call to\r
+ ACE_get_flag_handle() when the name of the flag is known, or by iterating\r
+ though all flags associated with an analog input channel using the\r
+ ACE_get_channel_first_flag() and ACE_get_channel_next_flag().\r
+ \r
+ @param assertion_value\r
+ The assertion_value parameter is the Post Processing Engine sample value that\r
+ must be reached for the flag, identified through the flag_handle parameter,\r
+ to become asserted. The PPE sample value is always a 12 bits sample value\r
+ regardless of the configuration of the ADC used to sample the input channel.\r
+ */\r
+void ACE_set_flag_assertion\r
+(\r
+ ace_flag_handle_t flag_handle,\r
+ uint16_t assertion_value\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ACE_set_flag_deassertion() function sets the PPE sample value that must be\r
+ reached in order for the flag specified as parameter to become deasserted. It\r
+ is used in conjunction with the ACE_set_flag_assertion() function as an\r
+ alternative to the ACE_set_flag_threshold() and ACE_set_flag_hysteresis()\r
+ functions to set the hysteresis window of an hysteresis flag.\r
+ The ACE_set_flag_assertion() and ACE_set_flag_deassertion() functions are\r
+ intended to be used where the threshold value is not centered within the\r
+ hysteresis window. They allow specifying the actual threshold values at which\r
+ the flag will be asserted and deasserted.\r
+ \r
+ @param flag_handle\r
+ The flag_handle parameter identifies one of the flags generated based on the\r
+ value of an analog input channel. The available flag handle values can be\r
+ found in the ace_handles.h file located in the .\drivers_config\mss_ace\r
+ subdirectory. The flag handle value can also be retrieved through a call to\r
+ ACE_get_flag_handle() when the name of the flag is known, or by iterating\r
+ though all flags associated with an analog input channel using the\r
+ ACE_get_channel_first_flag() and ACE_get_channel_next_flag().\r
+ \r
+ @param assertion_value\r
+ The assertion_value parameter is the Post Processing Engine sample value\r
+ that must be reached for the flag, identified through the flag_handle\r
+ parameter, to become de-asserted. The PPE sample value is always a 12 bits\r
+ sample value regardless of the configuration of the ADC used to sample the\r
+ input channel.\r
+ */\r
+void ACE_set_flag_deassertion\r
+(\r
+ ace_flag_handle_t flag_handle,\r
+ uint16_t assertion_value\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ACE_set_channel_hysteresis() function sets the hysteresis applied to\r
+ analog input channel sample values when generating flags. It sets the\r
+ hysteresis for all flags generated based on the value of the analog input\r
+ channel identified by the channel handle passed as first parameter.\r
+ \r
+ @param channel_handle\r
+ The channel_handle parameter identifies one of the analog input channels\r
+ monitored by the ACE. The available channel handle values can be found in\r
+ the ace_handles.h file located in the .\drivers_config\mss_ace subdirectory.\r
+ The channel handle value can also be retrieved through a call to\r
+ ACE_get_channel_handle() when the name of the channel is known, or by\r
+ iterating though all analog input channel using the ACE_get_first_channel()\r
+ and ACE_get_next_channel().\r
+\r
+ @param adc_hysteresis\r
+ The adc_hysteresis parameter is the value to add and subtract to the\r
+ threshold value to obtain the hysteresis high and low limits triggering flag\r
+ assertion and deassertion. The adc_hysteresis parameter is a PPE conversion\r
+ result offset.\r
+ */\r
+void\r
+ACE_set_channel_hysteresis\r
+(\r
+ ace_channel_handle_t channel_handle,\r
+ uint16_t adc_hysteresis\r
+);\r
+\r
+\r
+/** @} */\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+ \r
+/*==============================================================================\r
+ ================================== Flags ======================================\r
+ =============================================================================*/\r
+/*=========================================================================*//**\r
+ @defgroup group6 Post Processing Engine Flags\r
+ The following functions are used to control interrupts generated by the ACE's\r
+ Post Processing Engine (PPE) when monitored inputs rise above or fall below\r
+ thresholds specified in the ACE configurator software tool.\r
+ @{\r
+ *//*=========================================================================*/\r
+\r
+ /*-------------------------------------------------------------------------*//**\r
+ These constant definitions are the return values of the ACE_get_flag_status()\r
+ function. They specify the status of the Post Processing Engine (PPE) flag.\r
+ */\r
+#define UNKNOWN_FLAG (int32_t)(-1)\r
+#define FLAG_ASSERTED (int32_t)1\r
+#define FLAG_NOT_ASSERTED (int32_t)0\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ This constant is returned by the ACE_get_flag_handle function when the driver\r
+ can\92t find a valid handle for the Post Processing Engine (PPE) flag.\r
+ */\r
+#define INVALID_FLAG_HANDLE NB_OF_ACE_FLAG_HANDLES\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ACE_get_flag_handle() function returns the handle of the flag identified\r
+ by the flag name passed as parameter. The flag handle obtained through this\r
+ function is then used as parameter to other flag control functions to identify\r
+ which flag is to be controlled by the called function.\r
+ \r
+ @param p_sz_full_flag_name\r
+ The p_sz_full_flag_name parameter is a pointer to a zero-terminated string\r
+ holding the name of the flag as specified in the ACE configurator. The full\r
+ name of a flag contains both the name of the monitored input channel and the\r
+ name of the flag generated based the level of that input separated by ":".\r
+ For example, the full name for the flag called "CriticalOver" raised when\r
+ the input channel called "MainSupply" reaches a critical level would be\r
+ named "MainSupply:CriticalOver".\r
+ \r
+ @return\r
+ The ACE_get_flag_handle() returns the flag handle associated with the flag\r
+ name passed as parameter. It returns INVALID_FLAG_HANDLE when the flag name\r
+ is invalid and not recognized by the ACE driver.\r
+ */\r
+ace_flag_handle_t\r
+ACE_get_flag_handle\r
+(\r
+ const uint8_t * p_sz_full_flag_name\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ACE_get_flag_status() function returns the current status of the flag\r
+ specified as parameter. The flag is identified through the name specified in\r
+ the ACE configurator when the flag was created.\r
+ \r
+ @param flag_handle\r
+ The flag_handle parameter identifies one of the flags generated based on the\r
+ value of an analog input channel. The available flag handle values can be\r
+ found in the ace_handles.h file located in the .\drivers_config\mss_ace\r
+ subdirectory. The flag handle value can also be retrieved through a call to\r
+ ACE_get_flag_handle() when the name of the flag is known, or by iterating\r
+ though all flags associated with an analog input channel using the\r
+ ACE_get_channel_first_flag() and ACE_get_channel_next_flag().\r
+ \r
+ @return\r
+ The ACE_get_flag_status() function returns one of the following values\r
+ depending on the current status of the flag:\r
+ - FLAG_ASSERTED if the flag is raised/asserted.\r
+ - FLAG_NOT_ASSERTED if the flag is not asserted.\r
+ - UNKNOWN_FLAG if the flag name is not recognized by the driver.\r
+*/\r
+int32_t\r
+ACE_get_flag_status\r
+(\r
+ ace_flag_handle_t flag_handle\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ACE_enable_channel_flags_irq() function enables all flags generated based\r
+ on the value of the analog input channel passed as parameter to generate\r
+ interrupts. Flags used to detect that thresholds are crossed by the value\r
+ sampled on the analog input channel identified as parameter are enabled to\r
+ generate interrupts by this function. It enables flag interrupts both at the\r
+ ACE PEE flag and Cortex-M3 interrupt controller levels.\r
+ \r
+ @param channel_handle\r
+ The channel_handle parameter identifies one of the analog input channels\r
+ monitored by the ACE. The available channel handle values can be found in the\r
+ ace_handles.h file located in the ./drivers_config/mss_ace subdirectory. The\r
+ channel handle value can also be retrieved through a call to\r
+ ACE_get_channel_handle() when the name of the channel is known, or by\r
+ iterating though all analog input channel using the ACE_get_first_channel()\r
+ and ACE_get_next_channel().\r
+ */\r
+void ACE_enable_channel_flags_irq\r
+(\r
+ ace_channel_handle_t channel_handle\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ACE_disable_channel_flags_irq() function disables all flags generated\r
+ based on the value of the analog input channel passed as parameter to generate\r
+ interrupts. Flags used to detect that thresholds are crossed by the value\r
+ sampled on the analog input channel identified as parameter are disabled from\r
+ generating interrupts by this function. The interrupt is only disabled at the\r
+ ACE PPE flag level in order to avoid disabling other cahnnel's flag interrupts\r
+ which may happen to use the same ACE threshold interrupt line.\r
+ \r
+ @param channel_handle\r
+ The channel_handle parameter identifies one of the analog input channels\r
+ monitored by the ACE. The available channel handle values can be found in the\r
+ ace_handles.h file located in the ./drivers_config/mss_ace subdirectory. The\r
+ channel handle value can also be retrieved through a call to\r
+ ACE_get_channel_handle() when the name of the channel is known, or by\r
+ iterating though all analog input channel using the ACE_get_first_channel()\r
+ and ACE_get_next_channel().\r
+ */\r
+void ACE_disable_channel_flags_irq\r
+(\r
+ ace_channel_handle_t channel_handle\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ACE_clear_channel_flags_irq() function clears all interrupts generated by\r
+ flags associated with the analog input channel passed as parameter. Interrupt\r
+ generated by flags used to detect that thresholds are crossed by the value\r
+ sampled on the analog input channel identified as parameter are cleared by\r
+ this function. This function would typically be used before enabling the flag\r
+ interrupts in order to ignore past events.\r
+ \r
+ @param channel_handle\r
+ The channel_handle parameter identifies one of the analog input channels\r
+ monitored by the ACE. The available channel handle values can be found in the\r
+ ace_handles.h file located in the ./drivers_config/mss_ace subdirectory. The\r
+ channel handle value can also be retrieved through a call to\r
+ ACE_get_channel_handle() when the name of the channel is known, or by\r
+ iterating though all analog input channel using the ACE_get_first_channel()\r
+ and ACE_get_next_channel().\r
+ */\r
+void ACE_clear_channel_flags_irq\r
+(\r
+ ace_channel_handle_t channel_handle\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ACE_enable_flag_irq() function enables the ACE post processing engine (PPE)\r
+ generated flags specified as parameter to interrupt the Cortex-M3 processor.\r
+ It enables flag interrupts both at the ACE PPE flag and Cortex-M3 interrupt\r
+ controller levels.\r
+ \r
+ @param flag_handle\r
+ The flag_handle parameter identifies one of the flags generated based on the\r
+ value of an analog input channel. The available flag handle values can be\r
+ found in the ace_handles.h file located in the .\drivers_config\mss_ace\r
+ subdirectory. The flag handle value can also be retrieved through a call to\r
+ ACE_get_flag_handle() when the name of the flag is known, or by iterating\r
+ though all flags associated with an analog input channel using the\r
+ ACE_get_channel_first_flag() and ACE_get_channel_next_flag().\r
+ */\r
+void ACE_enable_flag_irq\r
+(\r
+ ace_flag_handle_t flag_handle\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ACE_disable_flag_irq() function disables ACE post processing engine (PPE)\r
+ generated flags from interrupting the Cortex-M3. The interrupt is only\r
+ disabled at the ACE PPE flag level in order to avoid disabling other flags\r
+ interrupts which may happen to use the same ACE threshold interrupt line.\r
+ \r
+ @param flag_handle\r
+ The flag_handle parameter identifies one of the flags generated based on the\r
+ value of an analog input channel. The available flag handle values can be\r
+ found in the ace_handles.h file located in the .\drivers_config\mss_ace\r
+ subdirectory. The flag handle value can also be retrieved through a call to\r
+ ACE_get_flag_handle() when the name of the flag is known, or by iterating\r
+ though all flags associated with an analog input channel using the\r
+ ACE_get_channel_first_flag() and ACE_get_channel_next_flag().\r
+ */\r
+void ACE_disable_flag_irq\r
+(\r
+ ace_flag_handle_t flag_handle\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ACE_clear_flag_irq() function clears the interrupt for the flag specified\r
+ as parameter. This function would typically be used before enabling the flag\r
+ interrupt in order to ignore past events.\r
+ \r
+ @param flag_handle\r
+ The flag_handle parameter identifies one of the flags generated based on the\r
+ value of an analog input channel. The available flag handle values can be\r
+ found in the ace_handles.h file located in the .\drivers_config\mss_ace\r
+ subdirectory. The flag handle value can also be retrieved through a call to\r
+ ACE_get_flag_handle() when the name of the flag is known, or by iterating\r
+ though all flags associated with an analog input channel using the\r
+ ACE_get_channel_first_flag() and ACE_get_channel_next_flag().\r
+ */\r
+void ACE_clear_flag_irq\r
+(\r
+ ace_flag_handle_t flag_handle\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ACE_get_flag_name() function returns the name of the flag identified by\r
+ the flag handle passed as parameter.\r
+ \r
+ @param flag_handle\r
+ The flag_handle parameter identifies one of the flags generated based on the\r
+ value of an analog input channel. The available flag handle values can be\r
+ found in the ace_handles.h file located in the .\drivers_config\mss_ace\r
+ subdirectory. The flag handle value can also be retrieved through a call to\r
+ ACE_get_flag_handle() when the name of the flag is known, or by iterating\r
+ though all flags associated with an analog input channel using the\r
+ ACE_get_channel_first_flag() and ACE_get_channel_next_flag().\r
+ \r
+ @return\r
+ The ACE_get_flag_name() function returns a pointer to a zero-terminated\r
+ string containing the name of the flag identified by the flag handle passed\r
+ as parameter. It returns 0 if the flag handle passed as parameter is invalid.\r
+ */\r
+const uint8_t *\r
+ACE_get_flag_name\r
+(\r
+ ace_flag_handle_t flag_handle\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ACE_get_flag_channel() function returns the handle of the channel\r
+ monitored in order to generate the flag identified by the flag handle passed\r
+ as parameter.\r
+ \r
+ @param flag_handle\r
+ The flag_handle parameter identifies one of the flags generated based on the\r
+ value of an analog input channel. The available flag handle values can be\r
+ found in the ace_handles.h file located in the .\drivers_config\mss_ace\r
+ subdirectory. The flag handle value can also be retrieved through a call to\r
+ ACE_get_flag_handle() when the name of the flag is known, or by iterating\r
+ though all flags associated with an analog input channel using the\r
+ ACE_get_channel_first_flag() and ACE_get_channel_next_flag().\r
+ \r
+ @return\r
+ The ACE_get_flag_channel() function returns a channel handle identifying the\r
+ analog input channel monitored by the flag passed as parameter.\r
+ */\r
+ace_channel_handle_t\r
+ACE_get_flag_channel\r
+(\r
+ ace_flag_handle_t flag_handle\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ACE_get_channel_flag_count() function returns the total number of flags\r
+ associated with the input channel specified by the channel_handle parameter.\r
+ It indicates how many flags are generated based on the value of the specified\r
+ analog input channel.\r
+ \r
+ @param channel_handle\r
+ The channel_handle parameter identifies one of the analog input channels\r
+ monitored by the ACE. The available channel handle values can be found in\r
+ the ace_handles.h file located in the .\drivers_config\mss_ace subdirectory.\r
+ The channel handle value can also be retrieved through a call to\r
+ ACE_get_channel_handle() when the name of the channel is known, or by\r
+ iterating though all analog input channel using the ACE_get_first_channel()\r
+ and ACE_get_next_channel().\r
+ \r
+ @return\r
+ The ACE_get_channel_flag_count() function returns the total number of flags\r
+ that are generated based on the value of the specified analog input channel.\r
+ The ACE_get_channel_flag_count() function returns 0 if no input channels were\r
+ configured.\r
+ \r
+ Example\r
+ @code\r
+ uint32_t inc;\r
+ uint32_t nb_of_flags;\r
+ uint16_t flag_iterator;\r
+ ace_flag_handle_t current_flag;\r
+ ace_channel_handle_t channel_handle;\r
+ \r
+ nb_of_flags = ACE_get_channel_flag_count(channel_handle);\r
+ current_flag = ACE_get_channel_first_flag(channel_handle, &flag_iterator);\r
+ \r
+ for (inc = 0; inc < nb_of_flags; ++inc)\r
+ {\r
+ current_flag = ACE_get_channel_next_flag(channel_handle, &flag_iterator);\r
+ display_flag_properties(current_flag);\r
+ }\r
+ @endcode\r
+ */\r
+uint32_t\r
+ACE_get_channel_flag_count\r
+(\r
+ ace_channel_handle_t channel_handle\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ACE_get_channel_first_flag() function retrieves the handle of the first\r
+ flag associated with the analog input channel identified by the channel handle\r
+ passed as parameter. It also initialises the value of the iterator variable\r
+ pointed to by the second function parameter. The iterator can be used\r
+ subsequently as a parameter to the ACE_get_channel_next_flag() function to\r
+ iterate through all flags associated with the analog input channel.\r
+ \r
+ @param channel_handle\r
+ The channel_handle parameter identifies one of the analog input channels\r
+ monitored by the ACE. The available channel handle values can be found in the\r
+ ace_handles.h file located in the ./drivers_config/mss_ace subdirectory.\r
+ The channel handle value can also be retrieved through a call to\r
+ ACE_get_channel_handle() when the name of the channel is known, or by\r
+ iterating though all analog input channel using the ACE_get_first_channel()\r
+ and ACE_get_next_channel().\r
+ \r
+ @param iterator\r
+ The iterator parameter is a pointer to a uint16_t iterator variable. The\r
+ value of the iterator variable will be set by the ACE_get_channel_first_flag()\r
+ functions so that it can be used in subsequent calls to\r
+ ACE_get_channel_next_flag() to keep track of the current location in the\r
+ list of flags associated with the analog input channel.\r
+ \r
+ @return\r
+ The ACE_get_channel_first_flag() function returns a flag handle identifying\r
+ one of the flags generated based on the value of the analog input channel\r
+ identified by the channel_handle parameter. It returns INVALID_FLAG_HANDLE\r
+ if no flags are generated based on the analog input channel input or if the\r
+ channel handle is invalid.\r
+ \r
+ Example\r
+ @code\r
+ uint32_t inc;\r
+ uint32_t nb_of_flags;\r
+ uint16_t flag_iterator;\r
+ ace_flag_handle_t current_flag;\r
+ ace_channel_handle_t channel_handle;\r
+ \r
+ nb_of_flags = ACE_get_channel_flag_count(channel_handle);\r
+ current_flag = ACE_get_channel_first_flag(channel_handle, &flag_iterator);\r
+ \r
+ for (inc = 0; inc < nb_of_flags; ++inc)\r
+ {\r
+ current_flag = ACE_get_channel_next_flag(channel_handle, &flag_iterator);\r
+ display_flag_properties(current_flag);\r
+ }\r
+ @endcode\r
+ */\r
+ace_flag_handle_t\r
+ACE_get_channel_first_flag\r
+(\r
+ ace_channel_handle_t channel_handle,\r
+ uint16_t * iterator\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ACE_get_channel_next_flag() function retrieves the handle of a flag\r
+ associated with the analog input channel identified by the channel handle\r
+ passed as parameter. The retrieved flag handle is the next one in the driver's\r
+ internal flag list based on the iterator parameter.\r
+ \r
+ @param channel_handle\r
+ The channel_handle parameter identifies one of the analog input channels\r
+ monitored by the ACE. The available channel handle values can be found in the\r
+ ace_handles.h file located in the .\drivers_config\mss_ace subdirectory.\r
+ The channel handle value can also be retrieved through a call to\r
+ ACE_get_channel_handle() when the name of the channel is known, or by\r
+ iterating though all analog input channel using the ACE_get_first_channel()\r
+ and ACE_get_next_channel().\r
+ \r
+ @param iterator\r
+ The iterator parameter is a pointer to a uint16_t iterator variable. The value\r
+ of the iterator variable will be set by the ACE_get_channel_first_flag()\r
+ functions so that it can be used in subsequent calls to\r
+ ACE_get_channel_next_flag() to keep track of the current location in the list\r
+ of flags associated with the analog input channel.\r
+ \r
+ Example\r
+ @code\r
+ uint32_t inc;\r
+ uint32_t nb_of_flags;\r
+ uint16_t flag_iterator;\r
+ ace_flag_handle_t current_flag;\r
+ ace_channel_handle_t channel_handle;\r
+ \r
+ nb_of_flags = ACE_get_channel_flag_count(channel_handle);\r
+ current_flag = ACE_get_channel_first_flag(channel_handle, &flag_iterator);\r
+ \r
+ for (inc = 0; inc < nb_of_flags; ++inc)\r
+ {\r
+ current_flag = ACE_get_channel_next_flag(channel_handle, &flag_iterator);\r
+ display_flag_properties(current_flag);\r
+ }\r
+ @endcode\r
+ */\r
+ace_flag_handle_t\r
+ACE_get_channel_next_flag\r
+(\r
+ ace_channel_handle_t channel_handle,\r
+ uint16_t * iterator\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ This defines the function prototype that must be followed by MSS ACE Post\r
+ Processing Engine (PPE) flag handler functions. These functions are registered\r
+ with the ACE driver and associated with a particular flag through the\r
+ ACE_register_flag_isr() function. The ACE driver will call the flag handler\r
+ function when the associated flag is raised.\r
+ \r
+ Declaring and Implementing PPE Flag Handler Functions\r
+ PPE flag handler functions should follow the following prototype:\r
+ void my_flag_handler ( ace_flag_handle_t flag_handle );\r
+ The actual name of the PPE flag handler is unimportant. You can use any name of\r
+ your choice for the PPE flag handler. \r
+ The flag_handle parameter passes the handle of the raised flag to the flag\r
+ handler function.\r
+ */\r
+typedef void (*flag_isr_t)( ace_flag_handle_t flag_handle );\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ACE_register_flag_isr() function is used to register a handler function\r
+ with the ACE driver. The registered function will be called by the ACE driver\r
+ when the associated flag is raised by the ACE post processing engine.\r
+ \r
+ @param flag_handle\r
+ The flag_handle parameter identifies one of the flags generated based on the\r
+ value of an analog input channel. The available flag handle values can be\r
+ found in the ace_handles.h file located in the .\drivers_config\mss_ace\r
+ subdirectory. The flag handle value can also be retrieved through a call to\r
+ ACE_get_flag_handle() when the name of the flag is known, or by iterating\r
+ though all flags associated with an analog input channel using the\r
+ ACE_get_channel_first_flag() and ACE_get_channel_next_flag().\r
+ \r
+ @param flag_isr\r
+ The flag_isr parameter is a pointer to a flag handler function with the\r
+ following prototype: \r
+ void handler_function_name(ace_flag_handle_t flag_handle) \r
+ The flag handler function is called by the ACE driver as part of the relevant\r
+ post processing engine flag interrupt service routine. It does not need to\r
+ handle flag interrupt clearing as this is done by the ACE driver.\r
+\r
+ \r
+ @code\r
+ void my_critical_handler( void );\r
+ \r
+ void system_init( void )\r
+ {\r
+ ace_flag_handle_t flag_handle;\r
+ \r
+ flag_handle = ACE_get_flag_handle( "MainSupply:CriticalLevel" );\r
+ ACE_register_flag_isr( flag_handle, my_critical_handler );\r
+ ACE_enable_flag_irq( flag_handle );\r
+ }\r
+ \r
+ void my_critical_handler( ace_flag_handle_t flag_handle )\r
+ {\r
+ panic( flag_handle );\r
+ }\r
+ \r
+ @endcode\r
+ */\r
+void ACE_register_flag_isr\r
+(\r
+ ace_flag_handle_t flag_handle,\r
+ flag_isr_t flag_isr\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ This defines the function prototype that must be followed by MSS ACE Post\r
+ Processing Engine (PPE) channel flag handler functions. These functions are\r
+ registered with the ACE driver and associated with a particular ADC input\r
+ channel through the ACE_register_channel_flags_isr() function. The ACE driver\r
+ will call the channel flags handler function when one of the flags for the\r
+ associated ADC input channel is raised.\r
+ \r
+ Declaring and Implementing PPE Channel Flag Handler Functions\r
+ PPE channel flag handler functions should follow the following prototype:\r
+ void my_channel_flag_handler ( ace_flag_handle_t flag_handle );\r
+ The actual name of the PPE channel flag handler is unimportant. You can use\r
+ any name of your choice for the PPE channel flag handler. The flag_handle\r
+ parameter passes the handle of the raised flag to the channel flag handler\r
+ function.\r
+ */\r
+typedef void (*channel_flag_isr_t)( ace_flag_handle_t flag_handle );\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ACE_register_channel_flags_isr() function is used to register a flag\r
+ interrupt handler function with the ACE driver. The registered interrupt\r
+ handler will be called by the ACE driver when one of the flag generated based\r
+ on the value of the analog input channel identified by the channel handle\r
+ passed as parameter is asserted.\r
+ \r
+ @param channel_handle\r
+ The channel_handle parameter identifies one of the analog input channels\r
+ monitored by the ACE. The available channel handle values can be found in the\r
+ ace_handles.h file located in the ./drivers_config/mss_ace subdirectory. The\r
+ channel handle value can also be retrieved through a call to\r
+ ACE_get_channel_handle() when the name of the channel is known, or by\r
+ iterating though all analog input channel using the ACE_get_first_channel()\r
+ and ACE_get_next_channel().\r
+ \r
+ @param channel_flag_isr\r
+ The channel_flag_isr parameter is pointer to a function taking a flag handle\r
+ as parameter. \r
+ void handler_function_name(ace_flag_handle_t flag_handle) \r
+ The flag handler function is called by the ACE driver as part of the relevant\r
+ post processing engine flag interrupt service routine. It does not need to\r
+ handle flag interrupt clearing as this is done by the ACE driver.\r
+ \r
+ Example\r
+ The example below demonstrates the use of the ACE_register_channel_flags_isr()\r
+ function in a system where the ACE is configured to have an analog input\r
+ channels named "MainSupply" with one flag named "Critical" generated based\r
+ on the value of "MainSupply" channel. The names "MainSupply" and "Critical"\r
+ were user selected in the ACE configurator. \r
+ @code\r
+ void main_supply_handler (ace_flag_handle_t flag_handle);\r
+ \r
+ void system_init(void)\r
+ {\r
+ ACE_register_channel_flag_isr(MainSupply, main_supply_handler);\r
+ ACE_enable_channel_flags_irq(MainSupply);\r
+ }\r
+ \r
+ void main_supply_handler (ace_flag_handle_t flag_handle)\r
+ {\r
+ if (MainSupply_Critical == flag_handle)\r
+ {\r
+ panic(flag_handle);\r
+ }\r
+ }\r
+ \r
+ @endcode\r
+*/\r
+void ACE_register_channel_flags_isr\r
+(\r
+ ace_channel_handle_t channel_handle,\r
+ channel_flag_isr_t channel_flag_isr\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ This defines the function prototype that must be followed by MSS ACE Post\r
+ Processing Engine (PPE) global flag handler functions. These functions are\r
+ registered with the ACE driver through the ACE_register_global_flags_isr()\r
+ function. The ACE driver will call the global flags handler function when any\r
+ flag for any ADC input channel is raised.\r
+ \r
+ Declaring and Implementing Global Flag Handler Functions\r
+ PPE global flag handler functions should follow the following prototype:\r
+ void my_global_flag_handler( \r
+ ace_flag_handle_t flag_handle, \r
+ ace_channel_handle_t channel_handle \r
+ );\r
+ The actual name of the PPE global flag handler is unimportant. You can use any\r
+ name of your choice for the PPE global flag handler. The flag_handle parameter\r
+ passes the handle of the raised flag to the global flag handler function. The\r
+ channel_handle parameter passes the handle of the channel for which the flag\r
+ was raised to the global flag handler function.\r
+\r
+ */\r
+typedef void (*global_flag_isr_t)( ace_flag_handle_t flag_handle, ace_channel_handle_t channel_handle );\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ACE_register_global_flags_isr() function is used to register a global\r
+ flag handler function with the ACE driver. The registered global handler will\r
+ be called when any flag interrupt is generated.\r
+ \r
+ @param global_flag_isr\r
+ The global_flag_isr parameter is a pointer to a function taking a flag\r
+ handle and channel handle as parameter.\r
+ */\r
+void ACE_register_global_flags_isr\r
+(\r
+ global_flag_isr_t global_flag_isr\r
+);\r
+\r
+/** @} */\r
+\r
+/*=========================================================================*//**\r
+ @defgroup group11 Conversion Functions\r
+ The following functions are used to convert an ADC sample value to a real\r
+ world unit.\r
+ @{\r
+ *//*=========================================================================*/\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ACE_convert_adc_input_to_mV() function converts an ADC sample value into\r
+ the value in millivolts of the voltage seen at ADC input. It does not account\r
+ for prescaling taking place before the ADC hardware input.\r
+\r
+ @param channel_handle\r
+ The channel_handle parameter identifies one of the analog input channels\r
+ monitored by the ACE. The available channel handle values can be found in the\r
+ ace_handles.h file located in the ./drivers_config/mss_ace subdirectory. The\r
+ channel handle value can also be retrieved through a call to\r
+ ACE_get_channel_handle() when the name of the channel is known, or by\r
+ iterating though all analog input channel using the ACE_get_first_channel()\r
+ and ACE_get_next_channel().\r
+ \r
+ @param sample_value\r
+ The sample_value parameter is the result of an analog to digital conversion.\r
+ \r
+ @return\r
+ The ACE_convert_adc_input_to_mV() returns the number of millivolts derived\r
+ from the ADC sample value passed as parameter.\r
+ */\r
+uint32_t ACE_convert_adc_input_to_mV\r
+(\r
+ ace_channel_handle_t channel_handle,\r
+ uint16_t sample_value\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ACE_convert_to_mV() function converts a PPE sample value into milli-Volts.\r
+ It handles prescaling adjusments based on ACE configuration for ABPS inputs.\r
+ \r
+ @param channel_handle\r
+ The channel_handle parameter identifies one of the analog input channels\r
+ monitored by the ACE. The available channel handle values can be found in the\r
+ ace_handles.h file located in the ./drivers_config/mss_ace subdirectory. The\r
+ channel handle value can also be retrieved through a call to\r
+ ACE_get_channel_handle() when the name of the channel is known, or by\r
+ iterating though all analog input channel using the ACE_get_first_channel()\r
+ and ACE_get_next_channel().\r
+ \r
+ @param sample_value\r
+ The sample_value parameter is the result of an analog to digital conversion.\r
+ \r
+ @return\r
+ The ACE_convert_to_mV() returns the number of millivolts derived from the\r
+ PPE sample value passed as parameter. The returned value can be either\r
+ positive or negative since prescaling is accounted for in the conversion.\r
+ */\r
+int32_t ACE_convert_to_mV\r
+(\r
+ ace_channel_handle_t channel_handle,\r
+ uint16_t sample_value\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ACE_convert_to_mA() function converts a PPE sample value into milli-Amps.\r
+ The result of the conversion is only meaningful if the PPE sample value\r
+ results from the conversion of a current monitor input.\r
+ \r
+ @param channel_handle\r
+ The channel_handle parameter identifies one of the analog input channels\r
+ monitored by the ACE. The available channel handle values can be found in the\r
+ ace_handles.h file located in the ./drivers_config/mss_ace subdirectory. The\r
+ channel handle value can also be retrieved through a call to\r
+ ACE_get_channel_handle() when the name of the channel is known, or by\r
+ iterating though all analog input channel using the ACE_get_first_channel()\r
+ and ACE_get_next_channel().\r
+ \r
+ @param sample_value\r
+ The sample_value parameter is the result of an analog to digital conversion\r
+ of the voltage generated by a current monitor analog block.\r
+ \r
+ @return\r
+ The ACE_convert_to_mA() returns the number of milliamps derived from the\r
+ PPE sample value passed as parameter.\r
+ */\r
+uint32_t ACE_convert_to_mA\r
+(\r
+ ace_channel_handle_t channel_handle,\r
+ uint16_t sample_value\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ACE_convert_to_Kelvin() function converts a PPE sample value into degrees\r
+ Kelvin. The result of the conversion is only meaningful if the PPE sample value\r
+ results from the conversion of a temperature monitor input.\r
+ \r
+ @param channel_handle\r
+ The channel_handle parameter identifies one of the analog input channels\r
+ monitored by the ACE. The available channel handle values can be found in the\r
+ ace_handles.h file located in the ./drivers_config/mss_ace subdirectory. The\r
+ channel handle value can also be retrieved through a call to\r
+ ACE_get_channel_handle() when the name of the channel is known, or by\r
+ iterating though all analog input channel using the ACE_get_first_channel()\r
+ and ACE_get_next_channel().\r
+ \r
+ @param sample_value\r
+ The sample_value parameter is the result of an analog to digital conversion\r
+ of the voltage generated by a temperature monitor analog block.\r
+ \r
+ @return\r
+ The ACE_convert_to_Kelvin() returns the number of degrees Kelvin derived\r
+ from the PPE sample value passed as parameter.\r
+ */\r
+uint32_t ACE_convert_to_Kelvin\r
+(\r
+ ace_channel_handle_t channel_handle,\r
+ uint16_t sample_value\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ACE_convert_to_Celsius() function converts a PPE sample value into tenths\r
+ of degrees Celsius. The result of the conversion is only meaningful if the PPE\r
+ sample value results from the conversion of a temperature monitor input.\r
+ \r
+ @param channel_handle\r
+ The channel_handle parameter identifies one of the analog input channels\r
+ monitored by the ACE. The available channel handle values can be found in the\r
+ ace_handles.h file located in the ./drivers_config/mss_ace subdirectory. The\r
+ channel handle value can also be retrieved through a call to\r
+ ACE_get_channel_handle() when the name of the channel is known, or by\r
+ iterating though all analog input channel using the ACE_get_first_channel()\r
+ and ACE_get_next_channel().\r
+ \r
+ @param sample_value\r
+ The sample_value parameter is the result of an analog to digital conversion\r
+ of the voltage generated by a temperature monitor analog block.\r
+ \r
+ @return\r
+ The ACE_convert_to_Celsius() returns the number of tenths of degrees Celsius\r
+ derived from the PPE sample value passed as parameter.\r
+ */\r
+int32_t ACE_convert_to_Celsius\r
+(\r
+ ace_channel_handle_t channel_handle,\r
+ uint16_t sample_value\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ACE_convert_to_Fahrenheit() function converts a PPE sample value into\r
+ degrees Fahrenheit. The result of the conversion is only meaningful if the PPE\r
+ sample value results from the conversion of a temperature monitor input.\r
+ \r
+ @param channel_handle\r
+ The channel_handle parameter identifies one of the analog input channels\r
+ monitored by the ACE. The available channel handle values can be found in the\r
+ ace_handles.h file located in the ./drivers_config/mss_ace subdirectory. The\r
+ channel handle value can also be retrieved through a call to\r
+ ACE_get_channel_handle() when the name of the channel is known, or by\r
+ iterating though all analog input channel using the ACE_get_first_channel()\r
+ and ACE_get_next_channel().\r
+ \r
+ @param sample_value\r
+ The sample_value parameter is the result of an analog to digital conversion\r
+ of the voltage generated by a temperature monitor analog block.\r
+ \r
+ @return\r
+ The ACE_convert_to_Fahrenheit() returns the number of degrees Fahrenheit\r
+ derived from the PPE sample value passed as parameter.\r
+ */\r
+int32_t ACE_convert_to_Fahrenheit\r
+(\r
+ ace_channel_handle_t channel_handle,\r
+ uint16_t sample_value\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ACE_convert_mV_to_adc_value() function converts a voltage value given in\r
+ milli-Volts into the ADC sample value that would result from sampling this\r
+ voltage value on the analog input channel specified as parameter.\r
+ This function is intended for use when directly controlling the ADC, not when\r
+ using samples read from the PPE. It does not account for prescaling taking\r
+ place before the ADC hardware input.\r
+ \r
+ @param channel_handle\r
+ The channel_handle parameter identifies one of the analog input channels\r
+ monitored by the ACE. The available channel handle values can be found in the\r
+ ace_handles.h file located in the ./drivers_config/mss_ace subdirectory. The\r
+ channel handle value can also be retrieved through a call to\r
+ ACE_get_channel_handle() when the name of the channel is known, or by\r
+ iterating though all analog input channel using the ACE_get_first_channel()\r
+ and ACE_get_next_channel().\r
+ \r
+ @param voltage\r
+ The voltage parameter is the milli-Volts voltage value for which we want this\r
+ function to return the associated ADC sample result value.\r
+ \r
+ @return\r
+ The ACE_convert_mV_to_adc_value() returns the ADC sample value that would be\r
+ produced if the analog input channel identified by channel_handle was set to\r
+ the voltage value passed as second parameter.\r
+ */\r
+uint16_t ACE_convert_mV_to_adc_value\r
+(\r
+ ace_channel_handle_t channel_handle,\r
+ uint32_t voltage\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ACE_convert_from_mV() function converts a voltage value given in\r
+ milli-Volts into the PPE sample value that would result from sampling this\r
+ voltage value on the analog input channel specified as parameter.\r
+ This function handles prescaling adjusments based on ACE configuration for\r
+ ABPS inputs.\r
+ \r
+ @param channel_handle\r
+ The channel_handle parameter identifies one of the analog input channels\r
+ monitored by the ACE. The available channel handle values can be found in the\r
+ ace_handles.h file located in the ./drivers_config/mss_ace subdirectory. The\r
+ channel handle value can also be retrieved through a call to\r
+ ACE_get_channel_handle() when the name of the channel is known, or by\r
+ iterating though all analog input channel using the ACE_get_first_channel()\r
+ and ACE_get_next_channel().\r
+ \r
+ @param voltage\r
+ The voltage parameter is the milli-Volts voltage value for which we want this\r
+ function to return the associated PPE sample result value.\r
+ \r
+ @return\r
+ The ACE_convert_from_mV() returns the PPE sample value that would be produced\r
+ if the analog input channel identified by channel_handle was set to the\r
+ voltage value passed as second parameter.\r
+ */\r
+uint16_t ACE_convert_from_mV\r
+(\r
+ ace_channel_handle_t channel_handle,\r
+ int32_t voltage\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ACE_convert_from_mA() function converts a current value given in\r
+ milli-Amps into the PPE sample value that would result from sampling this\r
+ current value on the analog input channel specified as parameter.\r
+ The result of the conversion is only meaningful if the analog input channel\r
+ specified as parameter is configured as a current monitoring channel.\r
+ \r
+ @param channel_handle\r
+ The channel_handle parameter identifies one of the analog input channels\r
+ monitored by the ACE. The available channel handle values can be found in the\r
+ ace_handles.h file located in the ./drivers_config/mss_ace subdirectory. The\r
+ channel handle value can also be retrieved through a call to\r
+ ACE_get_channel_handle() when the name of the channel is known, or by\r
+ iterating though all analog input channel using the ACE_get_first_channel()\r
+ and ACE_get_next_channel().\r
+ \r
+ @param current\r
+ The current parameter is the milli-Amps current value for which we want this\r
+ function to return the associated PPE sample result value.\r
+ \r
+ @return\r
+ The ACE_convert_from_mA() returns the PPE sample value that would be produced\r
+ if the analog input channel identified by channel_handle was set to the\r
+ current value passed as second parameter.\r
+ */\r
+uint16_t ACE_convert_from_mA\r
+(\r
+ ace_channel_handle_t channel_handle,\r
+ uint32_t current\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ACE_convert_from_Kelvin() function converts a temperature value given in\r
+ degrees Kelvin into the PPE sample value that would result from sampling this\r
+ temperature value on the analog input channel specified as parameter.\r
+ The result of the conversion is only meaningful if the analog input channel\r
+ specified as parameter is configured as a temperature monitoring channel.\r
+ \r
+ @param channel_handle\r
+ The channel_handle parameter identifies one of the analog input channels\r
+ monitored by the ACE. The available channel handle values can be found in the\r
+ ace_handles.h file located in the ./drivers_config/mss_ace subdirectory. The\r
+ channel handle value can also be retrieved through a call to\r
+ ACE_get_channel_handle() when the name of the channel is known, or by\r
+ iterating though all analog input channel using the ACE_get_first_channel()\r
+ and ACE_get_next_channel().\r
+ \r
+ @param temperature\r
+ The temperature parameter is the degrees Kelvin temperature value for which\r
+ we want this function to return the associated PPE sample result value.\r
+ \r
+ @return\r
+ The ACE_convert_from_Kelvin() returns the PPE sample value that would be\r
+ produced if the analog input channel identified by channel_handle was set to\r
+ the temperature value passed as second parameter.\r
+ */\r
+uint16_t ACE_convert_from_Kelvin\r
+(\r
+ ace_channel_handle_t channel_handle,\r
+ uint32_t temperature\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ACE_convert_from_Celsius() function converts a temperature value given in\r
+ degrees Celsius into the PPE sample value that would result from sampling this\r
+ temperature value on the analog input channel specified as parameter.\r
+ The result of the conversion is only meaningful if the analog input channel\r
+ specified as parameter is configured as a temperature monitoring channel.\r
+ \r
+ @param channel_handle\r
+ The channel_handle parameter identifies one of the analog input channels\r
+ monitored by the ACE. The available channel handle values can be found in the\r
+ ace_handles.h file located in the ./drivers_config/mss_ace subdirectory. The\r
+ channel handle value can also be retrieved through a call to\r
+ ACE_get_channel_handle() when the name of the channel is known, or by\r
+ iterating though all analog input channel using the ACE_get_first_channel()\r
+ and ACE_get_next_channel().\r
+ \r
+ @param temperature\r
+ The temperature parameter is the degrees Celsius temperature value for which\r
+ we want this function to return the associated PPE sample result value.\r
+ \r
+ @return\r
+ The ACE_convert_from_Celsius() returns the PPE sample value that would be\r
+ produced if the analog input channel identified by channel_handle was set to\r
+ the temperature value passed as second parameter.\r
+ */\r
+uint16_t ACE_convert_from_Celsius\r
+(\r
+ ace_channel_handle_t channel_handle,\r
+ int32_t temperature\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ACE_convert_from_Fahrenheit() function converts a temperature value given\r
+ in degrees Fahrenheit into the PPE sample value that would result from sampling\r
+ this temperature value on the analog input channel specified as parameter.\r
+ The result of the conversion is only meaningful if the analog input channel\r
+ specified as parameter is configured as a temperature monitoring channel.\r
+ \r
+ @param channel_handle\r
+ The channel_handle parameter identifies one of the analog input channels\r
+ monitored by the ACE. The available channel handle values can be found in the\r
+ ace_handles.h file located in the ./drivers_config/mss_ace subdirectory. The\r
+ channel handle value can also be retrieved through a call to\r
+ ACE_get_channel_handle() when the name of the channel is known, or by\r
+ iterating though all analog input channel using the ACE_get_first_channel()\r
+ and ACE_get_next_channel().\r
+ \r
+ @param temperature\r
+ The temperature parameter is the degrees Fahrenheit temperature value for\r
+ which we want this function to return the associated PPE sample result value.\r
+ \r
+ @return\r
+ The ACE_convert_from_Fahrenheit() returns the PPE sample value that would be\r
+ produced if the analog input channel identified by channel_handle was set to\r
+ the temperature value passed as second parameter.\r
+ */\r
+uint16_t ACE_convert_from_Fahrenheit\r
+(\r
+ ace_channel_handle_t channel_handle,\r
+ int32_t temperature\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ACE_translate_pdma_value() function translates PDMA sampling values,\r
+ received from the ACE via PDMA transfers, into input channel ID and PPE\r
+ sample value.\r
+ The PDMA sampling values are generated by the ACE as a result of selecting\r
+ "Send result to DMA" in the ACE configurator analog input configuration. The\r
+ PDMA sampling values can be either raw ADC values, filtered values or the\r
+ result of a linear transformation.\r
+ The PDMA sampling values are obtained by configuring the PDMA controller to\r
+ transfer data from the ACE into a memory buffer. The ACE_translate_pdma_value()\r
+ function is used to interpret the content of that memory buffer.\r
+ \r
+ Please note that the translation of PDMA data containing raw ADC values from\r
+ ABPS inputs will result in sample values with an unexpected polarity.\r
+ The returned sample value will have the opposite polarity to the actual analog\r
+ value seen on the ABPS input. This is due to the internal characteristics of\r
+ the analog front end that are normally hidden by the PPE processing of ADC raw\r
+ samples. The translation of raw ADC values from analog inputs other than ABPS\r
+ inputs will result in correct sample values.\r
+ \r
+ @param pdma_value\r
+ The pdma_value parameter is a 32-bit value received from the ACE through a\r
+ peripheral DMA transfer. \r
+ \r
+ @param channel_id\r
+ The channel_id parameter is a pointer to an ADC channel ID variable. It is\r
+ used to return the ID of the ADC channel from which the PPE sample value\r
+ was generated from. This parameter can be set to zero if retrieving the\r
+ channel ID is not required.\r
+ \r
+ @return\r
+ The ACE_translate_pdma_value() returns the PPE sample value extracted from\r
+ the PDMA sampling value.\r
+ \r
+ Example:\r
+ @code\r
+ uint16_t ppe_value;\r
+ uint16_t pdma_value;\r
+ adc_channel_id_t channel_id;\r
+ ace_channel_handle_t channel_handle;\r
+ \r
+ pdma_value = get_next_pdma_ace_sample();\r
+ ppe_value = ACE_translate_pdma_value(pdma_value, &channel_id);\r
+ channel_handle = ACE_get_input_channel_handle(channel_id);\r
+ if (channel_handle != INVALID_CHANNEL_HANDLE)\r
+ {\r
+ display_value(channel_handle, ppe_value);\r
+ }\r
+ @endcode\r
+ \r
+ */\r
+uint16_t ACE_translate_pdma_value\r
+(\r
+ uint32_t pdma_value,\r
+ adc_channel_id_t * channel_id\r
+);\r
+\r
+/** @} */\r
+\r
+/*=========================================================================*//**\r
+ @defgroup group12 Dynamic Linear Transform Control Functions\r
+ The following functions are used to dynamically adjust the linear transform\r
+ applied to analog input samples by the post processing engine:\r
+ - ACE_get_default_m_factor()\r
+ - ACE_get_default_c_offset()\r
+ - ACE_set_linear_transform()\r
+ The post processing engine performs a linear transform on analog input samples\r
+ obtained from the sample sequencing engine. The main purpose of this linear \r
+ transform is to apply part specific factory calibration to the analog samples\r
+ in order to achieve high accuracy. A second user specified linear transform\r
+ can also be optionally applied to the analog samples. This second linear\r
+ transform can be used to adjust for board level calibration or application\r
+ specific tuning. The functions described in this section apply to the user\r
+ defined transform. Factory calibration will not be affected by the use of the\r
+ ACE_set_linear_transform() function.\r
+ Note:\r
+ The post processing engine actually only performs one single linear\r
+ transform on analog samples. This transform takes into account factory\r
+ calibration and the user defined transform. The applied y = m.x + c\r
+ transform uses an m factor equal to m1.m2.mext and c offset equal to\r
+ (m2.c1.mext) + (c2.mext) where m1 and c1 are the factory calibration factor\r
+ and offset; m2 and c2 are the user defined transform factor and offset; and\r
+ mext is a factory calibration factor depending on the reference voltage\r
+ used by the ADC generating the sample.\r
+ @{\r
+ *//*=========================================================================*/\r
+\r
+\r
+/*------------------------------------------------------------------------*//**\r
+ The ACE_get_default_m_factor() function retrieves the default value of the m\r
+ factor of the user defined linear transform applied by the post processing\r
+ engine to analog samples. The user defined linear transform m factor default\r
+ value is selected in the ACE configurator tool.\r
+ \r
+ @param channel_handle\r
+ The channel_handle parameter identifies one of the analog input channels\r
+ monitored by the ACE. The available channel handle values can be found in\r
+ the ace_handles.h file located in the .\drivers_config\mss_ace\r
+ subdirectory. The channel handle value can also be retrieved through a call\r
+ to ACE_get_channel_handle() when the name of the channel is known, or by\r
+ iterating though all analog input channel using the ACE_get_first_channel()\r
+ and ACE_get_next_channel().\r
+ \r
+ @return\r
+ The ACE_get_default_m_factor() function returns the user transform m factor\r
+ default value. It is a signed 16-bit number representing a factor in the\r
+ range -2 to +1.99993896484375. The value of the m factor is obtained by\r
+ multiplying the return value\92s absolute value by 2-14.\r
+ */\r
+int16_t ACE_get_default_m_factor\r
+(\r
+ ace_channel_handle_t channel_handle\r
+);\r
+\r
+/*------------------------------------------------------------------------*//**\r
+ The ACE_get_default_c_offset() function retrieves the default value of the c\r
+ offset of the user defined linear transform applied by the post processing\r
+ engine to analog samples. The user defined linear transform c offset default\r
+ value is selected in the ACE configurator tool.\r
+ \r
+ @param channel_handle\r
+ The channel_handle parameter identifies one of the analog input channels\r
+ monitored by the ACE. The available channel handle values can be found in\r
+ the ace_handles.h file located in the .\drivers_config\mss_ace\r
+ subdirectory. The channel handle value can also be retrieved through a call\r
+ to ACE_get_channel_handle() when the name of the channel is known, or by\r
+ iterating though all analog input channel using the ACE_get_first_channel()\r
+ and ACE_get_next_channel().\r
+ \r
+ @return\r
+ The ACE_get_default_c_offset() function returns the user linear transform\92s\r
+ c offset default value. It is a signed 16-bit number representing a factor\r
+ in the range -2 to +1.99993896484375. The value of the c offset is obtained\r
+ by multiplying the return value\92s absolute value by 2-14.\r
+ */\r
+int16_t ACE_get_default_c_offset\r
+(\r
+ ace_channel_handle_t channel_handle\r
+);\r
+\r
+/*------------------------------------------------------------------------*//**\r
+ The ACE_set_linear_transform() function allows adjusting the user defined\r
+ linear transform applied to analog input samples by the post processing\r
+ engine. The linear transform is of the form y = m.x + b where the m factor\r
+ and c offset are in the range -2 to +1.99993896484375.\r
+ \r
+ @param channel_handle\r
+ The channel_handle parameter identifies one of the analog input channels\r
+ monitored by the ACE. The available channel handle values can be found in\r
+ the ace_handles.h file located in the .\drivers_config\mss_ace\r
+ subdirectory. The channel handle value can also be retrieved through a call\r
+ to ACE_get_channel_handle() when the name of the channel is known, or by\r
+ iterating though all analog input channel using the ACE_get_first_channel()\r
+ and ACE_get_next_channel().\r
+ \r
+ @param m2\r
+ The m2 parameter specifies the user defined transform\92s m factor. It is a\r
+ signed 16-bit number representing a factor in the range -2 to\r
+ +1.99993896484375. The value of the m2 factor is obtained by multiplying the\r
+ parameter\92s absolute value by 2^-14. For example, a value of 0x7000\r
+ represents a 1.75 factor and a value of 0xE000 represents a -0.5 factor.\r
+ \r
+ @param c2\r
+ The c2 parameter specifies the user defined transform\92s c offset. It is a\r
+ signed 16-bit number representing an offset in the range -2 to\r
+ +1.99993896484375. The value of the c2 offset is obtained by multiplying the\r
+ parameter\92s absolute value by 2^-14. For example, a value of 0x1000 represents\r
+ a 0.25 offset and a value of 0xB000 represents a -1.25 offset.\r
+ \r
+ @code\r
+ void reset_to_default(ace_channel_handle_t channel_handle)\r
+ {\r
+ int16_t m;\r
+ int16_t c;\r
+ \r
+ m = ACE_get_default_m_factor(channel_handle);\r
+ c = ACE_get_default_c_offset(channel_handle);\r
+ ACE_set_linear_transform(channel_handle, m, c);\r
+ }\r
+ @endcode\r
+ */\r
+void ACE_set_linear_transform\r
+(\r
+ ace_channel_handle_t channel_handle,\r
+ int16_t m2,\r
+ int16_t c2\r
+);\r
+\r
+/** @} */\r
+ \r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __MSS_ACE_H_ */\r
--- /dev/null
+/*******************************************************************************\r
+ * (c) Copyright 2009 Actel Corporation. All rights reserved.\r
+ * \r
+ * SVN $Revision: 2841 $\r
+ * SVN $Date: 2010-07-20 18:10:00 +0100 (Tue, 20 Jul 2010) $\r
+ */\r
+\r
+/*=========================================================================*//**\r
+ @mainpage ACE Configurator data provided to ACE Driver.\r
+\r
+ @section intro_sec Introduction\r
+ This file contains the definition of data structures used by the ACE\r
+ Configurator software tool for sharing information about the ACE configuration\r
+ with the ACE driver. It also contains the API for accessor functions used by\r
+ the ACE driver to extract relevant information from these data structures.\r
+ *//*=========================================================================*/\r
+#ifndef __MSS_ACE_CONFIGURATOR_H_\r
+#define __MSS_ACE_CONFIGURATOR_H_\r
+\r
+#include "mss_ace.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif \r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ Post Processing Engine (PPE) flags IDs.\r
+ */\r
+typedef enum\r
+{\r
+ PPE_FLAGS0_0 = 0,\r
+ PPE_FLAGS0_1 = 1,\r
+ PPE_FLAGS0_2 = 2,\r
+ PPE_FLAGS0_3 = 3,\r
+ PPE_FLAGS0_4 = 4,\r
+ PPE_FLAGS0_5 = 5,\r
+ PPE_FLAGS0_6 = 6,\r
+ PPE_FLAGS0_7 = 7,\r
+ PPE_FLAGS0_8 = 8,\r
+ PPE_FLAGS0_9 = 9,\r
+ PPE_FLAGS0_10 = 10,\r
+ PPE_FLAGS0_11 = 11,\r
+ PPE_FLAGS0_12 = 12,\r
+ PPE_FLAGS0_13 = 13,\r
+ PPE_FLAGS0_14 = 14,\r
+ PPE_FLAGS0_15 = 15,\r
+ PPE_FLAGS0_16 = 16,\r
+ PPE_FLAGS0_17 = 17,\r
+ PPE_FLAGS0_18 = 18,\r
+ PPE_FLAGS0_19 = 19,\r
+ PPE_FLAGS0_20 = 20,\r
+ PPE_FLAGS0_21 = 21,\r
+ PPE_FLAGS0_22 = 22,\r
+ PPE_FLAGS0_23 = 23,\r
+ PPE_FLAGS0_24 = 24,\r
+ PPE_FLAGS0_25 = 25,\r
+ PPE_FLAGS0_26 = 26,\r
+ PPE_FLAGS0_27 = 27,\r
+ PPE_FLAGS0_28 = 28,\r
+ PPE_FLAGS0_29 = 29,\r
+ PPE_FLAGS0_30 = 30,\r
+ PPE_FLAGS0_31 = 31,\r
+ PPE_FLAGS1_0 = 32,\r
+ PPE_FLAGS1_1 = 33,\r
+ PPE_FLAGS1_2 = 34,\r
+ PPE_FLAGS1_3 = 35,\r
+ PPE_FLAGS1_4 = 36,\r
+ PPE_FLAGS1_5 = 37,\r
+ PPE_FLAGS1_6 = 38,\r
+ PPE_FLAGS1_7 = 39,\r
+ PPE_FLAGS1_8 = 40,\r
+ PPE_FLAGS1_9 = 41,\r
+ PPE_FLAGS1_10 = 42,\r
+ PPE_FLAGS1_11 = 43,\r
+ PPE_FLAGS1_12 = 44,\r
+ PPE_FLAGS1_13 = 45,\r
+ PPE_FLAGS1_14 = 46,\r
+ PPE_FLAGS1_15 = 47,\r
+ PPE_FLAGS1_16 = 48,\r
+ PPE_FLAGS1_17 = 49,\r
+ PPE_FLAGS1_18 = 50,\r
+ PPE_FLAGS1_19 = 51,\r
+ PPE_FLAGS1_20 = 52,\r
+ PPE_FLAGS1_21 = 53,\r
+ PPE_FLAGS1_22 = 54,\r
+ PPE_FLAGS1_23 = 55,\r
+ PPE_FLAGS1_24 = 56,\r
+ PPE_FLAGS1_25 = 57,\r
+ PPE_FLAGS1_26 = 58,\r
+ PPE_FLAGS1_27 = 59,\r
+ PPE_FLAGS1_28 = 60,\r
+ PPE_FLAGS1_29 = 61,\r
+ PPE_FLAGS1_30 = 62,\r
+ PPE_FLAGS1_31 = 63,\r
+ PPE_FLAGS2_0 = 64,\r
+ PPE_FLAGS2_1 = 65,\r
+ PPE_FLAGS2_2 = 66,\r
+ PPE_FLAGS2_3 = 67,\r
+ PPE_FLAGS2_4 = 68,\r
+ PPE_FLAGS2_5 = 69,\r
+ PPE_FLAGS2_6 = 70,\r
+ PPE_FLAGS2_7 = 71,\r
+ PPE_FLAGS2_8 = 72,\r
+ PPE_FLAGS2_9 = 73,\r
+ PPE_FLAGS2_10 = 74,\r
+ PPE_FLAGS2_11 = 75,\r
+ PPE_FLAGS2_12 = 76,\r
+ PPE_FLAGS2_13 = 77,\r
+ PPE_FLAGS2_14 = 78,\r
+ PPE_FLAGS2_15 = 79,\r
+ PPE_FLAGS2_16 = 80,\r
+ PPE_FLAGS2_17 = 81,\r
+ PPE_FLAGS2_18 = 82,\r
+ PPE_FLAGS2_19 = 83,\r
+ PPE_FLAGS2_20 = 84,\r
+ PPE_FLAGS2_21 = 85,\r
+ PPE_FLAGS2_22 = 86,\r
+ PPE_FLAGS2_23 = 87,\r
+ PPE_FLAGS2_24 = 88,\r
+ PPE_FLAGS2_25 = 89,\r
+ PPE_FLAGS2_26 = 90,\r
+ PPE_FLAGS2_27 = 91,\r
+ PPE_FLAGS2_28 = 92,\r
+ PPE_FLAGS2_29 = 93,\r
+ PPE_FLAGS2_30 = 94,\r
+ PPE_FLAGS2_31 = 95,\r
+ PPE_FLAGS3_0 = 96,\r
+ PPE_FLAGS3_1 = 97,\r
+ PPE_FLAGS3_2 = 98,\r
+ PPE_FLAGS3_3 = 99,\r
+ PPE_FLAGS3_4 = 100,\r
+ PPE_FLAGS3_5 = 101,\r
+ PPE_FLAGS3_6 = 102,\r
+ PPE_FLAGS3_7 = 103,\r
+ PPE_FLAGS3_8 = 104,\r
+ PPE_FLAGS3_9 = 105,\r
+ PPE_FLAGS3_10 = 106,\r
+ PPE_FLAGS3_11 = 107,\r
+ PPE_FLAGS3_12 = 108,\r
+ PPE_FLAGS3_13 = 109,\r
+ PPE_FLAGS3_14 = 110,\r
+ PPE_FLAGS3_15 = 111,\r
+ PPE_FLAGS3_16 = 112,\r
+ PPE_FLAGS3_17 = 113,\r
+ PPE_FLAGS3_18 = 114,\r
+ PPE_FLAGS3_19 = 115,\r
+ PPE_FLAGS3_20 = 116,\r
+ PPE_FLAGS3_21 = 117,\r
+ PPE_FLAGS3_22 = 118,\r
+ PPE_FLAGS3_23 = 119,\r
+ PPE_FLAGS3_24 = 120,\r
+ PPE_FLAGS3_25 = 121,\r
+ PPE_FLAGS3_26 = 122,\r
+ PPE_FLAGS3_27 = 123,\r
+ PPE_FLAGS3_28 = 124,\r
+ PPE_FLAGS3_29 = 125,\r
+ PPE_FLAGS3_30 = 126,\r
+ PPE_FLAGS3_31 = 127,\r
+ PPE_SFFLAGS_0 = 128,\r
+ PPE_SFFLAGS_1 = 129,\r
+ PPE_SFFLAGS_2 = 130,\r
+ PPE_SFFLAGS_3 = 131,\r
+ PPE_SFFLAGS_4 = 132,\r
+ PPE_SFFLAGS_5 = 133,\r
+ PPE_SFFLAGS_6 = 134,\r
+ PPE_SFFLAGS_7 = 135,\r
+ PPE_SFFLAGS_8 = 136,\r
+ PPE_SFFLAGS_9 = 137,\r
+ PPE_SFFLAGS_10 = 138,\r
+ PPE_SFFLAGS_11 = 139,\r
+ PPE_SFFLAGS_12 = 140,\r
+ PPE_SFFLAGS_13 = 141,\r
+ PPE_SFFLAGS_14 = 142,\r
+ PPE_SFFLAGS_15 = 143,\r
+ PPE_SFFLAGS_16 = 144,\r
+ PPE_SFFLAGS_17 = 145,\r
+ PPE_SFFLAGS_18 = 146,\r
+ PPE_SFFLAGS_19 = 147,\r
+ PPE_SFFLAGS_20 = 148,\r
+ PPE_SFFLAGS_21 = 149,\r
+ PPE_SFFLAGS_22 = 150,\r
+ PPE_SFFLAGS_23 = 151,\r
+ PPE_SFFLAGS_24 = 152,\r
+ PPE_SFFLAGS_25 = 153,\r
+ PPE_SFFLAGS_26 = 154,\r
+ PPE_SFFLAGS_27 = 155,\r
+ PPE_SFFLAGS_28 = 156,\r
+ PPE_SFFLAGS_29 = 157,\r
+ PPE_SFFLAGS_30 = 158,\r
+ PPE_SFFLAGS_31 = 159,\r
+ NB_OF_PPE_FLAGS = 160\r
+} ppe_flag_id_t;\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ Flag types.\r
+ The following defines are used to indicate the type of flag selected in the\r
+ ACE configurator.\r
+ */\r
+/**\r
+ A flag configured as BASIC_THRESHOLD_OVER will be asserted when the value of\r
+ the input channel exceeds the value of the flag threshold. The flag will be\r
+ de-asserted once the value of the input channel falls back under the threshold\r
+ value. No hysteresis or state filtering is applied to the flag.\r
+ */\r
+#define BASIC_THRESHOLD_OVER 0u\r
+\r
+/**\r
+ A flag configured as BASIC_THRESHOLD_UNDER will be asserted when the value of\r
+ the input channel falls under the value of the flag threshold. The flag will be\r
+ de-asserted once the value of the input channel exceeds the threshold value.\r
+ No hysteresis or state filtering is applied to the flag.\r
+ */\r
+#define BASIC_THRESHOLD_UNDER 1u\r
+\r
+/**\r
+ A flag configured as STATE_FILTERED_OVER will be asserted when n consecutive\r
+ samples of the analog input are seen to exceed the value of the flag threshold,\r
+ where n is the number selected in the "assert samples" option of the ACE\r
+ configuration softwaretool flag's configuration.\r
+ The flag will be de-asserted once m consecutive samples as seen below the flag\r
+ threshold value, where m is the number selected in the "deassert samples"\r
+ option of the flag's configuration user interface.\r
+ */\r
+#define STATE_FILTERED_OVER 2u\r
+\r
+/**\r
+ A flag configured as STATE_FILTERED_UNDER will be asserted when n consecutive\r
+ samples of the analog input are seen below the value of the flag threshold,\r
+ where n is the number selected in the "assert samples" option of the ACE\r
+ configuration softwaretool flag's configuration.\r
+ The flag will be de-asserted once m consecutive samples as seen to exceed the\r
+ flag threshold value, where m is the number selected in the "deassert samples"\r
+ option of the flag's configuration user interface.\r
+ */\r
+#define STATE_FILTERED_UNDER 3u\r
+\r
+/**\r
+ A flag configured as DUAL_HYSTERESIS_OVER will be asserted when the value\r
+ of the input channel exceeds the threshold value plus the hysteresis value.\r
+ The flag will be deasserted when the value of the input channel falls under the\r
+ threshold value minus the hysteresis value.\r
+ */\r
+#define DUAL_HYSTERESIS_OVER 4u\r
+\r
+/**\r
+ A flag configured as DUAL_HYSTERESIS_UNDER will be asserted when the value\r
+ of the input channel falls under the threshold value minus the hysteresis value.\r
+ The flag will be deasserted when the value of the input channel exceeds the\r
+ threshold value plus the hysteresis value.\r
+ */\r
+#define DUAL_HYSTERESIS_UNDER 5u\r
+\r
+/**\r
+ A flag configured as IPMI_HYSTERESIS_OVER will be asserted when the value\r
+ of the input channel exceeds the threshold value. The flag will be deasserted\r
+ when the value of the input channel falls under the threshold value minus the\r
+ hysteresis value.\r
+ */\r
+#define IPMI_HYSTERESIS_OVER 6u\r
+\r
+/**\r
+ A flag configured as IPMI_HYSTERESIS_UNDER will be asserted when the value\r
+ of the input channel falls under the threshold value. The flag will be\r
+ deasserted when the value of the input channel exceeds the threshold value\r
+ plus the hysteresis value.\r
+ */\r
+#define IPMI_HYSTERESIS_UNDER 7u\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ State filtered flag configuration.\r
+ */\r
+typedef struct __state_filtering_cfg\r
+{\r
+ /**\r
+ Number of consecutive samples required for flag assertion.\r
+ */\r
+ uint8_t assert_samples;\r
+ \r
+ /**\r
+ Number of consecutive samples required for flag deassertion.\r
+ */\r
+ uint8_t deassert_samples;\r
+} state_filtering_cfg_t;\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ Post Processing Engine generated flag descriptor.\r
+ */\r
+typedef struct\r
+{\r
+ /**\r
+ Pointer to a zero-terminated string identifying the flag described by this\r
+ structure. This unique flag name is the name selected in the ACE configurator\r
+ software tool when creating a flag.\r
+ The flag unique name contains both the name of the monitored input channel\r
+ and the name of the flag generated based the level of that input separated\r
+ by ":". For example, the unique name for the flag called "CriticalOver"\r
+ raised when the input channel called "MainSupply" reaches a critical level\r
+ would be named "MainSupply:CriticalOver".\r
+ */\r
+ const uint8_t * p_sz_flag_name;\r
+ \r
+ /**\r
+ The flag_id element identifies which PPE hardware flag will be asserted\r
+ when the flag conditions are found to be met by the Post Processing Engine.\r
+ This flag_id is typically used by the ACE driver to determine which ACE\r
+ register is used to enable, disable and clear interrupts on the associated\r
+ flag.\r
+ */\r
+ ppe_flag_id_t flag_id;\r
+ \r
+ /**\r
+ The flag_type element specifies the type of the described flag. It is\r
+ specified using one of the following:\r
+ - BASIC_THRESHOLD_OVER\r
+ - BASIC_THRESHOLD_UNDER\r
+ - STATE_FILTERED_OVER\r
+ - STATE_FILTERED_UNDER\r
+ - DUAL_HYSTERESIS_OVER\r
+ - DUAL_HYSTERESIS_UNDER\r
+ - IPMI_HYSTERESIS_OVER\r
+ - IPMI_HYSTERESIS_UNDER\r
+ */\r
+ uint8_t flag_type;\r
+ \r
+ /**\r
+ PPE RAM offset of flag threshold level.\r
+ This is the 32-bit word offset within the Post Processing Engine RAM where\r
+ the threshold associated with this flag is stored. This is used to allow\r
+ the ACE driver dynamically modifying the threshold beyond which a flag is\r
+ asserted.\r
+ In the case of hysteresis flags, threshold_ppe_offset indicates the\r
+ start location of two consecutive PPE RAM words containing the ADC value\r
+ of the hysteresis low limit followed by the ADC value for the high\r
+ hysteresis limit.\r
+ */\r
+ uint16_t threshold_ppe_offset;\r
+\r
+ /**\r
+ The default_threshold element specifies the value of the flag's threshold\r
+ selected in the ACE Configurator. It is the ADC value for which the flag\r
+ would be raised if hysteresis was not applied.\r
+ */\r
+ uint16_t default_threshold;\r
+ \r
+ /**\r
+ The flag_properties takes a different meaning depending whether the flag is\r
+ an hysteresis flag or a state filtered flag.\r
+ \r
+ Hysteresis flags:\r
+ The flag_properties element specifies the ADC value to be applied as\r
+ hysteresis to the threshold value that was selected in the ACE Configurator.\r
+ A non-zero value indicates that an hysteresis must be applied and that\r
+ threshold_ppe_offset refers to the first of the two ADC values defining\r
+ the hysteresis applied to the input signal.\r
+ \r
+ State filtered flags:\r
+ The flag_properties element specifies the number of consecutive samples that\r
+ must be over or under the threshold value for the flag state to change.\r
+ */\r
+ uint16_t flag_properties;\r
+ \r
+ /**\r
+ The channel_handle element specifies the monitored analog input channel.\r
+ It can be used as parameter to a call to function ACE_get_ppe_sample() in\r
+ order to read the current value of the analog input channel which caused\r
+ the flag described by this structure to be raised.\r
+ */\r
+ ace_channel_handle_t channel_handle;\r
+ \r
+} ppe_flag_desc_t;\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ace_procedure_desc_t structure is used as a procedure descriptor. It\r
+ contains all information required by the ACE driver to use and manage an ACE\r
+ procedure that was created using the ACE Configurator software tool.\r
+ */\r
+typedef struct\r
+{\r
+ /**\r
+ Pointer to a zero-terminated string identifying an ACE procedure.\r
+ This procedure name is the one selected when created procedures using the\r
+ ACE Configurator software tool.\r
+ */\r
+ const uint8_t * p_sz_proc_name;\r
+ \r
+ /**\r
+ Sample Sequencing Engine procedure loop start program counter value.\r
+ */\r
+ uint16_t sse_loop_pc;\r
+ \r
+ /**\r
+ Sample Sequencing Engine microcode offset.\r
+ This is the 16-bit instruction offset from which the SSE microcode for the\r
+ procedure must be loaded at into the ACE SSE RAM.\r
+ This is also the value that must be writtent into one of the ACE's SSE program\r
+ counter registers in order to start the procedure after having loaded its\r
+ microcode into SSE RAM. The actual program counter register written depends\r
+ on the analog module used by the procedure. It is determined by the value\r
+ of this structure's sse_pc_id element.\r
+ */\r
+ uint16_t sse_load_offset;\r
+ \r
+ /**\r
+ Sample Sequencing Engine microcode length.\r
+ This is the number of 16-bit SSE instructions that must be loaded into\r
+ SSE RAM in order to load the procedure into the ACE.\r
+ */\r
+ uint16_t sse_ucode_length;\r
+ \r
+ /**\r
+ Pointer to ucode.\r
+ */\r
+ const uint16_t * sse_ucode;\r
+ \r
+ /**\r
+ SSE program counter ID.\r
+ This value identifies whether the procedure is used to control analog\r
+ module 0, 1 or 2. It is used to know which SSE program counter should\r
+ be set when starting the procedure.\r
+ */\r
+ uint8_t sse_pc_id;\r
+} ace_procedure_desc_t;\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ace_channel_desc_t structure is used as an analog input channel\r
+ descriptor. It contains the name of a channel as selected in the ACE\r
+ Configurator software tool and the identifier used to identify the ADC channel\r
+ to which the analog input signal is connected.\r
+ */\r
+typedef struct\r
+{\r
+ /**\r
+ Analog input signal name as selected in the ACE Configurator software tool.\r
+ */\r
+ const uint8_t * p_sz_channel_name;\r
+ \r
+ /**\r
+ Analog block input channel connected to the input signal.\r
+ */\r
+ adc_channel_id_t signal_id;\r
+ \r
+ /**\r
+ Offset into Post Processing Engine RAM where the result of post processing\r
+ on sample for the signal will be stored.\r
+ */\r
+ uint16_t signal_ppe_offset;\r
+ \r
+ /**\r
+ Number of PPE generated flags associated with the analog input channel\r
+ described by this structure. The nb_of_flags specifies the number of items\r
+ found in the p_flags_array array.\r
+ */\r
+ uint16_t nb_of_flags;\r
+ \r
+ /**\r
+ The p_flags_array element is a pointer to an array of indexes into the\r
+ g_ppe_flags_desc_table flag descriptors table. The array it points to\r
+ lists the flags generated base don the value of the analog input channel\r
+ described by this structure.\r
+ */\r
+ const uint16_t * p_flags_array;\r
+ \r
+} ace_channel_desc_t;\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ struct ace_config_desc_t\r
+ The ace_config_descr_t structure is used to provide information about the\r
+ configuration of the ACE and analog block. A single instance of this structure\r
+ is intended to be used to inform the ACE driver of the ACE configuration\r
+ seleted using the ACE Configurator software tool and programmed into the ACE\r
+ hardware at system boot time.\r
+ */\r
+typedef struct\r
+{\r
+ /*--------------------------------------------------------------------------\r
+ * Procedures information\r
+ */\r
+ /**\r
+ Procedure descriptors table location.\r
+ This is a pointer to an array of procedure descriptors.\r
+ @see nb_of_procedures\r
+ */\r
+ ace_procedure_desc_t * proc_descr_table;\r
+ \r
+ /**\r
+ Total number of available procedures. This indicates the number of elements\r
+ of the procedure descriptor array.\r
+ @see proc_descr_table\r
+ */\r
+ uint16_t nb_of_procedures;\r
+ \r
+ /**\r
+ Number of procedures loaded into the ACE hardware at system boot time.\r
+ @see boot_loaded_proc_idx_list\r
+ */\r
+ uint16_t nb_boot_loaded_proc;\r
+ /**\r
+ Pointer to list of procedures loaded into the ACE hardware at system boot\r
+ time. That list contains the indexes into the procedure descriptors array\r
+ of the procedures loaded into the ACE hardware.\r
+ @see nb_boot_loaded_proc\r
+ */\r
+ uint16_t * boot_loaded_proc_idx_list;\r
+ \r
+ /*--------------------------------------------------------------------------\r
+ * Analog to Digital Converter signals\r
+ */\r
+ /**\r
+ Total number of configured analog input signals.\r
+ This is the number of analog input signals that were added to the ACE\r
+ configuration using the ACE Configurator software tool. It is also the\r
+ number of elements in the signal descriptor table pointed to by this\r
+ structure's signals_descr_table field.\r
+ @see signals_descr_table\r
+ */\r
+ uint16_t nb_of_signals;\r
+ \r
+ /**\r
+ Signal descriptors table location.\r
+ This is a pointer to an array of signal descriptors describing every\r
+ configured analog input signals.\r
+ @see nb_of_signals\r
+ */\r
+ ace_channel_desc_t * signals_descr_table;\r
+ \r
+ /*--------------------------------------------------------------------------\r
+ * One Bit DACs\r
+ */\r
+ /**\r
+ One Bit DAC (OBD) names as specified in ACE configurator software tool.\r
+ This array is indexed on the analog block number. i.e. sz_obd_names[0]\r
+ contains the name used to identify the OBD contained in analog module 0.\r
+ A value of 0 in this array indicates that no name was assigned to the\r
+ associated OBD.\r
+ */\r
+ const uint8_t * sz_obd_names[3];\r
+ \r
+ /*--------------------------------------------------------------------------\r
+ * PPE generated flags\r
+ */\r
+ /**\r
+ Flag descriptors array location.\r
+ This is a pointer to an array of ppe_flag_desc_t structures describing the\r
+ properties of each of the flags generated by the Post Processing Engine.\r
+ The size of that array is specified by the nb_of_flags element of this\r
+ structure.\r
+ */\r
+ ppe_flag_desc_t * flags_descr_table;\r
+\r
+ /**\r
+ Number of flags used in the ACE Configurator generated configuration.\r
+ */\r
+ uint8_t nb_of_flags;\r
+ \r
+ /*--------------------------------------------------------------------------\r
+ * Analog comparators\r
+ */\r
+ /**\r
+ *\r
+ */\r
+} ace_config_desc_t;\r
+\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ace_adc_config_t data structure is used by the ACE configurator to inform\r
+ the ACE driver of an analog to digital converter's configuration.\r
+ */\r
+typedef struct\r
+{\r
+ /**\r
+ ADC resolution. Values can be 256, 1024 or 4096 depending whether the ADC\r
+ is configured for 8, 10 or 12 bits.\r
+ */\r
+ uint16_t adc_resolution;\r
+ \r
+ /**\r
+ VA_REF value in milli-Volts. This should be set to 2560 if internal VAREF\r
+ is used.\r
+ */\r
+ uint16_t va_ref;\r
+ \r
+} ace_adc_config_t;\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The ppe_transforms_desc_t data structure is used by the ACE configurator to\r
+ inform the ACE driver of the location of the "m" factor and "c" offset used\r
+ by the PPE to perform a linear transform of the form y = m*x + c. This linear\r
+ transform is used to apply calibration to the ADC samples. It can also include\r
+ a user defined linear transform specified by the user using the ACE\r
+ configurator. The factor and offset of the user defined transform is included\r
+ in the default_m2 and default_c2 items. \r
+ */\r
+typedef struct\r
+{\r
+ /**\r
+ Offset into Post Processing Engine RAM where the linear transform m factor\r
+ is stored.\r
+ */\r
+ uint16_t m_ppe_offset;\r
+ \r
+ /**\r
+ Offset into Post Processing Engine RAM where the linear transform c offset\r
+ is stored.\r
+ */\r
+ uint16_t c_ppe_offset;\r
+ \r
+ /**\r
+ Default value of the user defined linear transform m2 factor.\r
+ */\r
+ int16_t default_m2;\r
+ \r
+ /**\r
+ Default value of the user defined linear transform c2 offset.\r
+ */\r
+ int16_t default_c2;\r
+} ppe_transforms_desc_t;\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __MSS_ACE_CONFIGURATOR_H_ */\r
--- /dev/null
+/*******************************************************************************\r
+ * (c) Copyright 2008 Actel Corporation. All rights reserved.\r
+ * \r
+ * Manufacturing Test Data data structures.\r
+ * This header files specified the layout of the various data structures used\r
+ * to store manaufacturing test data within eNVM.\r
+ *\r
+ * SVN $Revision: 700 $\r
+ * SVN $Date: 2009-03-13 13:22:03 +0000 (Fri, 13 Mar 2009) $\r
+ */\r
+#ifndef MTD_DATA_H\r
+#define MTD_DATA_H\r
+\r
+#include <stdint.h>\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif \r
+\r
+/*\r
+ * Analog block specifications\r
+ */\r
+#define NB_OF_QUADS 6\r
+#define NB_OF_ABPS_PER_QUAD 2\r
+#define TOTAL_NB_OF_ABPS (NB_OF_QUADS * NB_OF_ABPS_PER_QUAD)\r
+#define NB_OF_ABPS_RANGES 4\r
+#define NB_OF_ANALOG_MODULES 3\r
+#define NB_OF_OBD_MODES 2\r
+#define NB_OF_QUADS_PER_MODULE 2\r
+#define NB_OF_CHOPPING_OPTIONS 2\r
+#define NB_OF_DIRECT_INPUTS_PER_ADC 4\r
+\r
+#define NB_OF_ADC_CHANNELS 13\r
+\r
+/*------------------------------------------------------------------------------\r
+ * mtd_global_settings_t\r
+ *------------------------------------------------------------------------------\r
+ * This typedef specifies the layout of the data structure holding the \r
+ * manufacturing test data global settings.\r
+ */\r
+typedef struct __mtd_global_settings_t\r
+{\r
+ uint16_t crc16;\r
+ uint8_t serial[6];\r
+ uint32_t revision;\r
+ uint16_t sram_repair[8];\r
+ uint16_t varef_m;\r
+ uint16_t spare;\r
+ uint8_t big_dec;\r
+ uint8_t reserved0;\r
+ uint16_t reserved1;\r
+} mtd_global_settings_t;\r
+\r
+/*------------------------------------------------------------------------------\r
+ * mtd_abps_trim_t\r
+ *------------------------------------------------------------------------------\r
+ * The following data structure is used to store ABPS trimming information.\r
+ */\r
+typedef struct __mtd_abps_trim_t\r
+{\r
+ uint8_t dacdec;\r
+ uint8_t negtrim_per4_per3b_gtdec;\r
+} mtd_abps_trim_t;\r
+\r
+\r
+/*------------------------------------------------------------------------------\r
+ * mtd_calibration_mc_t\r
+ *------------------------------------------------------------------------------\r
+ * The following data structure is used to store M and C calibration\r
+ * coefficients.\r
+ */\r
+typedef struct __mtd_calibration_mc_t\r
+{\r
+ uint16_t m;\r
+ uint16_t c;\r
+} mtd_calibration_mc_t;\r
+\r
+\r
+/*------------------------------------------------------------------------------\r
+ * mtd_data_t\r
+ *------------------------------------------------------------------------------\r
+ * The following data structure is used to hold the full set of manufacturing\r
+ * test data.\r
+ */\r
+typedef struct __mtd_data_t\r
+{\r
+ mtd_global_settings_t global_settings;\r
+ mtd_abps_trim_t abps_trimming[NB_OF_QUADS][NB_OF_ABPS_PER_QUAD][NB_OF_ABPS_RANGES];\r
+ uint8_t odb_trimming[NB_OF_ANALOG_MODULES][NB_OF_OBD_MODES][NB_OF_CHOPPING_OPTIONS];\r
+ mtd_calibration_mc_t abps_calibration[NB_OF_QUADS][NB_OF_ABPS_PER_QUAD][NB_OF_ABPS_RANGES];\r
+ mtd_calibration_mc_t obd_calibration[NB_OF_ANALOG_MODULES][NB_OF_OBD_MODES][NB_OF_CHOPPING_OPTIONS];\r
+ mtd_calibration_mc_t cm_calibration[NB_OF_QUADS];\r
+ mtd_calibration_mc_t tm_calibration[NB_OF_QUADS];\r
+ mtd_calibration_mc_t quads_direct_input_cal[NB_OF_QUADS][2];\r
+ mtd_calibration_mc_t adc_direct_input_cal[NB_OF_ANALOG_MODULES][NB_OF_DIRECT_INPUTS_PER_ADC];\r
+ uint16_t comparators_offsets[NB_OF_QUADS];\r
+ uint32_t ccc_delays_cal;\r
+} mtd_data_t;\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif\r
--- /dev/null
+/***************************************************************************//**\r
+ * @file\r
+ * crc32 source file.\r
+ * \r
+ * CRC-32-IEEE 802.3 \r
+ * x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + \r
+ * x^4 + x^2 + x + 1\r
+ *\r
+ * (c) Copyright 2007 Actel Corporation\r
+ *\r
+ * SVN $Revision: 2369 $\r
+ * SVN $Date: 2010-03-01 18:31:45 +0000 (Mon, 01 Mar 2010) $\r
+ ******************************************************************************/\r
+\r
+ #ifdef __cplusplus\r
+extern "C" {\r
+#endif \r
+\r
+#include "crc32.h"\r
+\r
+static const uint32_t crc32_table[] = {\r
+ 0x00000000UL, 0x77073096UL, 0xee0e612cUL, 0x990951baUL, 0x076dc419UL, 0x706af48fUL,\r
+ 0xe963a535UL, 0x9e6495a3UL, 0x0edb8832UL, 0x79dcb8a4UL, 0xe0d5e91eUL, 0x97d2d988UL,\r
+ 0x09b64c2bUL, 0x7eb17cbdUL, 0xe7b82d07UL, 0x90bf1d91UL, 0x1db71064UL, 0x6ab020f2UL,\r
+ 0xf3b97148UL, 0x84be41deUL, 0x1adad47dUL, 0x6ddde4ebUL, 0xf4d4b551UL, 0x83d385c7UL,\r
+ 0x136c9856UL, 0x646ba8c0UL, 0xfd62f97aUL, 0x8a65c9ecUL, 0x14015c4fUL, 0x63066cd9UL,\r
+ 0xfa0f3d63UL, 0x8d080df5UL, 0x3b6e20c8UL, 0x4c69105eUL, 0xd56041e4UL, 0xa2677172UL,\r
+ 0x3c03e4d1UL, 0x4b04d447UL, 0xd20d85fdUL, 0xa50ab56bUL, 0x35b5a8faUL, 0x42b2986cUL,\r
+ 0xdbbbc9d6UL, 0xacbcf940UL, 0x32d86ce3UL, 0x45df5c75UL, 0xdcd60dcfUL, 0xabd13d59UL,\r
+ 0x26d930acUL, 0x51de003aUL, 0xc8d75180UL, 0xbfd06116UL, 0x21b4f4b5UL, 0x56b3c423UL,\r
+ 0xcfba9599UL, 0xb8bda50fUL, 0x2802b89eUL, 0x5f058808UL, 0xc60cd9b2UL, 0xb10be924UL,\r
+ 0x2f6f7c87UL, 0x58684c11UL, 0xc1611dabUL, 0xb6662d3dUL, 0x76dc4190UL, 0x01db7106UL,\r
+ 0x98d220bcUL, 0xefd5102aUL, 0x71b18589UL, 0x06b6b51fUL, 0x9fbfe4a5UL, 0xe8b8d433UL,\r
+ 0x7807c9a2UL, 0x0f00f934UL, 0x9609a88eUL, 0xe10e9818UL, 0x7f6a0dbbUL, 0x086d3d2dUL,\r
+ 0x91646c97UL, 0xe6635c01UL, 0x6b6b51f4UL, 0x1c6c6162UL, 0x856530d8UL, 0xf262004eUL,\r
+ 0x6c0695edUL, 0x1b01a57bUL, 0x8208f4c1UL, 0xf50fc457UL, 0x65b0d9c6UL, 0x12b7e950UL,\r
+ 0x8bbeb8eaUL, 0xfcb9887cUL, 0x62dd1ddfUL, 0x15da2d49UL, 0x8cd37cf3UL, 0xfbd44c65UL,\r
+ 0x4db26158UL, 0x3ab551ceUL, 0xa3bc0074UL, 0xd4bb30e2UL, 0x4adfa541UL, 0x3dd895d7UL,\r
+ 0xa4d1c46dUL, 0xd3d6f4fbUL, 0x4369e96aUL, 0x346ed9fcUL, 0xad678846UL, 0xda60b8d0UL,\r
+ 0x44042d73UL, 0x33031de5UL, 0xaa0a4c5fUL, 0xdd0d7cc9UL, 0x5005713cUL, 0x270241aaUL,\r
+ 0xbe0b1010UL, 0xc90c2086UL, 0x5768b525UL, 0x206f85b3UL, 0xb966d409UL, 0xce61e49fUL,\r
+ 0x5edef90eUL, 0x29d9c998UL, 0xb0d09822UL, 0xc7d7a8b4UL, 0x59b33d17UL, 0x2eb40d81UL,\r
+ 0xb7bd5c3bUL, 0xc0ba6cadUL, 0xedb88320UL, 0x9abfb3b6UL, 0x03b6e20cUL, 0x74b1d29aUL,\r
+ 0xead54739UL, 0x9dd277afUL, 0x04db2615UL, 0x73dc1683UL, 0xe3630b12UL, 0x94643b84UL,\r
+ 0x0d6d6a3eUL, 0x7a6a5aa8UL, 0xe40ecf0bUL, 0x9309ff9dUL, 0x0a00ae27UL, 0x7d079eb1UL,\r
+ 0xf00f9344UL, 0x8708a3d2UL, 0x1e01f268UL, 0x6906c2feUL, 0xf762575dUL, 0x806567cbUL,\r
+ 0x196c3671UL, 0x6e6b06e7UL, 0xfed41b76UL, 0x89d32be0UL, 0x10da7a5aUL, 0x67dd4accUL,\r
+ 0xf9b9df6fUL, 0x8ebeeff9UL, 0x17b7be43UL, 0x60b08ed5UL, 0xd6d6a3e8UL, 0xa1d1937eUL,\r
+ 0x38d8c2c4UL, 0x4fdff252UL, 0xd1bb67f1UL, 0xa6bc5767UL, 0x3fb506ddUL, 0x48b2364bUL,\r
+ 0xd80d2bdaUL, 0xaf0a1b4cUL, 0x36034af6UL, 0x41047a60UL, 0xdf60efc3UL, 0xa867df55UL,\r
+ 0x316e8eefUL, 0x4669be79UL, 0xcb61b38cUL, 0xbc66831aUL, 0x256fd2a0UL, 0x5268e236UL,\r
+ 0xcc0c7795UL, 0xbb0b4703UL, 0x220216b9UL, 0x5505262fUL, 0xc5ba3bbeUL, 0xb2bd0b28UL,\r
+ 0x2bb45a92UL, 0x5cb36a04UL, 0xc2d7ffa7UL, 0xb5d0cf31UL, 0x2cd99e8bUL, 0x5bdeae1dUL,\r
+ 0x9b64c2b0UL, 0xec63f226UL, 0x756aa39cUL, 0x026d930aUL, 0x9c0906a9UL, 0xeb0e363fUL,\r
+ 0x72076785UL, 0x05005713UL, 0x95bf4a82UL, 0xe2b87a14UL, 0x7bb12baeUL, 0x0cb61b38UL,\r
+ 0x92d28e9bUL, 0xe5d5be0dUL, 0x7cdcefb7UL, 0x0bdbdf21UL, 0x86d3d2d4UL, 0xf1d4e242UL,\r
+ 0x68ddb3f8UL, 0x1fda836eUL, 0x81be16cdUL, 0xf6b9265bUL, 0x6fb077e1UL, 0x18b74777UL,\r
+ 0x88085ae6UL, 0xff0f6a70UL, 0x66063bcaUL, 0x11010b5cUL, 0x8f659effUL, 0xf862ae69UL,\r
+ 0x616bffd3UL, 0x166ccf45UL, 0xa00ae278UL, 0xd70dd2eeUL, 0x4e048354UL, 0x3903b3c2UL,\r
+ 0xa7672661UL, 0xd06016f7UL, 0x4969474dUL, 0x3e6e77dbUL, 0xaed16a4aUL, 0xd9d65adcUL,\r
+ 0x40df0b66UL, 0x37d83bf0UL, 0xa9bcae53UL, 0xdebb9ec5UL, 0x47b2cf7fUL, 0x30b5ffe9UL,\r
+ 0xbdbdf21cUL, 0xcabac28aUL, 0x53b39330UL, 0x24b4a3a6UL, 0xbad03605UL, 0xcdd70693UL,\r
+ 0x54de5729UL, 0x23d967bfUL, 0xb3667a2eUL, 0xc4614ab8UL, 0x5d681b02UL, 0x2a6f2b94UL,\r
+ 0xb40bbe37UL, 0xc30c8ea1UL, 0x5a05df1bUL, 0x2d02ef8dUL\r
+};\r
+\r
+/**\r
+ * Calculates 32 bits CRC value of given data.\r
+ */\r
+uint32_t\r
+mss_mac_crc32\r
+(\r
+ uint32_t value,\r
+ const uint8_t *data,\r
+ uint32_t data_length\r
+)\r
+{\r
+ uint32_t a;\r
+ \r
+ for(a=0; a<data_length; a++) {\r
+ value = crc32_table[(value ^ data[a]) & 0xff] ^ (value >> 8);\r
+ }\r
+ \r
+ return value;\r
+}\r
+\r
+/**\r
+ * Calculates 32 bits CRC value of given data, using standart Ethernet CRC \r
+ * function.\r
+ */\r
+uint32_t\r
+mss_ethernet_crc\r
+(\r
+ const uint8_t *data,\r
+ uint32_t data_length\r
+)\r
+{\r
+ return mss_mac_crc32( 0xffffffffUL, data, data_length );\r
+}\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
--- /dev/null
+/***************************************************************************//**\r
+ * @file\r
+ * crc32 header file.\r
+ *\r
+ * (c) Copyright 2007 Actel Corporation\r
+ *\r
+ * SVN $Revision: 2369 $\r
+ * SVN $Date: 2010-03-01 18:31:45 +0000 (Mon, 01 Mar 2010) $\r
+ ******************************************************************************/\r
+ \r
+#ifndef __MSS_ETHERNET_MAC_CRC32_H\r
+#define __MSS_ETHERNET_MAC_CRC32_H 1\r
+\r
+#include <stdint.h>\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif \r
+\r
+/**\r
+ * Calculates 32 bits CRC value of given data.\r
+ */\r
+uint32_t\r
+mss_mac_crc32\r
+(\r
+ uint32_t value,\r
+ const uint8_t *data,\r
+ uint32_t data_length\r
+);\r
+\r
+/**\r
+ * Calculates 32 bits CRC value of given data, using standart Ethernet CRC \r
+ * function.\r
+ */\r
+uint32_t\r
+mss_ethernet_crc\r
+(\r
+ const uint8_t *data,\r
+ uint32_t data_length\r
+);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __MSS_ETHERNET_MAC_CRC32_H */\r
--- /dev/null
+/***************************************************************************//**\r
+ * @file\r
+ * SmartFusion MSS Ethernet MAC driver implementation.\r
+ *\r
+ * (c) Copyright 2007 Actel Corporation\r
+ *\r
+ * SVN $Revision: 2369 $\r
+ * SVN $Date: 2010-03-01 18:31:45 +0000 (Mon, 01 Mar 2010) $\r
+ *\r
+ ******************************************************************************/\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif \r
+\r
+\r
+#include "crc32.h"\r
+\r
+#include "mss_ethernet_mac.h"\r
+#include "mss_ethernet_mac_regs.h"\r
+#include "mss_ethernet_mac_desc.h"\r
+#include "mss_ethernet_mac_conf.h"\r
+#include "../../CMSIS/mss_assert.h"\r
+\r
+#include "phy.h"\r
+\r
+/**************************** INTERNAL DEFINES ********************************/\r
+\r
+#define MAC_CHECK(CHECK,ERRNO) \\r
+ {if(!(CHECK)){g_mss_mac.last_error=(ERRNO); ASSERT((CHECK));}}\r
+\r
+/*\r
+ * Flags\r
+ */\r
+#define FLAG_MAC_INIT_DONE 1u\r
+#define FLAG_PERFECT_FILTERING 2u\r
+#define FLAG_CRC_DISABLE 4u\r
+#define FLAG_EXCEED_LIMIT 8u\r
+\r
+/*\r
+ * Return types\r
+ */\r
+#define MAC_OK 0\r
+#define MAC_FAIL (-1)\r
+#define MAC_WRONG_PARAMETER (-2)\r
+#define MAC_TOO_BIG_PACKET (-3)\r
+#define MAC_BUFFER_IS_FULL (-4)\r
+#define MAC_NOT_ENOUGH_SPACE (-5)\r
+#define MAC_TIME_OUT (-6)\r
+#define MAC_TOO_SMALL_PACKET (-7)\r
+\r
+/***************************************************************/\r
+MAC_instance_t g_mss_mac;\r
+\r
+/**************************** INTERNAL DATA ***********************************/\r
+#define ERROR_MESSAGE_COUNT 8\r
+#define MAX_ERROR_MESSAGE_WIDTH 40\r
+static const int8_t unknown_error[] = "Unknown error";\r
+static const int8_t ErrorMessages[][MAX_ERROR_MESSAGE_WIDTH] = {\r
+ "No error occured",\r
+ "Method failed",\r
+ "Wrong parameter pased to function",\r
+ "Frame is too long",\r
+ "Not enough space in buffer",\r
+ "Not enough space in buffer",\r
+ "Timed out",\r
+ "Frame is too small"\r
+};\r
+\r
+/*\r
+ * Null variables\r
+ */\r
+static MAC_instance_t* NULL_instance;\r
+static uint8_t* NULL_buffer;\r
+static MSS_MAC_callback_t NULL_callback;\r
+\r
+/**************************** INTERNAL FUNCTIONS ******************************/\r
+\r
+static int32_t MAC_test_instance( void );\r
+\r
+static int32_t MAC_dismiss_bad_frames( void );\r
+static int32_t MAC_send_setup_frame( void );\r
+\r
+static int32_t MAC_stop_transmission( void );\r
+static void MAC_start_transmission( void );\r
+static int32_t MAC_stop_receiving( void );\r
+static void MAC_start_receiving( void );\r
+\r
+static void MAC_set_time_out( uint32_t time_out );\r
+static uint32_t MAC_get_time_out( void );\r
+\r
+static void MAC_memset(uint8_t *s, uint8_t c, uint32_t n);\r
+static void MAC_memcpy(uint8_t *dest, const uint8_t *src, uint32_t n);\r
+static void MAC_memset_All(MAC_instance_t *s, uint32_t c);\r
+\r
+/***************************************************************************//**\r
+ * Initializes the Ethernet Controller.\r
+ * This function will prepare the Ethernet Controller for first time use in a\r
+ * given hardware/software configuration. This function should be called before\r
+ * any other Ethernet API functions are called.\r
+ *\r
+ * Initialization of registers - config registers, enable Tx/Rx interrupts,\r
+ * enable Tx/Rx, initialize MAC addr, init PHY, autonegotiation, MAC address\r
+ * filter table (unicats/multicast)/hash init\r
+ */\r
+void\r
+MSS_MAC_init\r
+(\r
+ uint8_t phy_address\r
+)\r
+{\r
+ const uint8_t mac_address[6] = { DEFAULT_MAC_ADDRESS };\r
+\r
+ int32_t a;\r
+\r
+ /* Try to reset chip */\r
+ MAC_BITBAND->CSR0_SWR = 1u;\r
+ \r
+ while ( 1u == MAC_BITBAND->CSR0_SWR )\r
+ {\r
+ ;\r
+ }\r
+\r
+ /* Check reset values of some registers to constrol\r
+ * base address validity */\r
+ ASSERT( MAC->CSR0 == 0xFE000000uL );\r
+ ASSERT( MAC->CSR5 == 0xF0000000uL );\r
+ ASSERT( MAC->CSR6 == 0x32000040uL );\r
+\r
+ /* Instance setup */\r
+ MAC_memset_All( &g_mss_mac, 0u );\r
+\r
+ g_mss_mac.base_address = MAC_BASE;\r
+ g_mss_mac.phy_address = phy_address;\r
+\r
+ for( a=0; a<RX_RING_SIZE; a++ )\r
+ {\r
+ /* Give the ownership to the MAC */\r
+ g_mss_mac.rx_descriptors[a].descriptor_0 = RDES0_OWN;\r
+ g_mss_mac.rx_descriptors[a].descriptor_1 = (MSS_RX_BUFF_SIZE << RDES1_RBS1_OFFSET);\r
+ g_mss_mac.rx_descriptors[a].buffer_1 = (uint32_t)g_mss_mac.rx_buffers[a];\r
+ }\r
+ g_mss_mac.rx_descriptors[RX_RING_SIZE-1].descriptor_1 |= RDES1_RER;\r
+\r
+ for( a = 0; a < TX_RING_SIZE; a++ )\r
+ {\r
+ g_mss_mac.tx_descriptors[a].buffer_1 = (uint32_t)g_mss_mac.tx_buffers[a];\r
+ }\r
+ g_mss_mac.tx_descriptors[TX_RING_SIZE - 1].descriptor_1 |= TDES1_TER;\r
+\r
+ /* Configurable settings */\r
+ MAC_BITBAND->CSR0_DBO = DESCRIPTOR_BYTE_ORDERING_MODE;\r
+ MAC->CSR0 = (MAC->CSR0 & ~CSR0_PBL_MASK) | ((uint32_t)PROGRAMMABLE_BURST_LENGTH << CSR0_PBL_SHIFT);\r
+ MAC_BITBAND->CSR0_BLE = BUFFER_BYTE_ORDERING_MODE;\r
+ MAC_BITBAND->CSR0_BAR = (uint32_t)BUS_ARBITRATION_SCHEME;\r
+\r
+ /* Fixed settings */\r
+ /* No automatic polling */\r
+ MAC->CSR0 = MAC->CSR0 &~ CSR0_TAP_MASK;\r
+ /* No space between descriptors */\r
+ MAC->CSR0 = MAC->CSR0 &~ CSR0_DSL_MASK;\r
+ /* General-purpose timer works in continuous mode */\r
+ MAC_BITBAND->CSR11_CON = 1u;\r
+ /* Start general-purpose */\r
+ MAC->CSR11 = (MAC->CSR11 & ~CSR11_TIM_MASK) | (0x0000FFFFuL << CSR11_TIM_SHIFT);\r
+\r
+ /* Disable promiscuous mode */\r
+ MAC_BITBAND->CSR6_PR = 0u;\r
+\r
+ /* Enable store and forward */\r
+ MAC_BITBAND->CSR6_SF = 1u;\r
+\r
+ /* Set descriptors */\r
+ MAC->CSR3 = (uint32_t)&(g_mss_mac.rx_descriptors[0].descriptor_0);\r
+ MAC->CSR4 = (uint32_t)&(g_mss_mac.tx_descriptors[0].descriptor_0);\r
+ \r
+ /* enable normal interrupts */\r
+ MAC_BITBAND->CSR7_NIE = 1u;\r
+\r
+ /* Detect PHY */\r
+ if( g_mss_mac.phy_address > MSS_PHY_ADDRESS_MAX )\r
+ {\r
+ PHY_probe();\r
+ ASSERT( g_mss_mac.phy_address <= MSS_PHY_ADDRESS_MAX );\r
+ }\r
+\r
+ /* Reset PHY */\r
+ PHY_reset();\r
+\r
+ /* Set flags */\r
+ g_mss_mac.flags = FLAG_MAC_INIT_DONE | FLAG_PERFECT_FILTERING;\r
+\r
+ /* Configure chip according to PHY status */\r
+ MSS_MAC_auto_setup_link();\r
+\r
+ /* Set default MAC address and reset mac filters */\r
+ MAC_memcpy( g_mss_mac.mac_address, mac_address, 6u );\r
+ MSS_MAC_set_mac_filters( 0u, NULL_buffer );\r
+\r
+\r
+ /* Start receiving and transmission */\r
+ MAC_start_receiving();\r
+ MAC_start_transmission();\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * Sets the configuration of the Ethernet Controller.\r
+ * After the EthernetInit function has been called, this API function can be\r
+ * used to configure the various features of the Ethernet Controller.\r
+ *\r
+ * @param instance Pointer to a MAC_instance_t structure\r
+ * @param config The logical OR of the following values:\r
+ * - #MSS_MAC_CFG_RECEIVE_ALL\r
+ * - #MSS_MAC_CFG_TRANSMIT_THRESHOLD_MODE\r
+ * - #MSS_MSS_MAC_CFG_STORE_AND_FORWARD\r
+ * - #MAC_CFG_THRESHOLD_CONTROL_[00,01,10,11]\r
+ * - #MSS_MAC_CFG_FULL_DUPLEX_MODE\r
+ * - #MSS_MAC_CFG_PASS_ALL_MULTICAST\r
+ * - #MSS_MAC_CFG_PROMISCUOUS_MODE\r
+ * - #MSS_MAC_CFG_PASS_BAD_FRAMES\r
+ * @see MAC_get_configuration()\r
+ */\r
+void\r
+MSS_MAC_configure\r
+(\r
+ uint32_t configuration\r
+)\r
+{\r
+ int32_t ret;\r
+\r
+ ASSERT( MAC_test_instance() == MAC_OK );\r
+\r
+ ret = MAC_stop_transmission();\r
+ ASSERT( ret == MAC_OK );\r
+\r
+ ret = MAC_stop_receiving();\r
+ ASSERT( ret == MAC_OK );\r
+\r
+ MAC_BITBAND->CSR6_RA = (uint32_t)(((configuration & MSS_MAC_CFG_RECEIVE_ALL) != 0u) ? 1u : 0u );\r
+ MAC_BITBAND->CSR6_TTM = (((configuration & MSS_MAC_CFG_TRANSMIT_THRESHOLD_MODE) != 0u) ? 1u : 0u );\r
+ MAC_BITBAND->CSR6_SF = (uint32_t)(((configuration & MSS_MAC_CFG_STORE_AND_FORWARD) != 0u) ? 1u : 0u );\r
+ \r
+ switch( configuration & MSS_MAC_CFG_THRESHOLD_CONTROL_11 ) {\r
+ case MSS_MAC_CFG_THRESHOLD_CONTROL_00:\r
+ MAC->CSR6 = MAC->CSR6 & ~CSR6_TR_MASK;\r
+ break;\r
+ case MSS_MAC_CFG_THRESHOLD_CONTROL_01:\r
+ MAC->CSR6 = (MAC->CSR6 & ~CSR6_TR_MASK) | ((uint32_t)1 << CSR6_TR_SHIFT );\r
+ break;\r
+ case MSS_MAC_CFG_THRESHOLD_CONTROL_10:\r
+ MAC->CSR6 = (MAC->CSR6 & ~CSR6_TR_MASK) | ((uint32_t)2 << CSR6_TR_SHIFT );\r
+ break;\r
+ case MSS_MAC_CFG_THRESHOLD_CONTROL_11:\r
+ MAC->CSR6 = (MAC->CSR6 & ~CSR6_TR_MASK) | ((uint32_t)3 << CSR6_TR_SHIFT );\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+ MAC_BITBAND->CSR6_FD = (uint32_t)(((configuration & MSS_MAC_CFG_FULL_DUPLEX_MODE) != 0u) ? 1u : 0u );\r
+ MAC_BITBAND->CSR6_PM = (uint32_t)(((configuration & MSS_MAC_CFG_PASS_ALL_MULTICAST) != 0u) ? 1u : 0u );\r
+ MAC_BITBAND->CSR6_PR = (uint32_t)(((configuration & MSS_MAC_CFG_PROMISCUOUS_MODE) != 0u) ? 1u : 0u );\r
+ MAC_BITBAND->CSR6_PB = (uint32_t)(((configuration & MSS_MAC_CFG_PASS_BAD_FRAMES) != 0u) ? 1u : 0u );\r
+ PHY_set_link_type( (uint8_t)\r
+ ((((configuration & MSS_MAC_CFG_TRANSMIT_THRESHOLD_MODE) != 0u) ? MSS_MAC_LINK_STATUS_100MB : 0u ) |\r
+ (((configuration & MSS_MAC_CFG_FULL_DUPLEX_MODE) != 0u) ? MSS_MAC_LINK_STATUS_FDX : 0u )) );\r
+\r
+ MAC_start_transmission();\r
+ MAC_start_receiving();\r
+\r
+ MSS_MAC_auto_setup_link();\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * Returns the configuration of the Ethernet Controller.\r
+ *\r
+ * @param instance Pointer to a MAC_instance_t structure\r
+ * @return The logical OR of the following values:\r
+ * - #MSS_MAC_CFG_RECEIVE_ALL\r
+ * - #MSS_MAC_CFG_TRANSMIT_THRESHOLD_MODE\r
+ * - #MSS_MAC_CFG_STORE_AND_FORWARD\r
+ * - #MAC_CFG_THRESHOLD_CONTROL_[00,01,10,11]\r
+ * - #MSS_MAC_CFG_FULL_DUPLEX_MODE\r
+ * - #MSS_MAC_CFG_PASS_ALL_MULTICAST\r
+ * - #MSS_MAC_CFG_PROMISCUOUS_MODE\r
+ * - #MSS_MAC_CFG_INVERSE_FILTERING\r
+ * - #MSS_MAC_CFG_PASS_BAD_FRAMES\r
+ * - #MSS_MAC_CFG_HASH_ONLY_FILTERING_MODE\r
+ * - #MSS_MAC_CFG_HASH_PERFECT_RECEIVE_FILTERING_MODE\r
+ * @see MAC_configure()\r
+ */\r
+int32_t\r
+MSS_MAC_get_configuration( void )\r
+{\r
+ uint32_t configuration;\r
+\r
+ ASSERT( MAC_test_instance() == MAC_OK );\r
+\r
+ configuration = 0u;\r
+ if( MAC_BITBAND->CSR6_RA != 0u ) {\r
+ configuration |= MSS_MAC_CFG_RECEIVE_ALL;\r
+ }\r
+\r
+ if( MAC_BITBAND->CSR6_TTM != 0u ) {\r
+ configuration |= MSS_MAC_CFG_TRANSMIT_THRESHOLD_MODE;\r
+ }\r
+\r
+ if( MAC_BITBAND->CSR6_SF != 0u ) {\r
+ configuration |= MSS_MAC_CFG_STORE_AND_FORWARD;\r
+ }\r
+\r
+ switch( (MAC->CSR6 & CSR6_TR_MASK) >> CSR6_TR_SHIFT ) {\r
+ case 1: configuration |= MSS_MAC_CFG_THRESHOLD_CONTROL_01; break;\r
+ case 2: configuration |= MSS_MAC_CFG_THRESHOLD_CONTROL_10; break;\r
+ case 3: configuration |= MSS_MAC_CFG_THRESHOLD_CONTROL_11; break;\r
+ default: break;\r
+ }\r
+ if( MAC_BITBAND->CSR6_FD != 0u ) {\r
+ configuration |= MSS_MAC_CFG_FULL_DUPLEX_MODE;\r
+ }\r
+\r
+ if( MAC_BITBAND->CSR6_PM != 0u ) {\r
+ configuration |= MSS_MAC_CFG_PASS_ALL_MULTICAST;\r
+ }\r
+\r
+ if( MAC_BITBAND->CSR6_PR != 0u ) {\r
+ configuration |= MSS_MAC_CFG_PROMISCUOUS_MODE;\r
+ }\r
+\r
+ if( MAC_BITBAND->CSR6_IF != 0u ) {\r
+ configuration |= MSS_MAC_CFG_INVERSE_FILTERING;\r
+ }\r
+\r
+ if( MAC_BITBAND->CSR6_PB != 0u ) {\r
+ configuration |= MSS_MAC_CFG_PASS_BAD_FRAMES;\r
+ }\r
+\r
+ if( MAC_BITBAND->CSR6_HO != 0u ) {\r
+ configuration |= MSS_MAC_CFG_HASH_ONLY_FILTERING_MODE;\r
+ }\r
+\r
+ if( MAC_BITBAND->CSR6_HP != 0u ) {\r
+ configuration |= MSS_MAC_CFG_HASH_PERFECT_RECEIVE_FILTERING_MODE;\r
+ }\r
+ \r
+ return (int32_t)configuration;\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ Sends a packet to the Ethernet Controller.\r
+ The MSS_MAC_tx_packet() function is used to send a packet to the MSS Ethernet\r
+ MAC. This function writes pacLen bytes of the packet contained in pacData into\r
+ the transmit FIFO and then activates the transmitter for this packet. If space\r
+ is available in the FIFO, the function will return once pacLen bytes of the\r
+ packet have been placed into the FIFO and the transmitter has been started.\r
+ This function will not wait for the transmission to complete. If space is not\r
+ available in FIFO, the function will keep trying until time_out expires. The\r
+ function will wait for the transmission to complete when the time_out parameter\r
+ is set to MSS_MAC_BLOCKING.\r
+ \r
+ @param pacData\r
+ The pacData parameter is a pointer to the packet data to be transmitted.\r
+ \r
+ @param pacLen\r
+ The pacLen parameter is the number of bytes in the packet to be transmitted.\r
+ \r
+ @param time_out\r
+ The time_out parameter is the timeout value for the transmission in milliseconds.\r
+ The time_out parameter value can be one of the following values:\r
+ \95 Unsigned integer greater than 0 and less than 0x01000000\r
+ \95 MSS_MAC_BLOCKING \96 there will be no timeout. \r
+ \95 MSS_MAC_NONBLOCKING \96 the function will return immediately if the MSS Ethernet\r
+ MAC does not have any available transmit descriptor. This would happen when\r
+ several packets are already queued into the MSS Ethernet MAC transmit descriptor FIFO.\r
+\r
+ @return\r
+ The function returns zero if a timeout occurs otherwise it returns size of the packet.\r
+ \r
+ @see MAC_rx_packet()\r
+ */\r
+\r
+int32_t\r
+MSS_MAC_tx_packet\r
+(\r
+ const uint8_t *pacData,\r
+ uint16_t pacLen,\r
+ uint32_t time_out\r
+)\r
+{\r
+ uint32_t desc;\r
+ int32_t error = MAC_OK;\r
+\r
+ ASSERT( MAC_test_instance() == MAC_OK );\r
+\r
+ ASSERT( pacData != NULL_buffer );\r
+\r
+ ASSERT( pacLen >= 12 );\r
+\r
+ if( (g_mss_mac.flags & FLAG_EXCEED_LIMIT) == 0u )\r
+ {\r
+ ASSERT( pacLen <= MSS_MAX_PACKET_SIZE );\r
+ }\r
+\r
+ ASSERT( (time_out == MSS_MAC_BLOCKING) ||\r
+ (time_out == MSS_MAC_NONBLOCKING) ||\r
+ ((time_out >= 1) && (time_out <= 0x01000000uL)) );\r
+\r
+ if( time_out == MSS_MAC_NONBLOCKING )\r
+ {\r
+ /* Check if current descriptor is free */\r
+ if(((g_mss_mac.tx_descriptors[ g_mss_mac.tx_desc_index ].descriptor_0) & TDES0_OWN) == TDES0_OWN )\r
+ {\r
+ error = MAC_BUFFER_IS_FULL;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Wait until descriptor is free */\r
+ if( time_out != MSS_MAC_BLOCKING ) {\r
+ MAC_set_time_out( time_out );\r
+ }\r
+ \r
+ while( (((g_mss_mac.tx_descriptors[ g_mss_mac.tx_desc_index ].descriptor_0) & TDES0_OWN) == TDES0_OWN )\r
+ && (error == MAC_OK) )\r
+ {\r
+ /* transmit poll demand */\r
+ MAC->CSR1 = 1u;\r
+ \r
+ if(time_out != MSS_MAC_BLOCKING){\r
+ if(MAC_get_time_out() == 0u) {\r
+ error = MAC_TIME_OUT;\r
+ }\r
+ }\r
+ }\r
+ }\r
+\r
+ if( error == MAC_OK ) {\r
+\r
+ g_mss_mac.tx_descriptors[ g_mss_mac.tx_desc_index ].descriptor_1 = 0u;\r
+\r
+ if( (g_mss_mac.flags & FLAG_CRC_DISABLE) != 0u ) {\r
+ g_mss_mac.tx_descriptors[ g_mss_mac.tx_desc_index ].descriptor_1 |= TDES1_AC;\r
+ }\r
+\r
+ /* Every buffer can hold a full frame so they are always first and last\r
+ descriptor */\r
+ g_mss_mac.tx_descriptors[ g_mss_mac.tx_desc_index ].descriptor_1 |= TDES1_LS | TDES1_FS;\r
+\r
+ /* set data size */\r
+ g_mss_mac.tx_descriptors[ g_mss_mac.tx_desc_index ].descriptor_1 |= pacLen;\r
+\r
+ /* reset end of ring */\r
+ g_mss_mac.tx_descriptors[TX_RING_SIZE-1].descriptor_1 |= TDES1_TER;\r
+\r
+ /* copy data into buffer */\r
+ if( pacLen > MSS_TX_BUFF_SIZE ) /* FLAG_EXCEED_LIMIT */\r
+ {\r
+ pacLen = (uint16_t)MSS_TX_BUFF_SIZE;\r
+ }\r
+ MAC_memcpy(\r
+ (uint8_t*)\r
+ g_mss_mac.tx_descriptors[ g_mss_mac.tx_desc_index ].buffer_1,\r
+ pacData, (uint32_t)pacLen );\r
+\r
+ /* update counters */\r
+ desc = g_mss_mac.tx_descriptors[ g_mss_mac.tx_desc_index ].descriptor_0;\r
+ if( (desc & TDES0_LO) != 0u ) {\r
+ g_mss_mac.statistics.tx_loss_of_carrier++;\r
+ }\r
+ if( (desc & TDES0_NC) != 0u ) {\r
+ g_mss_mac.statistics.tx_no_carrier++;\r
+ }\r
+ if( (desc & TDES0_LC) != 0u ) {\r
+ g_mss_mac.statistics.tx_late_collision++;\r
+ }\r
+ if( (desc & TDES0_EC) != 0u ) {\r
+ g_mss_mac.statistics.tx_excessive_collision++;\r
+ }\r
+ if( (desc & TDES0_UF) != 0u ) {\r
+ g_mss_mac.statistics.tx_underflow_error++;\r
+ }\r
+ g_mss_mac.statistics.tx_collision_count +=\r
+ (desc >> TDES0_CC_OFFSET) & TDES0_CC_MASK;\r
+\r
+ /* Give ownership of descriptor to the MAC */\r
+ g_mss_mac.tx_descriptors[ g_mss_mac.tx_desc_index ].descriptor_0 = RDES0_OWN;\r
+\r
+ g_mss_mac.tx_desc_index = (g_mss_mac.tx_desc_index + 1u) % (uint32_t)TX_RING_SIZE;\r
+\r
+ /* Start transmission */\r
+ MAC_start_transmission();\r
+\r
+ /* transmit poll demand */\r
+ MAC->CSR1 = 1u;\r
+ }\r
+ \r
+ if (error == MAC_OK)\r
+ {\r
+ error = (int32_t)pacLen;\r
+ }\r
+ else\r
+ {\r
+ error = 0;\r
+ }\r
+ return ( error );\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * Returns available packet size.\r
+ *\r
+ * @param instance Pointer to a MAC_instance_t structure\r
+ * @return size of packet, bigger than 0, if a packet is available.\r
+ * If not, returns 0.\r
+ * @see MAC_rx_packet()\r
+ */\r
+int32_t\r
+MSS_MAC_rx_pckt_size\r
+(\r
+ void\r
+)\r
+{\r
+ int32_t retval;\r
+ ASSERT( MAC_test_instance() == MAC_OK );\r
+\r
+ MAC_dismiss_bad_frames();\r
+\r
+ if( (g_mss_mac.rx_descriptors[ g_mss_mac.rx_desc_index ].descriptor_0 & RDES0_OWN) != 0u )\r
+ {\r
+ /* Current descriptor is empty */\r
+ retval = 0;\r
+ }\r
+ else\r
+ {\r
+ uint32_t frame_length;\r
+ frame_length = ( g_mss_mac.rx_descriptors[ g_mss_mac.rx_desc_index ].descriptor_0 >> RDES0_FL_OFFSET ) & RDES0_FL_MASK;\r
+ retval = (int32_t)( frame_length );\r
+ }\r
+ return retval;\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * Receives a packet from the Ethernet Controller.\r
+ * This function reads a packet from the receive FIFO of the controller and\r
+ * places it into pacData. If time_out parameter is zero the function will return\r
+ * immediately (after the copy operation if data is available. Otherwise the function\r
+ * will keep trying to read till time_out expires or data is read, if MSS_MAC_BLOCKING\r
+ * value is given as time_out, function will wait for the reception to complete.\r
+ *\r
+ * @param instance Pointer to a MAC_instance_t structure\r
+ * @param pacData The pointer to the packet data.\r
+ * @param pacLen The pacLen parameter is the size in bytes of the pacData\r
+ * buffer where the received data will be copied.\r
+ * @param time_out Time out value in milli seconds for receiving.\r
+ * if value is #MSS_MAC_BLOCKING, there will be no time out.\r
+ * if value is #MSS_MAC_NONBLOCKING, function will return immediately\r
+ * if there is no packet waiting.\r
+ * Otherwise value must be greater than 0 and smaller than\r
+ * 0x01000000.\r
+ * @return Size of packet if packet fits in pacData.\r
+ * 0 if there is no received packet.\r
+ * @see MAC_rx_pckt_size()\r
+ * @see MAC_tx_packet()\r
+ */\r
+int32_t\r
+MSS_MAC_rx_packet\r
+(\r
+ uint8_t *pacData,\r
+ uint16_t pacLen,\r
+ uint32_t time_out\r
+)\r
+{\r
+ uint16_t frame_length=0u;\r
+ int8_t exit=0;\r
+\r
+ ASSERT( MAC_test_instance() == MAC_OK );\r
+\r
+ ASSERT( pacData != NULL_buffer );\r
+\r
+ ASSERT( (time_out == MSS_MAC_BLOCKING) ||\r
+ (time_out == MSS_MAC_NONBLOCKING) ||\r
+ ((time_out >= 1) && (time_out <= 0x01000000UL)) );\r
+\r
+ MAC_dismiss_bad_frames();\r
+\r
+ /* wait for a packet */\r
+ if( time_out != MSS_MAC_BLOCKING ) {\r
+ if( time_out == MSS_MAC_NONBLOCKING ) {\r
+ MAC_set_time_out( 0u );\r
+ } else {\r
+ MAC_set_time_out( time_out );\r
+ }\r
+ }\r
+\r
+ while( ((g_mss_mac.rx_descriptors[ g_mss_mac.rx_desc_index ].descriptor_0 &\r
+ RDES0_OWN) != 0u) && (exit == 0) )\r
+ {\r
+ if( time_out != MSS_MAC_BLOCKING )\r
+ {\r
+ if( MAC_get_time_out() == 0u ) {\r
+ exit = 1;\r
+ }\r
+ }\r
+ }\r
+\r
+ if(exit == 0)\r
+ {\r
+ frame_length = ( (\r
+ g_mss_mac.rx_descriptors[ g_mss_mac.rx_desc_index ].descriptor_0 >>\r
+ RDES0_FL_OFFSET ) & RDES0_FL_MASK );\r
+\r
+ /* strip crc */\r
+ frame_length -= 4u;\r
+\r
+ if( frame_length > pacLen ) {\r
+ return MAC_NOT_ENOUGH_SPACE;\r
+ }\r
+ \r
+ MAC_memcpy( pacData,\r
+ (uint8_t*)\r
+ g_mss_mac.rx_descriptors[ g_mss_mac.rx_desc_index ].buffer_1,\r
+ (uint32_t)frame_length );\r
+\r
+ MSS_MAC_prepare_rx_descriptor();\r
+ \r
+ }\r
+ return ((int32_t)frame_length);\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * Receives a packet from the Ethernet Controller.\r
+ * This function reads a packet from the receive FIFO of the controller and\r
+ * sets the address of pacData to the received data. \r
+ * If time_out parameter is zero the function will return\r
+ * immediately (after the copy operation if data is available. Otherwise the function\r
+ * will keep trying to read till time_out expires or data is read, if MSS_MAC_BLOCKING\r
+ * value is given as time_out, function will wait for the reception to complete.\r
+ *\r
+ * @param instance Pointer to a MAC_instance_t structure\r
+ * @param pacData The pointer to the packet data.\r
+ * @param time_out Time out value in milli seconds for receiving.\r
+ * if value is #MSS_MAC_BLOCKING, there will be no time out.\r
+ * if value is #MSS_MAC_NONBLOCKING, function will return immediately\r
+ * if there is no packet waiting.\r
+ * Otherwise value must be greater than 0 and smaller than\r
+ * 0x01000000.\r
+ * @return Size of packet if packet fits in pacData.\r
+ * 0 if there is no received packet.\r
+ * @see MAC_rx_pckt_size()\r
+ * @see MAC_tx_packet()\r
+ */\r
+int32_t\r
+MSS_MAC_rx_packet_ptrset\r
+(\r
+ uint8_t **pacData,\r
+ uint32_t time_out\r
+)\r
+{\r
+ uint16_t frame_length = 0u;\r
+ int8_t exit = 0;\r
+\r
+ ASSERT( MAC_test_instance() == MAC_OK );\r
+\r
+ ASSERT( (time_out == MSS_MAC_BLOCKING) ||\r
+ (time_out == MSS_MAC_NONBLOCKING) ||\r
+ ((time_out >= 1) && (time_out <= 0x01000000UL)) );\r
+\r
+ MAC_dismiss_bad_frames();\r
+\r
+ /* wait for a packet */\r
+ if( time_out != MSS_MAC_BLOCKING ) {\r
+ if( time_out == MSS_MAC_NONBLOCKING ) {\r
+ MAC_set_time_out( 0u );\r
+ } else {\r
+ MAC_set_time_out( time_out );\r
+ }\r
+ }\r
+\r
+ while( ((g_mss_mac.rx_descriptors[ g_mss_mac.rx_desc_index ].descriptor_0 &\r
+ RDES0_OWN) != 0u) && (exit == 0) )\r
+ {\r
+ if( time_out != MSS_MAC_BLOCKING )\r
+ {\r
+ if( MAC_get_time_out() == 0u ) {\r
+ exit = 1;\r
+ }\r
+ }\r
+ }\r
+\r
+ if(exit == 0)\r
+ {\r
+ frame_length = ( (\r
+ g_mss_mac.rx_descriptors[ g_mss_mac.rx_desc_index ].descriptor_0 >>\r
+ RDES0_FL_OFFSET ) & RDES0_FL_MASK );\r
+\r
+ /* strip crc */\r
+ frame_length -= 4u;\r
+\r
+ /* Here we are setting the buffer 'pacData' address to the address\r
+ RX descriptor address. After this is called, the following function\r
+ must be called 'MAC_prepare_rx_descriptor' \r
+ to prepare the current rx descriptor for receiving the next packet.\r
+ */ \r
+ *pacData = (uint8_t *)g_mss_mac.rx_descriptors[ g_mss_mac.rx_desc_index ].buffer_1 ; \r
+ \r
+ }\r
+ return ((int32_t)frame_length);\r
+}\r
+\r
+/***************************************************************************//**\r
+ * Returns the status of connection.\r
+ *\r
+ * @return the logical OR of the following values:\r
+ * #MSS_MAC_LINK_STATUS_LINK - Link up/down\r
+ * #MSS_MAC_LINK_STATUS_100MB - Connection is 100Mb/10Mb\r
+ * #MSS_MAC_LINK_STATUS_FDX - Connection is full/half duplex\r
+ * @see MAC_auto_setup_link()\r
+ */\r
+int32_t\r
+MSS_MAC_link_status\r
+(\r
+ void\r
+)\r
+{\r
+ uint32_t link;\r
+\r
+ ASSERT( MAC_test_instance() == MAC_OK );\r
+\r
+ link = PHY_link_status();\r
+ if( link == MSS_MAC_LINK_STATUS_LINK ) {\r
+ link |= PHY_link_type();\r
+ }\r
+\r
+ return ((int32_t)link);\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * Setups the link between PHY and MAC and returns the status of connection.\r
+ *\r
+ * @return the logical OR of the following values:\r
+ * #MSS_MAC_LINK_STATUS_LINK - Link up/down\r
+ * #MSS_MAC_LINK_STATUS_100MB - Connection is 100Mb/10Mb\r
+ * #MSS_MAC_LINK_STATUS_FDX - Connection is full/half duplex\r
+ * @see MAC_link_status()\r
+ */\r
+int32_t\r
+MSS_MAC_auto_setup_link\r
+(\r
+ void\r
+)\r
+{\r
+ int32_t link;\r
+ ASSERT( MAC_test_instance() == MAC_OK );\r
+\r
+ PHY_auto_negotiate();\r
+\r
+ link = MSS_MAC_link_status();\r
+\r
+ if( (link & MSS_MAC_LINK_STATUS_LINK) != 0u ) {\r
+ int32_t ret;\r
+ ret = MAC_stop_transmission();\r
+ MAC_CHECK( ret == MAC_OK, ret );\r
+\r
+ ret = MAC_stop_receiving();\r
+ MAC_CHECK( ret == MAC_OK, ret );\r
+ MAC_BITBAND->CSR6_TTM = (uint32_t)((((uint32_t)link & MSS_MAC_LINK_STATUS_100MB) != 0u) ? 1u : 0u );\r
+ MAC_BITBAND->CSR6_FD = (uint32_t)((((uint32_t)link & MSS_MAC_LINK_STATUS_FDX) != 0u) ? 1u : 1u );\r
+ MAC_start_transmission();\r
+ MAC_start_receiving();\r
+ }\r
+\r
+ return link;\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * Sets mac address. New address must be unicast.\r
+ *\r
+ * @param new_address Pointer to a MAC_instance_t structure\r
+ * @see MAC_get_mac_address()\r
+ */\r
+void\r
+MSS_MAC_set_mac_address\r
+(\r
+ const uint8_t *new_address\r
+)\r
+{\r
+ ASSERT( MAC_test_instance() == MAC_OK );\r
+ /* Check if the new address is unicast */\r
+ ASSERT( (new_address[0]&1) == 0 );\r
+\r
+ MAC_memcpy( g_mss_mac.mac_address, new_address, 6u );\r
+\r
+ if((g_mss_mac.flags & FLAG_PERFECT_FILTERING) != 0u ) {\r
+ int32_t a;\r
+ /* set unused filters to the new mac address */\r
+ for( a=14*6; a>=0; a-=6 ) {\r
+ if( (g_mss_mac.mac_filter_data[a] & 1u) != 0u ) {\r
+ /* Filters with multicast addresses are used */\r
+ a = -1;\r
+ } else {\r
+ MAC_memcpy( &(g_mss_mac.mac_filter_data[a]),\r
+ g_mss_mac.mac_address, 6u );\r
+ }\r
+ }\r
+ }\r
+\r
+ MAC_send_setup_frame();\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * Returns mac address.\r
+ *\r
+ * @param address Pointer to receive the MAC address\r
+ * @see MAC_set_mac_address()\r
+ */\r
+void\r
+MSS_MAC_get_mac_address\r
+(\r
+ uint8_t *address\r
+)\r
+{\r
+ ASSERT( MAC_test_instance() == MAC_OK );\r
+\r
+ MAC_memcpy( address, g_mss_mac.mac_address, 6u );\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * Sets mac address filters. Addresses must be multicast.\r
+ *\r
+ * @param filter_count number of addresses\r
+ * @param filters Pointer to addresses to be filtered\r
+ */\r
+void\r
+MSS_MAC_set_mac_filters\r
+(\r
+ uint16_t filter_count,\r
+ const uint8_t *filters\r
+)\r
+{\r
+ ASSERT( MAC_test_instance() == MAC_OK );\r
+ ASSERT( (filter_count==0) || (filters != NULL_buffer) );\r
+ /* Check if the mac addresses is multicast */\r
+ {\r
+ int32_t a;\r
+ for( a = 0u; a < filter_count; a++ ) {\r
+ ASSERT( (filters[a*6]&1) == 1 );\r
+ }\r
+ }\r
+\r
+ if( filter_count <= 15 ){\r
+ int32_t a;\r
+ g_mss_mac.flags |= FLAG_PERFECT_FILTERING;\r
+\r
+ /* copy new filters */\r
+ MAC_memcpy( g_mss_mac.mac_filter_data, filters, (uint32_t)(filter_count*6));\r
+\r
+ /* set unused filters to our mac address */\r
+ for( a=filter_count; a<15; a++ ) {\r
+ MAC_memcpy( &(g_mss_mac.mac_filter_data[a*6]),\r
+ g_mss_mac.mac_address, 6 );\r
+ }\r
+ } else {\r
+ int32_t a,b;\r
+ uint32_t hash;\r
+\r
+ g_mss_mac.flags &= ~FLAG_PERFECT_FILTERING;\r
+\r
+ /* reset hash table */\r
+ MAC_memset( g_mss_mac.mac_filter_data, 0u, 64u );\r
+\r
+ for( a=0, b=0; a<filter_count; a++, b+=6 ) {\r
+ hash = mss_ethernet_crc( &(filters[b]), 6 ) & 0x1FF;\r
+ g_mss_mac.mac_filter_data[ hash / 8 ] |= 1 << (hash & 0x7);\r
+ }\r
+ }\r
+\r
+ MAC_send_setup_frame();\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * MAC interrupt service routine.\r
+ *\r
+ * @param instance Pointer to a MAC_instance_t structure\r
+ * @see MAC_set_callback()\r
+ */\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void EthernetMAC_IRQHandler( void )\r
+#else\r
+void EthernetMAC_IRQHandler( void )\r
+#endif\r
+{\r
+ uint32_t events;\r
+ uint32_t intr_status;\r
+\r
+ ASSERT( MAC_test_instance() == MAC_OK );\r
+\r
+ events = 0u;\r
+ intr_status = MAC->CSR5;\r
+\r
+ if( (intr_status & CSR5_NIS_MASK) != 0u ) {\r
+ if( (intr_status & CSR5_TI_MASK) != 0u ) { /* Transmit */\r
+ g_mss_mac.statistics.tx_interrupts++;\r
+ events |= MSS_MAC_EVENT_PACKET_SEND;\r
+ }\r
+\r
+ if( (intr_status & CSR5_RI_MASK) != 0u ) { /* Receive */\r
+ g_mss_mac.statistics.rx_interrupts++;\r
+ events |= MSS_MAC_EVENT_PACKET_RECEIVED;\r
+ }\r
+ }\r
+\r
+ /* Clear interrupts */\r
+ MAC->CSR5 = CSR5_INT_BITS;\r
+ \r
+ if( (events != 0u) && (g_mss_mac.listener != NULL_callback) ) {\r
+ g_mss_mac.listener( events );\r
+ }\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * Sets MAC event listener.\r
+ * Sets the given event listener function to be triggered inside MAC_isr().\r
+ * Assigning NULL pointer as the listener function will disable it.\r
+ *\r
+ * @param instance Pointer to a MAC_instance_t structure\r
+ * @param listener function pointer to a MAC_callback_t function\r
+ * @return #MAC_OK if everything is OK\r
+ * #MAC_WRONG_PARAMETER if instance is null or hasn't been\r
+ * initialized.\r
+ * @see MAC_isr()\r
+ */\r
+void\r
+MSS_MAC_set_callback\r
+(\r
+ MSS_MAC_callback_t listener\r
+)\r
+{\r
+ ASSERT( MAC_test_instance() == MAC_OK );\r
+\r
+ /* disable tx and rx interrupts */\r
+ MAC_BITBAND->CSR7_RIE = 0u;\r
+ MAC_BITBAND->CSR7_TIE = 0u;\r
+ \r
+ g_mss_mac.listener = listener;\r
+\r
+ if( listener != NULL_callback ) {\r
+ /* enable tx and rx interrupts */\r
+ MAC_BITBAND->CSR7_RIE = 1u;\r
+ MAC_BITBAND->CSR7_TIE = 1u;\r
+ }\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * Returns description of last error.\r
+ *\r
+ * @param instance Pointer to a MAC_instance_t structure\r
+ * @return A string describing the error. This string must not be\r
+ * modified by the application.\r
+ * #MAC_WRONG_PARAMETER if instance is null or hasn't been\r
+ * initialized.\r
+ */\r
+const int8_t*\r
+MSS_MAC_last_error\r
+(\r
+ void\r
+)\r
+{\r
+ int8_t error_msg_nb;\r
+ const int8_t* returnvalue;\r
+ \r
+ ASSERT( MAC_test_instance() == MAC_OK );\r
+\r
+ error_msg_nb = -(g_mss_mac.last_error);\r
+ if( error_msg_nb >= ERROR_MESSAGE_COUNT ) {\r
+ returnvalue = unknown_error;\r
+ } else {\r
+ returnvalue = ErrorMessages[error_msg_nb];\r
+ }\r
+ return returnvalue;\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * Returns statistics counter of stat_id identifier.\r
+ *\r
+ * @param instance Pointer to a MAC_instance_t structure\r
+ * @param stat_id Identifier of statistics counter.\r
+ * @return Statistics counter of stat_id identifier.\r
+ * On error returns 0.\r
+ */\r
+uint32_t\r
+MSS_MAC_get_statistics\r
+(\r
+ mss_mac_statistics_id_t stat_id\r
+)\r
+{\r
+ uint32_t returnval = 0u;\r
+ ASSERT( MAC_test_instance() == MAC_OK );\r
+\r
+ switch( stat_id ) {\r
+ case MSS_MAC_RX_INTERRUPTS:\r
+ returnval = g_mss_mac.statistics.rx_interrupts;\r
+ break;\r
+ case MSS_MAC_RX_FILTERING_FAIL:\r
+ returnval = g_mss_mac.statistics.rx_filtering_fail;\r
+ break;\r
+ case MSS_MAC_RX_DESCRIPTOR_ERROR:\r
+ returnval = g_mss_mac.statistics.rx_descriptor_error;\r
+ break;\r
+ case MSS_MAC_RX_RUNT_FRAME:\r
+ returnval = g_mss_mac.statistics.rx_runt_frame;\r
+ break;\r
+ case MSS_MAC_RX_NOT_FIRST:\r
+ returnval = g_mss_mac.statistics.rx_not_first;\r
+ break;\r
+ case MSS_MAC_RX_NOT_LAST:\r
+ returnval = g_mss_mac.statistics.rx_not_last;\r
+ break;\r
+ case MSS_MAC_RX_FRAME_TOO_LONG:\r
+ returnval = g_mss_mac.statistics.rx_frame_too_long;\r
+ break;\r
+ case MSS_MAC_RX_COLLISION_SEEN:\r
+ returnval = g_mss_mac.statistics.rx_collision_seen;\r
+ break;\r
+ case MSS_MAC_RX_CRC_ERROR:\r
+ returnval = g_mss_mac.statistics.rx_crc_error;\r
+ break;\r
+ case MSS_MAC_RX_FIFO_OVERFLOW:\r
+ returnval = g_mss_mac.statistics.rx_fifo_overflow;\r
+ break;\r
+ case MSS_MAC_RX_MISSED_FRAME:\r
+ returnval = g_mss_mac.statistics.rx_missed_frame;\r
+ break;\r
+ case MSS_MAC_TX_INTERRUPTS:\r
+ returnval = g_mss_mac.statistics.tx_interrupts;\r
+ break;\r
+ case MSS_MAC_TX_LOSS_OF_CARRIER:\r
+ returnval = g_mss_mac.statistics.tx_loss_of_carrier;\r
+ break;\r
+ case MSS_MAC_TX_NO_CARRIER:\r
+ returnval = g_mss_mac.statistics.tx_no_carrier;\r
+ break;\r
+ case MSS_MAC_TX_LATE_COLLISION:\r
+ returnval = g_mss_mac.statistics.tx_late_collision;\r
+ break;\r
+ case MSS_MAC_TX_EXCESSIVE_COLLISION:\r
+ returnval = g_mss_mac.statistics.tx_excessive_collision;\r
+ break;\r
+ case MSS_MAC_TX_COLLISION_COUNT:\r
+ returnval = g_mss_mac.statistics.tx_collision_count;\r
+ break;\r
+ case MSS_MAC_TX_UNDERFLOW_ERROR:\r
+ returnval = g_mss_mac.statistics.tx_underflow_error;\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+\r
+ return returnval;\r
+}\r
+\r
+\r
+/**************************** INTERNAL FUNCTIONS ******************************/\r
+\r
+/***************************************************************************//**\r
+ * Checks if instace is valid.\r
+ */\r
+static int32_t\r
+MAC_test_instance\r
+(\r
+ void\r
+)\r
+{\r
+ uint32_t val1;\r
+ uint32_t val2;\r
+ int32_t retval = MAC_WRONG_PARAMETER;\r
+\r
+ val1 = MAC->CSR3;\r
+ val2 = MAC->CSR4;\r
+\r
+ if( (&g_mss_mac != NULL_instance) &&\r
+ ((g_mss_mac.flags & FLAG_MAC_INIT_DONE) != 0u) &&\r
+ ( val1 == (uint32_t)g_mss_mac.rx_descriptors) &&\r
+ (val2 == (uint32_t)g_mss_mac.tx_descriptors ) )\r
+ {\r
+ retval = MAC_OK;\r
+ }\r
+ return retval;\r
+}\r
+\r
+/***************************************************************************//**\r
+ * Prepares current rx descriptor for receiving.\r
+ */\r
+void\r
+MSS_MAC_prepare_rx_descriptor\r
+(\r
+ void\r
+)\r
+{\r
+ uint32_t desc;\r
+\r
+ /* update counters */\r
+ desc = g_mss_mac.rx_descriptors[ g_mss_mac.rx_desc_index ].descriptor_0;\r
+ if( (desc & RDES0_FF) != 0u ) {\r
+ g_mss_mac.statistics.rx_filtering_fail++;\r
+ }\r
+ if( (desc & RDES0_DE) != 0u ) {\r
+ g_mss_mac.statistics.rx_descriptor_error++;\r
+ }\r
+ if( (desc & RDES0_RF) != 0u ) {\r
+ g_mss_mac.statistics.rx_runt_frame++;\r
+ }\r
+ if( (desc & RDES0_FS) == 0u ) {\r
+ g_mss_mac.statistics.rx_not_first++;\r
+ }\r
+ if( (desc & RDES0_LS) == 0u ) {\r
+ g_mss_mac.statistics.rx_not_last++;\r
+ }\r
+ if( (desc & RDES0_TL) != 0u ) {\r
+ g_mss_mac.statistics.rx_frame_too_long++;\r
+ }\r
+ if( (desc & RDES0_CS) != 0u ) {\r
+ g_mss_mac.statistics.rx_collision_seen++;\r
+ }\r
+ if( (desc & RDES0_CE) != 0u ) {\r
+ g_mss_mac.statistics.rx_crc_error++;\r
+ }\r
+ \r
+ desc = MAC->CSR8;\r
+ g_mss_mac.statistics.rx_fifo_overflow +=\r
+ (desc & (CSR8_OCO_MASK|CSR8_FOC_MASK)) >> CSR8_FOC_SHIFT;\r
+ g_mss_mac.statistics.rx_missed_frame +=\r
+ (desc & (CSR8_MFO_MASK|CSR8_MFC_MASK));\r
+\r
+ /* Give ownership of descriptor to the MAC */\r
+ g_mss_mac.rx_descriptors[ g_mss_mac.rx_desc_index ].descriptor_0 =\r
+ RDES0_OWN;\r
+ g_mss_mac.rx_desc_index = (g_mss_mac.rx_desc_index + 1u) % RX_RING_SIZE;\r
+\r
+ /* Start receive */\r
+ MAC_start_receiving();\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * Prepares a setup frame and sends it to MAC.\r
+ * This function is blocking.\r
+ * @return #MAC_OK if everything is ok.\r
+ * #MAC_TIME_OUT if timed out before packet send.\r
+ */\r
+static int32_t\r
+MAC_send_setup_frame\r
+(\r
+ void\r
+)\r
+{\r
+ volatile MAC_descriptor_t descriptor;\r
+ uint8_t frame_data[192];\r
+ uint8_t *data;\r
+ int32_t a,b,c,d;\r
+ int32_t ret;\r
+\r
+ /* prepare descriptor */\r
+ descriptor.descriptor_0 = TDES0_OWN;\r
+ descriptor.descriptor_1 = TDES1_SET | TDES1_TER |\r
+ (sizeof(frame_data) << TDES1_TBS1_OFFSET);\r
+\r
+ if( (g_mss_mac.flags & FLAG_PERFECT_FILTERING) == 0u ) {\r
+ descriptor.descriptor_1 |= TDES1_FT0;\r
+ }\r
+\r
+ descriptor.buffer_1 = (uint32_t)frame_data;\r
+ descriptor.buffer_2 = 0u;\r
+\r
+ /* prepare frame */\r
+ if( (g_mss_mac.flags & FLAG_PERFECT_FILTERING) != 0u ) {\r
+ b = 0;\r
+ d = 12;\r
+ c = 90;\r
+ } else {\r
+ b = 156;\r
+ d = 0;\r
+ c = 64;\r
+ }\r
+\r
+ data = g_mss_mac.mac_address;\r
+ frame_data[b] = data[0];\r
+ frame_data[b+1] = data[1];\r
+ frame_data[b+4] = data[2];\r
+ frame_data[b+5] = data[3];\r
+ frame_data[b+8] = data[4];\r
+ frame_data[b+9] = data[5];\r
+\r
+ data = g_mss_mac.mac_filter_data;\r
+ for( a = 0; a < c; ) {\r
+ frame_data[d] = data[a++];\r
+ frame_data[d+1] = data[a++];\r
+ frame_data[d+4] = data[a++];\r
+ frame_data[d+5] = data[a++];\r
+ frame_data[d+8] = data[a++];\r
+ frame_data[d+9] = data[a++];\r
+ d += 12;\r
+ }\r
+\r
+ /* Stop transmission */\r
+ ret = MAC_stop_transmission();\r
+ ASSERT( ret == MAC_OK );\r
+\r
+ ret = MAC_stop_receiving();\r
+ ASSERT( ret == MAC_OK );\r
+\r
+ /* Set descriptor */\r
+ MAC->CSR4 = (uint32_t)&descriptor;\r
+ \r
+ /* Start transmission */\r
+ MAC_start_transmission();\r
+\r
+ /* Wait until transmission over */\r
+ ret = MAC_OK;\r
+ MAC_set_time_out( (uint32_t)SETUP_FRAME_TIME_OUT );\r
+ \r
+ while( (((MAC->CSR5 & CSR5_TS_MASK) >> CSR5_TS_SHIFT) != \r
+ CSR5_TS_SUSPENDED) && (MAC_OK == ret) )\r
+ {\r
+ /* transmit poll demand */\r
+ MAC->CSR1 = 1u;\r
+ if( MAC_get_time_out() == 0u ) {\r
+ ret = MAC_TIME_OUT;\r
+ }\r
+ }\r
+\r
+ MAC_CHECK( MAC_stop_transmission() == MAC_OK, MAC_FAIL );\r
+\r
+ /* Set tx descriptor */\r
+ MAC->CSR4 = (uint32_t)g_mss_mac.tx_descriptors;\r
+ \r
+ /* Start receiving and transmission */\r
+ MAC_start_receiving();\r
+ MAC_start_transmission();\r
+\r
+ return ret;\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * Stops transmission.\r
+ * Function will wait until transmit operation enters stop state.\r
+ *\r
+ * @return #MAC_OK if everything is ok.\r
+ * #MAC_TIME_OUT if timed out.\r
+ */\r
+static int32_t\r
+MAC_stop_transmission\r
+(\r
+ void\r
+)\r
+{\r
+ int32_t retval = MAC_OK;\r
+ MAC_set_time_out( (uint16_t)STATE_CHANGE_TIME_OUT );\r
+ \r
+ while( (((MAC->CSR5 & CSR5_TS_MASK) >> CSR5_TS_SHIFT) !=\r
+ CSR5_TS_STOPPED) && (retval == MAC_OK) )\r
+ {\r
+ MAC_BITBAND->CSR6_ST = 0u;\r
+ if( MAC_get_time_out() == 0u ) {\r
+ retval = MAC_TIME_OUT;\r
+ }\r
+ }\r
+ return retval;\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * Starts transmission.\r
+ */\r
+static void\r
+MAC_start_transmission\r
+(\r
+ void\r
+)\r
+{\r
+ MAC_BITBAND->CSR6_ST = 1u;\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * Stops transmission.\r
+ * Function will wait until transmit operation enters stop state.\r
+ *\r
+ * @return #MAC_OK if everything is ok.\r
+ * #MAC_TIME_OUT if timed out.\r
+ */\r
+static int32_t\r
+MAC_stop_receiving\r
+(\r
+ void\r
+)\r
+{\r
+ int32_t retval = MAC_OK;\r
+ MAC_set_time_out( (uint16_t)STATE_CHANGE_TIME_OUT );\r
+\r
+ while( (((MAC->CSR5 & CSR5_RS_MASK) >> CSR5_RS_SHIFT) != CSR5_RS_STOPPED)\r
+ && (retval == MAC_OK) )\r
+ {\r
+ MAC_BITBAND->CSR6_SR = 0u;\r
+ if( MAC_get_time_out() == 0u ) {\r
+ retval = MAC_TIME_OUT;\r
+ }\r
+ }\r
+\r
+ return retval;\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * Starts transmission.\r
+ */\r
+static void\r
+MAC_start_receiving\r
+(\r
+ void\r
+)\r
+{\r
+ MAC_BITBAND->CSR6_SR = 1u;\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * Dismisses bad frames.\r
+ *\r
+ * @return dismissed frame count.\r
+ */\r
+static int32_t\r
+MAC_dismiss_bad_frames\r
+(\r
+ void\r
+)\r
+{\r
+ int32_t dc = 0;\r
+ int8_t cont = 1;\r
+ \r
+ if( MAC_BITBAND->CSR6_PB != 0u ) {\r
+ /* User wants bad frames too, don't dismiss anything */\r
+ cont = 0;\r
+ }\r
+\r
+ while( ( (g_mss_mac.rx_descriptors[ g_mss_mac.rx_desc_index ].descriptor_0 &\r
+ RDES0_OWN) == 0u) && (cont == 1) ) /* Host owns this descriptor */\r
+ {\r
+ /* check error summary */\r
+ if( (g_mss_mac.rx_descriptors[ g_mss_mac.rx_desc_index ].descriptor_0 &\r
+ (RDES0_ES | RDES0_LS | RDES0_FS)) != (RDES0_LS | RDES0_FS) )\r
+ {\r
+ MSS_MAC_prepare_rx_descriptor();\r
+ dc++;\r
+ }\r
+ else\r
+ {\r
+ cont = 0;\r
+ }\r
+ }\r
+\r
+ return dc;\r
+}\r
+\r
+/***************************************************************************//**\r
+ * Sets time out value.\r
+ * #MAC_get_time_out must be called frequently to make time out value updated.\r
+ * Because of user may not be using ISR, we can not update time out in ISR.\r
+ *\r
+ * @time_out time out value in milli seconds.\r
+ * Must be smaller than 0x01000000.\r
+ */\r
+static void\r
+MAC_set_time_out\r
+(\r
+ uint32_t time_out\r
+)\r
+{\r
+ g_mss_mac.time_out_value = (time_out * 122u) / 10u;\r
+\r
+ g_mss_mac.last_timer_value = (uint16_t)( MAC->CSR11 & CSR11_TIM_MASK );\r
+}\r
+\r
+/***************************************************************************//**\r
+ * Returns time out value.\r
+ *\r
+ * @return timer out value in milli seconds.\r
+ */\r
+static uint32_t\r
+MAC_get_time_out\r
+(\r
+ void\r
+)\r
+{\r
+ uint32_t timer;\r
+ uint32_t time = 0u;\r
+ \r
+ timer = ( MAC->CSR11 & CSR11_TIM_MASK );\r
+ \r
+ if( timer > g_mss_mac.last_timer_value ) {\r
+ time = 0x0000ffffUL;\r
+ }\r
+ time += g_mss_mac.last_timer_value - timer;\r
+ \r
+ if( MAC_BITBAND->CSR6_TTM == 0u ) {\r
+ time *= 10u;\r
+ }\r
+ if( g_mss_mac.time_out_value <= time ){\r
+ g_mss_mac.time_out_value = 0u;\r
+ } else {\r
+ g_mss_mac.time_out_value -= time;\r
+ }\r
+\r
+ g_mss_mac.last_timer_value = (uint16_t)timer;\r
+\r
+ return ((g_mss_mac.time_out_value * 10u) / 122u);\r
+}\r
+\r
+/***************************************************************************//**\r
+ * Fills the first n bytes of the memory area pointed to by s with the constant\r
+ * byte c.\r
+ */\r
+static void MAC_memset(uint8_t *s, uint8_t c, uint32_t n)\r
+{\r
+ uint8_t *sb = s;\r
+\r
+ while( n > 0u ) {\r
+ n--;\r
+ sb[n] = c;\r
+ }\r
+}\r
+\r
+/***************************************************************************//**\r
+ * Fills all fields of MAC_instance_t with c.\r
+ *\r
+ * @return a pointer to the given MAC_instance_t s.\r
+ */\r
+static void MAC_memset_All(MAC_instance_t *s, uint32_t c)\r
+{\r
+ int32_t count;\r
+ s->base_address = (addr_t)c;\r
+ s->flags = (uint8_t)c;\r
+ s->last_error = (int8_t)c;\r
+ s->last_timer_value = (uint16_t)c;\r
+ s->listener = NULL_callback;\r
+ MAC_memset( s->mac_address, (uint8_t)c, 6u );\r
+ MAC_memset( s->mac_filter_data, (uint8_t)c, 90u );\r
+ s->phy_address = (uint8_t)c;\r
+ for(count = 0; count<RX_RING_SIZE ;count++)\r
+ {\r
+ MAC_memset(s->rx_buffers[count], (uint8_t)c, (MSS_RX_BUFF_SIZE + 4u) );\r
+ }\r
+ s->rx_desc_index =c;\r
+ for(count = 0; count<RX_RING_SIZE ;count++)\r
+ {\r
+ s->rx_descriptors[count].buffer_1 = c;\r
+ s->rx_descriptors[count].buffer_2 = c;\r
+ s->rx_descriptors[count].descriptor_0 = c;\r
+ s->rx_descriptors[count].descriptor_1 = c;\r
+ }\r
+ s->statistics.rx_collision_seen =c;\r
+ s->statistics.rx_crc_error = c;\r
+ s->statistics.rx_descriptor_error = c;\r
+ s->statistics.rx_fifo_overflow = c;\r
+ s->statistics.rx_filtering_fail = c;\r
+ s->statistics.rx_frame_too_long = c;\r
+ s->statistics.rx_interrupts = c;\r
+ s->statistics.rx_missed_frame = c;\r
+ s->statistics.rx_not_first = c;\r
+ s->statistics.rx_not_last = c;\r
+ s->statistics.rx_runt_frame = c;\r
+ s->statistics.tx_collision_count = c;\r
+ s->statistics.tx_excessive_collision = c;\r
+ s->statistics.tx_interrupts = c;\r
+ s->statistics.tx_late_collision = c;\r
+ s->statistics.tx_loss_of_carrier = c;\r
+ s->statistics.tx_no_carrier = c;\r
+ s->statistics.tx_underflow_error = c;\r
+ s->time_out_value = c;\r
+ for(count = 0; count < TX_RING_SIZE ;count++)\r
+ {\r
+ MAC_memset( s->tx_buffers[count], (uint8_t)c, MSS_TX_BUFF_SIZE );\r
+ }\r
+ s->tx_desc_index = c;\r
+ for(count = 0; count < TX_RING_SIZE ;count++)\r
+ {\r
+ s->tx_descriptors[count].buffer_1 = c;\r
+ s->tx_descriptors[count].buffer_2 = c;\r
+ s->tx_descriptors[count].descriptor_0 = c;\r
+ s->tx_descriptors[count].descriptor_1 = c;\r
+ }\r
+}\r
+\r
+/***************************************************************************//**\r
+ * Copies n bytes from memory area src to memory area dest.\r
+ * The memory areas should not overlap.\r
+ *\r
+ * @return a pointer to the memory area dest.\r
+ */\r
+static void MAC_memcpy(uint8_t *dest, const uint8_t *src, uint32_t n)\r
+{\r
+ uint8_t *d = dest;\r
+\r
+ while( n > 0u ) {\r
+ n--;\r
+ d[n] = src[n];\r
+ }\r
+}\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/******************************** END OF FILE *********************************/\r
+\r
--- /dev/null
+/***************************************************************************//**\r
+ * @file\r
+ * SmartFusion MSS Ethernet MAC header file.\r
+ *\r
+ * (c) Copyright 2007 Actel Corporation\r
+ *\r
+ * SVN $Revision: 2364 $\r
+ * SVN $Date: 2010-03-01 17:58:41 +0000 (Mon, 01 Mar 2010) $\r
+ *\r
+ *******************************************************************************/\r
+\r
+#ifndef __MSS_ETHERNET_MAC_H\r
+#define __MSS_ETHERNET_MAC_H 1\r
+\r
+#include <stdint.h>\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif \r
+\r
+/******************************** DEFINES *************************************/\r
+\r
+/*******************************************************************************\r
+ * Configure values.\r
+ */\r
+/**\r
+ * Receive all.\r
+ * When set, all incoming frames are received, regardless of their destination address.\r
+ * An address check is performed, and the result of the check is written into the receive\r
+ * descriptor.\r
+ */\r
+#define MSS_MAC_CFG_RECEIVE_ALL 0x00000001u\r
+\r
+/**\r
+ * Transmit threshold mode.\r
+ * 1 - Transmit FIFO threshold set for 100 Mbps mode\r
+ * 0 - Transmit FIFO threshold set for 10 Mbps mode\r
+ * This bit can be changed only when a transmit process is in a stopped state.\r
+ */\r
+#define MSS_MAC_CFG_TRANSMIT_THRESHOLD_MODE 0x00000002u\r
+\r
+/**\r
+ * Store and forward.\r
+ * When set, the transmission starts after a full packet is written into the transmit\r
+ * FIFO, regardless of the current FIFO threshold level.\r
+ * This bit can be changed only when the transmit process is in the stopped state.\r
+ */\r
+#define MSS_MAC_CFG_STORE_AND_FORWARD 0x00000004u\r
+\r
+/**\r
+ * Threshold control bits.\r
+ * These bits, together with TTM, SF, and PS, control the threshold level for the\r
+ * transmit FIFO.\r
+ */\r
+#define MSS_MAC_CFG_THRESHOLD_CONTROL_00 0x00000000u\r
+#define MSS_MAC_CFG_THRESHOLD_CONTROL_01 0x00000008u\r
+#define MSS_MAC_CFG_THRESHOLD_CONTROL_10 0x00000010u\r
+#define MSS_MAC_CFG_THRESHOLD_CONTROL_11 0x00000018u\r
+\r
+/**\r
+ * Full-duplex mode.\r
+ * 0 - Half-duplex mode <br>\r
+ * 1 - Forcing full-duplex mode <br>\r
+ * Changing of this bit is allowed only when both the transmitter and receiver processes\r
+ * are in the stopped state.\r
+ */\r
+#define MSS_MAC_CFG_FULL_DUPLEX_MODE 0x00000020u\r
+\r
+/**\r
+ * Pass all multicast.\r
+ * When set, all frames with multicast destination addresses will be received, regardless\r
+ * of the address check result.\r
+ */\r
+#define MSS_MAC_CFG_PASS_ALL_MULTICAST 0x00000040u\r
+\r
+/**\r
+ * Promiscuous mode.\r
+ * When set, all frames will be received regardless of the address check result. An\r
+ * address check is not performed.\r
+ */\r
+#define MSS_MAC_CFG_PROMISCUOUS_MODE 0x00000080u\r
+\r
+/**\r
+ * Inverse filtering (read-only).\r
+ * If this bit is set when working in a perfect filtering mode, the receiver performs an\r
+ * inverse filtering during the address check process.\r
+ * The 'filtering type' bits of the setup frame determine the state of this bit.\r
+ */\r
+#define MSS_MAC_CFG_INVERSE_FILTERING 0x00000100u\r
+\r
+/**\r
+ * Pass bad frames.\r
+ * When set, Core10/100 transfers all frames into the data buffers, regardless of the\r
+ * receive errors. This allows the runt frames, collided fragments, and truncated frames\r
+ * to be received.\r
+ */\r
+#define MSS_MAC_CFG_PASS_BAD_FRAMES 0x00000200u\r
+\r
+/**\r
+ * Hash-only filtering mode (read-only).\r
+ * When set, Core10/100 performs an imperfect filtering over both the multicast and\r
+ * physical addresses.\r
+ * The 'filtering type' bits of the setup frame determine the state of this bit.\r
+ */\r
+#define MSS_MAC_CFG_HASH_ONLY_FILTERING_MODE 0x00000400u\r
+\r
+/**\r
+ * Hash/perfect receive filtering mode (read-only).\r
+ * 0 - Perfect filtering of the incoming frames is performed according to the physical\r
+ * addresses specified in a setup frame. <br>\r
+ * 1 - Imperfect filtering over the frames with the multicast addresses is performed\r
+ * according to the hash table specified in a setup frame. <br>\r
+ * A physical address check is performed according to the CSR6.2 (HO, hash-only) bit.\r
+ * When both the HO and HP bits are set, an imperfect filtering is performed on all of\r
+ * the addresses.\r
+ * The 'filtering type' bits of the setup frame determine the state of this bit.\r
+ */\r
+#define MSS_MAC_CFG_HASH_PERFECT_RECEIVE_FILTERING_MODE 0x00000800u\r
+\r
+\r
+/*******************************************************************************\r
+ * Link status values.\r
+ */\r
+#define MSS_MAC_LINK_STATUS_LINK 0x0001u /**< Link up/down */\r
+#define MSS_MAC_LINK_STATUS_100MB 0x0002u /**< Connection is 100Mb/10Mb */\r
+#define MSS_MAC_LINK_STATUS_FDX 0x0004u /**< Connection is full/half duplex */\r
+\r
+\r
+/**\r
+ * Size of the max packet that can be received/transmited.\r
+ */\r
+#define MSS_MAX_PACKET_SIZE 1514uL\r
+\r
+/**\r
+ * Size of a receive/transmit buffer.\r
+ * Buffer size must be enough big to hold a full frame and must be multiple of\r
+ * four. For rx buffer +4 bytes allocated for crc values. These bytes doesn't\r
+ * copied to the user buffer.\r
+ */\r
+#define MSS_TX_BUFF_SIZE ((MSS_MAX_PACKET_SIZE + 3u) & (~(uint32_t)3))\r
+#define MSS_RX_BUFF_SIZE ((MSS_MAX_PACKET_SIZE + 7u) & (~(uint32_t)3))\r
+\r
+/*******************************************************************************\r
+ * Time out values.\r
+ */\r
+#define MSS_MAC_NONBLOCKING 0u\r
+#define MSS_MAC_BLOCKING 0xFFFFFFFFUL\r
+\r
+/***************************************************************************//**\r
+ * MAC events.\r
+ */\r
+#define MSS_MAC_EVENT_PACKET_SEND 1u\r
+#define MSS_MAC_EVENT_PACKET_RECEIVED 2u\r
+\r
+/***************************************************************************//**\r
+ * PHY addresses.\r
+ */\r
+#define MSS_PHY_ADDRESS_MIN 0u\r
+#define MSS_PHY_ADDRESS_MAX 31u\r
+#define MSS_PHY_ADDRESS_AUTO_DETECT 255u\r
+\r
+/***************************************************************************//**\r
+ * Listener function type defines the function prototype that might be followed \r
+ * by MAC_isr which is triggered with each receive and transmit related interrupts.\r
+ * Listener functions should follow the following prototype:\r
+ * void MAC_Listener( uint32_t events );\r
+ * The parameter is used to inform the listener function about the triggering event\r
+ * or events. Events input to the system are:\r
+ * #define MSS_MAC_EVENT_PACKET_SEND 1\r
+ * #define MSS_MAC_EVENT_PACKET_RECEIVED 2\r
+ * Listener function should be defined by the application using this driver if \r
+ * needed. This function may be assigned to the driver using MAC_set_callback\r
+ * routine and may be un assigned again by using the same routine with a NULL pointer\r
+ * as the event listener function. It is recommended to use this property for interrupt\r
+ * triggered systems and it is not recommended for polling mechanisms.\r
+ */\r
+typedef void (*MSS_MAC_callback_t)(uint32_t events);\r
+\r
+/***************************************************************************//**\r
+ * Statistics counter identifiers are used with MAC_get_statistics routine to \r
+ * receive the count of the requested errors/interrupts occurrences.\r
+ *\r
+ * MSS_MAC_RX_INTERRUPTS\r
+ * Used to receive the number of receive interrupts occurred.\r
+ *\r
+ * MSS_MAC_RX_FILTERING_FAIL\r
+ * Used to receive the number of received frames which did not pass the\r
+ * address recognition process.\r
+ *\r
+ * MSS_MAC_RX_DESCRIPTOR_ERROR\r
+ * Used to receive the number of occurrences of; no receive buffer was\r
+ * available when trying to store the received data.\r
+ *\r
+ * MSS_MAC_RX_RUNT_FRAME\r
+ * Used to receive the number of occurrences of; the frame is damaged by a\r
+ * collision or by a premature termination before the end of a collision\r
+ * window.\r
+ *\r
+ * MSS_MAC_RX_NOT_FIRST\r
+ * Used to receive the number of occurrences of; start of the frame is not\r
+ * the first descriptor of a frame.\r
+ *\r
+ * MSS_MAC_RX_NOT_LAST\r
+ * Used to receive the number of occurrences of; end of the frame is not\r
+ * the first descriptor of a frame.\r
+ *\r
+ * MSS_MAC_RX_FRAME_TOO_LONG\r
+ * Used to receive the number of occurrences of; a current frame is longer\r
+ * than maximum size of 1,518 bytes, as specified by 802.3.\r
+ *\r
+ * MSS_MAC_RX_COLLISION_SEEN\r
+ * Used to receive the number of occurrences of; a late collision was seen\r
+ * (collision after 64 bytes following SFD).\r
+ *\r
+ * MSS_MAC_RX_CRC_ERROR\r
+ * Used to receive the number of occurrences of; a CRC error has occurred\r
+ * in the received frame.\r
+ *\r
+ * MSS_MAC_RX_FIFO_OVERFLOW\r
+ * Used to receive the number of frames not accepted due to the receive\r
+ * FIFO overflow.\r
+ *\r
+ * MSS_MAC_RX_MISSED_FRAME\r
+ * Used to receive the number of frames not accepted due to the\r
+ * unavailability of the receive descriptor.\r
+ *\r
+ * MSS_MAC_TX_INTERRUPTS\r
+ * Used to receive the number of transmit interrupts occurred.\r
+ *\r
+ * MSS_MAC_TX_LOSS_OF_CARRIER\r
+ * Used to receive the number of occurrences of; a loss of the carrier\r
+ * during a transmission.\r
+ *\r
+ * MSS_MAC_TX_NO_CARRIER\r
+ * Used to receive the number of occurrences of; the carrier was not asserted\r
+ * by an external transceiver during the transmission.\r
+ *\r
+ * MSS_MAC_TX_LATE_COLLISION\r
+ * Used to receive the number of occurrences of; a collision was detected\r
+ * after transmitting 64 bytes.\r
+ *\r
+ * MSS_MAC_TX_EXCESSIVE_COLLISION\r
+ * Used to receive the number of occurrences of; the transmission was aborted\r
+ * after 16 retries.\r
+ *\r
+ * MSS_MAC_TX_COLLISION_COUNT\r
+ * Used to receive the number of collisions occurred.\r
+ *\r
+ * MSS_MAC_TX_UNDERFLOW_ERROR\r
+ * Used to receive the number of occurrences of; the FIFO was empty during\r
+ * the frame transmission.\r
+ */\r
+typedef enum {\r
+ MSS_MAC_RX_INTERRUPTS,\r
+ MSS_MAC_RX_FILTERING_FAIL,\r
+ MSS_MAC_RX_DESCRIPTOR_ERROR,\r
+ MSS_MAC_RX_RUNT_FRAME,\r
+ MSS_MAC_RX_NOT_FIRST,\r
+ MSS_MAC_RX_NOT_LAST,\r
+ MSS_MAC_RX_FRAME_TOO_LONG,\r
+ MSS_MAC_RX_COLLISION_SEEN,\r
+ MSS_MAC_RX_CRC_ERROR,\r
+ MSS_MAC_RX_FIFO_OVERFLOW,\r
+ MSS_MAC_RX_MISSED_FRAME,\r
+ \r
+ MSS_MAC_TX_INTERRUPTS,\r
+ MSS_MAC_TX_LOSS_OF_CARRIER,\r
+ MSS_MAC_TX_NO_CARRIER,\r
+ MSS_MAC_TX_LATE_COLLISION,\r
+ MSS_MAC_TX_EXCESSIVE_COLLISION,\r
+ MSS_MAC_TX_COLLISION_COUNT,\r
+ MSS_MAC_TX_UNDERFLOW_ERROR\r
+} mss_mac_statistics_id_t; \r
+\r
+/******************************* FUNCTIONS ************************************/\r
+\r
+/***************************************************************************//**\r
+ * Initializes an Ethernet MAC controller and data structures.\r
+ * This function will prepare the Ethernet Controller for first time use in a\r
+ * given hardware/software configuration. This function should be called before\r
+ * any other Ethernet API functions are called.\r
+ *\r
+ * Initialization of registers - config registers, enable Tx/Rx interrupts,\r
+ * enable Tx/Rx, initialize MAC addr, init PHY, autonegotiation, MAC address\r
+ * filter table (unicast/multicast)/hash init\r
+ *\r
+ */\r
+void\r
+MSS_MAC_init\r
+(\r
+ uint8_t phy_address\r
+);\r
+\r
+\r
+/***************************************************************************//**\r
+ * Sets the configuration of the Ethernet Controller.\r
+ * After the MAC_init function has been called, this API function can be\r
+ * used to configure the various features of the Ethernet Controller.\r
+ *\r
+ * @param configuration The logical OR of the following values:\r
+ * - #MSS_MAC_CFG_RECEIVE_ALL\r
+ * - #MSS_MAC_CFG_TRANSMIT_THRESHOLD_MODE\r
+ * - #MSS_MAC_CFG_STORE_AND_FORWARD\r
+ * - #MSS_MAC_CFG_THRESHOLD_CONTROL_[00,01,10,11]\r
+ * - #MSS_MAC_CFG_FULL_DUPLEX_MODE\r
+ * - #MSS_MAC_CFG_PASS_ALL_MULTICAST\r
+ * - #MSS_MAC_CFG_PROMISCUOUS_MODE\r
+ * - #MSS_MAC_CFG_PASS_BAD_FRAMES\r
+ * @see MAC_get_configuration()\r
+ */\r
+void\r
+MSS_MAC_configure\r
+(\r
+ uint32_t configuration\r
+);\r
+\r
+\r
+/***************************************************************************//**\r
+ * Returns the configuration of the Ethernet Controller.\r
+ * After the MAC_init function has been called, this API function can be used to \r
+ * get the configuration of the Ethernet Controller.\r
+ *\r
+ * @return The logical OR of the following values:\r
+ * - #MSS_MAC_CFG_RECEIVE_ALL\r
+ * - #MSS_MAC_CFG_TRANSMIT_THRESHOLD_MODE\r
+ * - #MSS_MAC_CFG_STORE_AND_FORWARD\r
+ * - #MSS_MAC_CFG_THRESHOLD_CONTROL_[00,01,10,11]\r
+ * - #MSS_MAC_CFG_FULL_DUPLEX_MODE\r
+ * - #MSS_MAC_CFG_PASS_ALL_MULTICAST\r
+ * - #MSS_MAC_CFG_PROMISCUOUS_MODE\r
+ * - #MSS_MAC_CFG_INVERSE_FILTERING\r
+ * - #MSS_MAC_CFG_PASS_BAD_FRAMES\r
+ * - #MSS_MAC_CFG_HASH_ONLY_FILTERING_MODE\r
+ * - #MSS_MAC_CFG_HASH_PERFECT_RECEIVE_FILTERING_MODE\r
+ * @see MAC_configure()\r
+ */\r
+int32_t\r
+MSS_MAC_get_configuration\r
+(\r
+ void\r
+);\r
+\r
+\r
+/***************************************************************************//**\r
+ * Sends a packet to the Ethernet Controller.\r
+ * This function writes pacLen bytes of the packet contained in pacData into the\r
+ * transmit FIFO of the controller and then activates the transmitter for this\r
+ * packet. If space is available in FIFO, the function will return once lBufLen\r
+ * bytes of the packet have been placed into the FIFO and the transmitter has been\r
+ * started. The function will not wait for the transmission to complete. If space\r
+ * is not available in FIFO, the function will keep trying till time_out expires,\r
+ * if MSS_MAC_BLOCKING value is given as time_out, function will wait for the\r
+ * transmission to complete.\r
+ *\r
+ * @param pacData the pointer to the packet data to be transmitted.\r
+ * @param pacLen number of bytes in the packet to be transmitted.\r
+ * @param time_out Time out value for transmision.\r
+ * If value is #MSS_MAC_BLOCKING, there will be no time out.\r
+ * If value is #MSS_MAC_NONBLOCKING, function will return immediately \r
+ * on buffer full case.\r
+ * Otherwise value must be greater than 0 and smaller than \r
+ * 0x01000000.\r
+ * @return Returns 0 if time out occurs otherwise returns size \r
+ * of the packet.\r
+ * @see MAC_rx_packet()\r
+ */\r
+int32_t\r
+MSS_MAC_tx_packet\r
+(\r
+ const uint8_t *pacData,\r
+ uint16_t pacLen,\r
+ uint32_t time_out\r
+);\r
+\r
+\r
+/***************************************************************************//**\r
+ * Returns available packet's size.\r
+ *\r
+ * @return Size of packet, bigger than 0, if a packet is available,\r
+ * if not, returns 0. \r
+ * @see MAC_rx_packet()\r
+ */\r
+int32_t\r
+MSS_MAC_rx_pckt_size\r
+(\r
+ void\r
+);\r
+\r
+\r
+\r
+/***************************************************************************//**\r
+ * Prepares the RX descriptor for receiving packets.\r
+ *\r
+ * @return void\r
+ * @see MAC_rx_packet()\r
+ */\r
+void\r
+MSS_MAC_prepare_rx_descriptor\r
+(\r
+ void\r
+);\r
+\r
+/***************************************************************************//**\r
+ * Receives a packet from the Ethernet Controller.\r
+ * This function reads a packet from the receive FIFO of the controller and\r
+ * places it into pacData. If time_out parameter is zero the function will return \r
+ * immediately (after the copy operation if data is available. Otherwise the function\r
+ * will keep trying to read till time_out expires or data is read, if MSS_MAC_BLOCKING \r
+ * value is given as time_out, function will wait for the reception to complete.\r
+ *\r
+ * @param pacData The pointer to the buffer where received packet data will\r
+ * be copied. Memory for the buffer should be allocated prior \r
+ * to calling this function.\r
+ * @param pacLen Size of the buffer, which the received data will be copied in,\r
+ * given in number of bytes.\r
+ * @param time_out Time out value in milli seconds for receiving.\r
+ * if value is #MSS_MAC_BLOCKING, there will be no time out.\r
+ * if value is #MSS_MAC_NONBLOCKING, function will return immediately\r
+ * if there is no packet waiting.\r
+ * Otherwise value must be greater than 0 and smaller than \r
+ * 0x01000000.\r
+ * @return Size of packet if packet fits in pacData.\r
+ * 0 if there is no received packet.\r
+ * @see MAC_rx_pckt_size()\r
+ * @see MAC_tx_packet()\r
+ */\r
+int32_t\r
+MSS_MAC_rx_packet\r
+(\r
+ uint8_t *pacData,\r
+ uint16_t pacLen,\r
+ uint32_t time_out\r
+);\r
+\r
+\r
+/***************************************************************************//**\r
+ Receives a packet from the Ethernet Controller.\r
+ The MSS_MAC_rx_packet_ptrset() function is very similar to the MSS_MAC_rx_packet()\r
+ function, in that it receives data from the MSS Ethernet MAC. The difference\r
+ is that it sets pacData to point to the memory buffer where the MSS Ethernet\r
+ MAC copied the received packet instead of copying the received packet into a\r
+ buffer provided by the application. After this function is called and data is\r
+ used by the user application or copied to another buffer, the\r
+ MSS_MAC_prepare_rx_descriptor() function must be called to free up the receive\r
+ memory buffer used by the MSS Ethernet MAC\r
+ \r
+ @param pacData\r
+ The pacData parameter is a pointer to a memory buffer pointer. The uint8_t\r
+ pointer pointed to by the pacData parameter will contain the address of the\r
+ memory buffer containing the received packet after this function returns. The\r
+ value of pacData is only valid if the return value is larger than zero,\r
+ indicating that a packet was received.\r
+ \r
+ @param time_out\r
+ The time_out parameter is the timeout value for the transmission in milliseconds.\r
+ The time_out parameter value can be one of the following values:\r
+ \95 Unsigned integer greater than 0 and less than 0x01000000\r
+ \95 MSS_MAC_BLOCKING \96 there will be no timeout. \r
+ \95 MSS_MAC_NONBLOCKING \96 the function will return immediately if no packets\r
+ have been received. \r
+\r
+ @return\r
+ The function returns the size of the packet if the packet fits in pacData.\r
+ Returns zero if there is no received packet.\r
+ \r
+ @see MAC_rx_pckt_size()\r
+ @see MAC_tx_packet()\r
+ */\r
+int32_t\r
+MSS_MAC_rx_packet_ptrset\r
+(\r
+ uint8_t **pacData,\r
+ uint32_t time_out\r
+);\r
+\r
+/***************************************************************************//**\r
+ * Returns the status of connection by reading it from the PHY.\r
+ *\r
+ * @return the logical OR of the following values:\r
+ * #MSS_MAC_LINK_STATUS_LINK - Link up/down\r
+ * #MSS_MAC_LINK_STATUS_100MB - Connection is 100Mb/10Mb\r
+ * #MSS_MAC_LINK_STATUS_FDX - Connection is full/half duplex\r
+ * @see MAC_auto_setup_link()\r
+ */\r
+int32_t\r
+MSS_MAC_link_status\r
+(\r
+ void\r
+);\r
+\r
+\r
+/***************************************************************************//**\r
+ * Setups the link between PHY and MAC and returns the status of connection.\r
+ *\r
+ * @return the logical OR of the following values:\r
+ * #MSS_MAC_LINK_STATUS_LINK - Link up/down\r
+ * #MSS_MAC_LINK_STATUS_100MB - Connection is 100Mb/10Mb\r
+ * #MSS_MAC_LINK_STATUS_FDX - Connection is full/half duplex\r
+ * @see MAC_link_status()\r
+ */\r
+int32_t\r
+MSS_MAC_auto_setup_link\r
+(\r
+ void\r
+);\r
+\r
+\r
+/***************************************************************************//**\r
+ * Sets mac address.\r
+ *\r
+ * @param new_address Pointer to then new address value (6 bytes of data)\r
+ * @see MAC_get_mac_address()\r
+ */\r
+void\r
+MSS_MAC_set_mac_address\r
+(\r
+ const uint8_t *new_address\r
+);\r
+\r
+\r
+/***************************************************************************//**\r
+ * Returns mac address.\r
+ *\r
+ * @param address Pointer to the parameter to receive the MAC address.\r
+ * @see MAC_set_mac_address()\r
+ */\r
+void\r
+MSS_MAC_get_mac_address\r
+(\r
+ uint8_t *address\r
+);\r
+\r
+\r
+/***************************************************************************//**\r
+ * Sets mac address filters.\r
+ * If less than 15 addresses are subscribed, system works on perfect filtering mode\r
+ * else system works in hash table mode\r
+ *\r
+ * @param filter_count number of addresses\r
+ * @param filters Pointer to addresses to be filtered\r
+ */\r
+void\r
+MSS_MAC_set_mac_filters\r
+(\r
+ uint16_t filter_count,\r
+ const uint8_t *filters\r
+);\r
+\r
+/***************************************************************************//**\r
+ * Sets MAC event listener.\r
+ * Sets the given event listener function to be triggered inside MAC_isr().\r
+ * Assigning NULL pointer as the listener function will disable it.\r
+ *\r
+ * @param listener function pointer to a MSS_MAC_callback_t function\r
+ * @see MAC_isr()\r
+ */\r
+void\r
+MSS_MAC_set_callback\r
+(\r
+ MSS_MAC_callback_t listener\r
+);\r
+\r
+\r
+/***************************************************************************//**\r
+ * Returns description of latest error happened.\r
+ *\r
+ * @return A string describing the error. This string must not be \r
+ * modified by the application.\r
+ */\r
+const int8_t* \r
+MSS_MAC_last_error\r
+(\r
+ void\r
+);\r
+\r
+\r
+/***************************************************************************//**\r
+ * Returns statistics counter of stat_id identifier.\r
+ * \r
+ * @param stat_id Identifier of statistics counter.\r
+ * @return Statistics counter of stat_id identifier.\r
+ * On error returns 0.\r
+ */\r
+uint32_t\r
+MSS_MAC_get_statistics\r
+(\r
+ mss_mac_statistics_id_t stat_id\r
+);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __MSS_ETHERNET_MAC_H */\r
+\r
--- /dev/null
+/***************************************************************************//**\r
+ * @file\r
+ * SmartFusion MSS Ethenet MAC configuration header file.\r
+ *\r
+ * (c) Copyright 2007 Actel Corporation\r
+ *\r
+ * SVN $Revision: 2299 $\r
+ * SVN $Date: 2010-02-24 21:21:12 +0000 (Wed, 24 Feb 2010) $\r
+ *******************************************************************************/\r
+#ifndef __MSS_ETHERNET_MAC_CONF_H\r
+#define __MSS_ETHERNET_MAC_CONF_H 1\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif \r
+\r
+/**\r
+ * Default MAC address\r
+ */\r
+#define DEFAULT_MAC_ADDRESS 0xC0u,0xB1u,0x3Cu,0x88u,0x88u,0x88u\r
+#define BROADCAST_MAC_ADDRESS 0xFFu,0xFFu,0xFFu,0xFFu,0xFFu,0xFFu\r
+\r
+/**\r
+ * Descriptor byte ordering mode.\r
+ * 1 - Big-endian mode used for data descriptors <br>\r
+ * 0 - Little-endian mode used for data descriptors <br>\r
+ */\r
+#define DESCRIPTOR_BYTE_ORDERING_MODE LITTLEENDIAN\r
+\r
+/**\r
+ * Big/little endian.\r
+ * Selects the byte-ordering mode used by the data buffers.\r
+ * 1 - Big-endian mode used for the data buffers\r
+ * 0 - Little-endian mode used for the data buffers\r
+ */\r
+#define BUFFER_BYTE_ORDERING_MODE LITTLEENDIAN\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __MSS_ETHERNET_MAC_CONF_H */\r
+\r
--- /dev/null
+/***************************************************************************//**\r
+ * @file\r
+ * SmartFusion MSS Ethernet MAC internal defines header file.\r
+ *\r
+ * (c) Copyright 2007 Actel Corporation\r
+ *\r
+ * SVN $Revision: 2299 $\r
+ * SVN $Date: 2010-02-24 21:21:12 +0000 (Wed, 24 Feb 2010) $\r
+ *******************************************************************************/\r
+#ifndef __MSS_ETHERNET_MAC_DESC_H\r
+#define __MSS_ETHERNET_MAC_DESC_H 1\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif \r
+\r
+/*******************************************************************************\r
+ * Receive descriptor bits\r
+ */\r
+\r
+/***************************************************************************//**\r
+ * Ownership bit.\r
+ * 1 - Core10/100 owns the descriptor. <br>\r
+ * 0 - The host owns the descriptor. <br>\r
+ * Core10/100 will clear this bit when it completes a current frame reception or \r
+ * when the data buffers associated with a given descriptor are already full.\r
+ */\r
+#define RDES0_OWN 0x80000000UL\r
+\r
+/***************************************************************************//**\r
+ * Filtering fail.\r
+ * When set, indicates that a received frame did not pass the address recognition process.\r
+ * This bit is valid only for the last descriptor of the frame (RDES0.8 set), when the CSR6.30 (receive all) bit\r
+ * is set and the frame is at least 64 bytes long.\r
+ */\r
+#define RDES0_FF 0x40000000UL\r
+\r
+/***************************************************************************//**\r
+ * Frame length.\r
+ * Indicates the length, in bytes, of the data transferred into a host memory for a given frame\r
+ * This bit is valid only when RDES0.8 (last descriptor) is set and RDES0.14 (descriptor error) is cleared.\r
+ */\r
+#define RDES0_FL_MASK 0x00003FFFUL\r
+#define RDES0_FL_OFFSET 16\r
+\r
+/***************************************************************************//**\r
+ * Error summary.\r
+ * This bit is a logical OR of the following bits:\r
+ * RDES0.1 - CRC error\r
+ * RDES0.6 - Collision seen\r
+ * RDES0.7 - Frame too long\r
+ * RDES0.11 - Runt frame\r
+ * RDES0.14 - Descriptor error\r
+ * This bit is valid only when RDES0.8 (last descriptor) is set.\r
+ */\r
+#define RDES0_ES 0x00008000UL\r
+\r
+/***************************************************************************//**\r
+ * Descriptor error.\r
+ * Set by Core10/100 when no receive buffer was available when trying to store the received data.\r
+ * This bit is valid only when RDES0.8 (last descriptor) is set.\r
+ */\r
+#define RDES0_DE 0x00004000UL\r
+\r
+/***************************************************************************//**\r
+ * Runt frame.\r
+ * When set, indicates that the frame is damaged by a collision or by a premature termination before the end\r
+ * of a collision window.\r
+ * This bit is valid only when RDES0.8 (last descriptor) is set.\r
+ */\r
+#define RDES0_RF 0x00000800UL\r
+\r
+/***************************************************************************//**\r
+ * Multicast frame.\r
+ * When set, indicates that the frame has a multicast address.\r
+ * This bit is valid only when RDES0.8 (last descriptor) is set.\r
+ */\r
+#define RDES0_MF 0x00000400UL\r
+\r
+/***************************************************************************//**\r
+ * First descriptor.\r
+ * When set, indicates that this is the first descriptor of a frame.\r
+ */\r
+#define RDES0_FS 0x00000200UL\r
+\r
+/***************************************************************************//**\r
+ * Last descriptor.\r
+ * When set, indicates that this is the last descriptor of a frame.\r
+ */\r
+#define RDES0_LS 0x00000100UL\r
+\r
+/***************************************************************************//**\r
+ * Frame too long.\r
+ * When set, indicates that a current frame is longer than maximum size of 1,518 bytes, as specified by 802.3.\r
+ * TL (frame too long) in the receive descriptor has been set when the received frame is longer than\r
+ * 1,518 bytes. This flag is valid in all receive descriptors when multiple descriptors are used for one frame.\r
+ */\r
+#define RDES0_TL 0x00000080UL\r
+\r
+/***************************************************************************//**\r
+ * Collision seen.\r
+ * When set, indicates that a late collision was seen (collision after 64 bytes following SFD).\r
+ * This bit is valid only when RDES0.8 (last descriptor) is set.\r
+ */\r
+#define RDES0_CS 0x00000040UL\r
+\r
+/***************************************************************************//**\r
+ * Frame type.\r
+ * When set, indicates that the frame has a length field larger than 1,500 (Ethernet-type frame). When\r
+ * cleared, indicates an 802.3-type frame.\r
+ * This bit is valid only when RDES0.8 (last descriptor) is set.\r
+ * Additionally, FT is invalid for runt frames shorter than 14 bytes.\r
+ */\r
+#define RDES0_FT 0x00000020UL\r
+\r
+/***************************************************************************//**\r
+ * Report on MII error.\r
+ * When set, indicates that an error has been detected by a physical layer chip connected through the MII\r
+ * interface.\r
+ * This bit is valid only when RDES0.8 (last descriptor) is set.\r
+ */\r
+#define RDES0_RE 0x00000008UL\r
+\r
+/***************************************************************************//**\r
+ * Dribbling bit.\r
+ * When set, indicates that the frame was not byte-aligned.\r
+ * This bit is valid only when RDES0.8 (last descriptor) is set.\r
+ */\r
+#define RDES0_DB 0x00000004UL\r
+\r
+/***************************************************************************//**\r
+ * CRC error.\r
+ * When set, indicates that a CRC error has occurred in the received frame.\r
+ * This bit is valid only when RDES0.8 (last descriptor) is set.\r
+ * Additionally, CE is not valid when the received frame is a runt frame.\r
+ */\r
+#define RDES0_CE 0x00000002UL\r
+\r
+/***************************************************************************//**\r
+ * This bit is reset for frames with a legal length.\r
+ */\r
+#define RDES0_ZERO 0x00000001UL\r
+\r
+/***************************************************************************//**\r
+ * Receive end of ring.\r
+ * When set, indicates that this is the last descriptor in the receive descriptor ring. Core10/100 returns to the\r
+ * first descriptor in the ring, as specified by CSR3 (start of receive list address).\r
+ */\r
+#define RDES1_RER 0x02000000UL\r
+\r
+/***************************************************************************//**\r
+ * Second address chained.\r
+ * When set, indicates that the second buffer's address points to the next descriptor and not to the data buffer.\r
+ * Note that RER takes precedence over RCH.\r
+ */\r
+#define RDES1_RCH 0x01000000UL\r
+\r
+/***************************************************************************//**\r
+ * Buffer 2 size.\r
+ * Indicates the size, in bytes, of memory space used by the second data buffer. This number must be a\r
+ * multiple of four. If it is 0, Core10/100 ignores the second data buffer and fetches the next data descriptor.\r
+ * This number is valid only when RDES1.24 (second address chained) is cleared.\r
+ */\r
+#define RDES1_RBS2_MASK 0x7FF\r
+#define RDES1_RBS2_OFFSET 11\r
+\r
+/***************************************************************************//**\r
+ * Buffer 1 size\r
+ * Indicates the size, in bytes, of memory space used by the first data buffer. This number must be a multiple of\r
+ * four. If it is 0, Core10/100 ignores the first data buffer and uses the second data buffer.\r
+ */\r
+#define RDES1_RBS1_MASK 0x7FF\r
+#define RDES1_RBS1_OFFSET 0\r
+\r
+\r
+/*******************************************************************************\r
+ * Transmit descriptor bits\r
+ */\r
+\r
+/***************************************************************************//**\r
+ * Ownership bit.\r
+ * 1 - Core10/100 owns the descriptor.\r
+ * 0 - The host owns the descriptor.\r
+ * Core10/100 will clear this bit when it completes a current frame transmission or when the data buffers\r
+ * associated with a given descriptor are empty.\r
+ */\r
+#define TDES0_OWN 0x80000000uL\r
+\r
+/***************************************************************************//**\r
+ * Error summary.\r
+ * This bit is a logical OR of the following bits:\r
+ * TDES0.1 - Underflow error\r
+ * TDES0.8 - Excessive collision error\r
+ * TDES0.9 - Late collision\r
+ * TDES0.10 - No carrier\r
+ * TDES0.11 - Loss of carrier\r
+ * This bit is valid only when TDES1.30 (last descriptor) is set.\r
+ */\r
+#define TDES0_ES ((uint32_t)1 << 15)\r
+\r
+/***************************************************************************//**\r
+ * Loss of carrier.\r
+ * When set, indicates a loss of the carrier during a transmission.\r
+ * This bit is valid only when TDES1.30 (last descriptor) is set.\r
+ */\r
+#define TDES0_LO ((uint32_t)1 << 11)\r
+\r
+/***************************************************************************//**\r
+ * No carrier.\r
+ * When set, indicates that the carrier was not asserted by an external transceiver during the transmission.\r
+ * This bit is valid only when TDES1.30 (last descriptor) is set.\r
+ */\r
+#define TDES0_NC ((uint32_t)1 << 10)\r
+\r
+/***************************************************************************//**\r
+ * Late collision.\r
+ * When set, indicates that a collision was detected after transmitting 64 bytes.\r
+ * This bit is not valid when TDES0.1 (underflow error) is set.\r
+ * This bit is valid only when TDES1.30 (last descriptor) is set.\r
+ */\r
+#define TDES0_LC ((uint32_t)1 << 9)\r
+\r
+/***************************************************************************//**\r
+ * Excessive collisions.\r
+ * When set, indicates that the transmission was aborted after 16 retries.\r
+ * This bit is valid only when TDES1.30 (last descriptor) is set.\r
+ */\r
+#define TDES0_EC ((uint32_t)1 << 8)\r
+\r
+/***************************************************************************//**\r
+ * Collision count.\r
+ * This field indicates the number of collisions that occurred before the end of a frame transmission.\r
+ * This value is not valid when TDES0.8 (excessive collisions bit) is set.\r
+ * This bit is valid only when TDES1.30 (last descriptor) is set.\r
+ */\r
+#define TDES0_CC_MASK 0xFu\r
+#define TDES0_CC_OFFSET 3u\r
+\r
+/***************************************************************************//**\r
+ * Underflow error.\r
+ * When set, indicates that the FIFO was empty during the frame transmission.\r
+ * This bit is valid only when TDES1.30 (last descriptor) is set.\r
+ */\r
+#define TDES0_UF ((uint32_t)1 << 1)\r
+\r
+/***************************************************************************//**\r
+ * Deferred.\r
+ * When set, indicates that the frame was deferred before transmission. Deferring occurs if the carrier is detected\r
+ * when the transmission is ready to start.\r
+ * This bit is valid only when TDES1.30 (last descriptor) is set.\r
+ */\r
+#define TDES0_DE (1)\r
+\r
+/***************************************************************************//**\r
+ * Interrupt on completion.\r
+ * Setting this flag instructs Core10/100 to set CSR5.0 (transmit interrupt) immediately after processing a\r
+ * current frame.\r
+ * This bit is valid when TDES1.30 (last descriptor) is set or for a setup packet.\r
+ */\r
+#define TDES1_IC ((uint32_t)1 << 31)\r
+\r
+/***************************************************************************//**\r
+ * Last descriptor.\r
+ * When set, indicates the last descriptor of the frame.\r
+ */\r
+#define TDES1_LS ((uint32_t)1 << 30)\r
+\r
+/***************************************************************************//**\r
+ * First descriptor.\r
+ * When set, indicates the first descriptor of the frame.\r
+ */\r
+#define TDES1_FS ((uint32_t)1 << 29)\r
+\r
+/***************************************************************************//**\r
+ * Filtering type.\r
+ * This bit, together with TDES0.22 (FT0), controls a current filtering mode.\r
+ * This bit is valid only for the setup frames.\r
+ */\r
+#define TDES1_FT1 ((uint32_t)1 << 28)\r
+\r
+/***************************************************************************//**\r
+ * Setup packet.\r
+ * When set, indicates that this is a setup frame descriptor.\r
+ */\r
+#define TDES1_SET ((uint32_t)1 << 27)\r
+\r
+/***************************************************************************//**\r
+ * Add CRC disable.\r
+ * When set, Core10/100 does not append the CRC value at the end of the frame. The exception is when the\r
+ * frame is shorter than 64 bytes and automatic byte padding is enabled. In that case, the CRC field is added,\r
+ * despite the state of the AC flag.\r
+ */\r
+#define TDES1_AC ((uint32_t)1 << 26)\r
+\r
+/***************************************************************************//**\r
+ * Transmit end of ring.\r
+ * When set, indicates the last descriptor in the descriptor ring.\r
+ */\r
+#define TDES1_TER ((uint32_t)1 << 25)\r
+\r
+/***************************************************************************//**\r
+ * Second address chained.\r
+ * When set, indicates that the second descriptor's address points to the next descriptor and not to the data\r
+ * buffer.\r
+ * This bit is valid only when TDES1.25 (transmit end of ring) is reset.\r
+ */\r
+#define TDES1_TCH ((uint32_t)1 << 24)\r
+\r
+/***************************************************************************//**\r
+ * Disabled padding.\r
+ * When set, automatic byte padding is disabled. Core10/100 normally appends the PAD field after the INFO\r
+ * field when the size of an actual frame is less than 64 bytes. After padding bytes, the CRC field is also\r
+ * inserted, despite the state of the AC flag. When DPD is set, no padding bytes are appended.\r
+ */\r
+#define TDES1_DPD ((uint32_t)1 << 23)\r
+\r
+/***************************************************************************//**\r
+ * Filtering type.\r
+ * This bit, together with TDES0.28 (FT1), controls the current filtering mode.\r
+ * This bit is valid only when the TDES1.27 (SET) bit is set.\r
+ */\r
+#define TDES1_FT0 ((uint32_t)1 << 22)\r
+\r
+/***************************************************************************//**\r
+ * Buffer 2 size.\r
+ * Indicates the size, in bytes, of memory space used by the second data buffer. If it is zero, Core10/100 ignores\r
+ * the second data buffer and fetches the next data descriptor.\r
+ * This bit is valid only when TDES1.24 (second address chained) is cleared.\r
+ */\r
+#define TDES1_TBS2_MASK 0x7FF\r
+#define TDES1_TBS2_OFFSET 11u\r
+\r
+/***************************************************************************//**\r
+ * Buffer 1 size.\r
+ * Indicates the size, in bytes, of memory space used by the first data buffer. If it is 0, Core10/100 ignores the\r
+ * first data buffer and uses the second data buffer.\r
+ */\r
+#define TDES1_TBS1_MASK 0x7FF\r
+#define TDES1_TBS1_OFFSET 0u\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __MSS_ETHERNET_MAC_DESC_H */\r
+\r
--- /dev/null
+/***************************************************************************//**\r
+ * @file\r
+ * SmartFusion MSS Ethernet MAC registers.\r
+ *\r
+ * (c) Copyright 2007 Actel Corporation\r
+ *\r
+ * IP core registers definitions. This file contains the definitions required\r
+ * for accessing the IP core through the hardware abstraction layer (HAL).\r
+ * This file was automatically generated, using "get_header.exe" version 0.4.0,\r
+ * from the IP-XACT description for:\r
+ *\r
+ *\r
+ * SVN $Revision: 2364 $\r
+ * SVN $Date: 2010-03-01 17:58:41 +0000 (Mon, 01 Mar 2010) $\r
+ *\r
+ *******************************************************************************/\r
+#ifndef MSS_ETHERNET_MAC_REGISTERS_H_\r
+#define MSS_ETHERNET_MAC_REGISTERS_H_\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif \r
+\r
+#include "../../CMSIS/a2fxxxm3.h"\r
+#include "mss_ethernet_mac.h"\r
+#include "mss_ethernet_mac_user_cfg.h"\r
+ \r
+typedef uint32_t addr_t;\r
+\r
+\r
+/***************************************************************************//**\r
+ * Descriptor structure\r
+ */\r
+typedef struct {\r
+ volatile uint32_t descriptor_0;\r
+ volatile uint32_t descriptor_1;\r
+ volatile uint32_t buffer_1;\r
+ volatile uint32_t buffer_2;\r
+} MAC_descriptor_t;\r
+\r
+\r
+/***************************************************************************//**\r
+ * There should be one instance of this structure for each instance of\r
+ * the MAC in your system. MSS_MAC_init routine initializes this structure.\r
+ * It is used to identify the various MACs in your system and an initilized \r
+ * MAC instance's structure should be passed as first parameter to MAC functions \r
+ * to identify which MAC should perform the requested operation.\r
+ * Software using the MAC driver should only need to create one single \r
+ * instance of this data structure for each MAC hardware instance in \r
+ * the system. Using MAC_get_configuration routine, latest status of the driver\r
+ * may be read by receiving its flags field, similarly MAC_configure routine lets\r
+ * you modify some of these flags.\r
+ */\r
+typedef struct {\r
+ addr_t base_address; /**< Register base address of the driver*/\r
+ uint8_t flags; /**< Configuration of the driver*/\r
+ int8_t last_error; /**< Index of last error happened inside the driver*/\r
+ uint8_t mac_address[6]; /**< MAC address of the drived instance*/\r
+ uint8_t mac_filter_data[90]; /**< MAC filter data, 15 addresses to be used for \r
+ received data filtering*/\r
+ uint16_t last_timer_value; /**< Last read value of timer */\r
+ uint32_t time_out_value; /**< Time out value */\r
+ MSS_MAC_callback_t listener; /**< Pointer to the call-back function to be triggered \r
+ when a package is received*/\r
+\r
+ /* transmit related info: */\r
+ uint32_t tx_desc_index; /**< index of the transmit descriptor getting used*/\r
+ uint8_t tx_buffers[TX_RING_SIZE][MSS_TX_BUFF_SIZE];/**< array of transmit buffers*/\r
+ MAC_descriptor_t tx_descriptors[TX_RING_SIZE];/**< array of transmit descriptors*/\r
+\r
+ /* receive related info: */\r
+ uint32_t rx_desc_index; /**< index of the receive descriptor getting used*/\r
+ uint8_t rx_buffers[RX_RING_SIZE][MSS_RX_BUFF_SIZE+4];/**< array of receive buffers*/\r
+ MAC_descriptor_t rx_descriptors[RX_RING_SIZE];/**< array of receive descriptors*/\r
+ \r
+ uint8_t phy_address; /**< MII address of the connected PHY*/\r
+ \r
+ struct {\r
+ uint32_t rx_interrupts; /**< Number of receive interrupts occurred.*/\r
+ uint32_t rx_filtering_fail; /**< Number of received frames which did not pass \r
+ the address recognition process.*/\r
+ uint32_t rx_descriptor_error; /**< Number of occurrences of; no receive buffer was\r
+ available when trying to store the received data.*/\r
+ uint32_t rx_runt_frame; /**< Number of occurrences of; the frame is damaged by \r
+ a collision or by a premature termination before \r
+ the end of a collision window.*/\r
+ uint32_t rx_not_first; /**< Number of occurrences of; start of the frame is \r
+ not the first descriptor of a frame.*/\r
+ uint32_t rx_not_last; /**< Number of occurrences of; end of the frame is not \r
+ the first descriptor of a frame.*/\r
+ uint32_t rx_frame_too_long; /**< Number of occurrences of; a current frame is \r
+ longer than maximum size of 1,518 bytes, as specified \r
+ by 802.3.*/\r
+ uint32_t rx_collision_seen; /**< Number of occurrences of; a late collision was seen \r
+ (collision after 64 bytes following SFD).*/\r
+ uint32_t rx_crc_error; /**< Number of occurrences of; a CRC error has occurred \r
+ in the received frame.*/\r
+ uint32_t rx_fifo_overflow; /**< Number of frames not accepted due to the receive \r
+ FIFO overflow.*/\r
+ uint32_t rx_missed_frame; /**< Number of frames not accepted due to the \r
+ unavailability of the receive descriptor.*/\r
+ \r
+ uint32_t tx_interrupts; /**< Number of transmit interrupts occurred.*/\r
+ uint32_t tx_loss_of_carrier; /**< Number of occurrences of; a loss of the carrier \r
+ during a transmission.*/\r
+ uint32_t tx_no_carrier; /**< Number of occurrences of; the carrier was not asserted\r
+ by an external transceiver during the transmission.*/\r
+ uint32_t tx_late_collision; /**< Number of occurrences of; a collision was detected \r
+ after transmitting 64 bytes.*/\r
+ uint32_t tx_excessive_collision;/**< Number of occurrences of; the transmission was \r
+ aborted after 16 retries.*/\r
+ uint32_t tx_collision_count; /**< Number of collisions occurred.*/\r
+ uint32_t tx_underflow_error; /**< Number of occurrences of; the FIFO was empty during \r
+ the frame transmission.*/\r
+ } statistics;\r
+} MAC_instance_t;\r
+\r
+\r
+/*------------------------------------------------------------------------------\r
+ *\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t CSR0_SWR;\r
+ uint32_t CSR0_BAR;\r
+ uint32_t CSR0_DSL[5];\r
+ uint32_t CSR0_BLE;\r
+ uint32_t CSR0_PBL[6];\r
+ uint32_t CSR0_RESERVED0[3];\r
+ uint32_t CSR0_TAP[3];\r
+ uint32_t CSR0_DBO;\r
+ uint32_t CSR0_RESERVED1[11];\r
+ \r
+ uint32_t MAC_CSR_RESERVED0[32];\r
+ \r
+ uint32_t CSR1[32];\r
+ \r
+ uint32_t MAC_CSR_RESERVED1[32];\r
+ \r
+ uint32_t CSR2[32];\r
+ \r
+ uint32_t MAC_CSR_RESERVED2[32];\r
+ \r
+ uint32_t CSR3[32];\r
+ \r
+ uint32_t MAC_CSR_RESERVED3[32];\r
+ \r
+ uint32_t CSR4[32];\r
+ \r
+ uint32_t MAC_CSR_RESERVED4[32];\r
+ \r
+ uint32_t CSR5_TI;\r
+ uint32_t CSR5_TPS;\r
+ uint32_t CSR5_TU;\r
+ uint32_t CSR5_RESERVED0[2]; \r
+ uint32_t CSR5_UNF;\r
+ uint32_t CSR5_RI;\r
+ uint32_t CSR5_RU;\r
+ uint32_t CSR5_RPS;\r
+ uint32_t CSR5_RESERVED1;\r
+ uint32_t CSR5_ETI;\r
+ uint32_t CSR5_GTE;\r
+ uint32_t CSR5_RESERVED2[2];\r
+ uint32_t CSR5_ERI;\r
+ uint32_t CSR5_AIS;\r
+ uint32_t CSR5_NIS;\r
+ uint32_t CSR5_RS[3];\r
+ uint32_t CSR5_TS[3];\r
+ uint32_t CSR5_RESERVED3[9];\r
+\r
+ uint32_t MAC_CSR_RESERVED5[32];\r
+ \r
+ uint32_t CSR6_HP;\r
+ uint32_t CSR6_SR;\r
+ uint32_t CSR6_HO;\r
+ uint32_t CSR6_PB;\r
+ uint32_t CSR6_IF;\r
+ uint32_t CSR6_RESERVED0;\r
+ uint32_t CSR6_PR;\r
+ uint32_t CSR6_PM;\r
+ uint32_t CSR6_RESERVED1;\r
+ uint32_t CSR6_FD;\r
+ uint32_t CSR6_RESERVED2[3];\r
+ uint32_t CSR6_ST;\r
+ uint32_t CSR6_TR[2];\r
+ uint32_t CSR6_RESERVED3[5];\r
+ uint32_t CSR6_SF;\r
+ uint32_t CSR6_TTM;\r
+ uint32_t CSR6_RESERVED4[7];\r
+ uint32_t CSR6_RA;\r
+ uint32_t CSR6_RESERVED5;\r
+\r
+ uint32_t MAC_CSR_RESERVED6[32];\r
+ \r
+ uint32_t CSR7_TIE;\r
+ uint32_t CSR7_TSE;\r
+ uint32_t CSR7_TUE;\r
+ uint32_t CSR7_RESERVED0[2];\r
+ uint32_t CSR7_UNE;\r
+ uint32_t CSR7_RIE;\r
+ uint32_t CSR7_RUE;\r
+ uint32_t CSR7_RSE;\r
+ uint32_t CSR7_RESERVED1;\r
+ uint32_t CSR7_ETE;\r
+ uint32_t CSR7_GTE;\r
+ uint32_t CSR7_RESERVED2[2];\r
+ uint32_t CSR7_ERE;\r
+ uint32_t CSR7_AIE;\r
+ uint32_t CSR7_NIE;\r
+ uint32_t CSR7[15];\r
+\r
+ uint32_t MAC_CSR_RESERVED7[32];\r
+ \r
+ uint32_t CSR8[32];\r
+\r
+ uint32_t MAC_CSR_RESERVED8[32];\r
+ \r
+ uint32_t CSR9_SCS;\r
+ uint32_t CSR9_SCLK;\r
+ uint32_t CSR9_SDI;\r
+ uint32_t CSR9_SDO;\r
+ uint32_t CSR9_RESERVED0[12];\r
+ uint32_t CSR9_MDC;\r
+ uint32_t CSR9_MDO;\r
+ uint32_t CSR9_MDEN;\r
+ uint32_t CSR9_MDI;\r
+ uint32_t CSR9_RESERVED1[12];\r
+\r
+ uint32_t MAC_CSR_RESERVED9[32];\r
+ \r
+ uint32_t CSR10[32];\r
+\r
+ uint32_t MAC_CSR_RESERVED10[32];\r
+ \r
+ uint32_t CSR11_TIM[16];\r
+ uint32_t CSR11_CON;\r
+ uint32_t CSR11_NRP[3];\r
+ uint32_t CSR11_RT[4];\r
+ uint32_t CSR11_NTP[3];\r
+ uint32_t CSR11_TT[4];\r
+ uint32_t CSR11_CS;\r
+} MAC_BitBand_TypeDef;\r
+\r
+#define MAC_BITBAND ((MAC_BitBand_TypeDef *) BITBAND_ADDRESS(MAC_BASE))\r
+\r
+/*******************************************************************************\r
+ * CSR0 register:\r
+ *------------------------------------------------------------------------------\r
+ * CSR0 - Bus Mode Register\r
+ */\r
+#define CSR0_REG_OFFSET 0x00\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR0_DBO:\r
+ * DBO field of register CSR0.\r
+ *------------------------------------------------------------------------------\r
+ * Descriptor byte ordering mode\r
+ */\r
+#define CSR0_DBO_OFFSET 0x00\r
+#define CSR0_DBO_MASK 0x00100000UL\r
+#define CSR0_DBO_SHIFT 20\r
+\r
+/*\r
+ * Allowed values for CSR0_DBO:\r
+ *------------------------------------------------------------------------------\r
+ * LITTLEENDIAN: Little endian mode used for data descriptors\r
+ * BIGENDIAN: Big endian mode used for data descriptors\r
+ */\r
+#define LITTLEENDIAN 0u\r
+#define BIGENDIAN 1u\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR0_TAP:\r
+ * TAP field of register CSR0.\r
+ *------------------------------------------------------------------------------\r
+ * Transmit automatic polling\r
+ */\r
+#define CSR0_TAP_OFFSET 0x00\r
+#define CSR0_TAP_MASK 0x000E0000UL\r
+#define CSR0_TAP_SHIFT 17\r
+\r
+/*\r
+ * Allowed values for CSR0_TAP:\r
+ *------------------------------------------------------------------------------\r
+ * TAP_DISABLED: TAP disabled\r
+ * TAP_819US: TAP 819/81.9us\r
+ * TAP_2450US: TAP 2450/245us\r
+ * TAP_5730US: TAP 5730/573us\r
+ * TAP_51_2US: TAP 51.2/5.12us\r
+ * TAP_102_4US: TAP 102.4/10.24us\r
+ * TAP_153_6US: TAP 156.6/15.26us\r
+ * TAP_358_4US: TAP 358.4/35.84us\r
+ */\r
+#define TAP_DISABLED 0x0\r
+#define TAP_819US 0x1\r
+#define TAP_2450US 0x2\r
+#define TAP_5730US 0x3\r
+#define TAP_51_2US 0x4\r
+#define TAP_102_4US 0x5\r
+#define TAP_153_6US 0x6\r
+#define TAP_358_4US 0x7\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR0_PBL:\r
+ * PBL field of register CSR0.\r
+ *------------------------------------------------------------------------------\r
+ * Programmable burst length\r
+ */\r
+#define CSR0_PBL_OFFSET 0x00\r
+#define CSR0_PBL_MASK 0x00003F00uL\r
+#define CSR0_PBL_SHIFT 8\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR0_BLE:\r
+ * BLE field of register CSR0.\r
+ *------------------------------------------------------------------------------\r
+ * Big/little endian\r
+ */\r
+#define CSR0_BLE_OFFSET 0x00\r
+#define CSR0_BLE_MASK 0x00000080uL\r
+#define CSR0_BLE_SHIFT 7\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR0_DSL:\r
+ * DSL field of register CSR0.\r
+ *------------------------------------------------------------------------------\r
+ * Descriptor skip length\r
+ */\r
+#define CSR0_DSL_OFFSET 0x00\r
+#define CSR0_DSL_MASK 0x0000007CuL\r
+#define CSR0_DSL_SHIFT 2\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR0_BAR:\r
+ * BAR field of register CSR0.\r
+ *------------------------------------------------------------------------------\r
+ * Bus arbitration scheme\r
+ */\r
+#define CSR0_BAR_OFFSET 0x00\r
+#define CSR0_BAR_MASK 0x00000002uL\r
+#define CSR0_BAR_SHIFT 1\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR0_SWR:\r
+ * SWR field of register CSR0.\r
+ *------------------------------------------------------------------------------\r
+ * Software reset\r
+ */\r
+#define CSR0_SWR_OFFSET 0x00\r
+#define CSR0_SWR_MASK 0x00000001uL\r
+#define CSR0_SWR_SHIFT 0\r
+\r
+/*******************************************************************************\r
+ * CSR1 register:\r
+ *------------------------------------------------------------------------------\r
+ * CSR1 - Transmit Poll Demand Register\r
+ */\r
+#define CSR1_REG_OFFSET 0x08\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR1_TPD3:\r
+ * TPD3 field of register CSR1.\r
+ *------------------------------------------------------------------------------\r
+ * TPD(31..24)\r
+ */\r
+#define CSR1_TPD3_OFFSET 0x08\r
+#define CSR1_TPD3_MASK 0xFF000000uL\r
+#define CSR1_TPD3_SHIFT 24\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR1_TPD2:\r
+ * TPD2 field of register CSR1.\r
+ *------------------------------------------------------------------------------\r
+ * TPD(23..16)\r
+ */\r
+#define CSR1_TPD2_OFFSET 0x08\r
+#define CSR1_TPD2_MASK 0x00FF0000uL\r
+#define CSR1_TPD2_SHIFT 16\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR1_TPD1:\r
+ * TPD1 field of register CSR1.\r
+ *------------------------------------------------------------------------------\r
+ * TPD(15..8)\r
+ */\r
+#define CSR1_TPD1_OFFSET 0x08\r
+#define CSR1_TPD1_MASK 0x0000FF00uL\r
+#define CSR1_TPD1_SHIFT 8\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR1_TPD0:\r
+ * TPD0 field of register CSR1.\r
+ *------------------------------------------------------------------------------\r
+ * TPD(7..0)\r
+ */\r
+#define CSR1_TPD0_OFFSET 0x08\r
+#define CSR1_TPD0_MASK 0x000000FFuL\r
+#define CSR1_TPD0_SHIFT 0\r
+\r
+/*******************************************************************************\r
+ * CSR2 register:\r
+ *------------------------------------------------------------------------------\r
+ * CSR2 - Receive Poll Demand Register\r
+ */\r
+#define CSR2_REG_OFFSET 0x10\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR2_RPD3:\r
+ * RPD3 field of register CSR2.\r
+ *------------------------------------------------------------------------------\r
+ * RPD(31..24)\r
+ */\r
+#define CSR2_RPD3_OFFSET 0x10\r
+#define CSR2_RPD3_MASK 0xFF000000uL\r
+#define CSR2_RPD3_SHIFT 24\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR2_RPD2:\r
+ * RPD2 field of register CSR2.\r
+ *------------------------------------------------------------------------------\r
+ * RPD(23..16)\r
+ */\r
+#define CSR2_RPD2_OFFSET 0x10\r
+#define CSR2_RPD2_MASK 0x00FF0000uL\r
+#define CSR2_RPD2_SHIFT 16\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR2_RPD1:\r
+ * RPD1 field of register CSR2.\r
+ *------------------------------------------------------------------------------\r
+ * RPD(15..8)\r
+ */\r
+#define CSR2_RPD1_OFFSET 0x10\r
+#define CSR2_RPD1_MASK 0x0000FF00uL\r
+#define CSR2_RPD1_SHIFT 8\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR2_RPD0:\r
+ * RPD0 field of register CSR2.\r
+ *------------------------------------------------------------------------------\r
+ * RPD(7..0)\r
+ */\r
+#define CSR2_RPD0_OFFSET 0x10\r
+#define CSR2_RPD0_MASK 0x000000FFuL\r
+#define CSR2_RPD0_SHIFT 0\r
+\r
+/*******************************************************************************\r
+ * CSR3 register:\r
+ *------------------------------------------------------------------------------\r
+ * CSR3 - Receive Descriptor List Base Address Register\r
+ */\r
+#define CSR3_REG_OFFSET 0x18\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR3_RLA3:\r
+ * RLA3 field of register CSR3.\r
+ *------------------------------------------------------------------------------\r
+ * RLA(31..24)\r
+ */\r
+#define CSR3_RLA3_OFFSET 0x18\r
+#define CSR3_RLA3_MASK 0xFF000000uL\r
+#define CSR3_RLA3_SHIFT 24\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR3_RLA2:\r
+ * RLA2 field of register CSR3.\r
+ *------------------------------------------------------------------------------\r
+ * RLA(23..16)\r
+ */\r
+#define CSR3_RLA2_OFFSET 0x18\r
+#define CSR3_RLA2_MASK 0x00FF0000uL\r
+#define CSR3_RLA2_SHIFT 16\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR3_RLA1:\r
+ * RLA1 field of register CSR3.\r
+ *------------------------------------------------------------------------------\r
+ * RLA(15..8)\r
+ */\r
+#define CSR3_RLA1_OFFSET 0x18\r
+#define CSR3_RLA1_MASK 0x0000FF00uL\r
+#define CSR3_RLA1_SHIFT 8\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR3_RLA0:\r
+ * RLA0 field of register CSR3.\r
+ *------------------------------------------------------------------------------\r
+ * RLA(7..0)\r
+ */\r
+#define CSR3_RLA0_OFFSET 0x18\r
+#define CSR3_RLA0_MASK 0x000000FFuL\r
+#define CSR3_RLA0_SHIFT 0\r
+\r
+/*******************************************************************************\r
+ * CSR4 register:\r
+ *------------------------------------------------------------------------------\r
+ * CSR4 - Transmit Descriptor List Base Address Register\r
+ */\r
+#define CSR4_REG_OFFSET 0x20\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR4_TLA3:\r
+ * TLA3 field of register CSR4.\r
+ *------------------------------------------------------------------------------\r
+ * TLA(31..24)\r
+ */\r
+#define CSR4_TLA3_OFFSET 0x20\r
+#define CSR4_TLA3_MASK 0xFF000000uL\r
+#define CSR4_TLA3_SHIFT 24\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR4_TLA2:\r
+ * TLA2 field of register CSR4.\r
+ *------------------------------------------------------------------------------\r
+ * TLA(23..16)\r
+ */\r
+#define CSR4_TLA2_OFFSET 0x20\r
+#define CSR4_TLA2_MASK 0x00FF0000uL\r
+#define CSR4_TLA2_SHIFT 16\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR4_TLA1:\r
+ * TLA1 field of register CSR4.\r
+ *------------------------------------------------------------------------------\r
+ * TLA(15..8)\r
+ */\r
+#define CSR4_TLA1_OFFSET 0x20\r
+#define CSR4_TLA1_MASK 0x0000FF00uL\r
+#define CSR4_TLA1_SHIFT 8\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR4_TLA0:\r
+ * TLA0 field of register CSR4.\r
+ *------------------------------------------------------------------------------\r
+ * TLA(7..0)\r
+ */\r
+#define CSR4_TLA0_OFFSET 0x20\r
+#define CSR4_TLA0_MASK 0x000000FFuL\r
+#define CSR4_TLA0_SHIFT 0\r
+\r
+/*******************************************************************************\r
+ * CSR5 register:\r
+ *------------------------------------------------------------------------------\r
+ * CSR5 - Status Register\r
+ */\r
+#define CSR5_REG_OFFSET 0x28\r
+#define CSR5_INT_BITS (CSR5_NIS_MASK | CSR5_AIS_MASK | CSR5_ERI_MASK | \\r
+ CSR5_GTE_MASK | CSR5_ETI_MASK | CSR5_RPS_MASK | CSR5_RU_MASK | \\r
+ CSR5_RI_MASK | CSR5_UNF_MASK | CSR5_TU_MASK | CSR5_TPS_MASK | CSR5_TI_MASK)\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR5_TS:\r
+ * TS field of register CSR5.\r
+ *------------------------------------------------------------------------------\r
+ * Transmit process state\r
+ */\r
+#define CSR5_TS_OFFSET 0x28\r
+#define CSR5_TS_MASK 0x00700000uL\r
+#define CSR5_TS_SHIFT 20\r
+\r
+/** 000 - Stopped; RESET or STOP TRANSMIT command issued. */\r
+#define CSR5_TS_STOPPED 0u \r
+/** 001 - Running, fetching the transmit descriptor. */\r
+#define CSR5_TS_RUNNING_FD 1u \r
+/** 010 - Running, waiting for end of transmission. */\r
+#define CSR5_TS_RUNNING_WT 2u \r
+/** 011 - Running, transferring data buffer from host memory to FIFO. */\r
+#define CSR5_TS_RUNNING_TD 3u \r
+/** 101 - Running, setup packet. */\r
+#define CSR5_TS_RUNNING_SP 5u \r
+/** 110 - Suspended; FIFO underflow or unavailable descriptor. */\r
+#define CSR5_TS_SUSPENDED 6u \r
+/** 111 - Running, closing transmit descriptor. */\r
+#define CSR5_TS_RUNNING_CD 7u \r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR5_RS:\r
+ * RS field of register CSR5.\r
+ *------------------------------------------------------------------------------\r
+ * Receive process state\r
+ */\r
+#define CSR5_RS_OFFSET 0x28\r
+#define CSR5_RS_MASK 0x00060000uL\r
+#define CSR5_RS_SHIFT 17\r
+\r
+/** 000 - Stopped; RESET or STOP RECEIVE command issued. */\r
+#define CSR5_RS_STOPPED 0u \r
+/** 001 - Running, fetching the receive descriptor. */\r
+#define CSR5_RS_RUNNING_FD 1u \r
+/** 010 - Running, waiting for the end-of-receive packet before prefetch of the\r
+ *next descriptor. */ \r
+#define CSR5_RS_RUNNING_WR 2u \r
+/** 011 - Running, waiting for the receive packet. */\r
+#define CSR5_RS_RUNNING_RB 3u \r
+/** 100 - Suspended, unavailable receive buffer. */\r
+#define CSR5_RS_SUSPENDED 4u \r
+/** 101 - Running, closing the receive descriptor. */\r
+#define CSR5_RS_RUNNING_CD 5u \r
+/** 111 - Running, transferring data from FIFO to host memory. */ \r
+#define CSR5_RS_RUNNING_TD 7u\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR5_NIS:\r
+ * NIS field of register CSR5.\r
+ *------------------------------------------------------------------------------\r
+ * Normal interrupt summary\r
+ */\r
+#define CSR5_NIS_OFFSET 0x28\r
+#define CSR5_NIS_MASK 0x00010000uL\r
+#define CSR5_NIS_SHIFT 16\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR5_AIS:\r
+ * AIS field of register CSR5.\r
+ *------------------------------------------------------------------------------\r
+ * Abnormal interrupt summary\r
+ */\r
+#define CSR5_AIS_OFFSET 0x28\r
+#define CSR5_AIS_MASK 0x00008000UL\r
+#define CSR5_AIS_SHIFT 15\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR5_ERI:\r
+ * ERI field of register CSR5.\r
+ *------------------------------------------------------------------------------\r
+ * Early receive interrupt\r
+ */\r
+#define CSR5_ERI_OFFSET 0x28\r
+#define CSR5_ERI_MASK 0x00004000UL\r
+#define CSR5_ERI_SHIFT 14\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR5_GTE:\r
+ * GTE field of register CSR5.\r
+ *------------------------------------------------------------------------------\r
+ * General-purpose timer expiration\r
+ */\r
+#define CSR5_GTE_OFFSET 0x28\r
+#define CSR5_GTE_MASK 0x00000800UL\r
+#define CSR5_GTE_SHIFT 11\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR5_ETI:\r
+ * ETI field of register CSR5.\r
+ *------------------------------------------------------------------------------\r
+ * Early transmit interrupt\r
+ */\r
+#define CSR5_ETI_OFFSET 0x28\r
+#define CSR5_ETI_MASK 0x00000400UL\r
+#define CSR5_ETI_SHIFT 10\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR5_RPS:\r
+ * RPS field of register CSR5.\r
+ *------------------------------------------------------------------------------\r
+ * Receive process stopped\r
+ */\r
+#define CSR5_RPS_OFFSET 0x28\r
+#define CSR5_RPS_MASK 0x00000100UL\r
+#define CSR5_RPS_SHIFT 8\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR5_RU:\r
+ * RU field of register CSR5.\r
+ *------------------------------------------------------------------------------\r
+ * Receive buffer unavailable\r
+ */\r
+#define CSR5_RU_OFFSET 0x28\r
+#define CSR5_RU_MASK 0x00000080UL\r
+#define CSR5_RU_SHIFT 7\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR5_RI:\r
+ * RI field of register CSR5.\r
+ *------------------------------------------------------------------------------\r
+ * Receive interrupt\r
+ */\r
+#define CSR5_RI_OFFSET 0x28\r
+#define CSR5_RI_MASK 0x00000040UL\r
+#define CSR5_RI_SHIFT 6\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR5_UNF:\r
+ * UNF field of register CSR5.\r
+ *------------------------------------------------------------------------------\r
+ * Transmit underflow\r
+ */\r
+#define CSR5_UNF_OFFSET 0x28\r
+#define CSR5_UNF_MASK 0x00000020UL\r
+#define CSR5_UNF_SHIFT 5\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR5_TU:\r
+ * TU field of register CSR5.\r
+ *------------------------------------------------------------------------------\r
+ * Transmit buffer unavailable\r
+ */\r
+#define CSR5_TU_OFFSET 0x28\r
+#define CSR5_TU_MASK 0x00000004UL\r
+#define CSR5_TU_SHIFT 2\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR5_TPS:\r
+ * TPS field of register CSR5.\r
+ *------------------------------------------------------------------------------\r
+ * Transmit process stopped\r
+ */\r
+#define CSR5_TPS_OFFSET 0x28\r
+#define CSR5_TPS_MASK 0x00000002UL\r
+#define CSR5_TPS_SHIFT 1\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR5_TI:\r
+ * TI field of register CSR5.\r
+ *------------------------------------------------------------------------------\r
+ * Transmit interrupt\r
+ */\r
+#define CSR5_TI_OFFSET 0x28\r
+#define CSR5_TI_MASK 0x00000001UL\r
+#define CSR5_TI_SHIFT 0\r
+\r
+/*******************************************************************************\r
+ * CSR6 register:\r
+ *------------------------------------------------------------------------------\r
+ * CSR6 - Operation Mode Register\r
+ */\r
+#define CSR6_REG_OFFSET 0x30\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR6_RA:\r
+ * RA field of register CSR6.\r
+ *------------------------------------------------------------------------------\r
+ * Receive all\r
+ */\r
+#define CSR6_RA_OFFSET 0x30\r
+#define CSR6_RA_MASK 0x40000000UL\r
+#define CSR6_RA_SHIFT 30\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR6_TTM:\r
+ * TTM field of register CSR6.\r
+ *------------------------------------------------------------------------------\r
+ * Transmit threshold mode\r
+ */\r
+#define CSR6_TTM_OFFSET 0x30\r
+#define CSR6_TTM_MASK 0x00400000UL\r
+#define CSR6_TTM_SHIFT 22\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR6_SF:\r
+ * SF field of register CSR6.\r
+ *------------------------------------------------------------------------------\r
+ * Store and forward\r
+ */\r
+#define CSR6_SF_OFFSET 0x30\r
+#define CSR6_SF_MASK 0x00200000UL\r
+#define CSR6_SF_SHIFT 21\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR6_TR:\r
+ * TR field of register CSR6.\r
+ *------------------------------------------------------------------------------\r
+ * Threshold control bits\r
+ */\r
+#define CSR6_TR_OFFSET 0x30\r
+#define CSR6_TR_MASK 0x0000C000UL\r
+#define CSR6_TR_SHIFT 14\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR6_ST:\r
+ * ST field of register CSR6.\r
+ *------------------------------------------------------------------------------\r
+ * Start/stop transmit command\r
+ */\r
+#define CSR6_ST_OFFSET 0x30\r
+#define CSR6_ST_MASK 0x00002000UL\r
+#define CSR6_ST_SHIFT 13\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR6_FD:\r
+ * FD field of register CSR6.\r
+ *------------------------------------------------------------------------------\r
+ * Full-duplex mode\r
+ */\r
+#define CSR6_FD_OFFSET 0x30\r
+#define CSR6_FD_MASK 0x00000200UL\r
+#define CSR6_FD_SHIFT 9\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR6_PM:\r
+ * PM field of register CSR6.\r
+ *------------------------------------------------------------------------------\r
+ * Pass all multicast\r
+ */\r
+#define CSR6_PM_OFFSET 0x30\r
+#define CSR6_PM_MASK 0x00000080UL\r
+#define CSR6_PM_SHIFT 7\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR6_PR:\r
+ * PR field of register CSR6.\r
+ *------------------------------------------------------------------------------\r
+ * Promiscuous mode\r
+ */\r
+#define CSR6_PR_OFFSET 0x30\r
+#define CSR6_PR_MASK 0x00000040UL\r
+#define CSR6_PR_SHIFT 6\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR6_IF:\r
+ * IF field of register CSR6.\r
+ *------------------------------------------------------------------------------\r
+ * Inverse filtering\r
+ */\r
+#define CSR6_IF_OFFSET 0x30\r
+#define CSR6_IF_MASK 0x00000010UL\r
+#define CSR6_IF_SHIFT 4\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR6_PB:\r
+ * PB field of register CSR6.\r
+ *------------------------------------------------------------------------------\r
+ * Pass bad frames\r
+ */\r
+#define CSR6_PB_OFFSET 0x30\r
+#define CSR6_PB_MASK 0x00000008UL\r
+#define CSR6_PB_SHIFT 3\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR6_HO:\r
+ * HO field of register CSR6.\r
+ *------------------------------------------------------------------------------\r
+ * Hash-only filtering mode\r
+ */\r
+#define CSR6_HO_OFFSET 0x30\r
+#define CSR6_HO_MASK 0x00000004UL\r
+#define CSR6_HO_SHIFT 2\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR6_SR:\r
+ * SR field of register CSR6.\r
+ *------------------------------------------------------------------------------\r
+ * Start/stop receive command\r
+ */\r
+#define CSR6_SR_OFFSET 0x30\r
+#define CSR6_SR_MASK 0x00000002UL\r
+#define CSR6_SR_SHIFT 1\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR6_HP:\r
+ * HP field of register CSR6.\r
+ *------------------------------------------------------------------------------\r
+ * Hash/perfect receive filtering mode\r
+ */\r
+#define CSR6_HP_OFFSET 0x30\r
+#define CSR6_HP_MASK 0x00000001UL\r
+#define CSR6_HP_SHIFT 0\r
+\r
+/*******************************************************************************\r
+ * CSR7 register:\r
+ *------------------------------------------------------------------------------\r
+ * CSR7 - Interrupt Enable Register\r
+ */\r
+#define CSR7_REG_OFFSET 0x38\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR7_NIE:\r
+ * NIE field of register CSR7.\r
+ *------------------------------------------------------------------------------\r
+ * Normal interrupt summary enable\r
+ */\r
+#define CSR7_NIE_OFFSET 0x38\r
+#define CSR7_NIE_MASK 0x00010000UL\r
+#define CSR7_NIE_SHIFT 16\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR7_AIE:\r
+ * AIE field of register CSR7.\r
+ *------------------------------------------------------------------------------\r
+ * Abnormal interrupt summary enable\r
+ */\r
+#define CSR7_AIE_OFFSET 0x38\r
+#define CSR7_AIE_MASK 0x00008000UL\r
+#define CSR7_AIE_SHIFT 15\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR7_ERE:\r
+ * ERE field of register CSR7.\r
+ *------------------------------------------------------------------------------\r
+ * Early receive interrupt enable\r
+ */\r
+#define CSR7_ERE_OFFSET 0x38\r
+#define CSR7_ERE_MASK 0x00004000UL\r
+#define CSR7_ERE_SHIFT 14\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR7_GTE:\r
+ * GTE field of register CSR7.\r
+ *------------------------------------------------------------------------------\r
+ * General-purpose timer overflow enable\r
+ */\r
+#define CSR7_GTE_OFFSET 0x38\r
+#define CSR7_GTE_MASK 0x00000800UL\r
+#define CSR7_GTE_SHIFT 11\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR7_ETE:\r
+ * ETE field of register CSR7.\r
+ *------------------------------------------------------------------------------\r
+ * Early transmit interrupt enable\r
+ */\r
+#define CSR7_ETE_OFFSET 0x38\r
+#define CSR7_ETE_MASK 0x00000400UL\r
+#define CSR7_ETE_SHIFT 10\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR7_RSE:\r
+ * RSE field of register CSR7.\r
+ *------------------------------------------------------------------------------\r
+ * Receive stopped enable\r
+ */\r
+#define CSR7_RSE_OFFSET 0x38\r
+#define CSR7_RSE_MASK 0x00000100UL\r
+#define CSR7_RSE_SHIFT 8\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR7_RUE:\r
+ * RUE field of register CSR7.\r
+ *------------------------------------------------------------------------------\r
+ * Receive buffer unavailable enable\r
+ */\r
+#define CSR7_RUE_OFFSET 0x38\r
+#define CSR7_RUE_MASK 0x00000080UL\r
+#define CSR7_RUE_SHIFT 7\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR7_RIE:\r
+ * RIE field of register CSR7.\r
+ *------------------------------------------------------------------------------\r
+ * Receive interrupt enable\r
+ */\r
+#define CSR7_RIE_OFFSET 0x38\r
+#define CSR7_RIE_MASK 0x00000040UL\r
+#define CSR7_RIE_SHIFT 6\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR7_UNE:\r
+ * UNE field of register CSR7.\r
+ *------------------------------------------------------------------------------\r
+ * Underflow interrupt enable\r
+ */\r
+#define CSR7_UNE_OFFSET 0x38\r
+#define CSR7_UNE_MASK 0x00000020UL\r
+#define CSR7_UNE_SHIFT 5\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR7_TUE:\r
+ * TUE field of register CSR7.\r
+ *------------------------------------------------------------------------------\r
+ * Transmit buffer unavailable enable\r
+ */\r
+#define CSR7_TUE_OFFSET 0x38\r
+#define CSR7_TUE_MASK 0x00000004UL\r
+#define CSR7_TUE_SHIFT 2\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR7_TSE:\r
+ * TSE field of register CSR7.\r
+ *------------------------------------------------------------------------------\r
+ * Transmit stopped enable\r
+ */\r
+#define CSR7_TSE_OFFSET 0x38\r
+#define CSR7_TSE_MASK 0x00000002UL\r
+#define CSR7_TSE_SHIFT 1\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR7_TIE:\r
+ * TIE field of register CSR7.\r
+ *------------------------------------------------------------------------------\r
+ * Transmit interrupt enable\r
+ */\r
+#define CSR7_TIE_OFFSET 0x38\r
+#define CSR7_TIE_MASK 0x00000001UL\r
+#define CSR7_TIE_SHIFT 0\r
+\r
+/*******************************************************************************\r
+ * CSR8 register:\r
+ *------------------------------------------------------------------------------\r
+ * CSR8 - Missed Frames and Overflow Counter Register\r
+ */\r
+#define CSR8_REG_OFFSET 0x40\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR8_OCO:\r
+ * OCO field of register CSR8.\r
+ *------------------------------------------------------------------------------\r
+ * Overflow counter overflow\r
+ */\r
+#define CSR8_OCO_OFFSET 0x40\r
+#define CSR8_OCO_MASK 0x10000000UL\r
+#define CSR8_OCO_SHIFT 28\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR8_FOC:\r
+ * FOC field of register CSR8.\r
+ *------------------------------------------------------------------------------\r
+ * FIFO overflow counter\r
+ */\r
+#define CSR8_FOC_OFFSET 0x40\r
+#define CSR8_FOC_MASK 0x0FFE0000UL\r
+#define CSR8_FOC_SHIFT 17\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR8_MFO:\r
+ * MFO field of register CSR8.\r
+ *------------------------------------------------------------------------------\r
+ * Missed frame overflow\r
+ */\r
+#define CSR8_MFO_OFFSET 0x40\r
+#define CSR8_MFO_MASK 0x00010000UL\r
+#define CSR8_MFO_SHIFT 16\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR8_MFC:\r
+ * MFC field of register CSR8.\r
+ *------------------------------------------------------------------------------\r
+ * Missed frame counter\r
+ */\r
+#define CSR8_MFC_OFFSET 0x40\r
+#define CSR8_MFC_MASK 0x0000FFFFUL\r
+#define CSR8_MFC_SHIFT 0\r
+\r
+/*******************************************************************************\r
+ * CSR9 register:\r
+ *------------------------------------------------------------------------------\r
+ * CSR9 - MII Management and Serial ROM Interface Register\r
+ */\r
+#define CSR9_REG_OFFSET 0x48\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR9_MDI:\r
+ * MDI field of register CSR9.\r
+ *------------------------------------------------------------------------------\r
+ * MII management data in signal\r
+ */\r
+#define CSR9_MDI_OFFSET 0x48\r
+#define CSR9_MDI_MASK 0x00080000UL\r
+#define CSR9_MDI_SHIFT 19\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR9_MII:\r
+ * MII field of register CSR9.\r
+ *------------------------------------------------------------------------------\r
+ * MII management operation mode\r
+ */\r
+#define CSR9_MII_OFFSET 0x48\r
+#define CSR9_MII_MASK 0x00040000UL\r
+#define CSR9_MII_SHIFT 18\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR9_MDO:\r
+ * MDO field of register CSR9.\r
+ *------------------------------------------------------------------------------\r
+ * MII management write data\r
+ */\r
+#define CSR9_MDO_OFFSET 0x48\r
+#define CSR9_MDO_MASK 0x00020000UL\r
+#define CSR9_MDO_SHIFT 17\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR9_MDC:\r
+ * MDC field of register CSR9.\r
+ *------------------------------------------------------------------------------\r
+ * MII management clock\r
+ */\r
+#define CSR9_MDC_OFFSET 0x48\r
+#define CSR9_MDC_MASK 0x00010000UL\r
+#define CSR9_MDC_SHIFT 16\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR9_SDO:\r
+ * SDO field of register CSR9.\r
+ *------------------------------------------------------------------------------\r
+ * Serial ROM data output\r
+ */\r
+#define CSR9_SDO_OFFSET 0x48\r
+#define CSR9_SDO_MASK 0x00000008UL\r
+#define CSR9_SDO_SHIFT 3\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR9_SDI:\r
+ * SDI field of register CSR9.\r
+ *------------------------------------------------------------------------------\r
+ * Serial ROM data input\r
+ */\r
+#define CSR9_SDI_OFFSET 0x48\r
+#define CSR9_SDI_MASK 0x00000004UL\r
+#define CSR9_SDI_SHIFT 2\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR9_SCLK:\r
+ * SCLK field of register CSR9.\r
+ *------------------------------------------------------------------------------\r
+ * Serial ROM clock\r
+ */\r
+#define CSR9_SCLK_OFFSET 0x48\r
+#define CSR9_SCLK_MASK 0x00000002UL\r
+#define CSR9_SCLK_SHIFT 1\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR9_SCS:\r
+ * SCS field of register CSR9.\r
+ *------------------------------------------------------------------------------\r
+ * Serial ROM chip select\r
+ */\r
+#define CSR9_SCS_OFFSET 0x48\r
+#define CSR9_SCS_MASK 0x00000001UL\r
+#define CSR9_SCS_SHIFT 0\r
+\r
+/*******************************************************************************\r
+ * CSR11 register:\r
+ *------------------------------------------------------------------------------\r
+ * CSR11 - General-Purpose Timer and Interrupt Mitigation Control Register\r
+ */\r
+#define CSR11_REG_OFFSET 0x58\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR11_CS:\r
+ * CS field of register CSR11.\r
+ *------------------------------------------------------------------------------\r
+ * Cycle size\r
+ */\r
+#define CSR11_CS_OFFSET 0x58\r
+#define CSR11_CS_MASK 0x80000000UL\r
+#define CSR11_CS_SHIFT 31\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR11_TT:\r
+ * TT field of register CSR11.\r
+ *------------------------------------------------------------------------------\r
+ * Transmit timer\r
+ */\r
+#define CSR11_TT_OFFSET 0x58\r
+#define CSR11_TT_MASK 0x78000000UL\r
+#define CSR11_TT_SHIFT 27\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR11_NTP:\r
+ * NTP field of register CSR11.\r
+ *------------------------------------------------------------------------------\r
+ * Number of transmit packets\r
+ */\r
+#define CSR11_NTP_OFFSET 0x58\r
+#define CSR11_NTP_MASK 0x07000000UL\r
+#define CSR11_NTP_SHIFT 24\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR11_RT:\r
+ * RT field of register CSR11.\r
+ *------------------------------------------------------------------------------\r
+ * Receive timer\r
+ */\r
+#define CSR11_RT_OFFSET 0x58\r
+#define CSR11_RT_MASK 0x00F00000UL\r
+#define CSR11_RT_SHIFT 20\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR11_NRP:\r
+ * NRP field of register CSR11.\r
+ *------------------------------------------------------------------------------\r
+ * Number of receive packets\r
+ */\r
+#define CSR11_NRP_OFFSET 0x58\r
+#define CSR11_NRP_MASK 0x000E0000UL\r
+#define CSR11_NRP_SHIFT 17\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR11_CON:\r
+ * CON field of register CSR11.\r
+ *------------------------------------------------------------------------------\r
+ * Continuous mode\r
+ */\r
+#define CSR11_CON_OFFSET 0x58\r
+#define CSR11_CON_MASK 0x00010000UL\r
+#define CSR11_CON_SHIFT 16\r
+\r
+/*------------------------------------------------------------------------------\r
+ * CSR11_TIM:\r
+ * TIM field of register CSR11.\r
+ *------------------------------------------------------------------------------\r
+ * Timer value\r
+ */\r
+#define CSR11_TIM_OFFSET 0x58\r
+#define CSR11_TIM_MASK 0x0000FFFFUL\r
+#define CSR11_TIM_SHIFT 0\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* MSS_ETHERNET_MAC_REGISTERS_H_*/\r
--- /dev/null
+/*******************************************************************************\r
+ * (c) Copyright 2007 Actel Corporation. All rights reserved.\r
+ * \r
+ * Actel:Firmware:MSS_Ethernet_MAC_Driver:2.0.103 configuration.\r
+ *\r
+ */\r
+\r
+\r
+#ifndef ACTEL__FIRMWARE__MSS_ETHERNET_MAC_DRIVER__2_0_103_CONFIGURATION_HEADER\r
+#define ACTEL__FIRMWARE__MSS_ETHERNET_MAC_DRIVER__2_0_103_CONFIGURATION_HEADER\r
+\r
+\r
+#define CORE_VENDOR "Actel"\r
+#define CORE_LIBRARY "Firmware"\r
+#define CORE_NAME "MSS_Ethernet_MAC_Driver"\r
+#define CORE_VERSION "2.0.103"\r
+\r
+#define BUS_ARBITRATION_SCHEME 0\r
+#define PROGRAMMABLE_BURST_LENGTH 0\r
+#define RX_RING_SIZE 4\r
+#define SETUP_FRAME_TIME_OUT 10000\r
+#define STATE_CHANGE_TIME_OUT 10000\r
+#define TX_RING_SIZE 2\r
+\r
+#endif // ACTEL__FIRMWARE__MSS_ETHERNET_MAC_DRIVER__2_0_103_CONFIGURATION_HEADER\r
+\r
--- /dev/null
+/***************************************************************************//**\r
+ * PHY access methods for DP83848C.\r
+ * The implementation in this file is specific to the DP83848C,\r
+ * If a different PHY support is required the PHY specific registers must\r
+ * be updated.\r
+ * (c) Copyright 2007 Actel Corporation\r
+ *\r
+ * SVN $Revision: 2324 $\r
+ * SVN $Date: 2010-02-26 10:47:36 +0000 (Fri, 26 Feb 2010) $\r
+ *\r
+ ******************************************************************************/\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif \r
+\r
+\r
+#include "mss_ethernet_mac.h"\r
+#include "mss_ethernet_mac_regs.h"\r
+\r
+#include "phy.h"\r
+\r
+extern MAC_instance_t g_mss_mac;\r
+\r
+/***************************** MDIO FUNCTIONS *********************************/\r
+\r
+/* Defines ********************************************************************/\r
+#define MDIO_START 0x00004000UL\r
+#define MDIO_READ 0x00002000UL\r
+#define MDIO_WRITE 0x00001002UL\r
+#define MDIO_ADDR_OFFSET 7UL\r
+#define MDIO_ADDR_MASK 0x00000f80UL\r
+#define MDIO_REG_ADDR_OFFSET 2UL\r
+#define MDIO_REG_ADDR_MASK 0x0000007cUL\r
+#define PREAMBLECOUNT 32UL\r
+#define ONEMICROSECOND 20UL\r
+\r
+typedef enum {\r
+ MDIO_CMD_READ,\r
+ MDIO_CMD_WRITE\r
+}mdio_cmd_t;\r
+\r
+\r
+\r
+/***************************************************************************//**\r
+ * Set clock high or low.\r
+ */\r
+static void\r
+MDIO_management_clock\r
+(\r
+ int32_t clock\r
+)\r
+{\r
+ int32_t volatile a;\r
+ \r
+ MAC_BITBAND->CSR9_MDC = (uint32_t)clock;\r
+ \r
+ /* delay for 1us */\r
+ for( a = 0; a < ONEMICROSECOND; a++ ){}\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * Send read or write command to PHY.\r
+ */\r
+static void\r
+MDIO_send_cmd\r
+(\r
+ uint8_t regad,\r
+ mdio_cmd_t mdio_cmd\r
+)\r
+{\r
+ int32_t i;\r
+ uint16_t mask, data;\r
+\r
+ /* enable MII output */\r
+ MAC_BITBAND->CSR9_MDEN = 1;\r
+\r
+ /* send 32 1's preamble */\r
+ MAC_BITBAND->CSR9_MDO = 1;\r
+ for (i = 0; i < PREAMBLECOUNT; i++) {\r
+ MDIO_management_clock( 0 );\r
+ MDIO_management_clock( 1 );\r
+ }\r
+\r
+ /* calculate data bits */\r
+ data = MDIO_START |\r
+ (( mdio_cmd == MDIO_CMD_READ ) ? MDIO_READ : MDIO_WRITE ) |\r
+ ((g_mss_mac.phy_address << MDIO_ADDR_OFFSET) & MDIO_ADDR_MASK) |\r
+ ((regad << MDIO_REG_ADDR_OFFSET) & MDIO_REG_ADDR_MASK);\r
+\r
+ /* sent out */\r
+ for( mask = 0x00008000L; mask>0; mask >>= 1 )\r
+ {\r
+ if ((mask == 0x2) && (mdio_cmd == MDIO_CMD_READ)) {\r
+ /* enable MII input */\r
+ MAC_BITBAND->CSR9_MDEN = 0;\r
+ }\r
+\r
+ MDIO_management_clock( 0 );\r
+\r
+ /* prepare MDO */\r
+ MAC_BITBAND->CSR9_MDO = (uint32_t)((mask & data) != 0 ? 1UL : 0UL);\r
+ \r
+ MDIO_management_clock( 1 );\r
+ }\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * Reads a PHY register.\r
+ */\r
+static uint16_t\r
+MDIO_read\r
+(\r
+ uint8_t regad\r
+)\r
+{\r
+ uint16_t mask;\r
+ uint16_t data;\r
+\r
+ MDIO_send_cmd( regad, MDIO_CMD_READ);\r
+\r
+ /* read data */\r
+ data = 0;\r
+ for( mask = 0x00008000L; mask>0; mask >>= 1 )\r
+ {\r
+ MDIO_management_clock( 0 );\r
+\r
+ /* read MDI */\r
+ if(MAC_BITBAND-> CSR9_MDI != 0){\r
+ data |= mask;\r
+ }\r
+\r
+ MDIO_management_clock( 1 );\r
+ }\r
+\r
+ MDIO_management_clock( 0 );\r
+\r
+ return data;\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * Writes to a PHY register.\r
+ */\r
+static void\r
+MDIO_write\r
+(\r
+ uint8_t regad,\r
+ uint16_t data\r
+)\r
+{\r
+ uint16_t mask;\r
+\r
+ MDIO_send_cmd(regad, MDIO_CMD_WRITE);\r
+\r
+ /* write data */\r
+ for( mask = 0x00008000L; mask>0; mask >>= 1 )\r
+ {\r
+ MDIO_management_clock( 0 );\r
+\r
+ /* prepare MDO */\r
+ MAC_BITBAND->CSR9_MDO = (uint32_t)((mask & data) != 0 ? 1UL : 0UL);\r
+\r
+ MDIO_management_clock( 1 );\r
+ }\r
+\r
+ MDIO_management_clock( 0 );\r
+}\r
+\r
+\r
+/****************************** PHY FUNCTIONS *********************************/\r
+\r
+/* Defines ********************************************************************/\r
+\r
+/* Base registers */\r
+#define PHYREG_MIIMCR 0x00 /**< MII Management Control Register */\r
+#define MIIMCR_RESET (1<<15)\r
+#define MIIMCR_LOOPBACK (1<<14)\r
+#define MIIMCR_SPEED_SELECT (1<<13)\r
+#define MIIMCR_ENABLE_AUTONEGOTIATION (1<<12)\r
+#define MIIMCR_RESTART_AUTONEGOTIATION (1<<9)\r
+#define MIIMCR_DUPLEX_MODE (1<<8)\r
+#define MIIMCR_COLLISION_TEST (1<<7)\r
+\r
+#define PHYREG_MIIMSR 0x01 /**< MII Management Status Register */\r
+#define MIIMSR_ANC (1<<5) /**< Auto-Negotiation Completed. */\r
+#define MIIMSR_LINK (1<<2) /**< Link is established. */\r
+\r
+#define PHYREG_PHYID1R 0x02 /**< PHY Identifier 1 Register */\r
+#define PHYREG_PHYID2R 0x03 /**< PHY Identifier 2 Register */\r
+\r
+#define PHYREG_ANAR 0x04 /**< Auto-Negotiation Advertisement Register */\r
+#define ANAR_100FD (1<<8)\r
+#define ANAR_100HD (1<<7)\r
+#define ANAR_10FD (1<<6)\r
+#define ANAR_10HD (1<<5)\r
+\r
+#define PHYREG_ANLPAR 0x05 /**< Auto-Negotiation Link Partner Ability Register */\r
+#define PHYREG_ANER 0x06 /**< Auto-Negotiation Expansion Register */\r
+#define PHYREG_NPAR 0x07 /**< Next Page Advertisement Register */\r
+/* 0x08- 0x0F Reserved */\r
+#define PHYREG_MFR 0x10 /**< Miscellaneous Features Register */\r
+#define PHYREG_ICSR 0x11 /**< Interrupt Control/Status Register */\r
+\r
+#define PHYREG_DR 0x12 /**< Diagnostic Register */\r
+#define DR_DPLX (1<<11)\r
+#define DR_DATA_RATE (1<<10)\r
+\r
+#define PHYREG_PMLR 0x13 /**< Power Management & Loopback Register */\r
+/* 0x14 Reserved */\r
+#define PHYREG_MCR 0x15 /**< Mode Control Register */\r
+#define MCR_LED_SEL (1<<9)\r
+/* 0x16 Reserved */\r
+#define PHYREG_DCR 0x17 /**< Disconnect Counter */\r
+#define PHYREG_RECR 0x18 /**< Receive Error Counter */\r
+/* 0x19-0x1F Reserved */\r
+\r
+/***************************************************************************//**\r
+ * Probe used PHY.\r
+ *\r
+ * return PHY address. If PHY don't fount, returns 255.\r
+ */\r
+uint8_t PHY_probe( void )\r
+{\r
+ uint8_t phy;\r
+ uint8_t phy_found;\r
+ uint16_t reg;\r
+\r
+ phy_found = 0;\r
+ for (phy = MSS_PHY_ADDRESS_MIN; phy <= MSS_PHY_ADDRESS_MAX; phy++) {\r
+ g_mss_mac.phy_address = phy;\r
+\r
+ reg = MDIO_read( PHYREG_PHYID1R );\r
+\r
+ if ((reg != 0x0000ffffUL) && (reg != 0x00000000UL)) {\r
+ phy_found = 1;\r
+ phy = MSS_PHY_ADDRESS_MAX + 1;\r
+ }\r
+ }\r
+\r
+ if( phy_found == 0 ) {\r
+ g_mss_mac.phy_address = MSS_PHY_ADDRESS_AUTO_DETECT;\r
+ }\r
+ return g_mss_mac.phy_address;\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * Resets the PHY.\r
+ */\r
+void PHY_reset( void )\r
+{\r
+ MDIO_write( PHYREG_MIIMCR, MIIMCR_RESET );\r
+ MDIO_write( PHYREG_MIIMCR,\r
+ MIIMCR_ENABLE_AUTONEGOTIATION |\r
+ MIIMCR_RESTART_AUTONEGOTIATION |\r
+ MIIMCR_COLLISION_TEST );\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * Restarts PHY auto-negotiation and wait until it's over.\r
+ */\r
+void PHY_auto_negotiate( void )\r
+{\r
+ int32_t a;\r
+ uint16_t reg;\r
+ int32_t exit = 1;\r
+\r
+ reg = MDIO_read( PHYREG_MIIMCR );\r
+ MDIO_write( PHYREG_MIIMCR,\r
+ (uint16_t)( MIIMCR_ENABLE_AUTONEGOTIATION |\r
+ MIIMCR_RESTART_AUTONEGOTIATION |\r
+ reg) );\r
+\r
+ for(a=0; (a<1000) && (exit); a++) {\r
+ reg = MDIO_read( PHYREG_MIIMSR );\r
+ if( (reg & MIIMSR_ANC) != 0 ) {\r
+ exit = 0;\r
+ }\r
+ }\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * Returns link status.\r
+ *\r
+ * @return #MAC_LINK_STATUS_LINK if link is up.\r
+ */\r
+uint8_t PHY_link_status( void )\r
+{\r
+ uint8_t retval = 0;\r
+ if(( MDIO_read( PHYREG_MIIMSR ) & MIIMSR_LINK ) != 0 ){\r
+ retval = MSS_MAC_LINK_STATUS_LINK;\r
+ }\r
+ return retval;\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * Returns link type.\r
+ *\r
+ * @return the logical OR of the following values:\r
+ * #MAC_LINK_STATUS_100MB - Connection is 100Mb\r
+ * #MAC_LINK_STATUS_FDX - Connection is full duplex\r
+ */\r
+uint8_t PHY_link_type( void )\r
+{\r
+ uint16_t diagnostic;\r
+ uint8_t type = 0;\r
+\r
+ diagnostic = MDIO_read( PHYREG_DR );\r
+\r
+ if( (diagnostic & DR_DPLX) != 0 ) {\r
+ type = MSS_MAC_LINK_STATUS_FDX;\r
+ }\r
+\r
+ if( (diagnostic & DR_DATA_RATE) != 0 ) {\r
+ type |= MSS_MAC_LINK_STATUS_100MB;\r
+ }\r
+\r
+ return type;\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * Sets link type.\r
+ */\r
+void\r
+PHY_set_link_type\r
+(\r
+ uint8_t type\r
+)\r
+{\r
+ uint16_t reg;\r
+\r
+ reg = MDIO_read( PHYREG_ANAR );\r
+ reg |= ANAR_100FD | ANAR_100HD | ANAR_10FD | ANAR_10HD;\r
+\r
+ if( (type & MSS_MAC_LINK_STATUS_100MB) == 0 ) {\r
+ reg &= ~(ANAR_100FD | ANAR_100HD);\r
+ }\r
+\r
+ if( (type & MSS_MAC_LINK_STATUS_FDX) == 0 ) {\r
+ reg &= ~(ANAR_100FD | ANAR_10FD);\r
+ }\r
+\r
+ MDIO_write( PHYREG_ANAR, reg );\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * Puts the Phy in Loopback mode\r
+ */\r
+uint16_t\r
+PHY_set_loopback\r
+(\r
+ uint8_t enable\r
+)\r
+{\r
+\r
+ uint16_t reg = 0; \r
+ \r
+\r
+ reg = MDIO_read( PHYREG_MIIMCR );\r
+ // If set to one we need to set the LOCAL Phy loopback\r
+ if(enable == 1)\r
+ reg |= MIIMCR_LOOPBACK;\r
+ else // else we want to clear the bit..\r
+ reg ^= MIIMCR_LOOPBACK;\r
+ \r
+ \r
+ MDIO_write( PHYREG_MIIMCR,reg );\r
+ reg = MDIO_read( PHYREG_MIIMCR );\r
+ \r
+ return reg;\r
+ \r
+}\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/******************************** END OF FILE *********************************/\r
+\r
--- /dev/null
+/***************************************************************************//**\r
+ * PHY access methods.\r
+ *\r
+ * (c) Copyright 2007 Actel Corporation\r
+ *\r
+ * SVN $Revision: 2293 $\r
+ * SVN $Date: 2010-02-24 13:52:02 +0000 (Wed, 24 Feb 2010) $\r
+ *\r
+ ******************************************************************************/\r
+\r
+#ifndef __MSS_ETHERNET_MAC_PHY_H\r
+#define __MSS_ETHERNET_MAC_PHY_H 1\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif \r
+\r
+/***************************************************************************//**\r
+ * Resets the PHY.\r
+ */\r
+void PHY_reset( void );\r
+\r
+\r
+/***************************************************************************//**\r
+ * Restarts PHY auto-negotiation and wait until it's over.\r
+ */\r
+void PHY_auto_negotiate( void );\r
+\r
+\r
+/***************************************************************************//**\r
+ * Probe used PHY.\r
+ *\r
+ * return PHY address. If PHY don't fount, returns 255.\r
+ */\r
+uint8_t PHY_probe( void );\r
+\r
+\r
+/***************************************************************************//**\r
+ * Returns link status.\r
+ *\r
+ * @return #MAC_LINK_STATUS_LINK if link is up.\r
+ */\r
+uint8_t PHY_link_status( void );\r
+\r
+\r
+/***************************************************************************//**\r
+ * Returns link type.\r
+ *\r
+ * @return the logical OR of the following values:\r
+ * #MAC_LINK_STATUS_100MB - Connection is 100Mb\r
+ * #MAC_LINK_STATUS_FDX - Connection is full duplex\r
+ */\r
+uint8_t PHY_link_type( void );\r
+\r
+\r
+/***************************************************************************//**\r
+ * Sets link type.\r
+ */\r
+void\r
+PHY_set_link_type\r
+(\r
+ uint8_t type\r
+);\r
+\r
+/***************************************************************************//**\r
+ * Sets/Clears the phy loop back mode, based on the enable value\r
+ */\r
+uint16_t\r
+PHY_set_loopback\r
+(\r
+ uint8_t enable\r
+);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__MSS_ETHERNET_MAC_PHY_H*/\r
--- /dev/null
+/*******************************************************************************\r
+ * (c) Copyright 2008 Actel Corporation. All rights reserved.\r
+ * \r
+ * SmartFusion microcontroller subsystem GPIO bare metal driver implementation.\r
+ *\r
+ * SVN $Revision: 1753 $\r
+ * SVN $Date: 2009-12-11 15:12:18 +0000 (Fri, 11 Dec 2009) $\r
+ */\r
+#include "mss_gpio.h"\r
+#include "../../CMSIS/mss_assert.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif \r
+\r
+/*-------------------------------------------------------------------------*//**\r
+*\r
+*/\r
+#define GPIO_INT_ENABLE_MASK (uint32_t)0x00000008UL\r
+#define OUTPUT_BUFFER_ENABLE_MASK 0x00000004UL\r
+\r
+#define NB_OF_GPIO (uint32_t)32\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ * Lookup table of GPIO configuration registers address indexed on GPIO ID.\r
+ */\r
+static uint32_t volatile * const g_config_reg_lut[NB_OF_GPIO] =\r
+{\r
+ &(GPIO->GPIO_0_CFG),\r
+ &(GPIO->GPIO_1_CFG),\r
+ &(GPIO->GPIO_2_CFG),\r
+ &(GPIO->GPIO_3_CFG),\r
+ &(GPIO->GPIO_4_CFG),\r
+ &(GPIO->GPIO_5_CFG),\r
+ &(GPIO->GPIO_6_CFG),\r
+ &(GPIO->GPIO_7_CFG),\r
+ &(GPIO->GPIO_8_CFG),\r
+ &(GPIO->GPIO_9_CFG),\r
+ &(GPIO->GPIO_10_CFG),\r
+ &(GPIO->GPIO_11_CFG),\r
+ &(GPIO->GPIO_12_CFG),\r
+ &(GPIO->GPIO_13_CFG),\r
+ &(GPIO->GPIO_14_CFG),\r
+ &(GPIO->GPIO_15_CFG),\r
+ &(GPIO->GPIO_16_CFG),\r
+ &(GPIO->GPIO_17_CFG),\r
+ &(GPIO->GPIO_18_CFG),\r
+ &(GPIO->GPIO_19_CFG),\r
+ &(GPIO->GPIO_20_CFG),\r
+ &(GPIO->GPIO_21_CFG),\r
+ &(GPIO->GPIO_22_CFG),\r
+ &(GPIO->GPIO_23_CFG),\r
+ &(GPIO->GPIO_24_CFG),\r
+ &(GPIO->GPIO_25_CFG),\r
+ &(GPIO->GPIO_26_CFG),\r
+ &(GPIO->GPIO_27_CFG),\r
+ &(GPIO->GPIO_28_CFG),\r
+ &(GPIO->GPIO_29_CFG),\r
+ &(GPIO->GPIO_30_CFG),\r
+ &(GPIO->GPIO_31_CFG)\r
+};\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ * Lookup table of Cortex-M3 GPIO interrupt number indexed on GPIO ID.\r
+ */\r
+static const IRQn_Type g_gpio_irqn_lut[NB_OF_GPIO] =\r
+{\r
+ GPIO0_IRQn,\r
+ GPIO1_IRQn,\r
+ GPIO2_IRQn,\r
+ GPIO3_IRQn,\r
+ GPIO4_IRQn,\r
+ GPIO5_IRQn,\r
+ GPIO6_IRQn,\r
+ GPIO7_IRQn,\r
+ GPIO8_IRQn,\r
+ GPIO9_IRQn,\r
+ GPIO10_IRQn,\r
+ GPIO11_IRQn,\r
+ GPIO12_IRQn,\r
+ GPIO13_IRQn,\r
+ GPIO14_IRQn,\r
+ GPIO15_IRQn,\r
+ GPIO16_IRQn,\r
+ GPIO17_IRQn,\r
+ GPIO18_IRQn,\r
+ GPIO19_IRQn,\r
+ GPIO20_IRQn,\r
+ GPIO21_IRQn,\r
+ GPIO22_IRQn,\r
+ GPIO23_IRQn,\r
+ GPIO24_IRQn,\r
+ GPIO25_IRQn,\r
+ GPIO26_IRQn,\r
+ GPIO27_IRQn,\r
+ GPIO28_IRQn,\r
+ GPIO29_IRQn,\r
+ GPIO30_IRQn,\r
+ GPIO31_IRQn\r
+};\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ * MSS_GPIO_init\r
+ * See "mss_gpio.h" for details of how to use this function.\r
+ */\r
+void MSS_GPIO_init( void )\r
+{\r
+ uint32_t i;\r
+ \r
+ /* reset MSS GPIO hardware */\r
+ SYSREG->SOFT_RST_CR |= SYSREG_GPIO_SOFTRESET_MASK;\r
+ /* Clear any previously pended MSS GPIO interrupt */\r
+ for ( i = 0U; i < NB_OF_GPIO; ++i )\r
+ {\r
+ NVIC_ClearPendingIRQ( g_gpio_irqn_lut[i] );\r
+ }\r
+ /* Take MSS GPIO hardware out of reset. */\r
+ SYSREG->SOFT_RST_CR &= ~SYSREG_GPIO_SOFTRESET_MASK;\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ * MSS_GPIO_config\r
+ * See "mss_gpio.h" for details of how to use this function.\r
+ */\r
+void MSS_GPIO_config\r
+(\r
+ mss_gpio_id_t port_id,\r
+ uint32_t config\r
+)\r
+{\r
+ uint32_t gpio_idx = (uint32_t)port_id;\r
+ \r
+ ASSERT( gpio_idx < NB_OF_GPIO );\r
+\r
+ if ( gpio_idx < NB_OF_GPIO )\r
+ {\r
+ *(g_config_reg_lut[gpio_idx]) = config;\r
+ }\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ * MSS_GPIO_set_output\r
+ * See "mss_gpio.h" for details of how to use this function.\r
+ */\r
+void MSS_GPIO_set_output\r
+(\r
+ mss_gpio_id_t port_id,\r
+ uint8_t value\r
+)\r
+{\r
+ uint32_t gpio_idx = (uint32_t)port_id;\r
+ \r
+ ASSERT( gpio_idx < NB_OF_GPIO );\r
+ \r
+ if ( gpio_idx < NB_OF_GPIO )\r
+ {\r
+ GPIO_BITBAND->GPIO_OUT[gpio_idx] = (uint32_t)value;\r
+ }\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ * MSS_GPIO_drive_inout\r
+ * See "mss_gpio.h" for details of how to use this function.\r
+ */\r
+void MSS_GPIO_drive_inout\r
+(\r
+ mss_gpio_id_t port_id,\r
+ mss_gpio_inout_state_t inout_state\r
+)\r
+{\r
+ uint32_t outputs_state;\r
+ uint32_t config;\r
+ uint32_t gpio_idx = (uint32_t)port_id;\r
+ \r
+ ASSERT( gpio_idx < NB_OF_GPIO );\r
+ \r
+ if ( gpio_idx < NB_OF_GPIO )\r
+ {\r
+ switch( inout_state )\r
+ {\r
+ case MSS_GPIO_DRIVE_HIGH:\r
+ /* Set output high */\r
+ outputs_state = GPIO->GPIO_OUT;\r
+ outputs_state |= (uint32_t)1 << gpio_idx;\r
+ GPIO->GPIO_OUT = outputs_state;\r
+ /* Enable output buffer */\r
+ config = *(g_config_reg_lut[gpio_idx]);\r
+ config |= OUTPUT_BUFFER_ENABLE_MASK;\r
+ *(g_config_reg_lut[gpio_idx]) = config;\r
+ break;\r
+ \r
+ case MSS_GPIO_DRIVE_LOW:\r
+ /* Set output low */\r
+ outputs_state = GPIO->GPIO_OUT;\r
+ outputs_state &= ~((uint32_t)((uint32_t)1 << gpio_idx));\r
+ GPIO->GPIO_OUT = outputs_state;\r
+ /* Enable output buffer */\r
+ config = *(g_config_reg_lut[gpio_idx]);\r
+ config |= OUTPUT_BUFFER_ENABLE_MASK;\r
+ *(g_config_reg_lut[gpio_idx]) = config;\r
+ break;\r
+ \r
+ case MSS_GPIO_HIGH_Z:\r
+ /* Disable output buffer */\r
+ config = *(g_config_reg_lut[gpio_idx]);\r
+ config &= ~OUTPUT_BUFFER_ENABLE_MASK;\r
+ *(g_config_reg_lut[gpio_idx]) = config;\r
+ break;\r
+ \r
+ default:\r
+ ASSERT(0);\r
+ break;\r
+ }\r
+ }\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ * MSS_GPIO_enable_irq\r
+ * See "mss_gpio.h" for details of how to use this function.\r
+ */\r
+void MSS_GPIO_enable_irq\r
+(\r
+ mss_gpio_id_t port_id\r
+)\r
+{\r
+ uint32_t cfg_value;\r
+ uint32_t gpio_idx = (uint32_t)port_id;\r
+ \r
+ ASSERT( gpio_idx < NB_OF_GPIO );\r
+ \r
+ if ( gpio_idx < NB_OF_GPIO )\r
+ {\r
+ cfg_value = *(g_config_reg_lut[gpio_idx]);\r
+ *(g_config_reg_lut[gpio_idx]) = (cfg_value | GPIO_INT_ENABLE_MASK);\r
+ NVIC_EnableIRQ( g_gpio_irqn_lut[gpio_idx] );\r
+ }\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ * MSS_GPIO_disable_irq\r
+ * See "mss_gpio.h" for details of how to use this function.\r
+ */\r
+void MSS_GPIO_disable_irq\r
+(\r
+ mss_gpio_id_t port_id\r
+)\r
+{\r
+ uint32_t cfg_value;\r
+ uint32_t gpio_idx = (uint32_t)port_id;\r
+ \r
+ ASSERT( gpio_idx < NB_OF_GPIO );\r
+\r
+ if ( gpio_idx < NB_OF_GPIO )\r
+ {\r
+ cfg_value = *(g_config_reg_lut[gpio_idx]);\r
+ *(g_config_reg_lut[gpio_idx]) = (cfg_value & ~GPIO_INT_ENABLE_MASK);\r
+ }\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ * MSS_GPIO_clear_irq\r
+ * See "mss_gpio.h" for details of how to use this function.\r
+ */\r
+void MSS_GPIO_clear_irq\r
+(\r
+ mss_gpio_id_t port_id\r
+)\r
+{\r
+ uint32_t gpio_idx = (uint32_t)port_id;\r
+ \r
+ ASSERT( gpio_idx < NB_OF_GPIO );\r
+ \r
+ if ( gpio_idx < NB_OF_GPIO )\r
+ {\r
+ GPIO->GPIO_IRQ = ((uint32_t)1) << gpio_idx;\r
+ NVIC_ClearPendingIRQ( g_gpio_irqn_lut[gpio_idx] );\r
+ }\r
+}\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
--- /dev/null
+/*******************************************************************************\r
+ * (c) Copyright 2008 Actel Corporation. All rights reserved.\r
+ * \r
+ * SmartFusion Microcontroller Subsystem GPIO bare metal software driver public\r
+ * API.\r
+ *\r
+ * SVN $Revision: 1751 $\r
+ * SVN $Date: 2009-12-11 15:05:48 +0000 (Fri, 11 Dec 2009) $\r
+ */\r
+\r
+/*=========================================================================*//**\r
+ @mainpage SmartFusion MSS GPIO Bare Metal Driver.\r
+\r
+ @section intro_sec Introduction\r
+ The SmartFusion Microcontroller Subsystem (MSS) includes a block of 32 general\r
+ purpose input/outputs (GPIO).\r
+ This software driver provides a set of functions for controlling the MSS GPIO\r
+ block as part of a bare metal system where no operating system is available.\r
+ This driver can be adapted for use as part of an operating system but the\r
+ implementation of the adaptation layer between this driver and the operating\r
+ system's driver model is outside the scope of this driver.\r
+ \r
+ @section hw_dependencies Hardware Flow Dependencies\r
+ The configuration of all features of the MSS GPIOs is covered by this driver\r
+ with the exception of the SmartFusion IOMUX configuration. SmartFusion allows\r
+ multiple non-concurrent use of some external pins through IOMUX configuration.\r
+ This feature allows optimizing external pin usage by assigning external pins\r
+ for usage by either the microcontroller subsystem or the FPGA fabric.\r
+ The MSS GPIO ports 0 to 15 are always connected to external pins but GPIO ports\r
+ 16 to 31 are routed through IOMUX to the SmartFusion device external pins.\r
+ These IOMUX are configured using the MSS Configurator tool.\r
+ Make sure the MSS GPIOs 16 to 31 are enabled in the MSS Configurator tool if\r
+ you wish to use them\r
+ \r
+ @section theory_op Theory of Operation\r
+ The MSS GPIO driver uses the SmartFusion "Cortex Microcontroler Software\r
+ Interface Standard - Peripheral Access Layer" (CMSIS-PAL) to access MSS hardware\r
+ registers. You must ensure that the SmartFusion CMSIS-PAL is either included\r
+ in the software toolchain used to build your project or is included in your\r
+ project. The most up-to-date SmartFusion CMSIS-PAL files can be obtained using\r
+ the Actel Firmware Catalog.\r
+ \r
+ The MSS GPIO driver functions are grouped into the following categories:\r
+ - Initiliazation\r
+ - Configuration\r
+ - Reading and setting GPIO state\r
+ - Interrupt control\r
+ \r
+ The MSS GPIO driver is initialized through a call to the GPIO_init() function.\r
+ The GPIO_init() function must be called before any other GPIO driver functions\r
+ can be called.\r
+ \r
+ Each GPIO port is individually configured through a call to the\r
+ MSS_GPIO_config() function. Configuration includes deciding if a GPIO port\r
+ will be used as an input, an output or both. GPIO ports configured as inputs can be\r
+ further configured to generate interrupts based on the input's state.\r
+ Interrupts can be level or edge sensitive.\r
+ \r
+ The state of the GPIO ports can be read and set using the following functions:\r
+ - MSS_GPIO_get_inputs()\r
+ - MSS_GPIO_get_outputs()\r
+ - MSS_GPIO_set_outputs()\r
+ - MSS_GPIO_set_output()\r
+ - MSS_GPIO_drive_inout()\r
+ \r
+ Interrupts generated by GPIO ports configured as inputs are controlled using\r
+ the following functions:\r
+ - MSS_GPIO_enable_irq()\r
+ - MSS_GPIO_disable_irq()\r
+ - MSS_GPIO_clear_irq()\r
+ \r
+ *//*=========================================================================*/\r
+#ifndef MSS_GPIO_H_\r
+#define MSS_GPIO_H_\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif \r
+\r
+#include "../../CMSIS/a2fxxxm3.h"\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The mss_gpio_id_t enumeration is used to identify GPIOs as part of the\r
+ parameter to functions:\r
+ - MSS_GPIO_config(),\r
+ - MSS_GPIO_drive_inout(),\r
+ - MSS_GPIO_enable_irq(),\r
+ - MSS_GPIO_disable_irq(),\r
+ - MSS_GPIO_clear_irq()\r
+ */\r
+typedef enum __mss_gpio_id_t\r
+{\r
+ MSS_GPIO_0 = 0,\r
+ MSS_GPIO_1 = 1,\r
+ MSS_GPIO_2 = 2,\r
+ MSS_GPIO_3 = 3,\r
+ MSS_GPIO_4 = 4,\r
+ MSS_GPIO_5 = 5,\r
+ MSS_GPIO_6 = 6,\r
+ MSS_GPIO_7 = 7,\r
+ MSS_GPIO_8 = 8,\r
+ MSS_GPIO_9 = 9,\r
+ MSS_GPIO_10 = 10,\r
+ MSS_GPIO_11 = 11,\r
+ MSS_GPIO_12 = 12,\r
+ MSS_GPIO_13 = 13,\r
+ MSS_GPIO_14 = 14,\r
+ MSS_GPIO_15 = 15,\r
+ MSS_GPIO_16 = 16,\r
+ MSS_GPIO_17 = 17,\r
+ MSS_GPIO_18 = 18,\r
+ MSS_GPIO_19 = 19,\r
+ MSS_GPIO_20 = 20,\r
+ MSS_GPIO_21 = 21,\r
+ MSS_GPIO_22 = 22,\r
+ MSS_GPIO_23 = 23,\r
+ MSS_GPIO_24 = 24,\r
+ MSS_GPIO_25 = 25,\r
+ MSS_GPIO_26 = 26,\r
+ MSS_GPIO_27 = 27,\r
+ MSS_GPIO_28 = 28,\r
+ MSS_GPIO_29 = 29,\r
+ MSS_GPIO_30 = 30,\r
+ MSS_GPIO_31 = 31\r
+} mss_gpio_id_t;\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ GPIO ports definitions used to identify GPIOs as part of the parameter to\r
+ function MSS_GPIO_set_outputs().\r
+ These definitions can also be used to identity GPIO through logical\r
+ operations on the return value of function MSS_GPIO_get_inputs().\r
+ */\r
+#define MSS_GPIO_0_MASK 0x00000001UL\r
+#define MSS_GPIO_1_MASK 0x00000002UL\r
+#define MSS_GPIO_2_MASK 0x00000004UL\r
+#define MSS_GPIO_3_MASK 0x00000008UL\r
+#define MSS_GPIO_4_MASK 0x00000010UL\r
+#define MSS_GPIO_5_MASK 0x00000020UL\r
+#define MSS_GPIO_6_MASK 0x00000040UL\r
+#define MSS_GPIO_7_MASK 0x00000080UL\r
+#define MSS_GPIO_8_MASK 0x00000100UL\r
+#define MSS_GPIO_9_MASK 0x00000200UL\r
+#define MSS_GPIO_10_MASK 0x00000400UL\r
+#define MSS_GPIO_11_MASK 0x00000800UL\r
+#define MSS_GPIO_12_MASK 0x00001000UL\r
+#define MSS_GPIO_13_MASK 0x00002000UL\r
+#define MSS_GPIO_14_MASK 0x00004000UL\r
+#define MSS_GPIO_15_MASK 0x00008000UL\r
+#define MSS_GPIO_16_MASK 0x00010000UL\r
+#define MSS_GPIO_17_MASK 0x00020000UL\r
+#define MSS_GPIO_18_MASK 0x00040000UL\r
+#define MSS_GPIO_19_MASK 0x00080000UL\r
+#define MSS_GPIO_20_MASK 0x00100000UL\r
+#define MSS_GPIO_21_MASK 0x00200000UL\r
+#define MSS_GPIO_22_MASK 0x00400000UL\r
+#define MSS_GPIO_23_MASK 0x00800000UL\r
+#define MSS_GPIO_24_MASK 0x01000000UL\r
+#define MSS_GPIO_25_MASK 0x02000000UL\r
+#define MSS_GPIO_26_MASK 0x04000000UL\r
+#define MSS_GPIO_27_MASK 0x08000000UL\r
+#define MSS_GPIO_28_MASK 0x10000000UL\r
+#define MSS_GPIO_29_MASK 0x20000000UL\r
+#define MSS_GPIO_30_MASK 0x40000000UL\r
+#define MSS_GPIO_31_MASK 0x80000000UL\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ * GPIO modes\r
+ */\r
+#define MSS_GPIO_INPUT_MODE 0x0000000002UL\r
+#define MSS_GPIO_OUTPUT_MODE 0x0000000005UL\r
+#define MSS_GPIO_INOUT_MODE 0x0000000003UL\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ * Possible GPIO inputs interrupt configurations.\r
+ */\r
+#define MSS_GPIO_IRQ_LEVEL_HIGH 0x0000000000UL\r
+#define MSS_GPIO_IRQ_LEVEL_LOW 0x0000000020UL\r
+#define MSS_GPIO_IRQ_EDGE_POSITIVE 0x0000000040UL\r
+#define MSS_GPIO_IRQ_EDGE_NEGATIVE 0x0000000060UL\r
+#define MSS_GPIO_IRQ_EDGE_BOTH 0x0000000080UL\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ * Possible states for GPIO configured as INOUT.\r
+ */\r
+typedef enum mss_gpio_inout_state\r
+{\r
+ MSS_GPIO_DRIVE_LOW = 0,\r
+ MSS_GPIO_DRIVE_HIGH,\r
+ MSS_GPIO_HIGH_Z\r
+} mss_gpio_inout_state_t;\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The MSS_GPIO_init() function initializes the SmartFusion MSS GPIO block. It\r
+ resets the MSS GPIO hardware block and it also clears any pending MSS GPIO\r
+ interrupts in the Cortex-M3 interrupt controller.\r
+ \r
+ @return\r
+ none.\r
+ */\r
+void MSS_GPIO_init( void );\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The MSS_GPIO_config() function is used to configure an individual\r
+ GPIO port.\r
+ \r
+ @param port_id\r
+ The port_id parameter identifies the GPIO port to be configured.\r
+ An enumeration item of the form MSS_GPIO_n where n is the number of the GPIO\r
+ port is used to identify the GPIO port. For example MSS_GPIO_0 identifies\r
+ the first GPIO port and MSS_GPIO_31 the last one.\r
+ \r
+ @param config\r
+ The config parameter specifies the configuration to be applied to the GPIO\r
+ port identified by the port_id parameter. It is a logical OR of the required\r
+ I/O mode and the required interrupt mode. The interrupt mode is not relevant\r
+ if the GPIO is configured as an output only.\r
+ These I/O mode constants are allowed:\r
+ - MSS_GPIO_INPUT_MODE\r
+ - MSS_GPIO_OUTPUT_MODE\r
+ - MSS_GPIO_INOUT_MODE\r
+ These interrupt mode constants are allowed:\r
+ - MSS_GPIO_IRQ_LEVEL_HIGH\r
+ - MSS_GPIO_IRQ_LEVEL_LOW\r
+ - MSS_GPIO_IRQ_EDGE_POSITIVE\r
+ - MSS_GPIO_IRQ_EDGE_NEGATIVE\r
+ - MSS_GPIO_IRQ_EDGE_BOTH\r
+ \r
+ @return\r
+ none.\r
+\r
+ Example:\r
+ The following call will configure GPIO 4 as an input generating interrupts on\r
+ a low to high transition of the input:\r
+ @code\r
+ MSS_GPIO_config( MSS_GPIO_4, MSS_GPIO_INPUT_MODE | MSS_GPIO_IRQ_EDGE_POSITIVE );\r
+ @endcode\r
+ */\r
+void MSS_GPIO_config\r
+(\r
+ mss_gpio_id_t port_id,\r
+ uint32_t config\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The MSS_GPIO_set_outputs() function is used to set the state of all GPIO\r
+ ports configured as outputs.\r
+ \r
+ @param value\r
+ The value parameter specifies the state of the GPIO ports configured as\r
+ outputs. It is a bit mask of the form (MSS_GPIO_n_MASK | MSS_GPIO_m_MASK) where n\r
+ and m are numbers identifying GPIOs.\r
+ For example (MSS_GPIO_0_MASK | MSS_GPIO_1_MASK | MSS_GPIO_2_MASK ) specifies\r
+ that the first, second and third GPIOs' must be set high and all other\r
+ outputs set low.\r
+ The driver provides 32 mask constants, MSS_GPIO_0_MASK to MSS_GPIO_31_MASK\r
+ inclusive, for this purpose.\r
+ \r
+ @return\r
+ none.\r
+\r
+ Example 1:\r
+ Set GPIOs outputs 0 and 8 high and all other GPIO outputs low.\r
+ @code\r
+ MSS_GPIO_set_outputs( MSS_GPIO_0_MASK | MSS_GPIO_8_MASK );\r
+ @endcode\r
+\r
+ Example 2:\r
+ Set GPIOs outputs 2 and 4 low without affecting other GPIO outputs.\r
+ @code\r
+ uint32_t gpio_outputs;\r
+ gpio_outputs = MSS_GPIO_get_outputs();\r
+ gpio_outputs &= ~( MSS_GPIO_2_MASK | MSS_GPIO_4_MASK );\r
+ MSS_GPIO_set_outputs( gpio_outputs );\r
+ @endcode\r
+\r
+ @see MSS_GPIO_get_outputs()\r
+ */\r
+static __INLINE void\r
+MSS_GPIO_set_outputs\r
+(\r
+ uint32_t value\r
+)\r
+{\r
+ GPIO->GPIO_OUT = value;\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The MSS_GPIO_set_output() function is used to set the state of a single GPIO\r
+ port configured as output.\r
+ \r
+ @param port_id\r
+ The port_id parameter identifies the GPIO port that is to have its output set.\r
+ An enumeration item of the form MSS_GPIO_n where n is the number of the GPIO\r
+ port is used to identify the GPIO port. For example MSS_GPIO_0 identifies the\r
+ first GPIO port and MSS_GPIO_31 the last one.\r
+ \r
+ @param value\r
+ The value parameter specifies the desired state for the GPIO output. A value\r
+ of 0 will set the output low and a value of 1 will set the output high.\r
+ \r
+ @return\r
+ none.\r
+ */\r
+void MSS_GPIO_set_output\r
+(\r
+ mss_gpio_id_t port_id,\r
+ uint8_t value\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The MSS_GPIO_get_inputs() function is used to read the current state of all\r
+ GPIO ports confgured as inputs.\r
+ \r
+ @return\r
+ This function returns a 32 bit unsigned integer where each bit represents\r
+ the state of a GPIO input. The least significant bit represents the state of\r
+ GPIO input 0 and the most significant bit the state of GPIO input 31.\r
+\r
+ Example:\r
+ Read and assign the current state of the GPIO outputs to a variable.\r
+ @code\r
+ uint32_t gpio_inputs;\r
+ gpio_inputs = MSS_GPIO_get_inputs();\r
+ @endcode\r
+ */\r
+static __INLINE uint32_t\r
+MSS_GPIO_get_inputs( void )\r
+{\r
+ return GPIO->GPIO_IN;\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The MSS_GPIO_get_outputs() function is used to read the current state of all\r
+ GPIO ports confgured as outputs.\r
+ \r
+ @return\r
+ This function returns a 32 bit unsigned integer where each bit represents\r
+ the state of a GPIO output. The least significant bit represents the state\r
+ of GPIO output 0 and the most significant bit the state of GPIO output 31.\r
+\r
+ Example:\r
+ Read and assign the current state of the GPIO outputs to a variable.\r
+ @code\r
+ uint32_t gpio_outputs;\r
+ gpio_outputs = MSS_GPIO_get_outputs();\r
+ @endcode\r
+ */\r
+static __INLINE uint32_t\r
+MSS_GPIO_get_outputs( void )\r
+{\r
+ return GPIO->GPIO_OUT;\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The MSS_GPIO_drive_inout() function is used to set the output state of a single\r
+ GPIO port configured as an INOUT. An INOUT GPIO can be in one of three states:\r
+ - high\r
+ - low\r
+ - high impedance\r
+ An INOUT output would typically be used where several devices can drive the\r
+ state of a shared signal line. The high and low states are equivalent to the\r
+ high and low states of a GPIO configured as output. The high impedance state\r
+ is used to prevent the GPIO from driving its output state onto the signal line,\r
+ while at the same time allowing the input state of the GPIO to be read\r
+ \r
+ @param port_id\r
+ The port_id parameter identifies the GPIO port for which you want to change\r
+ the output state.\r
+ An enumeration item of the form MSS_GPIO_n where n is the number of the GPIO\r
+ port is used to identify the GPIO port. For example MSS_GPIO_0 identifies\r
+ the first GPIO port and MSS_GPIO_31 the last one.\r
+ \r
+ @param inout_state\r
+ The inout_state parameter specifies the state of the GPIO port identified by\r
+ the port_id parameter. Allowed values of type mss_gpio_inout_state_t are:\r
+ - MSS_GPIO_DRIVE_HIGH\r
+ - MSS_GPIO_DRIVE_LOW\r
+ - MSS_GPIO_HIGH_Z (high impedance)\r
+\r
+ @return\r
+ none.\r
+\r
+ Example:\r
+ The call to MSS_GPIO_drive_inout() below will set the GPIO 7 output to the\r
+ high impedance state.\r
+ @code\r
+ MSS_GPIO_drive_inout( MSS_GPIO_7, MSS_GPIO_HIGH_Z );\r
+ @endcode\r
+ */\r
+void MSS_GPIO_drive_inout\r
+(\r
+ mss_gpio_id_t port_id,\r
+ mss_gpio_inout_state_t inout_state\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The MSS_GPIO_enable_irq() function is used to enable interrupt generation\r
+ for the specified GPIO input. Interrupts are generated based on the state of\r
+ the GPIO input and the interrupt mode configured for it by MSS_GPIO_config().\r
+ \r
+ @param port_id\r
+ The port_id parameter identifies the GPIO port for which you want to enable\r
+ interrupt generation.\r
+ An enumeration item of the form MSS_GPIO_n where n is the number of the GPIO\r
+ port is used to identify the GPIO port. For example MSS_GPIO_0 identifies the\r
+ first GPIO port and MSS_GPIO_31 the last one.\r
+ \r
+ @return\r
+ none.\r
+\r
+ Example:\r
+ The call to MSS_GPIO_enable_irq() below will allow GPIO 8 to generate\r
+ interrupts.\r
+ @code\r
+ MSS_GPIO_enable_irq( MSS_GPIO_8 );\r
+ @endcode\r
+ */\r
+void MSS_GPIO_enable_irq\r
+(\r
+ mss_gpio_id_t port_id\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The MSS_GPIO_disable_irq() function is used to disable interrupt generation\r
+ for the specified GPIO input.\r
+ \r
+ @param port_id\r
+ The port_id parameter identifies the GPIO port for which you want to disable\r
+ interrupt generation.\r
+ An enumeration item of the form MSS_GPIO_n where n is the number of the GPIO\r
+ port is used to identify the GPIO port. For example MSS_GPIO_0 identifies the\r
+ first GPIO port and MSS_GPIO_31 the last one.\r
+ \r
+ @return\r
+ none.\r
+\r
+ Example:\r
+ The call to MSS_GPIO_disable_irq() below will prevent GPIO 8 from generating\r
+ interrupts.\r
+ @code\r
+ MSS_GPIO_disable_irq( MSS_GPIO_8 );\r
+ @endcode\r
+ */\r
+void MSS_GPIO_disable_irq\r
+(\r
+ mss_gpio_id_t port_id\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The MSS_GPIO_clear_irq() function is used to clear a pending interrupt from\r
+ the specified GPIO input.\r
+ Note: The MSS_GPIO_clear_irq() function must be called as part of any GPIO\r
+ interrupt service routine (ISR) in order to prevent the same interrupt event\r
+ retriggering a call to the GPIO ISR. The function also clears the interrupt\r
+ in the Cortex-M3 interrupt controller through a call to NVIC_ClearPendingIRQ().\r
+ \r
+ @param port_id\r
+ The port_id parameter identifies the GPIO input for which you want to clear the\r
+ interrupt.\r
+ An enumeration item of the form MSS_GPIO_n where n is the number of the GPIO\r
+ port is used to identify the GPIO port. For example MSS_GPIO_0 identifies the\r
+ first GPIO port and MSS_GPIO_31 the last one.\r
+ \r
+ @return\r
+ none.\r
+\r
+ Example:\r
+ The example below demonstrates the use of the MSS_GPIO_clear_irq() function\r
+ as part of the GPIO 9 interrupt service routine. \r
+ @code\r
+ void GPIO9_IRQHandler( void )\r
+ {\r
+ do_interrupt_processing();\r
+ \r
+ MSS_GPIO_clear_irq( MSS_GPIO_9 );\r
+ }\r
+ @endcode\r
+ */\r
+void MSS_GPIO_clear_irq\r
+(\r
+ mss_gpio_id_t port_id\r
+);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* MSS_GPIO_H_ */\r
--- /dev/null
+/*******************************************************************************\r
+ * (c) Copyright 2008 Actel Corporation. All rights reserved.\r
+ * \r
+ * SmartFusion microcontroller subsystem Peripheral DMA bare metal software\r
+ * driver implementation.\r
+ *\r
+ * SVN $Revision: 2110 $\r
+ * SVN $Date: 2010-02-05 15:24:19 +0000 (Fri, 05 Feb 2010) $\r
+ */\r
+#include "mss_pdma.h"\r
+#include "../../CMSIS/mss_assert.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif \r
+\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void DMA_IRQHandler( void );\r
+#else\r
+void DMA_IRQHandler( void );\r
+#endif\r
+\r
+/***************************************************************************//**\r
+ Offset of the posted writes WRITE_ADJ bits in a PDMA channel's configuration\r
+ register.\r
+ */\r
+#define CHANNEL_N_POSTED_WRITE_ADJUST_SHIFT 14\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ * Look-up table use to derice a channel's control register value from the\r
+ * requested source/destination. This table is incexed on the pdma_src_dest_t\r
+ * enumeration.\r
+ */\r
+#define CHANNEL_N_CTRL_PDMA_MASK (uint32_t)0x00000001\r
+#define CHANNEL_N_PERIPH_SELECT_SHIFT (uint32_t)23\r
+#define CHANNEL_N_DIRECTION_MASK (uint32_t)0x00000002\r
+\r
+const uint32_t src_dest_to_ctrl_reg_lut[] =\r
+{\r
+ CHANNEL_N_CTRL_PDMA_MASK, /* PDMA_FROM_UART_0 */\r
+ CHANNEL_N_CTRL_PDMA_MASK | ( (uint32_t)1 << CHANNEL_N_PERIPH_SELECT_SHIFT) | CHANNEL_N_DIRECTION_MASK, /* PDMA_TO_UART_0 */\r
+ CHANNEL_N_CTRL_PDMA_MASK | ( (uint32_t)2 << CHANNEL_N_PERIPH_SELECT_SHIFT), /* PDMA_FROM_UART_1 */\r
+ CHANNEL_N_CTRL_PDMA_MASK | ( (uint32_t)3 << CHANNEL_N_PERIPH_SELECT_SHIFT) | CHANNEL_N_DIRECTION_MASK, /* PDMA_TO_UART_1 */\r
+ CHANNEL_N_CTRL_PDMA_MASK | ( (uint32_t)4 << CHANNEL_N_PERIPH_SELECT_SHIFT), /* PDMA_FROM_SPI_0 */\r
+ CHANNEL_N_CTRL_PDMA_MASK | ( (uint32_t)5 << CHANNEL_N_PERIPH_SELECT_SHIFT) | CHANNEL_N_DIRECTION_MASK, /* PDMA_TO_SPI_0 */\r
+ CHANNEL_N_CTRL_PDMA_MASK | ( (uint32_t)6 << CHANNEL_N_PERIPH_SELECT_SHIFT), /* PDMA_FROM_SPI_1 */\r
+ CHANNEL_N_CTRL_PDMA_MASK | ( (uint32_t)7 << CHANNEL_N_PERIPH_SELECT_SHIFT) | CHANNEL_N_DIRECTION_MASK, /* PDMA_TO_SPI_1 */\r
+ CHANNEL_N_CTRL_PDMA_MASK | ( (uint32_t)8 << CHANNEL_N_PERIPH_SELECT_SHIFT), /* PDMA_FROM_FPGA_1 */\r
+ CHANNEL_N_CTRL_PDMA_MASK | ( (uint32_t)8 << CHANNEL_N_PERIPH_SELECT_SHIFT) | CHANNEL_N_DIRECTION_MASK, /* PDMA_TO_FPGA_1 */\r
+ CHANNEL_N_CTRL_PDMA_MASK | ( (uint32_t)9 << CHANNEL_N_PERIPH_SELECT_SHIFT), /* PDMA_FROM_FPGA_0 */\r
+ CHANNEL_N_CTRL_PDMA_MASK | ( (uint32_t)9 << CHANNEL_N_PERIPH_SELECT_SHIFT) | CHANNEL_N_DIRECTION_MASK, /* PDMA_TO_FPGA_0 */\r
+ CHANNEL_N_CTRL_PDMA_MASK | ( (uint32_t)10 << CHANNEL_N_PERIPH_SELECT_SHIFT) | CHANNEL_N_DIRECTION_MASK, /* PDMA_TO_ACE */\r
+ CHANNEL_N_CTRL_PDMA_MASK | ( (uint32_t)11 << CHANNEL_N_PERIPH_SELECT_SHIFT) /* PDMA_FROM_ACE */\r
+};\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+#define PDMA_MASTER_ENABLE (uint32_t)0x04\r
+#define PDMA_SOFT_RESET (uint32_t)0x20\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+#define NB_OF_PDMA_CHANNELS 8\r
+\r
+#define NEXT_CHANNEL_A 0U\r
+#define NEXT_CHANNEL_B 1U\r
+\r
+#define CHANNEL_STOPPED 0U\r
+#define CHANNEL_STARTED 1U\r
+\r
+static uint8_t g_pdma_next_channel[NB_OF_PDMA_CHANNELS];\r
+static uint8_t g_pdma_started_a[NB_OF_PDMA_CHANNELS];\r
+static uint8_t g_pdma_started_b[NB_OF_PDMA_CHANNELS];\r
+static pdma_channel_isr_t g_pdma_isr_table[NB_OF_PDMA_CHANNELS];\r
+static const uint16_t g_pdma_status_mask[NB_OF_PDMA_CHANNELS] =\r
+{\r
+ (uint16_t)0x0003, /* PDMA_CHANNEL_0 */\r
+ (uint16_t)0x000C, /* PDMA_CHANNEL_1 */\r
+ (uint16_t)0x0030, /* PDMA_CHANNEL_2 */\r
+ (uint16_t)0x00C0, /* PDMA_CHANNEL_3 */\r
+ (uint16_t)0x0300, /* PDMA_CHANNEL_4 */\r
+ (uint16_t)0x0C00, /* PDMA_CHANNEL_5 */\r
+ (uint16_t)0x3000, /* PDMA_CHANNEL_6 */\r
+ (uint16_t)0xC000, /* PDMA_CHANNEL_7 */\r
+};\r
+\r
+\r
+\r
+/***************************************************************************//**\r
+ * See mss_pdma.h for description of this function.\r
+ */\r
+void PDMA_init( void )\r
+{\r
+ int32_t i;\r
+ \r
+ /* Enable PDMA master access to comms matrix. */\r
+ SYSREG->AHB_MATRIX_CR |= PDMA_MASTER_ENABLE;\r
+ \r
+ /* Reset PDMA block. */\r
+ SYSREG->SOFT_RST_CR |= PDMA_SOFT_RESET;\r
+ \r
+ /* Clear any previously pended MSS PDMA interrupt */\r
+ NVIC_ClearPendingIRQ( DMA_IRQn );\r
+ \r
+ /* Take PDMA controller out of reset*/\r
+ SYSREG->SOFT_RST_CR &= ~PDMA_SOFT_RESET;\r
+ \r
+ /* Initialize channels state information. */\r
+ for ( i = 0; i < NB_OF_PDMA_CHANNELS; ++i )\r
+ {\r
+ g_pdma_next_channel[i] = NEXT_CHANNEL_A;\r
+ g_pdma_started_a[i] = CHANNEL_STOPPED;\r
+ g_pdma_started_b[i] = CHANNEL_STOPPED;\r
+ g_pdma_isr_table[i] = 0;\r
+ }\r
+}\r
+\r
+/***************************************************************************//**\r
+ * See mss_pdma.h for description of this function.\r
+ */\r
+#define CHANNEL_RESET_MASK (uint32_t)0x00000020\r
+\r
+void PDMA_configure\r
+(\r
+ pdma_channel_id_t channel_id,\r
+ pdma_src_dest_t src_dest,\r
+ uint32_t channel_cfg,\r
+ uint8_t write_adjust\r
+)\r
+{\r
+ /* Reset the channel. */\r
+ PDMA->CHANNEL[channel_id].CRTL |= CHANNEL_RESET_MASK;\r
+ PDMA->CHANNEL[channel_id].CRTL &= ~CHANNEL_RESET_MASK;\r
+\r
+ /* Configure PDMA channel's data source and destination. */\r
+ if ( src_dest != PDMA_MEM_TO_MEM )\r
+ {\r
+ PDMA->CHANNEL[channel_id].CRTL |= src_dest_to_ctrl_reg_lut[src_dest];\r
+ }\r
+ \r
+ /* Configure PDMA channel trnasfer size, priority, source and destination address increment. */\r
+ PDMA->CHANNEL[channel_id].CRTL |= channel_cfg;\r
+\r
+ /* Posted write adjust. */\r
+ PDMA->CHANNEL[channel_id].CRTL |= ((uint32_t)write_adjust << CHANNEL_N_POSTED_WRITE_ADJUST_SHIFT);\r
+}\r
+\r
+/***************************************************************************//**\r
+ * See mss_pdma.h for description of this function.\r
+ */\r
+#define PAUSE_MASK (uint32_t)0x00000010\r
+\r
+#define BUFFER_B_SELECT_MASK (uint32_t)0x00000004\r
+\r
+#define CLEAR_PORT_A_DONE_MASK (uint32_t)0x00000080\r
+#define CLEAR_PORT_B_DONE_MASK (uint32_t)0x00000100\r
+\r
+#define PORT_A_COMPLETE_MASK (uint32_t)0x00000001\r
+#define PORT_B_COMPLETE_MASK (uint32_t)0x00000002\r
+\r
+void PDMA_start\r
+(\r
+ pdma_channel_id_t channel_id,\r
+ uint32_t src_addr,\r
+ uint32_t dest_addr,\r
+ uint16_t transfer_count\r
+)\r
+{\r
+ /* Pause transfer. */\r
+ PDMA->CHANNEL[channel_id].CRTL |= PAUSE_MASK;\r
+ \r
+ /* Clear complete transfers. */\r
+ if ( PDMA->CHANNEL[channel_id].STATUS & PORT_A_COMPLETE_MASK )\r
+ {\r
+ PDMA->CHANNEL[channel_id].CRTL |= CLEAR_PORT_A_DONE_MASK;\r
+ g_pdma_started_a[channel_id] = CHANNEL_STOPPED;\r
+ }\r
+ if ( PDMA->CHANNEL[channel_id].STATUS & PORT_B_COMPLETE_MASK )\r
+ {\r
+ PDMA->CHANNEL[channel_id].CRTL |= CLEAR_PORT_B_DONE_MASK;\r
+ g_pdma_started_b[channel_id] = CHANNEL_STOPPED;\r
+ }\r
+ \r
+ /* Load source, destination and transfer count. */\r
+ if ( PDMA->CHANNEL[channel_id].STATUS & BUFFER_B_SELECT_MASK )\r
+ {\r
+ g_pdma_next_channel[channel_id] = NEXT_CHANNEL_A;\r
+ g_pdma_started_b[channel_id] = CHANNEL_STARTED;\r
+ \r
+ PDMA->CHANNEL[channel_id].BUFFER_B_SRC_ADDR = src_addr;\r
+ PDMA->CHANNEL[channel_id].BUFFER_B_DEST_ADDR = dest_addr;\r
+ PDMA->CHANNEL[channel_id].BUFFER_B_TRANSFER_COUNT = transfer_count;\r
+ }\r
+ else\r
+ {\r
+ g_pdma_next_channel[channel_id] = NEXT_CHANNEL_B;\r
+ g_pdma_started_a[channel_id] = CHANNEL_STARTED;\r
+ \r
+ PDMA->CHANNEL[channel_id].BUFFER_A_SRC_ADDR = src_addr;\r
+ PDMA->CHANNEL[channel_id].BUFFER_A_DEST_ADDR = dest_addr;\r
+ PDMA->CHANNEL[channel_id].BUFFER_A_TRANSFER_COUNT = transfer_count;\r
+ }\r
+ \r
+ /* Start transfer */\r
+ PDMA->CHANNEL[channel_id].CRTL &= ~PAUSE_MASK;\r
+}\r
+\r
+/***************************************************************************//**\r
+ * See mss_pdma.h for description of this function.\r
+ */\r
+void PDMA_load_next_buffer\r
+(\r
+ pdma_channel_id_t channel_id,\r
+ uint32_t src_addr,\r
+ uint32_t dest_addr,\r
+ uint16_t transfer_count\r
+)\r
+{\r
+ if ( NEXT_CHANNEL_A == g_pdma_next_channel[channel_id] )\r
+ {\r
+ /* Wait for channel A current transfer completion. */\r
+ if ( CHANNEL_STARTED == g_pdma_started_a[channel_id] )\r
+ {\r
+ uint32_t completed;\r
+ uint32_t channel_mask;\r
+ channel_mask = (uint32_t)1 << ((uint32_t)channel_id * 2U);\r
+ do {\r
+ completed = PDMA->BUFFER_STATUS & channel_mask;\r
+ } while( !completed );\r
+ PDMA->CHANNEL[channel_id].CRTL |= CLEAR_PORT_A_DONE_MASK;\r
+ }\r
+ /* Load source, destination and transfer count. */\r
+ PDMA->CHANNEL[channel_id].BUFFER_A_SRC_ADDR = src_addr;\r
+ PDMA->CHANNEL[channel_id].BUFFER_A_DEST_ADDR = dest_addr;\r
+ PDMA->CHANNEL[channel_id].BUFFER_A_TRANSFER_COUNT = transfer_count;\r
+ \r
+ /* Update channel state information. */\r
+ g_pdma_next_channel[channel_id] = NEXT_CHANNEL_B;\r
+ g_pdma_started_a[channel_id] = CHANNEL_STARTED;\r
+ }\r
+ else\r
+ {\r
+ /* Wait for channel B current transfer completion. */\r
+ if ( CHANNEL_STARTED == g_pdma_started_b[channel_id] )\r
+ {\r
+ uint32_t completed;\r
+ uint32_t channel_mask;\r
+ channel_mask = (uint32_t)1 << (((uint32_t)channel_id * 2U) + 1U);\r
+ do {\r
+ completed = PDMA->BUFFER_STATUS & channel_mask;\r
+ } while( !completed );\r
+ PDMA->CHANNEL[channel_id].CRTL |= CLEAR_PORT_B_DONE_MASK;\r
+ } \r
+ /* Load source, destination and transfer count. */\r
+ PDMA->CHANNEL[channel_id].BUFFER_B_SRC_ADDR = src_addr;\r
+ PDMA->CHANNEL[channel_id].BUFFER_B_DEST_ADDR = dest_addr;\r
+ PDMA->CHANNEL[channel_id].BUFFER_B_TRANSFER_COUNT = transfer_count;\r
+ \r
+ /* Update channel state information. */\r
+ g_pdma_next_channel[channel_id] = NEXT_CHANNEL_A;\r
+ g_pdma_started_b[channel_id] = CHANNEL_STARTED;\r
+ }\r
+}\r
+\r
+/***************************************************************************//**\r
+ * See mss_pdma.h for description of this function.\r
+ */\r
+uint32_t PDMA_status\r
+(\r
+ pdma_channel_id_t channel_id\r
+)\r
+{\r
+ uint32_t status;\r
+ \r
+ status = PDMA->CHANNEL[channel_id].STATUS & (PORT_A_COMPLETE_MASK | PORT_B_COMPLETE_MASK);\r
+ \r
+ return status;\r
+}\r
+\r
+/***************************************************************************//**\r
+ *\r
+ */\r
+#define CHANNEL_0_STATUS_BITS_MASK (uint16_t)0x0003\r
+#define CHANNEL_1_STATUS_BITS_MASK (uint16_t)0x000C\r
+#define CHANNEL_2_STATUS_BITS_MASK (uint16_t)0x0030\r
+#define CHANNEL_3_STATUS_BITS_MASK (uint16_t)0x00C0\r
+#define CHANNEL_4_STATUS_BITS_MASK (uint16_t)0x0300\r
+#define CHANNEL_5_STATUS_BITS_MASK (uint16_t)0x0C00\r
+#define CHANNEL_6_STATUS_BITS_MASK (uint16_t)0x3000\r
+#define CHANNEL_7_STATUS_BITS_MASK (uint16_t)0xC000\r
+\r
+static pdma_channel_id_t get_channel_id_from_status\r
+(\r
+ uint16_t status\r
+)\r
+{\r
+ pdma_channel_id_t channel_id = PDMA_CHANNEL_0;\r
+ \r
+ if ( status & CHANNEL_0_STATUS_BITS_MASK )\r
+ {\r
+ channel_id = PDMA_CHANNEL_0;\r
+ }\r
+ else if ( status & CHANNEL_1_STATUS_BITS_MASK )\r
+ {\r
+ channel_id = PDMA_CHANNEL_1;\r
+ }\r
+ else if ( status & CHANNEL_2_STATUS_BITS_MASK )\r
+ {\r
+ channel_id = PDMA_CHANNEL_2;\r
+ }\r
+ else if ( status & CHANNEL_3_STATUS_BITS_MASK )\r
+ {\r
+ channel_id = PDMA_CHANNEL_3;\r
+ }\r
+ else if ( status & CHANNEL_4_STATUS_BITS_MASK )\r
+ {\r
+ channel_id = PDMA_CHANNEL_4;\r
+ }\r
+ else if ( status & CHANNEL_5_STATUS_BITS_MASK )\r
+ {\r
+ channel_id = PDMA_CHANNEL_5;\r
+ }\r
+ else if ( status & CHANNEL_6_STATUS_BITS_MASK )\r
+ {\r
+ channel_id = PDMA_CHANNEL_6;\r
+ }\r
+ else if ( status & CHANNEL_7_STATUS_BITS_MASK )\r
+ {\r
+ channel_id = PDMA_CHANNEL_7;\r
+ }\r
+ else\r
+ {\r
+ ASSERT(0);\r
+ }\r
+ return channel_id;\r
+}\r
+\r
+/***************************************************************************//**\r
+ *\r
+ */\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void DMA_IRQHandler( void )\r
+#else\r
+void DMA_IRQHandler( void )\r
+#endif\r
+{\r
+ uint16_t status;\r
+ pdma_channel_id_t channel_id;\r
+ \r
+ status = (uint16_t)PDMA->BUFFER_STATUS;\r
+ \r
+ do {\r
+ channel_id = get_channel_id_from_status( status );\r
+ status &= (uint16_t)~g_pdma_status_mask[channel_id];\r
+ if ( 0 != g_pdma_isr_table[channel_id])\r
+ {\r
+ g_pdma_isr_table[channel_id]();\r
+ }\r
+ } while ( 0U != status );\r
+ \r
+ NVIC_ClearPendingIRQ( DMA_IRQn );\r
+}\r
+\r
+/***************************************************************************//**\r
+ * See mss_pdma.h for description of this function.\r
+ */\r
+void PDMA_set_irq_handler\r
+(\r
+ pdma_channel_id_t channel_id,\r
+ pdma_channel_isr_t handler\r
+)\r
+{\r
+ /* Save address of handler function in PDMA driver ISR lookup table. */\r
+ g_pdma_isr_table[channel_id] = handler;\r
+ \r
+ /* Enable PDMA channel's interrupt. */\r
+ PDMA->CHANNEL[channel_id].CRTL |= PDMA_IRQ_ENABLE_MASK;\r
+ \r
+ /* Enable PDMA interrupt in Cortex-M3 NVIC. */\r
+ NVIC_EnableIRQ( DMA_IRQn );\r
+}\r
+\r
+/***************************************************************************//**\r
+ * See mss_pdma.h for description of this function.\r
+ */\r
+void PDMA_enable_irq( pdma_channel_id_t channel_id )\r
+{\r
+ PDMA->CHANNEL[channel_id].CRTL |= PDMA_IRQ_ENABLE_MASK;\r
+ NVIC_EnableIRQ( DMA_IRQn );\r
+}\r
+\r
+/***************************************************************************//**\r
+ * See mss_pdma.h for description of this function.\r
+ */\r
+void PDMA_clear_irq\r
+(\r
+ pdma_channel_id_t channel_id\r
+)\r
+{\r
+ /* Clear interrupt in PDMA controller. */\r
+ PDMA->CHANNEL[channel_id].CRTL |= CLEAR_PORT_A_DONE_MASK;\r
+ PDMA->CHANNEL[channel_id].CRTL |= CLEAR_PORT_B_DONE_MASK;\r
+ \r
+ /* Clear interrupt in Cortex-M3 NVIC. */\r
+ NVIC_ClearPendingIRQ( DMA_IRQn );\r
+}\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
--- /dev/null
+/*******************************************************************************\r
+ * (c) Copyright 2008 Actel Corporation. All rights reserved.\r
+ * \r
+ * SmartFusion microcontroller subsystem Peripheral DMA bare metal software\r
+ * driver public API.\r
+ *\r
+ * SVN $Revision: 2110 $\r
+ * SVN $Date: 2010-02-05 15:24:19 +0000 (Fri, 05 Feb 2010) $\r
+ */\r
+/*=========================================================================*//**\r
+ @mainpage SmartFusion MSS GPIO Bare Metal Driver.\r
+\r
+ @section intro_sec Introduction\r
+ The SmartFusion Microcontroller Subsystem (MSS) includes an 8 channel\r
+ Peripheral DMA (PDMA) controller.\r
+ This software driver provides a set of functions for controlling the MSS PDMA\r
+ controller as part of a bare metal system where no operating system is available.\r
+ This driver can be adapted for use as part of an operating system but the\r
+ implementation of the adaptation layer between this driver and the operating\r
+ system's driver model is outside the scope of this driver.\r
+ \r
+ @section theory_op Theory of Operation\r
+ The MSS PDMA driver uses the SmartFusion "Cortex Microcontroler Software\r
+ Interface Standard - Peripheral Access Layer" (CMSIS-PAL) to access MSS hardware\r
+ registers. You must ensure that the SmartFusion CMSIS-PAL is either included\r
+ in the software toolchain used to build your project or is included in your\r
+ project. The most up-to-date SmartFusion CMSIS-PAL files can be obtained using\r
+ the Actel Firmware Catalog.\r
+ \r
+ The MSS PDMA driver functions are grouped into the following categories:\r
+ - Initialization\r
+ - Configuration\r
+ - DMA transfer control\r
+ - Interrupt control\r
+ \r
+ The MSS PDMA driver is initialized through a call to the PDMA_init() function.\r
+ The PDMA_init() function must be called before any other PDMA driver functions\r
+ can be called.\r
+ \r
+ Each PDMA channel is individually configured through a call to the PDMA_configure()\r
+ function. Configuration includes:\r
+ - channel priority\r
+ - transfer size\r
+ - source and/or destination address increment\r
+ - source or destination of the DMA transfer\r
+ PDMA channels can be divided into high and low priority channels. High priority\r
+ channels are given more opportunities to perform transfers than low priority\r
+ channels when there are continuous high priority channels requests. The ratio\r
+ of high priority to low priority PDMA transfers is configurable through the\r
+ PDMA_set_priority() function.\r
+ PDMA channels can be configured to perform byte (8 bits), half-word (16 bits)\r
+ or word (32 bits) transfers.\r
+ The source and destination address of a PDMA channel\92s transfers can be\r
+ independently configured to increment by 0, 1, 2 or 4 bytes. For example, the\r
+ content of a byte buffer located in RAM can be transferred into a peripheral\92s\r
+ transmit register by configuring the source address increment to one byte and\r
+ no increment of the destination address.\r
+ The source or destination of a PDMA channel\92s transfers can be configured to\r
+ be one of the MSS peripherals. This allows the PDMA controller to use some\r
+ hardware flow control signaling with the peripheral to avoid overrunning the\r
+ peripheral\92s data buffer when the peripheral is the destination of the DMA\r
+ transfer, or attempting to read data from the peripheral while it is not ready\r
+ when the peripheral is the source of the transfer.\r
+ A PDMA channel can also be configured to transfer data between two memory\r
+ mapped locations (memory to memory). No hardware flow control is used by the\r
+ PDMA controller for data transfer in this configuration.\r
+ \r
+ A DMA transfer can be initiated by a call to the PDMA_start() function after a\r
+ PDMA channel has been configured. Once started, further data can be pushed\r
+ through the PDMA channel by calling the PDMA_load_next_buffer() function. The\r
+ PDMA_load_next_buffer() function can be called every time a call to the\r
+ PDMA_status() function indicates that the PDMA channel used for the transfer\r
+ has a free buffer or it can be called as a result of a PDMA interrupt.\r
+ \r
+ A DMA transfer can be paused and resumed through calls to functions PDMA_pause()\r
+ and PDMA_resume().\r
+ \r
+ Your application can manage DMA transfers using interrupts through the use of\r
+ the following functions:\r
+ - PDMA_set_irq_handler()\r
+ - PDMA_enable_irq()\r
+ - PDMA_clear_irq()\r
+ - PDMA_disable_irq()\r
+ The PDMA_set_irq_handler() function is used to register PDMA channel interrupt\r
+ handler functions with the driver. You must create and register an interrupt\r
+ handler function for each interrupt driven PDMA channel used by the application.\r
+ Use the PDMA_enable_irq() function to enable interrupts for the PDMA channels. \r
+ Every time a PDMA channel completes the transfer of a buffer it causes a PDMA\r
+ interrupt to occur and the PDMA driver will call the interrupt handler\r
+ registered by the application for that PDMA channel.\r
+ \r
+ *//*=========================================================================*/\r
+#ifndef __MSS_PERIPHERAL_DMA_H_\r
+#define __MSS_PERIPHERAL_DMA_H_\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif \r
+\r
+#include "../../CMSIS/a2fxxxm3.h"\r
+\r
+/***************************************************************************//**\r
+ The pdma_channel_id_t enumeration is used to identify peripheral DMA channels.\r
+ It is used as function parameter to specify the PDMA channel used.\r
+ */\r
+typedef enum __pdma_channel_id\r
+{\r
+ PDMA_CHANNEL_0 = 0,\r
+ PDMA_CHANNEL_1,\r
+ PDMA_CHANNEL_2,\r
+ PDMA_CHANNEL_3,\r
+ PDMA_CHANNEL_4,\r
+ PDMA_CHANNEL_5,\r
+ PDMA_CHANNEL_6,\r
+ PDMA_CHANNEL_7\r
+} pdma_channel_id_t;\r
+\r
+/***************************************************************************//**\r
+ The pdma_src_dest_t enumeration is used to specify the source or destination\r
+ of transfers on a PDMA channel. It specifies which hardware peripheral will be\r
+ the source or destination of DMA transfers. This allows the PDMA controller\r
+ to use hardware flow control signals to avoid overrunning a\r
+ destination peripheral with data it is not ready to receive, or attempting to\r
+ transfer data from a peripheral while it has no data ready to transfer.\r
+ The pdma_src_dest_t enumeration can also be used to specify that a PDMA channel\r
+ is configured to transfer data between two memory mapped locations\r
+ (memory to memory). No hardware data flow control is used by the PDMA\r
+ controller in this configuration.\r
+ This enumeration is used as parameter to function PDMA_configure().\r
+ */\r
+typedef enum __pdma_src_dest\r
+{\r
+ PDMA_FROM_UART_0 = 0,\r
+ PDMA_TO_UART_0,\r
+ PDMA_FROM_UART_1,\r
+ PDMA_TO_UART_1,\r
+ PDMA_FROM_SPI_0,\r
+ PDMA_TO_SPI_0,\r
+ PDMA_FROM_SPI_1,\r
+ PDMA_TO_SPI_1,\r
+ PDMA_FROM_FPGA_1,\r
+ PDMA_TO_FPGA_1,\r
+ PDMA_FROM_FPGA_0,\r
+ PDMA_TO_FPGA_0,\r
+ PDMA_TO_ACE,\r
+ PDMA_FROM_ACE,\r
+ PDMA_MEM_TO_MEM\r
+} pdma_src_dest_t;\r
+\r
+/***************************************************************************//**\r
+ The pdma_priority_ratio_t enumeration is used to configure the ratio of high\r
+ priority to low priority PDMA channels. This ratio specifies how many DMA\r
+ transfer opportunities will be given to high priority channels before a DMA\r
+ transfer opportunity is given to a low priority channel when there are\r
+ continuous requests from high priority channels. This enumeration is used as\r
+ parameter to function PDMA_set_priority_ratio().\r
+ */\r
+typedef enum __pdma_priority_ratio_t\r
+{\r
+ PDMA_ROUND_ROBIN = 0,\r
+ PDMA_RATIO_HIGH_LOW_1_TO_1 = 1,\r
+ PDMA_RATIO_HIGH_LOW_3_TO_1 = 3,\r
+ PDMA_RATIO_HIGH_LOW_7_TO_1 = 7,\r
+ PDMA_RATIO_HIGH_LOW_15_TO_1 = 15,\r
+ PDMA_RATIO_HIGH_LOW_31_TO_1 = 31,\r
+ PDMA_RATIO_HIGH_LOW_63_TO_1 = 63,\r
+ PDMA_RATIO_HIGH_LOW_127_TO_1 = 127,\r
+ PDMA_RATIO_HIGH_LOW_255_TO_1 = 255\r
+} pdma_priority_ratio_t;\r
+\r
+\r
+/***************************************************************************//**\r
+ The pdma_channel_isr_t type is a pointer to a PDMA channel interrupt handler\r
+ function. It specifies the function prototype of functions that can be\r
+ registered as PDMA channel interrupt handlers. It is used as parameter to\r
+ function PDMA_set_irq_handler().\r
+ */\r
+typedef void (*pdma_channel_isr_t)( void );\r
+/***************************************************************************//**\r
+ These constants are used to build the channel_cfg parameter of the\r
+ PDMA_configure() function. They specify whether a channel is a high or low\r
+ priority channel.\r
+ */\r
+#define PDMA_LOW_PRIORITY 0x0000\r
+#define PDMA_HIGH_PRIORITY 0x0200\r
+\r
+/***************************************************************************//**\r
+ These constants are used to build the channel_cfg parameter of the\r
+ PDMA_configure() function. They specify the data width of the transfers\r
+ performed by a PDMA channel.\r
+ */\r
+#define PDMA_BYTE_TRANSFER 0x0000 /* Byte transfers (8 bits) */\r
+#define PDMA_HALFWORD_TRANSFER 0x0004 /* Half-word transfers (16 bits) */\r
+#define PDMA_WORD_TRANSFER 0x0008 /* Word transfers (32 bits) */\r
+\r
+/***************************************************************************//**\r
+ These constants are used to build the channel_cfg parameter of the\r
+ PDMA_configure() function. They specify the PDMA channel\92s source and\r
+ destination address increment.\r
+ */\r
+#define PDMA_NO_INC 0\r
+#define PDMA_INC_SRC_ONE_BYTE 0x0400\r
+#define PDMA_INC_SRC_TWO_BYTES 0x0800\r
+#define PDMA_INC_SRC_FOUR_BYTES 0x0C00\r
+#define PDMA_INC_DEST_ONE_BYTE 0x1000\r
+#define PDMA_INC_DEST_TWO_BYTES 0x2000\r
+#define PDMA_INC_DEST_FOUR_BYTES 0x3000\r
+\r
+/***************************************************************************//**\r
+ * Mask for various control register bits.\r
+ */\r
+#define PDMA_IRQ_ENABLE_MASK (uint32_t)0x00000040\r
+#define PDMA_PAUSE_MASK (uint32_t)0x00000010\r
+\r
+/***************************************************************************//**\r
+ These constants are used to specify the src_addr parameter to the PDMA_start()\r
+ and PDMA_load_next_buffer() functions. They specify the receive register\r
+ address of peripherals that can be the source of a DMA transfer. \r
+ When a PDMA channel is configured for DMA transfers from a peripheral to memory,\r
+ the constant specifying that peripheral\92s receive register address must be used\r
+ as the src_addr parameter.\r
+ */\r
+#define PDMA_SPI0_RX_REGISTER 0x40001010uL\r
+#define PDMA_SPI1_RX_REGISTER 0x40011010uL\r
+#define PDMA_UART0_RX_REGISTER 0x40000000uL\r
+#define PDMA_UART1_RX_REGISTER 0x40010000uL\r
+#define PDMA_ACE_PPE_DATAOUT 0x40021308uL\r
+\r
+/***************************************************************************//**\r
+ These constants are used to specify the dest_addr parameter to the PDMA_start()\r
+ and PDMA_load_next_buffer() functions. They specify the transmit register\r
+ address of peripherals that can be the destination of a DMA transfer. \r
+ When a PDMA channel is configured for DMA transfers from memory to a peripheral,\r
+ the constant specifying that peripheral\92s transmit register address must be used\r
+ as the dest_addr parameter.\r
+ */\r
+#define PDMA_SPI0_TX_REGISTER 0x40001014uL\r
+#define PDMA_SPI1_TX_REGISTER 0x40011014uL\r
+#define PDMA_UART0_TX_REGISTER 0x40000000uL\r
+#define PDMA_UART1_TX_REGISTER 0x40010000uL\r
+#define PDMA_ACE_SSE_DATAIN 0x40020700uL\r
+\r
+/***************************************************************************//**\r
+ The PDMA_DEFAULT_WRITE_ADJ constant provides a suitable default value for the\r
+ PDMA_configure() function write_adjust parameter.\r
+ */\r
+#define PDMA_DEFAULT_WRITE_ADJ 10u\r
+\r
+/***************************************************************************//**\r
+ The PDMA_init() function initializes the peripheral DMA hardware and driver\r
+ internal data. It resets the PDMA and it also clears any pending PDMA\r
+ interrupts in the Cortex-M3 interrupt controller. When the function exits, it\r
+ takes the PDMA block out of reset.\r
+ */\r
+void PDMA_init( void );\r
+\r
+/***************************************************************************//**\r
+ The PDMA_configure() function configures a PDMA channel.\r
+ It specifies:\r
+ - The peripheral which will be the source or destination of the DMA transfer.\r
+ - Whether the DMA channel will be a high or low priority channel\r
+ - The source and destination address increment that will take place after\r
+ each transfer.\r
+ \r
+ @param channel_id\r
+ The channel_id parameter identifies the PDMA channel used by the function.\r
+ \r
+ @param src_dest\r
+ The src_dest parameter specifies the source or destination of the DMA\r
+ transfers that will be performed. It can be one of the following:\r
+ - PDMA_FROM_UART_0\r
+ - PDMA_TO_UART_0\r
+ - PDMA_FROM_UART_1\r
+ - PDMA_TO_UART_1\r
+ - PDMA_FROM_SPI_0\r
+ - PDMA_TO_SPI_0\r
+ - PDMA_FROM_SPI_1\r
+ - PDMA_TO_SPI_1\r
+ - PDMA_FROM_FPGA_1\r
+ - PDMA_TO_FPGA_1\r
+ - PDMA_FROM_FPGA_0\r
+ - PDMA_TO_FPGA_0\r
+ - PDMA_TO_ACE\r
+ - PDMA_FROM_ACE\r
+ - PDMA_MEM_TO_MEM\r
+ \r
+ @param channel_cfg\r
+ The channel_cfg parameter specifies the configuration of the PDMA channel.\r
+ The configuration includes:\r
+ - channel priority\r
+ - transfer size\r
+ - source and/or destination address increment\r
+ The channel_cfg parameter value is a logical OR of:\r
+ One of the following to specify the channel priority:\r
+ - PDMA_LOW_PRIORITY\r
+ - PDMA_HIGH_PRIORITY\r
+ One of the following to specify the transfer size:\r
+ - PDMA_BYTE_TRANSFER\r
+ - PDMA_HALFWORD_TRANSFER\r
+ - PDMA_WORD_TRANSFER\r
+ One or two of the following to specify the source and/or destination address\r
+ increment:\r
+ - PDMA_NO_INC\r
+ - PDMA_INC_SRC_ONE_BYTE\r
+ - PDMA_INC_SRC_TWO_BYTES\r
+ - PDMA_INC_SRC_FOUR_BYTES\r
+ - PDMA_INC_DEST_ONE_BYTE\r
+ - PDMA_INC_DEST_TWO_BYTES\r
+ - PDMA_INC_DEST_FOUR_BYTES\r
+ \r
+ @param write_adjust\r
+ The write_adjust parameter specifies the number of Cortex-M3 clock cycles\r
+ the PDMA controller will wait before attempting another transfer cycle. This\r
+ delay is necessary when peripherals are used as destination of a DMA transfer\r
+ to ensure the DMA controller interprets the state of the peripheral\92s ready\r
+ signal only after data has actually been written to the peripheral. This delay\r
+ accounts for posted writes (dump and run) for write accesses to peripherals. \r
+ The effect of posted writes is that if the PDMA performs a write operation to\r
+ a peripheral, the data is not actually written into the peripheral until\r
+ sometime after the PDMA controller thinks it is written.\r
+ A suitable value for write_adjust depends on the target of the DMA transfer.\r
+ Guidelines for choosing this value are as follows:\r
+ \95 The PDMA_DEFAULT_WRITE_ADJ constant provides a suitable default value\r
+ for the write_adjust parameter when the PDMA channel is configured for\r
+ transfers with MSS peripherals.\r
+ \95 The PDMA_DEFAULT_WRITE_ADJ constant can also be used for DMA transfers\r
+ with FPGA fabric implemented peripherals making use of the DMAREADY0 or\r
+ DMAREADY1fabric interface signal to indicate that the peripheral is\r
+ ready for another DMA transfer.\r
+ \95 The write_adjust parameter can be set to zero to achieve maximum transfer\r
+ speed for genuine memory to memory transfers. \r
+ \95 The internal latency of FPGA implemented peripherals will decide the\r
+ write_adjust value for fabric peripherals that do not use the DMAREADY0\r
+ or DMAREADY1 fabric interface signals. You need to check the fabric\r
+ peripheral documentation for the value to use.\r
+ \r
+ Example:\r
+ @code\r
+ PDMA_configure\r
+ (\r
+ PDMA_CHANNEL_0,\r
+ PDMA_TO_SPI_1,\r
+ PDMA_LOW_PRIORITY | PDMA_BYTE_TRANSFER | PDMA_INC_SRC_ONE_BYTE,\r
+ PDMA_DEFAULT_WRITE_ADJ\r
+ );\r
+ @endcode\r
+ */\r
+void PDMA_configure\r
+(\r
+ pdma_channel_id_t channel_id,\r
+ pdma_src_dest_t src_dest,\r
+ uint32_t channel_cfg,\r
+ uint8_t write_adjust\r
+);\r
+\r
+\r
+/***************************************************************************//**\r
+ The PDMA_set_priority_ratio() function sets the ratio of high priority to low\r
+ priority DMA access opportunities. This ratio is used by the PDMA controller\r
+ arbiter to decide which PDMA channel will be given the opportunity to perform\r
+ a transfer when multiple PDMA channels are requesting to transfer data at the\r
+ same time. The priority ratio specifies how many DMA transfer opportunities\r
+ will be given to high priority channels before a DMA transfer opportunity is\r
+ given to a low priority channel when there are continuous requests from high\r
+ priority channels.\r
+ \r
+ @param priority_ratio\r
+ The priority_ratio parameter specifies the ratio of DMA access opportunities\r
+ given to high priority channels versus low priority channels.\r
+ Allowed values for this parameter are:\r
+ - PDMA_ROUND_ROBIN\r
+ - PDMA_RATIO_HIGH_LOW_1_TO_1\r
+ - PDMA_RATIO_HIGH_LOW_3_TO_1\r
+ - PDMA_RATIO_HIGH_LOW_7_TO_1\r
+ - PDMA_RATIO_HIGH_LOW_15_TO_1\r
+ - PDMA_RATIO_HIGH_LOW_31_TO_1\r
+ - PDMA_RATIO_HIGH_LOW_63_TO_1\r
+ - PDMA_RATIO_HIGH_LOW_127_TO_1\r
+ - PDMA_RATIO_HIGH_LOW_255_TO_1\r
+ \r
+ Example:\r
+ @code\r
+ PDMA_set_priority_ratio( PDMA_ROUND_ROBIN );\r
+ @endcode\r
+ */\r
+static __INLINE void PDMA_set_priority_ratio\r
+(\r
+ pdma_priority_ratio_t priority_ratio\r
+)\r
+{\r
+ PDMA->RATIO_HIGH_LOW = (uint32_t)priority_ratio;\r
+}\r
+\r
+/***************************************************************************//**\r
+ The PDMA_start() function initiates a DMA transfer. It specifies the source\r
+ and destination address of the transfer as well as the number of transfers\r
+ that must take place. The source and destination addresses can be the address\r
+ of peripheral registers.\r
+ \r
+ @param channel_id\r
+ The channel_id parameter identifies the PDMA channel used by the function.\r
+ \r
+ @param src_addr\r
+ The src_addr parameter specifies the address location of the data to be\r
+ transferred. You must ensure that this source address is consistent with the\r
+ DMA source configured for the selected channel using the PDMA_configure()\r
+ function.\r
+ For DMA transfers from MSS peripheral to memory, the following src_addr\r
+ parameter values are allowed:\r
+ \95 PDMA_SPI0_RX_REGISTER\r
+ \95 PDMA_SPI1_RX_REGISTER\r
+ \95 PDMA_UART0_RX_REGISTER\r
+ \95 PDMA_UART1_RX_REGISTER\r
+ \95 PDMA_ACE_PPE_DATAOUT\r
+ For DMA transfers from FPGA fabric peripheral to memory, the following\r
+ src_addr parameter values are allowed:\r
+ \95 An address in the FPGA fabric address space (0x40050000-0x400FFFFF)\r
+ For DMA transfers from memory to MSS peripheral, or from memory to FPGA\r
+ fabric peripheral, or from memory to memory, the following src_addr\r
+ parameter values are allowed:\r
+ \95 Any memory mapped address.\r
+\r
+ @param dest_addr\r
+ The dest_addr parameter specifies the destination address of the PDMA\r
+ transfer. You must ensure that this matches with the DMA destination\r
+ configured for the selected channel.\r
+ For DMA transfers from memory to MSS peripheral, the following dest_addr parameter values are allowed:\r
+ \95 PDMA_SPI0_TX_REGISTER\r
+ \95 PDMA_SPI1_TX_REGISTER\r
+ \95 PDMA_UART0_TX_REGISTER\r
+ \95 PDMA_UART1_TX_REGISTER\r
+ \95 PDMA_ACE_SSE_DATAIN\r
+ For DMA transfers from memory to FPGA fabric peripheral, the following\r
+ dest_addr parameter values are allowed:\r
+ \95 An address in the FPGA fabric address space (0x40050000-0x400FFFFF)\r
+ For DMA transfers from MSS peripheral to memory, or from FPGA fabric\r
+ peripheral to memory, or from memory to memory, the following dest_addr\r
+ parameter values are allowed:\r
+ \95 Any memory mapped address.\r
+\r
+ @param transfer_count\r
+ The transfer_count parameter specifies the number of transfers to be\r
+ performed. It is the number of bytes to transfer if the PDMA channel is\r
+ configured for byte transfer, the number of half-words to transfer if the\r
+ PDMA channel is configured for half-word transfer, or the number of words\r
+ to transfer if the PDMA channel is configured for word transfer.\r
+ \r
+ Example:\r
+ @code\r
+ PDMA_start\r
+ (\r
+ PDMA_CHANNEL_3,\r
+ PDMA_SPI1_RX_REGISTER,\r
+ (uint32_t)slave_rx_buffer,\r
+ sizeof(slave_rx_buffer)\r
+ ); \r
+ @endcode\r
+ */\r
+void PDMA_start\r
+(\r
+ pdma_channel_id_t channel_id,\r
+ uint32_t src_addr,\r
+ uint32_t dest_addr,\r
+ uint16_t transfer_count\r
+);\r
+\r
+/***************************************************************************//**\r
+ The PDMA_load_next_buffer() function sets the next buffer to be transferred.\r
+ This function is called after a transfer has been initiated using the\r
+ PDMA_start() function. Its purpose is to keep feeding a PDMA channel with data\r
+ buffers.\r
+ \r
+ @param channel_id\r
+ The channel_id parameter identifies the PDMA channel used by the function.\r
+ \r
+ @param src_addr\r
+ The src_addr parameter specifies the address location of the data to be\r
+ transferred. You must ensure that this source address is consistent with the\r
+ DMA source configured for the selected channel using the PDMA_configure()\r
+ function.\r
+ For DMA transfers from MSS peripheral to memory, the following src_addr parameter values are allowed:\r
+ \95 PDMA_SPI0_RX_REGISTER\r
+ \95 PDMA_SPI1_RX_REGISTER\r
+ \95 PDMA_UART0_RX_REGISTER\r
+ \95 PDMA_UART1_RX_REGISTER\r
+ \95 PDMA_ACE_PPE_DATAOUT\r
+ For DMA transfers from FPGA fabric peripheral to memory, the following src_addr parameter values are allowed:\r
+ \95 An address in the FPGA fabric address space (0x40050000-0x400FFFFF)\r
+ For DMA transfers from memory to MSS peripheral, or from memory to FPGA fabric peripheral, or from memory to memory, the following src_addr parameter values are allowed:\r
+ \95 Any memory mapped address.\r
+\r
+ @param dest_addr\r
+ The dest_addr parameter specifies the destination address of the PDMA\r
+ transfer. You must ensure that this matches with the DMA destination\r
+ configured for the selected channel.\r
+ For DMA transfers from memory to MSS peripheral, the following dest_addr parameter values are allowed:\r
+ \95 PDMA_SPI0_TX_REGISTER\r
+ \95 PDMA_SPI1_TX_REGISTER\r
+ \95 PDMA_UART0_TX_REGISTER\r
+ \95 PDMA_UART1_TX_REGISTER\r
+ \95 PDMA_ACE_SSE_DATAIN\r
+ For DMA transfers from memory to FPGA fabric peripheral, the following dest_addr parameter values are allowed:\r
+ \95 An address in the FPGA fabric address space (0x40050000-0x400FFFFF)\r
+ For DMA transfers from MSS peripheral to memory, or from FPGA fabric peripheral to memory, or from memory to memory, the following dest_addr parameter values are allowed:\r
+ \95 Any memory mapped address.\r
+ \r
+ @param transfer_count\r
+ The transfer_count parameter specifies the number of transfers to be\r
+ performed. It is the number of bytes to transfer if the PDMA channel is\r
+ configured for byte transfer, the number of half-words to transfer if the\r
+ PDMA channel is configured for half-word transfer or the number of words to\r
+ transfer if the PDMA channel is configured for word transfer.\r
+ \r
+ Example:\r
+ @code\r
+ void write_cmd_data\r
+ (\r
+ mss_spi_instance_t * this_spi,\r
+ const uint8_t * cmd_buffer,\r
+ uint16_t cmd_byte_size,\r
+ uint8_t * data_buffer,\r
+ uint16_t data_byte_size\r
+ )\r
+ {\r
+ uint32_t transfer_size;\r
+ \r
+ transfer_size = cmd_byte_size + data_byte_size;\r
+ \r
+ MSS_SPI_disable( this_spi );\r
+ MSS_SPI_set_transfer_byte_count( this_spi, transfer_size );\r
+ \r
+ PDMA_start\r
+ (\r
+ PDMA_CHANNEL_0,\r
+ (uint32_t)cmd_buffer,\r
+ PDMA_SPI1_TX_REGISTER,\r
+ cmd_byte_size\r
+ );\r
+ \r
+ PDMA_load_next_buffer\r
+ (\r
+ PDMA_CHANNEL_0,\r
+ (uint32_t)data_buffer,\r
+ PDMA_SPI1_TX_REGISTER,\r
+ data_byte_size\r
+ );\r
+ \r
+ MSS_SPI_enable( this_spi );\r
+ \r
+ while ( !MSS_SPI_tx_done(this_spi) )\r
+ {\r
+ ;\r
+ }\r
+ }\r
+ @endcode\r
+ */\r
+void PDMA_load_next_buffer\r
+(\r
+ pdma_channel_id_t channel_id,\r
+ uint32_t src_addr,\r
+ uint32_t dest_addr,\r
+ uint16_t transfer_count\r
+);\r
+\r
+/***************************************************************************//**\r
+ The PDMA_status() function returns the status of a DMA channel.\r
+ The returned value indicates if transfers have been completed using buffer A\r
+ or buffer B of the PDMA hardware block.\r
+ \r
+ @param channel_id\r
+ The channel_id parameter identifies the PDMA channel used by the function.\r
+ \r
+ @return\r
+ bit 0 of the return value indicates if buffer A has been trasnfered. It is\r
+ set to 1 if the transfer has completed.\r
+ bit 1 of the return value indicates if buffer B has been transfered. It is\r
+ set to 1 if the transfer has completed.\r
+ */\r
+uint32_t PDMA_status\r
+(\r
+ pdma_channel_id_t channel_id\r
+);\r
+\r
+/***************************************************************************//**\r
+ The PDMA_pause() function temporarily pauses a PDMA transfer taking place on\r
+ the specified PDMA channel. The transfer can later be resumed by using the\r
+ PDMA_resume() function.\r
+ \r
+ @param channel_id\r
+ The channel_id parameter identifies the PDMA channel used by the function.\r
+ */\r
+static __INLINE void PDMA_pause( pdma_channel_id_t channel_id )\r
+{\r
+ PDMA->CHANNEL[channel_id].CRTL |= PDMA_PAUSE_MASK;\r
+}\r
+\r
+/***************************************************************************//**\r
+ The PDMA_resume() function resumes a transfer previously paused using the\r
+ PDMA_pause() function.\r
+ \r
+ @param channel_id The channel_id parameter identifies the PDMA channel\r
+ used by the function.\r
+ */\r
+static __INLINE void PDMA_resume( pdma_channel_id_t channel_id )\r
+{\r
+ PDMA->CHANNEL[channel_id].CRTL &= ~PDMA_PAUSE_MASK;\r
+}\r
+\r
+/***************************************************************************//**\r
+ The PDMA_enable_irq() enables the PDMA hardware to generate an interrupt when\r
+ a DMA transfer completes on the specified PDMA channel. This function also\r
+ enables the PDMA interrupt in the Cortex-M3 interrupt controller.\r
+ \r
+ @param channel_id\r
+ The channel_id parameter identifies the PDMA channel used by the function.\r
+ */\r
+void PDMA_enable_irq( pdma_channel_id_t channel_id );\r
+\r
+/***************************************************************************//**\r
+ The PDMA_disable_irq() disables interrupts for a specific PDMA channel.\r
+ \r
+ @param channel_id\r
+ The channel_id parameter identifies the PDMA channel used by the function.\r
+ */\r
+static __INLINE void PDMA_disable_irq( pdma_channel_id_t channel_id )\r
+{\r
+ PDMA->CHANNEL[channel_id].CRTL &= ~PDMA_IRQ_ENABLE_MASK;\r
+}\r
+\r
+/***************************************************************************//**\r
+ The PDMA_set_irq_handler() function registers a handler function for\r
+ interrupts generated on the completion of a transfer on a specific PDMA\r
+ channel. This function also enables the PDMA interrupt both in the PDMA\r
+ controller and in the Cortex-M3 interrupt controller.\r
+ \r
+ @param channel_id\r
+ The channel_id parameter identifies the PDMA channel used by the function.\r
+ \r
+ @param handler\r
+ The handler parameter is a pointer to the function that will be called when\r
+ a transfer completes on the PDMA channel identified by channel_id and the\r
+ interrupt is enabled for that channel.\r
+ \r
+ Example:\r
+ @code\r
+ void slave_dma_irq_handler( void )\r
+ {\r
+ if ( g_spi1_rx_buffer[2] == 0x99 )\r
+ {\r
+ PDMA_load_next_buffer\r
+ (\r
+ PDMA_CHANNEL_0,\r
+ (uint32_t)g_spi1_tx_buffer_b,\r
+ PDMA_SPI1_TX_REGISTER,\r
+ sizeof(g_spi1_tx_buffer_b)\r
+ ); \r
+ }\r
+ PDMA_disable_irq( PDMA_CHANNEL_3 );\r
+ }\r
+ \r
+ void setup_dma( void )\r
+ {\r
+ PDMA_init();\r
+ PDMA_configure\r
+ (\r
+ PDMA_CHANNEL_0, \r
+ PDMA_TO_SPI_1, \r
+ PDMA_LOW_PRIORITY | PDMA_BYTE_TRANSFER | PDMA_INC_SRC_ONE_BYTE\r
+ );\r
+ PDMA_configure\r
+ ( \r
+ PDMA_CHANNEL_3,\r
+ PDMA_FROM_SPI_1,\r
+ PDMA_HIGH_PRIORITY | PDMA_BYTE_TRANSFER | PDMA_INC_DEST_ONE_BYTE\r
+ );\r
+ PDMA_set_irq_handler( PDMA_CHANNEL_3, slave_dma_irq_handler );\r
+ PDMA_start( PDMA_CHANNEL_3, PDMA_SPI1_RX_REGISTER, (uint32_t)g_spi1_rx_buffer, 3 ); \r
+ }\r
+ @endcode\r
+ */\r
+void PDMA_set_irq_handler\r
+(\r
+ pdma_channel_id_t channel_id,\r
+ pdma_channel_isr_t handler\r
+);\r
+\r
+/***************************************************************************//**\r
+ The PDMA_clear_irq() function clears interrupts for a specific PDMA channel.\r
+ This function also clears the PDMA interrupt in the Cortex-M3 NVIC.\r
+ \r
+ @param channel_id\r
+ The channel_id parameter identifies the PDMA channel used by the function.\r
+ */\r
+void PDMA_clear_irq\r
+(\r
+ pdma_channel_id_t channel_id\r
+);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __MSS_PERIPHERAL_DMA_H_ */\r
--- /dev/null
+/*******************************************************************************\r
+ * (c) Copyright 2008 Actel Corporation. All rights reserved.\r
+ * \r
+ * SmartFusion microcontroller subsystem SPI bare metal software driver\r
+ * implementation.\r
+ *\r
+ * SVN $Revision: 2176 $\r
+ * SVN $Date: 2010-02-15 21:04:22 +0000 (Mon, 15 Feb 2010) $\r
+ */\r
+#include "mss_spi.h"\r
+#include "../../CMSIS/mss_assert.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif \r
+\r
+/***************************************************************************//**\r
+ MSS SPI can operate as master or slave.\r
+ */\r
+#define MSS_SPI_MODE_SLAVE (uint32_t)0\r
+#define MSS_SPI_MODE_MASTER (uint32_t)1\r
+\r
+/***************************************************************************//**\r
+ * Mask of transfer protocol and SPO, SPH bits within control register.\r
+ */\r
+#define PROTOCOL_MODE_MASK (uint32_t)0x030000C0\r
+\r
+/***************************************************************************//**\r
+ * Mask of theframe count bits within the SPI control register.\r
+ */\r
+#define TXRXDFCOUNT_MASK (uint32_t)0x00FFFF00\r
+#define TXRXDFCOUNT_SHIFT (uint32_t)8\r
+\r
+/***************************************************************************//**\r
+ * SPI hardware FIFO depth.\r
+ */\r
+#define RX_FIFO_SIZE 4u\r
+\r
+/***************************************************************************//**\r
+ Marker used to detect that the configuration has not been selected for a\r
+ specific slave when operating as a master.\r
+ */\r
+#define NOT_CONFIGURED 0xFFFFFFFF\r
+\r
+/***************************************************************************//**\r
+ * SPI instance data structures for SPI0 and SPI1. A pointer to these data\r
+ * structures must be used as first parameter to any of the SPI driver functions\r
+ * to identify the SPI hardware block that will perform the requested operation.\r
+ */\r
+mss_spi_instance_t g_mss_spi0;\r
+mss_spi_instance_t g_mss_spi1;\r
+\r
+/***************************************************************************//**\r
+ SPI0 interrupt service routine\r
+ */\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void SPI0_IRQHandler( void );\r
+#else\r
+void SPI0_IRQHandler( void );\r
+#endif\r
+\r
+/***************************************************************************//**\r
+ SPI1 interrupt service routine\r
+ */\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void SPI1_IRQHandler( void );\r
+#else\r
+void SPI1_IRQHandler( void );\r
+#endif\r
+\r
+/***************************************************************************//**\r
+ * MSS_SPI_init()\r
+ * See "mss_spi.h" for details of how to use this function.\r
+ */\r
+void MSS_SPI_init\r
+(\r
+ mss_spi_instance_t * this_spi\r
+)\r
+{\r
+ uint16_t i;\r
+ \r
+ ASSERT( (this_spi == &g_mss_spi0) || (this_spi == &g_mss_spi1) );\r
+ \r
+ if (this_spi == &g_mss_spi0)\r
+ {\r
+ this_spi->hw_reg = SPI0;\r
+ this_spi->hw_reg_bit = SPI0_BITBAND;\r
+ this_spi->irqn = SPI0_IRQn;\r
+\r
+ /* reset SPI0 */\r
+ SYSREG->SOFT_RST_CR |= SYSREG_SPI0_SOFTRESET_MASK;\r
+ /* Clear any previously pended SPI0 interrupt */\r
+ NVIC_ClearPendingIRQ( SPI0_IRQn );\r
+ /* Take SPI0 out of reset. */\r
+ SYSREG->SOFT_RST_CR &= ~SYSREG_SPI0_SOFTRESET_MASK;\r
+ }\r
+ else\r
+ {\r
+ this_spi->hw_reg = SPI1;\r
+ this_spi->hw_reg_bit = SPI1_BITBAND;\r
+ this_spi->irqn = SPI1_IRQn;\r
+ \r
+ /* reset SPI1 */\r
+ SYSREG->SOFT_RST_CR |= SYSREG_SPI1_SOFTRESET_MASK;\r
+ /* Clear any previously pended SPI1 interrupt */\r
+ NVIC_ClearPendingIRQ( SPI1_IRQn );\r
+ /* Take SPI1 out of reset. */\r
+ SYSREG->SOFT_RST_CR &= ~SYSREG_SPI1_SOFTRESET_MASK;\r
+ }\r
+ \r
+ this_spi->frame_rx_handler = 0U;\r
+ this_spi->slave_tx_frame = 0U;\r
+ \r
+ this_spi->block_rx_handler = 0U;\r
+ \r
+ this_spi->slave_tx_buffer = 0U;\r
+ this_spi->slave_tx_size = 0U;\r
+ this_spi->slave_tx_idx = 0U;\r
+ \r
+ for ( i = 0u; i < (uint16_t)MSS_SPI_MAX_NB_OF_SLAVES; ++i )\r
+ {\r
+ this_spi->slaves_cfg[i].ctrl_reg = NOT_CONFIGURED;\r
+ }\r
+}\r
+\r
+/***************************************************************************//**\r
+ * MSS_SPI_configure_slave_mode()\r
+ * See "mss_spi.h" for details of how to use this function.\r
+ */\r
+void MSS_SPI_configure_slave_mode\r
+(\r
+ mss_spi_instance_t * this_spi,\r
+ mss_spi_protocol_mode_t protocol_mode,\r
+ mss_spi_pclk_div_t clk_rate,\r
+ uint8_t frame_bit_length\r
+)\r
+{\r
+ ASSERT( (this_spi == &g_mss_spi0) || (this_spi == &g_mss_spi1) );\r
+ ASSERT( frame_bit_length <= 32 );\r
+ \r
+ /* Set the mode. */\r
+ this_spi->hw_reg_bit->CTRL_MASTER = MSS_SPI_MODE_SLAVE;\r
+\r
+ /* Set the clock rate. */\r
+ this_spi->hw_reg_bit->CTRL_ENABLE = 0U;\r
+ this_spi->hw_reg->CONTROL = (this_spi->hw_reg->CONTROL & ~PROTOCOL_MODE_MASK) | (uint32_t)protocol_mode;\r
+ this_spi->hw_reg->CLK_GEN = (uint32_t)clk_rate;\r
+ \r
+ /* Set default frame size to byte size and number of data frames to 1. */\r
+ this_spi->hw_reg->CONTROL = (this_spi->hw_reg->CONTROL & ~TXRXDFCOUNT_MASK) | ((uint32_t)1 << TXRXDFCOUNT_SHIFT);\r
+ this_spi->hw_reg->TXRXDF_SIZE = frame_bit_length;\r
+ this_spi->hw_reg_bit->CTRL_ENABLE = 1U;\r
+}\r
+\r
+/***************************************************************************//**\r
+ * MSS_SPI_configure_master_mode()\r
+ * See "mss_spi.h" for details of how to use this function.\r
+ */\r
+void MSS_SPI_configure_master_mode\r
+(\r
+ mss_spi_instance_t * this_spi,\r
+ mss_spi_slave_t slave,\r
+ mss_spi_protocol_mode_t protocol_mode,\r
+ mss_spi_pclk_div_t clk_rate,\r
+ uint8_t frame_bit_length\r
+)\r
+{\r
+ ASSERT( (this_spi == &g_mss_spi0) || (this_spi == &g_mss_spi1) );\r
+ ASSERT( slave < MSS_SPI_MAX_NB_OF_SLAVES );\r
+ ASSERT( frame_bit_length <= 32 );\r
+ \r
+ /* Set the mode. */\r
+ this_spi->hw_reg_bit->CTRL_ENABLE = 0U;\r
+ this_spi->hw_reg_bit->CTRL_MASTER = MSS_SPI_MODE_MASTER;\r
+ this_spi->hw_reg_bit->CTRL_ENABLE = 1U;\r
+\r
+ /*\r
+ * Keep track of the required register configuration for this slave. These\r
+ * values will be used by the MSS_SPI_set_slave_select() function to configure\r
+ * the master to match the slave being selected.\r
+ */\r
+ if ( slave < MSS_SPI_MAX_NB_OF_SLAVES ) \r
+ {\r
+ this_spi->slaves_cfg[slave].ctrl_reg = 0x00000002uL | (uint32_t)protocol_mode | ((uint32_t)1 << TXRXDFCOUNT_SHIFT);\r
+ this_spi->slaves_cfg[slave].txrxdf_size_reg = frame_bit_length;\r
+ this_spi->slaves_cfg[slave].clk_gen = (uint8_t)clk_rate;\r
+ }\r
+}\r
+\r
+/***************************************************************************//**\r
+ * MSS_SPI_set_slave_select()\r
+ * See "mss_spi.h" for details of how to use this function.\r
+ */\r
+void MSS_SPI_set_slave_select\r
+(\r
+ mss_spi_instance_t * this_spi,\r
+ mss_spi_slave_t slave\r
+)\r
+{\r
+ ASSERT( (this_spi == &g_mss_spi0) || (this_spi == &g_mss_spi1) );\r
+ \r
+ /* This function is only intended to be used with an SPI master. */\r
+ ASSERT( this_spi->hw_reg_bit->CTRL_MASTER == MSS_SPI_MODE_MASTER );\r
+ ASSERT( this_spi->slaves_cfg[slave].ctrl_reg != NOT_CONFIGURED );\r
+\r
+ /* Set the clock rate. */\r
+ this_spi->hw_reg_bit->CTRL_ENABLE = 0U;\r
+ this_spi->hw_reg->CONTROL = this_spi->slaves_cfg[slave].ctrl_reg;\r
+ this_spi->hw_reg->CLK_GEN = this_spi->slaves_cfg[slave].clk_gen;\r
+ this_spi->hw_reg->TXRXDF_SIZE = this_spi->slaves_cfg[slave].txrxdf_size_reg;\r
+ this_spi->hw_reg_bit->CTRL_ENABLE = 1U;\r
+ \r
+ /* Set slave select */\r
+ this_spi->hw_reg->SLAVE_SELECT |= ((uint32_t)1 << (uint32_t)slave);\r
+}\r
+\r
+/***************************************************************************//**\r
+ * MSS_SPI_clear_slave_select()\r
+ * See "mss_spi.h" for details of how to use this function.\r
+ */\r
+void MSS_SPI_clear_slave_select\r
+(\r
+ mss_spi_instance_t * this_spi,\r
+ mss_spi_slave_t slave\r
+)\r
+{\r
+ ASSERT( (this_spi == &g_mss_spi0) || (this_spi == &g_mss_spi1) );\r
+ \r
+ /* This function is only intended to be used with an SPI master. */\r
+ ASSERT( this_spi->hw_reg_bit->CTRL_MASTER == MSS_SPI_MODE_MASTER );\r
+\r
+ this_spi->hw_reg->SLAVE_SELECT &= ~((uint32_t)1 << (uint32_t)slave);\r
+}\r
+\r
+/***************************************************************************//**\r
+ * MSS_SPI_transfer_frame()\r
+ * See "mss_spi.h" for details of how to use this function.\r
+ */\r
+uint32_t MSS_SPI_transfer_frame\r
+(\r
+ mss_spi_instance_t * this_spi,\r
+ uint32_t tx_bits\r
+)\r
+{\r
+ volatile uint32_t dummy;\r
+ \r
+ ASSERT( (this_spi == &g_mss_spi0) || (this_spi == &g_mss_spi1) );\r
+ \r
+ /* This function is only intended to be used with an SPI master. */\r
+ ASSERT( this_spi->hw_reg_bit->CTRL_MASTER == MSS_SPI_MODE_MASTER );\r
+ \r
+ /* Flush Rx FIFO. */\r
+ while ( this_spi->hw_reg_bit->STATUS_RX_RDY == 1U )\r
+ {\r
+ dummy = this_spi->hw_reg->RX_DATA;\r
+ dummy = dummy; /* Prevent Lint warning. */\r
+ }\r
+ \r
+ /* Send frame. */\r
+ this_spi->hw_reg->TX_DATA = tx_bits;\r
+ \r
+ /* Wait for frame Tx to complete. */\r
+ while ( this_spi->hw_reg_bit->STATUS_TX_DONE == 0U )\r
+ {\r
+ ;\r
+ }\r
+ \r
+ /* Read received frame. */\r
+ /* Wait for Rx complete. */\r
+ while ( this_spi->hw_reg_bit->STATUS_RX_RDY == 0U )\r
+ {\r
+ ;\r
+ }\r
+ /* Return Rx data. */\r
+ return( this_spi->hw_reg->RX_DATA );\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * MSS_SPI_transfer_block()\r
+ * See "mss_spi.h" for details of how to use this function.\r
+ */\r
+void MSS_SPI_transfer_block\r
+(\r
+ mss_spi_instance_t * this_spi,\r
+ const uint8_t * cmd_buffer,\r
+ uint16_t cmd_byte_size,\r
+ uint8_t * rd_buffer,\r
+ uint16_t rd_byte_size\r
+)\r
+{\r
+ uint16_t transfer_idx = 0U;\r
+ uint16_t tx_idx;\r
+ uint16_t rx_idx;\r
+ uint32_t frame_count;\r
+ volatile uint32_t rx_raw;\r
+ uint16_t transit = 0U;\r
+ \r
+ uint16_t transfer_size; /* Total number of bytes transfered. */\r
+ \r
+ ASSERT( (this_spi == &g_mss_spi0) || (this_spi == &g_mss_spi1) );\r
+ \r
+ /* This function is only intended to be used with an SPI master. */\r
+ ASSERT( this_spi->hw_reg_bit->CTRL_MASTER == MSS_SPI_MODE_MASTER );\r
+ \r
+ /* Compute number of bytes to transfer. */\r
+ transfer_size = cmd_byte_size + rd_byte_size;\r
+ \r
+ /* Adjust to 1 byte transfer to cater for DMA transfers. */\r
+ if ( transfer_size == 0U )\r
+ {\r
+ frame_count = 1U;\r
+ }\r
+ else\r
+ {\r
+ frame_count = transfer_size;\r
+ }\r
+ \r
+ /* Set frame size to 8 bits and the frame count to the tansfer size. */\r
+ this_spi->hw_reg_bit->CTRL_ENABLE = 0U;\r
+ this_spi->hw_reg->CONTROL = (this_spi->hw_reg->CONTROL & ~TXRXDFCOUNT_MASK) | ( (frame_count << TXRXDFCOUNT_SHIFT) & TXRXDFCOUNT_MASK);\r
+ this_spi->hw_reg->TXRXDF_SIZE = 8U;\r
+ this_spi->hw_reg_bit->CTRL_ENABLE = 1U;\r
+\r
+ /* Flush the receive FIFO. */\r
+ while ( !this_spi->hw_reg_bit->STATUS_RX_FIFO_EMPTY )\r
+ {\r
+ rx_raw = this_spi->hw_reg->RX_DATA;\r
+ }\r
+ \r
+ tx_idx = 0u;\r
+ rx_idx = 0u;\r
+ if ( tx_idx < cmd_byte_size )\r
+ {\r
+ this_spi->hw_reg->TX_DATA = cmd_buffer[tx_idx];\r
+ ++tx_idx;\r
+ ++transit;\r
+ }\r
+ else\r
+ {\r
+ if ( tx_idx < transfer_size )\r
+ {\r
+ this_spi->hw_reg->TX_DATA = 0x00U;\r
+ ++tx_idx;\r
+ ++transit;\r
+ }\r
+ }\r
+ /* Perform the remainder of the transfer by sending a byte every time a byte\r
+ * has been received. This should ensure that no Rx overflow can happen in\r
+ * case of an interrupt occurs during this function. */\r
+ while ( transfer_idx < transfer_size )\r
+ {\r
+ if ( !this_spi->hw_reg_bit->STATUS_RX_FIFO_EMPTY )\r
+ {\r
+ /* Process received byte. */\r
+ rx_raw = this_spi->hw_reg->RX_DATA;\r
+ if ( transfer_idx >= cmd_byte_size )\r
+ {\r
+ if ( rx_idx < rd_byte_size )\r
+ {\r
+ rd_buffer[rx_idx] = (uint8_t)rx_raw; \r
+ }\r
+ ++rx_idx;\r
+ }\r
+ ++transfer_idx;\r
+ --transit;\r
+ }\r
+\r
+ if ( !this_spi->hw_reg_bit->STATUS_TX_FIFO_FULL )\r
+ {\r
+ if (transit < RX_FIFO_SIZE)\r
+ {\r
+ /* Send another byte. */\r
+ if ( tx_idx < cmd_byte_size )\r
+ {\r
+ this_spi->hw_reg->TX_DATA = cmd_buffer[tx_idx];\r
+ ++tx_idx;\r
+ ++transit;\r
+ }\r
+ else\r
+ {\r
+ if ( tx_idx < transfer_size )\r
+ {\r
+ this_spi->hw_reg->TX_DATA = 0x00U;\r
+ ++tx_idx;\r
+ ++transit;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ }\r
+}\r
+\r
+/***************************************************************************//**\r
+ * MSS_SPI_set_frame_rx_handler()\r
+ * See "mss_spi.h" for details of how to use this function.\r
+ */\r
+void MSS_SPI_set_frame_rx_handler\r
+(\r
+ mss_spi_instance_t * this_spi,\r
+ mss_spi_frame_rx_handler_t rx_handler\r
+)\r
+{\r
+ ASSERT( (this_spi == &g_mss_spi0) || (this_spi == &g_mss_spi1) );\r
+ \r
+ /* This function is only intended to be used with an SPI slave. */\r
+ ASSERT( this_spi->hw_reg_bit->CTRL_MASTER == MSS_SPI_MODE_SLAVE );\r
+ \r
+ /* Disable block Rx handler as they are mutually exclusive. */\r
+ this_spi->block_rx_handler = 0U;\r
+ \r
+ /* Keep a copy of the pointer to the rx hnadler function. */\r
+ this_spi->frame_rx_handler = rx_handler;\r
+ \r
+ /* Enable Rx interrupt. */\r
+ this_spi->hw_reg_bit->CTRL_RX_INT_EN = 1U;\r
+ NVIC_EnableIRQ( this_spi->irqn );\r
+}\r
+\r
+/***************************************************************************//**\r
+ * MSS_SPI_set_slave_tx_frame()\r
+ * See "mss_spi.h" for details of how to use this function.\r
+ */\r
+void MSS_SPI_set_slave_tx_frame\r
+(\r
+ mss_spi_instance_t * this_spi,\r
+ uint32_t frame_value\r
+)\r
+{\r
+ ASSERT( (this_spi == &g_mss_spi0) || (this_spi == &g_mss_spi1) );\r
+\r
+ /* This function is only intended to be used with an SPI slave. */\r
+ ASSERT( this_spi->hw_reg_bit->CTRL_MASTER == MSS_SPI_MODE_SLAVE );\r
+ \r
+ /* Disable slave block tx buffer as it is mutually exclusive with frame\r
+ * level handling. */ \r
+ this_spi->slave_tx_buffer = 0U;\r
+ this_spi->slave_tx_size = 0U;\r
+ this_spi->slave_tx_idx = 0U;\r
+ \r
+ /* Keep a copy of the slave tx frame value. */\r
+ this_spi->slave_tx_frame = frame_value;\r
+ \r
+ /* Load frame into Tx data register. */\r
+ this_spi->hw_reg->TX_DATA = this_spi->slave_tx_frame;\r
+ \r
+ /* Enable Tx Done interrupt in order to reload the slave Tx frame after each\r
+ * time it has been sent. */\r
+ this_spi->hw_reg_bit->CTRL_TX_INT_EN = 1U;\r
+ NVIC_EnableIRQ( this_spi->irqn );\r
+}\r
+\r
+/***************************************************************************//**\r
+ * MSS_SPI_set_slave_block_buffers()\r
+ * See "mss_spi.h" for details of how to use this function.\r
+ */\r
+void MSS_SPI_set_slave_block_buffers\r
+(\r
+ mss_spi_instance_t * this_spi,\r
+ const uint8_t * tx_buffer,\r
+ uint32_t tx_buff_size,\r
+ uint8_t * rx_buffer,\r
+ uint32_t rx_buff_size,\r
+ mss_spi_block_rx_handler_t block_rx_handler\r
+)\r
+{\r
+ uint32_t frame_count;\r
+ \r
+ ASSERT( (this_spi == &g_mss_spi0) || (this_spi == &g_mss_spi1) );\r
+ \r
+ /* This function is only intended to be used with an SPI slave. */\r
+ ASSERT( this_spi->hw_reg_bit->CTRL_MASTER == MSS_SPI_MODE_SLAVE );\r
+ \r
+ /* Disable Rx frame handler as it is mutually exclusive with block rx handler. */\r
+ this_spi->frame_rx_handler = 0U;\r
+ \r
+ /* Keep a copy of the pointer to the block rx handler function. */\r
+ this_spi->block_rx_handler = block_rx_handler;\r
+ \r
+ this_spi->slave_rx_buffer = rx_buffer;\r
+ this_spi->slave_rx_size = rx_buff_size;\r
+ this_spi->slave_rx_idx = 0U;\r
+ \r
+ /**/\r
+ this_spi->slave_tx_buffer = tx_buffer;\r
+ this_spi->slave_tx_size = tx_buff_size;\r
+ this_spi->slave_tx_idx = 0U;\r
+\r
+ frame_count = rx_buff_size;\r
+ \r
+ /**/\r
+ this_spi->hw_reg_bit->CTRL_ENABLE = 0U;\r
+ this_spi->hw_reg->CONTROL = (this_spi->hw_reg->CONTROL & ~TXRXDFCOUNT_MASK) | (frame_count << TXRXDFCOUNT_SHIFT);\r
+ this_spi->hw_reg->TXRXDF_SIZE = 8U;\r
+ this_spi->hw_reg_bit->CTRL_ENABLE = 1U;\r
+ \r
+ /* Load the transmit FIFO. */\r
+ while ( !(this_spi->hw_reg_bit->STATUS_TX_FIFO_FULL) && ( this_spi->slave_tx_idx < this_spi->slave_tx_size ) )\r
+ {\r
+ this_spi->hw_reg->TX_DATA = this_spi->slave_tx_buffer[this_spi->slave_tx_idx];\r
+ ++this_spi->slave_tx_idx;\r
+ }\r
+ \r
+ /* Enable Rx interrupt. */\r
+ this_spi->hw_reg_bit->CTRL_RX_INT_EN = 1U;\r
+ NVIC_EnableIRQ( this_spi->irqn );\r
+}\r
+\r
+/***************************************************************************//**\r
+ * SPI interrupt service routine.\r
+ */\r
+static void mss_spi_isr\r
+(\r
+ mss_spi_instance_t * this_spi\r
+)\r
+{\r
+ uint32_t rx_frame;\r
+ \r
+ ASSERT( (this_spi == &g_mss_spi0) || (this_spi == &g_mss_spi1) );\r
+ \r
+ if ( this_spi->hw_reg_bit->MIS_RX_RDY )\r
+ {\r
+ while( !this_spi->hw_reg_bit->STATUS_RX_FIFO_EMPTY )\r
+ {\r
+ rx_frame = this_spi->hw_reg->RX_DATA;\r
+ if ( this_spi->frame_rx_handler != 0U )\r
+ {\r
+ /* Single frame handling mode. */\r
+ this_spi->frame_rx_handler( rx_frame );\r
+ }\r
+ else \r
+ {\r
+ if ( this_spi->block_rx_handler != 0U )\r
+ {\r
+ /* Block handling mode. */\r
+ if ( this_spi->slave_rx_idx < this_spi->slave_rx_size )\r
+ {\r
+ this_spi->slave_rx_buffer[this_spi->slave_rx_idx] = (uint8_t)rx_frame;\r
+ ++this_spi->slave_rx_idx;\r
+ if ( this_spi->slave_rx_idx == this_spi->slave_rx_size )\r
+ {\r
+ (*this_spi->block_rx_handler)( this_spi->slave_rx_buffer, this_spi->slave_rx_size );\r
+ }\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Feed transmit FIFO. */\r
+ if ( !(this_spi->hw_reg_bit->STATUS_TX_FIFO_FULL) && ( this_spi->slave_tx_idx < this_spi->slave_tx_size ) )\r
+ {\r
+ this_spi->hw_reg->TX_DATA = this_spi->slave_tx_buffer[this_spi->slave_tx_idx];\r
+ ++this_spi->slave_tx_idx;\r
+ }\r
+ }\r
+ this_spi->hw_reg_bit->INT_CLEAR_RX_RDY = 1U;\r
+ }\r
+ \r
+ if ( this_spi->hw_reg_bit->MIS_TX_DONE )\r
+ {\r
+ if ( this_spi->slave_tx_buffer != 0U )\r
+ {\r
+ this_spi->hw_reg->TX_DATA = this_spi->slave_tx_buffer[this_spi->slave_tx_idx];\r
+ ++this_spi->slave_tx_idx;\r
+ if ( this_spi->slave_tx_idx >= this_spi->slave_tx_size )\r
+ {\r
+ this_spi->slave_tx_idx = 0U;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Reload slave tx frame into Tx data register. */\r
+ this_spi->hw_reg->TX_DATA = this_spi->slave_tx_frame;\r
+ }\r
+ }\r
+}\r
+\r
+/***************************************************************************//**\r
+ * SPIO interrupt service routine.\r
+ * Please note that the name of this ISR is defined as part of the SmartFusion\r
+ * CMSIS startup code.\r
+ */\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void SPI0_IRQHandler( void )\r
+#else\r
+void SPI0_IRQHandler( void )\r
+#endif\r
+{\r
+ mss_spi_isr( &g_mss_spi0 );\r
+ NVIC_ClearPendingIRQ( SPI0_IRQn );\r
+}\r
+\r
+/***************************************************************************//**\r
+ * SPI1 interrupt service routine.\r
+ * Please note that the name of this ISR is defined as part of the SmartFusion\r
+ * CMSIS startup code.\r
+ */\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void SPI1_IRQHandler( void )\r
+#else\r
+void SPI1_IRQHandler( void )\r
+#endif\r
+{\r
+ mss_spi_isr( &g_mss_spi1 );\r
+ NVIC_ClearPendingIRQ( SPI1_IRQn );\r
+}\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
--- /dev/null
+/***************************************************************************//**\r
+ * (c) Copyright 2008 Actel Corporation. All rights reserved.\r
+ * \r
+ * SmartFusion microcontroller subsystem SPI bare metal software driver public API.\r
+ *\r
+ * The microcontroller subsystem SPI driver provides functions for implementing\r
+ * SPI master or SPI slave operations. These operations can be one of two\r
+ * classes: SPI frame operation or block transfer operations.\r
+ * Frame operations allow transferring SPI frames from 4 to 32 bits long. Block\r
+ * operations allow transferring blocks of data organized as 8 bit bytes. \r
+ *\r
+ * SVN $Revision: 2189 $\r
+ * SVN $Date: 2010-02-16 22:02:32 +0000 (Tue, 16 Feb 2010) $\r
+ */\r
+/*=========================================================================*//**\r
+ @mainpage SmartFusion MSS SPI Bare Metal Driver.\r
+\r
+ @section intro_sec Introduction\r
+ The SmartFusion\99 microcontroller subsystem (MSS) includes two serial\r
+ peripheral interface SPI peripherals for serial communication. This driver\r
+ provides a set of functions for controlling the MSS SPIs as part of a bare\r
+ metal system where no operating system is available. These drivers can be\r
+ adapted for use as part of an operating system, but the implementation of the\r
+ adaptation layer between this driver and the operating system's driver model\r
+ is outside the scope of this driver.\r
+ \r
+ @section hw_dependencies Hardware Flow Dependencies\r
+ The configuration of all features of the MSS SPIs is covered by this driver\r
+ with the exception of the SmartFusion IOMUX configuration. SmartFusion allows\r
+ multiple non-concurrent uses of some external pins through IOMUX configuration.\r
+ This feature allows optimization of external pin usage by assigning external\r
+ pins for use by either the microcontroller subsystem or the FPGA fabric. The\r
+ MSS SPIs serial signals are routed through IOMUXes to the SmartFusion device\r
+ external pins. These IOMUXes are automatically configured correctly by the MSS\r
+ configurator tool in the hardware flow when the MSS SPIs are enabled in that\r
+ tool. You must ensure that the MSS SPIs are enabled by the MSS configurator\r
+ tool in the hardware flow; otherwise the serial inputs and outputs will not be\r
+ connected to the chip's external pins. For more information on IOMUX, refer to\r
+ the IOMUX section of the SmartFusion Datasheet.\r
+ The base address, register addresses and interrupt number assignment for the\r
+ MSS SPI blocks are defined as constants in the SmartFusion CMSIS-PAL. You must\r
+ ensure that the SmartFusion CMSIS-PAL is either included in the software tool\r
+ chain used to build your project or is included in your project.\r
+ \r
+ @section theory_op Theory of Operation\r
+ The MSS SPI driver functions are grouped into the following categories:\r
+ \95 Initialization\r
+ \95 Configuration for either master or slave operations\r
+ \95 SPI master frame transfer control\r
+ \95 SPI master block transfer control\r
+ \95 SPI slave frame transfer control\r
+ \95 SPI slave block transfer control\r
+ \95 DMA block transfer\r
+ Frame transfers allow the MSS SPI to write or read up to 32 bits of data in a\r
+ SPI transaction. For example, a frame transfer of 12 bits might be used to\r
+ read the result of an ADC conversion from a SPI analog to digital converter.\r
+ Block transfers allow the MSS SPI to write or read a number of bytes in a SPI\r
+ transaction. Block transfer transactions allow data transfers in multiples of\r
+ 8 bits (8, 16, 24, 32, 40\85). Block transfers are typically used with byte\r
+ oriented devices like SPI FLASH devices.\r
+\r
+ Initialization \r
+ The MSS SPI driver is initialized through a call to the MSS_SPI_init()\r
+ function. The MSS_SPI_init() function takes only one parameter, a pointer\r
+ to one of two global data structures used by the driver to store state\r
+ information for each MSS SPI. A pointer to these data structures is also\r
+ used as first parameter to any of the driver functions to identify which MSS\r
+ SPI will be used by the called function. The names of these two data\r
+ structures are g_mss_spi0 and g_mss_spi1. Therefore any call to an MSS SPI\r
+ driver function should be of the form MSS_SPI_function_name( &g_mss_spi0, ... )\r
+ or MSS_SPI_function_name( &g_mss_spi1, ... ).\r
+ The MSS_SPI_init() function resets the specified MSS SPI hardware block and\r
+ clears any pending interrupts from that MSS SPI in the Cortex-M3 NVIC.\r
+ The MSS_SPI_init() function must be called before any other MSS SPI driver\r
+ functions can be called.\r
+\r
+ Configuration\r
+ A MSS SPI block can operate either as a master or slave SPI device. There\r
+ are two distinct functions for configuring a MSS SPI block for master or\r
+ slave operations.\r
+\r
+ Master configuration\r
+ The MSS_SPI_configure_master_mode() function configures the specified MSS\r
+ SPI block for operations as a SPI master. It must be called once for each\r
+ remote SPI slave device the MSS SPI block will communicate with. It is used\r
+ to provide the following information about each SPI slave\92s communication\r
+ characteristics:\r
+ \95 The SPI protocol mode\r
+ \95 The SPI clock speed\r
+ \95 The frame bit length\r
+ This information is held by the driver and will be used to alter the\r
+ configuration of the MSS SPI block each time a slave is selected through a\r
+ call to MSS_SPI_set_slave_select(). The SPI protocol mode defines the\r
+ initial state of the clock signal at the start of a transaction and which\r
+ clock edge will be used to sample the data signal, or it defines whether the\r
+ SPI block will operate in TI synchronous serial mode or in NSC MICROWIRE mode.\r
+\r
+ Slave configuration\r
+ The MSS_SPI_configure_slave_mode() function configures the specified MSS SPI\r
+ block for operations as a SPI slave. It configures the following SPI\r
+ communication characteristics:\r
+ \95 The SPI protocol mode \r
+ \95 The SPI clock speed\r
+ \95 The frame bit length\r
+ The SPI protocol mode defines the initial state of the clock signal at the\r
+ start of a transaction and which clock edge will be used to sample the data\r
+ signal, or it defines whether the SPI block will operate in TI synchronous\r
+ serial mode or in NSC MICROWIRE mode.\r
+\r
+ SPI master frame transfer control\r
+ The following functions are used as part of SPI master frame transfers:\r
+ \95 MSS_SPI_set_slave_select()\r
+ \95 MSS_SPI_transfer_frame()\r
+ \95 MSS_SPI_clear_slave_select()\r
+ The master must first select the target slave through a call to\r
+ MSS_SPI_set_slave_select(). This causes the relevant slave select line to\r
+ become asserted while data is clocked out onto the SPI data line.\r
+ A call to is then made to function MSS_SPI_transfer_frame() specifying and\r
+ the value of the data frame to be sent.\r
+ The function MSS_SPI_clear_slave_select() can be used after the transfer is\r
+ complete to prevent this slave select line from being asserted during\r
+ subsequent SPI transactions. A call to this function is only required if the\r
+ master is communicating with multiple slave devices.\r
+\r
+ SPI master block transfer control\r
+ The following functions are used as part of SPI master block transfers:\r
+ \95 MSS_SPI_set_slave_select()\r
+ \95 MSS_SPI_clear_slave_select()\r
+ \95 MSS_SPI_transfer_block()\r
+ The master must first select the target slave through a call to\r
+ MSS_SPI_set_slave_select(). This causes the relevant slave select line to\r
+ become asserted while data is clocked out onto the SPI data line.\r
+ Alternatively a GPIO can be used to control the state of the target slave\r
+ device\92s chip select signal.\r
+ A call to is then made to function MSS_SPI_transfer_block (). The\r
+ parameters of this function specify:\r
+ \95 the number of bytes to be transmitted\r
+ \95 a pointer to the buffer containing the data to be transmitted\r
+ \95 the number of bytes to be received\r
+ \95 a pointer to the buffer where received data will be stored\r
+ The number of bytes to be transmitted can be set to zero to indicate that\r
+ the transfer is purely a block read transfer. The number of bytes to be\r
+ received can be set to zero to specify that the transfer is purely a block\r
+ write transfer.\r
+ The function MSS_SPI_clear_slave_select() can be used after the transfer is\r
+ complete to prevent this slave select line from being asserted during\r
+ subsequent SPI transactions. A call to this function is only required if the\r
+ master is communicating with multiple slave devices.\r
+ \r
+ SPI slave frame transfer control\r
+ The following functions are used as part of SPI slave frame transfers:\r
+ \95 MSS_SPI_set_slave_tx_frame()\r
+ \95 MSS_SPI_set_frame_rx_handler()\r
+ The MSS_SPI_set_slave_tx_frame() function specifies the frame data that will\r
+ be returned to the SPI master. The frame data specified through this\r
+ function is the value that will be read over the SPI bus by the remote SPI\r
+ master when it initiates a transaction. A call to MSS_SPI_set_slave_tx_frame()\r
+ is only required if the MSS SPI slave is the target of SPI read transactions,\r
+ i.e. if data is meant to be read from the SmartFusion device over SPI.\r
+ The MSS_SPI_set_frame_rx_handler() function specifies the receive handler\r
+ function that will called when a frame of data has been received by the MSS\r
+ SPI when it is configured as a slave. The receive handler function specified\r
+ through this call will process the frame data written, over the SPI bus, to\r
+ the MSS SPI slave by the remote SPI master. The receive handler function must\r
+ be implemented as part of the application. It is only required if the MSS SPI\r
+ slave is the target of SPI frame write transactions.\r
+\r
+ SPI slave block transfer control\r
+ The following functions are used as part of SPI slave block transfers:\r
+ \95 MSS_SPI_set_slave_block_buffers()\r
+ The MSS_SPI_set_slave_block_buffers() function is used to configure a MSS SPI\r
+ slave for block transfer operations. It specifies:\r
+ \95 The buffer containing the data that will be returned to the remote SPI master\r
+ \95 The buffer where data received from the remote SPI master will be stored\r
+ \95 The handler function that will be called after the receive buffer is filled\r
+\r
+ DMA block transfer control\r
+ The following functions are used as part of MSS SPI DMA transfers:\r
+ \95 MSS_SPI_disable()\r
+ \95 MSS_SPI_set_transfer_byte_count()\r
+ \95 MSS_SPI_enable()\r
+ \95 MSS_SPI_tx_done()\r
+ The MSS SPI must first be disabled through a call to function MSS_SPI_disable().\r
+ The number of bytes to be transferred is then set through a call to function\r
+ MSS_SPI_set_transfer_byte_count(). The DMA transfer is then initiated by a call\r
+ to the MSS_PDMA_start() function provided by the MSS PDMA driver. The actual\r
+ DMA transfer will only start once the MSS SPI block has been re-enabled through\r
+ a call to MSS_SPI_enable(). The completion of the DMA driven SPI transfer can\r
+ be detected through a call to MSS_SPI_tx_done(). The direction of the SPI\r
+ transfer, write or read, depends on the DMA channel configuration. A SPI write\r
+ transfer occurs when the DMA channel is configured to write data to the MSS SPI\r
+ block. A SPI read transfer occurs when the DMA channel is configured to read data\r
+ from the MSS SPI block.\r
+\r
+ *//*=========================================================================*/\r
+#ifndef MSS_SPI_H_\r
+#define MSS_SPI_H_\r
+\r
+#include "../../CMSIS/a2fxxxm3.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif \r
+\r
+/***************************************************************************//**\r
+ This defines the function prototype that must be followed by MSS SPI slave\r
+ frame receive handler functions. These functions are registered with the MSS\r
+ SPI driver through the MSS_SPI_set_frame_rx_handler () function.\r
+ \r
+ Declaring and Implementing Slave Frame Receive Handler Functions:\r
+ Slave frame receive handler functions should follow the following prototype:\r
+ void slave_frame_receive_handler ( uint32_t rx_frame );\r
+ The actual name of the receive handler is unimportant. You can use any name\r
+ of your choice for the receive frame handler. The rx_frame parameter will\r
+ contain the value of the received frame.\r
+ */\r
+typedef void (*mss_spi_frame_rx_handler_t)( uint32_t rx_frame );\r
+\r
+/***************************************************************************//**\r
+ This defines the function prototype that must be followed by MSS SPI slave\r
+ block receive handler functions. These functions are registered with the MSS\r
+ SPI driver through the MSS_SPI_set_slave_block_buffers() function.\r
+ \r
+ Declaring and Implementing Slave Block Receive Handler Functions\r
+ Slave block receive handler functions should follow the following prototype:\r
+ void mss_spi_block_rx_handler ( uint8_t * rx_buff, uint16_t rx_size );\r
+ The actual name of the receive handler is unimportant. You can use any name\r
+ of your choice for the receive frame handler. The rx_buff parameter will\r
+ contain a pointer to the start of the received block. The rx_size parameter\r
+ will contain the number of bytes of the received block.\r
+\r
+ */\r
+typedef void (*mss_spi_block_rx_handler_t)( uint8_t * rx_buff, uint32_t rx_size );\r
+\r
+/***************************************************************************//**\r
+ This enumeration is used to define the settings for the SPI protocol mode\r
+ bits, CPHA and CPOL. It is used as a parameter to the MSS_SPI_configure_master_mode()\r
+ and MSS_SPI_configure_slave_mode() functions.\r
+ \r
+ - MSS_SPI_MODE0:\r
+ Clock starts low, data read on clock's rising edge, data changes on\r
+ falling edge.\r
+ \r
+ - MSS_SPI_MODE1:\r
+ Clock starts low, data read on clock's falling edge, data changes on\r
+ rising edge.\r
+ \r
+ - MSS_SPI_MODE2:\r
+ Clock starts high, data read on clock's falling edge, data changes on\r
+ rising edge.\r
+ \r
+ - MSS_SPI_MODE3:\r
+ Clock starts high, data read on clock's rising edge, data changes on\r
+ falling edge.\r
+ \r
+ - MSS_TI_MODE: \r
+ TI syncronous serial mode. Slave select is pulsed at start of transfer.\r
+ \r
+ - MSS_NSC_MODE:\r
+ NSC Microwire mode.\r
+ */\r
+typedef enum __mss_spi_protocol_mode_t\r
+{\r
+ MSS_SPI_MODE0 = 0x00000000,\r
+ MSS_SPI_TI_MODE = 0x00000004,\r
+ MSS_SPI_NSC_MODE = 0x00000008,\r
+ MSS_SPI_MODE2 = 0x01000000,\r
+ MSS_SPI_MODE1 = 0x02000000,\r
+ MSS_SPI_MODE3 = 0x03000000\r
+} mss_spi_protocol_mode_t;\r
+\r
+/***************************************************************************//**\r
+ This enumeration specifies the divider to be applied to the the APB bus clock\r
+ in order to generate the SPI clock. It is used as parameter to the\r
+ MSS_SPI_configure_master_mode() and MSS_SPI_configure_slave_mode()functions.\r
+ */\r
+ typedef enum __mss_spi_pclk_div_t\r
+ {\r
+ MSS_SPI_PCLK_DIV_2 = 0,\r
+ MSS_SPI_PCLK_DIV_4 = 1,\r
+ MSS_SPI_PCLK_DIV_8 = 2,\r
+ MSS_SPI_PCLK_DIV_16 = 3,\r
+ MSS_SPI_PCLK_DIV_32 = 4,\r
+ MSS_SPI_PCLK_DIV_64 = 5,\r
+ MSS_SPI_PCLK_DIV_128 = 6,\r
+ MSS_SPI_PCLK_DIV_256 = 7\r
+} mss_spi_pclk_div_t;\r
+\r
+/***************************************************************************//**\r
+ This enumeration is used to select a specific SPI slave device (0 to 7). It is\r
+ used as a parameter to the MSS_SPI_configure_master_mode(),\r
+ MSS_SPI_set_slave_select() and MSS_SPI_clear_slave_select () functions.\r
+ */\r
+ typedef enum __mss_spi_slave_t\r
+ {\r
+ MSS_SPI_SLAVE_0 = 0,\r
+ MSS_SPI_SLAVE_1 = 1,\r
+ MSS_SPI_SLAVE_2 = 2,\r
+ MSS_SPI_SLAVE_3 = 3,\r
+ MSS_SPI_SLAVE_4 = 4,\r
+ MSS_SPI_SLAVE_5 = 5,\r
+ MSS_SPI_SLAVE_6 = 6,\r
+ MSS_SPI_SLAVE_7 = 7,\r
+ MSS_SPI_MAX_NB_OF_SLAVES = 8\r
+} mss_spi_slave_t;\r
+\r
+/***************************************************************************//**\r
+ This constant defines a frame size of 8 bits when configuring an MSS SPI to\r
+ perform block transfer data transactions.\r
+ It must be used as the value for the frame_bit_length parameter of function\r
+ MSS_SPI_configure_master_mode() when performing block transfers between the\r
+ MSS SPI master and the target SPI slave.\r
+ It must also be used as the value for the frame_bit_length parameter of\r
+ function MSS_SPI_configure_slave_mode() when performing block transfers\r
+ between the MSS SPI slave and the remote SPI master.\r
+ */\r
+#define MSS_SPI_BLOCK_TRANSFER_FRAME_SIZE 8\r
+\r
+/***************************************************************************//**\r
+ The mss_spi_slave_cfg_t holds the MSS SPI configuration that must be used to\r
+ communicate with a specific SPI slave.\r
+ */\r
+typedef struct __mss_spi_slave_cfg_t\r
+{\r
+ uint32_t ctrl_reg;\r
+ uint8_t txrxdf_size_reg;\r
+ uint8_t clk_gen;\r
+} mss_spi_slave_cfg_t;\r
+\r
+/***************************************************************************//**\r
+ There is one instance of this structure for each of the microcontroller\r
+ subsystem's SPIs. Instances of this structure are used to identify a specific\r
+ SPI. A pointer to an instance of the mss_spi_instance_t structure is passed as\r
+ the first parameter to MSS SPI driver functions to identify which SPI should\r
+ perform the requested operation.\r
+ */\r
+typedef struct __mss_spi_instance_t\r
+{\r
+ /* CMSIS related defines identifying the SPI hardware. */\r
+ SPI_TypeDef * hw_reg; /*!< Pointer to SPI registers. */\r
+ SPI_BitBand_TypeDef * hw_reg_bit; /*!< Pointer to SPI registers bit band area. */\r
+ IRQn_Type irqn; /*!< SPI's Cortex-M3 NVIC interrupt number. */\r
+ \r
+ /* Internal transmit state: */\r
+ const uint8_t * slave_tx_buffer; /*!< Pointer to slave transmit buffer. */\r
+ uint32_t slave_tx_size; /*!< Size of slave transmit buffer. */\r
+ uint32_t slave_tx_idx; /*!< Current index into slave transmit buffer. */\r
+ \r
+ /* Internal receive state: */\r
+ uint8_t * slave_rx_buffer; /*!< Pointer to buffer where data received by a slave will be stored. */\r
+ uint32_t slave_rx_size; /*!< Slave receive buffer size. */\r
+ uint32_t slave_rx_idx; /*!< Current index into slave receive buffer. */\r
+ \r
+ /* Configuration for each target slave. */\r
+ mss_spi_slave_cfg_t slaves_cfg[MSS_SPI_MAX_NB_OF_SLAVES];\r
+ \r
+ /** Slave received frame handler: */\r
+ mss_spi_frame_rx_handler_t frame_rx_handler; /*!< Pointer to function that will be called when a frame is received when the SPI block is configured as slave. */\r
+ \r
+ uint32_t slave_tx_frame; /*!< Value of the data frame that will be transmited when the SPI block is configured as slave. */\r
+ \r
+ /* Slave block rx handler: */\r
+ mss_spi_block_rx_handler_t block_rx_handler; /*!< Pointer to the function that will be called when a data block has been received. */\r
+\r
+} mss_spi_instance_t;\r
+\r
+/***************************************************************************//**\r
+ This instance of mss_spi_instance_t holds all data related to the operations\r
+ performed by MSS SPI 0. A pointer to g_mss_spi0 is passed as the first\r
+ parameter to MSS SPI driver functions to indicate that MSS SPI 0 should\r
+ perform the requested operation.\r
+ */\r
+extern mss_spi_instance_t g_mss_spi0;\r
+\r
+/***************************************************************************//**\r
+ This instance of mss_spi_instance_t holds all data related to the operations\r
+ performed by MSS SPI 1. A pointer to g_mss_spi1 is passed as the first\r
+ parameter to MSS SPI driver functions to indicate that MSS SPI 1 should\r
+ perform the requested operation.\r
+ */\r
+extern mss_spi_instance_t g_mss_spi1;\r
+\r
+/***************************************************************************//**\r
+ The MSS_SPI_init() function initializes and hardware and data structures of\r
+ one of the SmartFusion MSS SPIs. The MSS_SPI_init() function must be called\r
+ before any other MSS SPI driver functions can be called.\r
+ \r
+ @param this_spi\r
+ The this_spi parameter is a pointer to an mss_spi_instance_t structure\r
+ identifying the MSS SPI hardware block to be initialized. There are two such\r
+ data structures, g_mss_spi0 and g_mss_spi1, associated with MSS SPI 0 and\r
+ MSS SPI 1 respectively. This parameter must point to either the g_mss_spi0\r
+ or g_mss_spi1 global data structure defined within the SPI driver.\r
+ \r
+ Example:\r
+ @code\r
+ MSS_SPI_init( &g_mss_spi0 );\r
+ @endcode\r
+ */\r
+void MSS_SPI_init\r
+(\r
+ mss_spi_instance_t * this_spi\r
+);\r
+\r
+/***************************************************************************//**\r
+ The MSS_SPI_configure_slave_mode() function configure a MSS SPI block for\r
+ operations as a slave SPI device. It configures the SPI hardware with the\r
+ selected SPI protocol mode and clock speed.\r
+ \r
+ @param this_spi\r
+ The this_spi parameter is a pointer to an mss_spi_instance_t structure\r
+ identifying the MSS SPI hardware block to be initialized. There are two such\r
+ data structures, g_mss_spi0 and g_mss_spi1, associated with MSS SPI 0 and\r
+ MSS SPI 1 respectively. This parameter must point to either the g_mss_spi0\r
+ or g_mss_spi1 global data structure defined within the SPI driver.\r
+ \r
+ @param protocol_mode\r
+ Serial peripheral interface operating mode. Allowed values are:\r
+ - MSS_SPI_MODE0\r
+ - MSS_SPI_MODE1\r
+ - MSS_SPI_MODE2\r
+ - MSS_SPI_MODE3\r
+ - MSS_TI_MODE\r
+ - MSS_NSC_MODE\r
+ \r
+ @param clk_rate\r
+ Divider value used to generate serial interface clock signal from PCLK.\r
+ Allowed values are:\r
+ - MSS_SPI_PCLK_DIV_2\r
+ - MSS_SPI_PCLK_DIV_4\r
+ - MSS_SPI_PCLK_DIV_8\r
+ - MSS_SPI_PCLK_DIV_16\r
+ - MSS_SPI_PCLK_DIV_32\r
+ - MSS_SPI_PCLK_DIV_64\r
+ - MSS_SPI_PCLK_DIV_128\r
+ - MSS_SPI_PCLK_DIV_256\r
+ \r
+ @param frame_bit_length\r
+ Number of bits making up the frame. The maximum frame length is 32 bits. You\r
+ must use the MSS_SPI_BLOCK_TRANSFER_FRAME_SIZE constant as the value for\r
+ frame_bit_length when configuring the MSS SPI master for block transfer\r
+ transactions with the target SPI slave.\r
+ \r
+ Example:\r
+ @code\r
+ MSS_SPI_init( &g_mss_spi0 );\r
+ MSS_SPI_configure_slave_mode\r
+ (\r
+ &g_mss_spi0,\r
+ MSS_SPI_MODE2,\r
+ MSS_SPI_PCLK_DIV_64,\r
+ MSS_SPI_BLOCK_TRANSFER_FRAME_SIZE\r
+ );\r
+ @endcode\r
+ \r
+ */ \r
+void MSS_SPI_configure_slave_mode\r
+(\r
+ mss_spi_instance_t * this_spi,\r
+ mss_spi_protocol_mode_t protocol_mode,\r
+ mss_spi_pclk_div_t clk_rate,\r
+ uint8_t frame_bit_length\r
+);\r
+\r
+/***************************************************************************//**\r
+ The MSS_SPI_configure_master_mode() function configures the protocol mode,\r
+ serial clock speed and frame size for a specific target SPI slave device. It\r
+ is used when the MSS SPI hardware block is used as a SPI master. This function\r
+ must be called once for each target SPI slave the SPI master is going to\r
+ communicate with. The SPI master hardware will be configured with the\r
+ configuration specified by this function during calls to\r
+ MSS_SPI_set_slave_select().\r
+ \r
+ @param this_spi\r
+ The this_spi parameter is a pointer to an mss_spi_instance_t structure\r
+ identifying the MSS SPI hardware block to be initialized. There are two such\r
+ data structures, g_mss_spi0 and g_mss_spi1, associated with MSS SPI 0 and\r
+ MSS SPI 1 respectively. This parameter must point to either the g_mss_spi0\r
+ or g_mss_spi1 global data structure defined within the SPI driver.\r
+ \r
+ \r
+ @param slave\r
+ The slave parameter is used to identify a target SPI slave. The driver will\r
+ hold the MSS SPI master configuration required to communicate with this\r
+ slave, as specified by the other function parameters. Allowed values are:\r
+ \95 MSS_SPI_SLAVE_0\r
+ \95 MSS_SPI_SLAVE_1\r
+ \95 MSS_SPI_SLAVE_2\r
+ \95 MSS_SPI_SLAVE_3\r
+ \95 MSS_SPI_SLAVE_4\r
+ \95 MSS_SPI_SLAVE_5\r
+ \95 MSS_SPI_SLAVE_6\r
+ \95 MSS_SPI_SLAVE_7\r
+ \r
+ @param protocol_mode\r
+ Serial peripheral interface operating mode. Allowed values are:\r
+ \95 MSS_SPI_MODE0\r
+ \95 MSS_SPI_MODE1\r
+ \95 MSS_SPI_MODE2\r
+ \95 MSS_SPI_MODE3\r
+ \95 MSS_SPI_TI_MODE\r
+ \95 MSS_SPI_NSC_MODE\r
+ \r
+ @param clk_rate\r
+ Divider value used to generate serial interface clock signal from PCLK.\r
+ Allowed values are:\r
+ \95 MSS_SPI_PCLK_DIV_2\r
+ \95 MSS_SPI_PCLK_DIV_4\r
+ \95 MSS_SPI_PCLK_DIV_8\r
+ \95 MSS_SPI_PCLK_DIV_16\r
+ \95 MSS_SPI_PCLK_DIV_32\r
+ \95 MSS_SPI_PCLK_DIV_64\r
+ \95 MSS_SPI_PCLK_DIV_128\r
+ \95 MSS_SPI_PCLK_DIV_256\r
+ \r
+ @param frame_bit_length\r
+ Number of bits making up the frame. The maximum frame length is 32 bits. You\r
+ must use the MSS_SPI_BLOCK_TRANSFER_FRAME_SIZE constant as the value for\r
+ frame_bit_length when configuring the MSS SPI master for block transfer\r
+ transactions with the target SPI slave.\r
+ \r
+ Example:\r
+ @code\r
+ MSS_SPI_init( &g_mss_spi0 );\r
+\r
+ MSS_SPI_configure_master_mode\r
+ (\r
+ &g_mss_spi0,\r
+ MSS_SPI_SLAVE_0,\r
+ MSS_SPI_MODE2,\r
+ MSS_SPI_PCLK_DIV_64,\r
+ 12\r
+ );\r
+\r
+ MSS_SPI_configure_master_mode\r
+ (\r
+ &g_mss_spi0,\r
+ MSS_SPI_SLAVE_1,\r
+ MSS_SPI_TI_MODE,\r
+ MSS_SPI_PCLK_DIV_128,\r
+ MSS_SPI_BLOCK_TRANSFER_FRAME_SIZE\r
+ );\r
+ @endcode\r
+ */ \r
+void MSS_SPI_configure_master_mode\r
+(\r
+ mss_spi_instance_t * this_spi,\r
+ mss_spi_slave_t slave,\r
+ mss_spi_protocol_mode_t protocol_mode,\r
+ mss_spi_pclk_div_t clk_rate,\r
+ uint8_t frame_bit_length\r
+);\r
+\r
+/*==============================================================================\r
+ * Master functions\r
+ *============================================================================*/\r
+\r
+/***************************************************************************//**\r
+ The MSS_SPI_slave_select() function is used by a MSS SPI master to select a\r
+ specific slave. This function causes the relevant slave select signal to be\r
+ asserted.\r
+ \r
+ @param this_spi\r
+ The this_spi parameter is a pointer to an mss_spi_instance_t structure\r
+ identifying the MSS SPI hardware block to be initialized. There are two such\r
+ data structures, g_mss_spi0 and g_mss_spi1, associated with MSS SPI 0 and\r
+ MSS SPI 1 respectively. This parameter must point to either the g_mss_spi0\r
+ or g_mss_spi1 global data structure defined within the SPI driver.\r
+ \r
+ \r
+ @param slave\r
+ The slave parameter is one of mss_spi_slave_t enumerated constants\r
+ identifying a slave.\r
+ \r
+ Example:\r
+ @code\r
+ const uint8_t frame_size = 25;\r
+ const uint32_t master_tx_frame = 0x0100A0E1;\r
+\r
+ MSS_SPI_init( &g_mss_spi0 );\r
+ MSS_SPI_configure_master_mode\r
+ (\r
+ &g_mss_spi0,\r
+ MSS_SPI_SLAVE_0,\r
+ MSS_SPI_MODE1,\r
+ MSS_SPI_PCLK_DIV_256,\r
+ frame_size\r
+ );\r
+\r
+ MSS_SPI_set_slave_select( &g_mss_spi0, MSS_SPI_SLAVE_0 );\r
+ MSS_SPI_transfer_frame( &g_mss_spi0, master_tx_frame );\r
+ MSS_SPI_clear_slave_select( &g_mss_spi0, MSS_SPI_SLAVE_0 );\r
+ @endcode\r
+ */\r
+void MSS_SPI_set_slave_select\r
+(\r
+ mss_spi_instance_t * this_spi,\r
+ mss_spi_slave_t slave\r
+);\r
+\r
+/***************************************************************************//**\r
+ The MSS_SPI_clear_slave_select() function is used by a MSS SPI Master to\r
+ deselect a specific slave. This function causes the relevant slave select\r
+ signal to be de-asserted.\r
+ \r
+ @param this_spi\r
+ The this_spi parameter is a pointer to an mss_spi_instance_t structure\r
+ identifying the MSS SPI hardware block to be initialized. There are two such\r
+ data structures, g_mss_spi0 and g_mss_spi1, associated with MSS SPI 0 and\r
+ MSS SPI 1 respectively. This parameter must point to either the g_mss_spi0\r
+ or g_mss_spi1 global data structure defined within the SPI driver.\r
+ \r
+ \r
+ @param slave\r
+ The slave parameter is one of mss_spi_slave_t enumerated constants\r
+ identifying a slave.\r
+ \r
+ Example:\r
+ @code\r
+ const uint8_t frame_size = 25;\r
+ const uint32_t master_tx_frame = 0x0100A0E1;\r
+\r
+ MSS_SPI_init( &g_mss_spi0 );\r
+ MSS_SPI_configure_master_mode\r
+ (\r
+ &g_mss_spi0,\r
+ MSS_SPI_SLAVE_0,\r
+ MSS_SPI_MODE1,\r
+ MSS_SPI_PCLK_DIV_256,\r
+ frame_size\r
+ );\r
+ MSS_SPI_set_slave_select( &g_mss_spi0, MSS_SPI_SLAVE_0 );\r
+ MSS_SPI_transfer_frame( &g_mss_spi0, master_tx_frame );\r
+ MSS_SPI_clear_slave_select( &g_mss_spi0, MSS_SPI_SLAVE_0 );\r
+ @endcode\r
+ */\r
+void MSS_SPI_clear_slave_select\r
+(\r
+ mss_spi_instance_t * this_spi,\r
+ mss_spi_slave_t slave\r
+);\r
+\r
+/***************************************************************************//**\r
+ The MSS_SPI_disable() function is used to temporarily disable a MSS SPI\r
+ hardware block. This function is typically used in conjunction with the\r
+ SPI_set_transfer_byte_count() function to setup a DMA controlled SPI transmit\r
+ transaction as the SPI_set_transfer_byte_count() function must only be used\r
+ when the MSS SPI hardware is disabled.\r
+ \r
+ @param this_spi\r
+ The this_spi parameter is a pointer to an mss_spi_instance_t structure\r
+ identifying the MSS SPI hardware block to be initialized. There are two such\r
+ data structures, g_mss_spi0 and g_mss_spi1, associated with MSS SPI 0 and\r
+ MSS SPI 1 respectively. This parameter must point to either the g_mss_spi0\r
+ or g_mss_spi1 global data structure defined within the SPI driver.\r
+ \r
+ Example:\r
+ @code\r
+ uint32_t transfer_size;\r
+ uint8_t tx_buffer[8] = { 1, 2, 3, 4, 5, 6, 7, 8 };\r
+ \r
+ transfer_size = sizeof(tx_buffer);\r
+ \r
+ MSS_SPI_disable( &g_mss_spi0 );\r
+ MSS_SPI_set_transfer_byte_count( &g_mss_spi0, transfer_size );\r
+ PDMA_start\r
+ (\r
+ PDMA_CHANNEL_0,\r
+ (uint32_t)tx_buffer,\r
+ PDMA_SPI1_TX_REGISTER,\r
+ transfer_size\r
+ );\r
+ MSS_SPI_enable( &g_mss_spi0 );\r
+ \r
+ while ( !MSS_SPI_tx_done( &g_mss_spi0 ) )\r
+ {\r
+ ;\r
+ }\r
+ @endcode\r
+ */\r
+static __INLINE void MSS_SPI_disable\r
+(\r
+ mss_spi_instance_t * this_spi\r
+)\r
+{\r
+ this_spi->hw_reg_bit->CTRL_ENABLE = 0;\r
+}\r
+\r
+/***************************************************************************//**\r
+ The MSS_SPI_enable() function is used to re-enable a MSS SPI hardware block\r
+ after it was disabled using the SPI_disable() function.\r
+ \r
+ @param this_spi\r
+ The this_spi parameter is a pointer to an mss_spi_instance_t structure\r
+ identifying the MSS SPI hardware block to be initialized. There are two such\r
+ data structures, g_mss_spi0 and g_mss_spi1, associated with MSS SPI 0 and\r
+ MSS SPI 1 respectively. This parameter must point to either the g_mss_spi0\r
+ or g_mss_spi1 global data structure defined within the SPI driver.\r
+ \r
+ Example:\r
+ @code\r
+ uint32_t transfer_size;\r
+ uint8_t tx_buffer[8] = { 1, 2, 3, 4, 5, 6, 7, 8 };\r
+ \r
+ transfer_size = sizeof(tx_buffer);\r
+ \r
+ MSS_SPI_disable( &g_mss_spi0 );\r
+ MSS_SPI_set_transfer_byte_count( &g_mss_spi0, transfer_size );\r
+ PDMA_start\r
+ (\r
+ PDMA_CHANNEL_0,\r
+ (uint32_t)tx_buffer,\r
+ PDMA_SPI1_TX_REGISTER,\r
+ transfer_size\r
+ );\r
+ MSS_SPI_enable( &g_mss_spi0 );\r
+ \r
+ while ( !MSS_SPI_tx_done( &g_mss_spi0 ) )\r
+ {\r
+ ;\r
+ }\r
+ @endcode\r
+ */\r
+static __INLINE void MSS_SPI_enable\r
+(\r
+ mss_spi_instance_t * this_spi\r
+)\r
+{\r
+ this_spi->hw_reg_bit->CTRL_ENABLE = 1;\r
+}\r
+\r
+/***************************************************************************//**\r
+ The MSS_SPI_set_transfer_byte_count() function is used as part of setting up\r
+ a SPI transfer using DMA. It specifies the number of bytes that must be\r
+ transferred before MSS_SPI_tx_done() indicates that the transfer is complete.\r
+ \r
+ @param this_spi\r
+ The this_spi parameter is a pointer to an mss_spi_instance_t structure\r
+ identifying the MSS SPI hardware block to be initialized. There are two such\r
+ data structures, g_mss_spi0 and g_mss_spi1, associated with MSS SPI 0 and\r
+ MSS SPI 1 respectively. This parameter must point to either the g_mss_spi0\r
+ or g_mss_spi1 global data structure defined within the SPI driver.\r
+ \r
+ \r
+ @param byte_count\r
+ The byte_count parameter specifies the number of bytes that must be\r
+ transferred by the SPI hardware block considering that a transaction has\r
+ been completed.\r
+ \r
+ Example:\r
+ @code\r
+ uint32_t transfer_size;\r
+ uint8_t tx_buffer[8] = { 1, 2, 3, 4, 5, 6, 7, 8 };\r
+ \r
+ transfer_size = sizeof(tx_buffer);\r
+ \r
+ MSS_SPI_disable( &g_mss_spi0 );\r
+ \r
+ MSS_SPI_set_transfer_byte_count( &g_mss_spi0, transfer_size );\r
+ \r
+ PDMA_start( PDMA_CHANNEL_0, (uint32_t)tx_buffer, 0x40011014, transfer_size );\r
+ \r
+ MSS_SPI_enable( &g_mss_spi0 );\r
+ \r
+ while ( !MSS_SPI_tx_done( &g_mss_spi0) )\r
+ {\r
+ ;\r
+ }\r
+ @endcode\r
+ */\r
+static __INLINE void MSS_SPI_set_transfer_byte_count\r
+(\r
+ mss_spi_instance_t * this_spi,\r
+ uint16_t byte_count\r
+)\r
+{\r
+ const uint32_t TXRXDFCOUNT_SHIFT = 8U;\r
+ const uint32_t TXRXDFCOUNT_MASK = 0x00FFFF00U;\r
+ \r
+ this_spi->hw_reg->CONTROL = (this_spi->hw_reg->CONTROL & ~TXRXDFCOUNT_MASK) | ( (byte_count << TXRXDFCOUNT_SHIFT) & TXRXDFCOUNT_MASK);\r
+ this_spi->hw_reg->TXRXDF_SIZE = 8U;\r
+}\r
+\r
+/***************************************************************************//**\r
+ The MSS_SPI_tx_done() function is used to find out if a DMA controlled transfer\r
+ has completed.\r
+ \r
+ @param this_spi\r
+ The this_spi parameter is a pointer to an mss_spi_instance_t structure\r
+ identifying the MSS SPI hardware block to be initialized. There are two such\r
+ data structures, g_mss_spi0 and g_mss_spi1, associated with MSS SPI 0 and\r
+ MSS SPI 1 respectively. This parameter must point to either the g_mss_spi0\r
+ or g_mss_spi1 global data structure defined within the SPI driver.\r
+ \r
+ Example:\r
+ @code\r
+ uint32_t transfer_size;\r
+ uint8_t tx_buffer[8] = { 1, 2, 3, 4, 5, 6, 7, 8 };\r
+ \r
+ transfer_size = sizeof(tx_buffer);\r
+ \r
+ MSS_SPI_disable( &g_mss_spi0 );\r
+ \r
+ MSS_SPI_set_transfer_byte_count( &g_mss_spi0, transfer_size );\r
+ \r
+ PDMA_start\r
+ (\r
+ PDMA_CHANNEL_0,\r
+ (uint32_t)tx_buffer,\r
+ PDMA_SPI1_TX_REGISTER,\r
+ transfer_size\r
+ );\r
+ \r
+ MSS_SPI_enable( &g_mss_spi0 );\r
+ \r
+ while ( !MSS_SPI_tx_done(&g_mss_spi0) )\r
+ {\r
+ ;\r
+ }\r
+ @endcode\r
+ */\r
+static __INLINE uint32_t MSS_SPI_tx_done\r
+(\r
+ mss_spi_instance_t * this_spi\r
+)\r
+{\r
+ return this_spi->hw_reg_bit->STATUS_TX_DONE;\r
+}\r
+\r
+/***************************************************************************//**\r
+ The MSS_SPI_transfer_frame() function is used by a MSS SPI master to transmit\r
+ and receive a frame up to 32 bits long. This function is typically used for\r
+ transactions with a SPI slave where the number of transmit and receive bits is\r
+ not divisible by 8.\r
+ \r
+ @param this_spi\r
+ The this_spi parameter is a pointer to an mss_spi_instance_t structure\r
+ identifying the MSS SPI hardware block to be initialized. There are two such\r
+ data structures, g_mss_spi0 and g_mss_spi1, associated with MSS SPI 0 and\r
+ MSS SPI 1 respectively. This parameter must point to either the g_mss_spi0\r
+ or g_mss_spi1 global data structure defined within the SPI driver.\r
+ \r
+ \r
+ @param tx_bits\r
+ The tx_bits parameter is a 32 bits word containing the value that will be\r
+ transmitted.\r
+ Note: The bit length of the value to be transmitted to the slave must be\r
+ specified as the frame_bit_length parameter in a previous call to\r
+ the MSS_SPI_configure_master() function.\r
+\r
+ @return\r
+ This function returns a 32 bits word containing the value that is received\r
+ from the slave.\r
+ \r
+ Example:\r
+ @code\r
+ const uint8_t frame_size = 25;\r
+ const uint32_t master_tx_frame = 0x0100A0E1;\r
+ uint32_t master_rx;\r
+ \r
+ MSS_SPI_init( &g_mss_spi0 );\r
+ MSS_SPI_configure_master_mode\r
+ (\r
+ &g_mss_spi0,\r
+ MSS_SPI_SLAVE_0,\r
+ MSS_SPI_MODE1,\r
+ MSS_SPI_PCLK_DIV_256,\r
+ frame_size\r
+ );\r
+ \r
+ MSS_SPI_set_slave_select( &g_mss_spi0, MSS_SPI_SLAVE_0 );\r
+ master_rx = MSS_SPI_transfer_frame( &g_mss_spi0, master_tx_frame );\r
+ MSS_SPI_clear_slave_select( &g_mss_spi0, MSS_SPI_SLAVE_0 );\r
+ @endcode\r
+ */\r
+uint32_t MSS_SPI_transfer_frame\r
+(\r
+ mss_spi_instance_t * this_spi,\r
+ uint32_t tx_bits\r
+);\r
+\r
+/***************************************************************************//**\r
+ The MSS_SPI_transfer_block() function is used by MSS SPI masters to transmit\r
+ and receive blocks of data organized as a specified number of bytes. It can be\r
+ used for:\r
+ \95 Writing a data block to a slave\r
+ \95 Reading a data block from a slave\r
+ \95 Sending a command to a slave followed by reading the outcome of the\r
+ command in a single SPI transaction. This function can be used alongside\r
+ Peripheral DMA functions to perform the actual moving to and from the SPI\r
+ hardware block using Peripheral DMA.\r
+ \r
+ @param this_spi\r
+ The this_spi parameter is a pointer to an mss_spi_instance_t structure\r
+ identifying the MSS SPI hardware block to be initialized. There are two such\r
+ data structures, g_mss_spi0 and g_mss_spi1, associated with MSS SPI 0 and\r
+ MSS SPI 1 respectively. This parameter must point to either the g_mss_spi0\r
+ or g_mss_spi1 global data structure defined within the SPI driver.\r
+ \r
+ \r
+ @param cmd_buffer\r
+ The cmd_buffer parameter is a pointer to the buffer containing the data that\r
+ will be sent by the master from the beginning of the transfer. This pointer\r
+ can be null (0) if the master does not need to send a command before reading\r
+ data or if the command part of the transfer is written to the SPI hardware\r
+ block using DMA.\r
+ \r
+ @param cmd_byte_size\r
+ The cmd_byte_size parameter specifies the number of bytes contained in\r
+ cmd_buffer that will be sent. A value of 0 indicates that no data needs to\r
+ be sent to the slave. A non-zero value while the cmd_buffer pointer is 0 is\r
+ used to indicate that the command data will be written to the SPI hardware\r
+ block using DMA.\r
+ \r
+ @param rd_buffer\r
+ The rd_buffer parameter is a pointer to the buffer where the data received\r
+ from the slave after the command has been sent will be stored.\r
+ \r
+ @param rd_byte_size\r
+ The rd_byte_size parameter specifies the number of bytes to be received from\r
+ the slave and stored in the rd_buffer. A value of 0 indicates that no data\r
+ is to be read from the slave. A non-zero value while the rd_buffer pointer\r
+ is null (0) is used to specify the receive size when using DMA to read from\r
+ the slave. \r
+ Note: All bytes received from the slave, including the bytes received\r
+ while the command is sent, will be read through DMA.\r
+ \r
+ Polled write transfer example:\r
+ @code\r
+ uint8_t master_tx_buffer[MASTER_TX_BUFFER] = \r
+ {\r
+ 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A\r
+ };\r
+ MSS_SPI_init( &g_mss_spi0 );\r
+ MSS_SPI_configure_master_mode\r
+ (\r
+ &g_mss_spi0,\r
+ MSS_SPI_SLAVE_0,\r
+ MSS_SPI_MODE1,\r
+ MSS_SPI_PCLK_DIV_256,\r
+ MSS_SPI_BLOCK_TRANSFER_FRAME_SIZE\r
+ );\r
+ \r
+ MSS_SPI_set_slave_select( &g_mss_spi0, MSS_SPI_SLAVE_0 );\r
+ MSS_SPI_transfer_block\r
+ (\r
+ &g_mss_spi0,\r
+ master_tx_buffer,\r
+ sizeof(master_tx_buffer),\r
+ 0,\r
+ 0\r
+ );\r
+ MSS_SPI_clear_slave_select( &g_mss_spi0, MSS_SPI_SLAVE_0 );\r
+ @endcode\r
+ \r
+ DMA transfer example:\r
+ In this example the transmit and receive buffers are not specified as part of\r
+ the call to MSS_SPI_transfer_block(). MSS_SPI_transfer_block() will only\r
+ prepare the MSS SPI hardware for a transfer. The MSS SPI transmit hardware\r
+ FIFO is filled using one DMA channel and a second DMA channel is used to read\r
+ the content of the MSS SPI receive hardware FIFO. The transmit and receive\r
+ buffers are specified by two separate calls to PDMA_start() to initiate DMA\r
+ transfers on the channel used for transmit data and the channel used for\r
+ receive data. \r
+ @code\r
+ uint8_t master_tx_buffer[MASTER_RX_BUFFER] =\r
+ {\r
+ 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA\r
+ };\r
+ uint8_t slave_rx_buffer[MASTER_RX_BUFFER] = \r
+ {\r
+ 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A\r
+ };\r
+ MSS_SPI_init( &g_mss_spi0 );\r
+\r
+ MSS_SPI_configure_master_mode\r
+ (\r
+ &g_mss_spi0,\r
+ MSS_SPI_SLAVE_0,\r
+ MSS_SPI_MODE1,\r
+ MSS_SPI_PCLK_DIV_256,\r
+ MSS_SPI_BLOCK_TRANSFER_FRAME_SIZE\r
+ );\r
+ MSS_SPI_set_slave_select( &g_mss_spi0, MSS_SPI_SLAVE_0 );\r
+ MSS_SPI_transfer_block( &g_mss_spi0, 0, 0, 0, 0 );\r
+ PDMA_start\r
+ (\r
+ PDMA_CHANNEL_1,\r
+ PDMA_SPI0_RX_REGISTER,\r
+ (uint32_t)master_rx_buffer,\r
+ sizeof(master_rx_buffer)\r
+ ); \r
+ PDMA_start\r
+ (\r
+ PDMA_CHANNEL_2,\r
+ (uint32_t)master_tx_buffer,\r
+ PDMA_SPI0_TX_REGISTER,\r
+ sizeof(master_tx_buffer)\r
+ ); \r
+ while( PDMA_status(PDMA_CHANNEL_1) == 0 )\r
+ {\r
+ ;\r
+ }\r
+ MSS_SPI_clear_slave_select( &g_mss_spi0, MSS_SPI_SLAVE_0 );\r
+ @endcode\r
+ */\r
+void MSS_SPI_transfer_block\r
+(\r
+ mss_spi_instance_t * this_spi,\r
+ const uint8_t * cmd_buffer,\r
+ uint16_t cmd_byte_size,\r
+ uint8_t * rd_buffer,\r
+ uint16_t rd_byte_size\r
+);\r
+\r
+/*==============================================================================\r
+ * Slave functions\r
+ *============================================================================*/\r
+\r
+/***************************************************************************//**\r
+ The MSS_SPI_set_frame_rx_handler() function is used by MSS SPI slaves to\r
+ specify the receive handler function that will be called by the MSS SPI driver\r
+ interrupt handler when a a frame of data is received by the MSS SPI slave.\r
+ \r
+ @param this_spi\r
+ The this_spi parameter is a pointer to an mss_spi_instance_t structure\r
+ identifying the MSS SPI hardware block to be initialized. There are two such\r
+ data structures, g_mss_spi0 and g_mss_spi1, associated with MSS SPI 0 and\r
+ MSS SPI 1 respectively. This parameter must point to either the g_mss_spi0\r
+ or g_mss_spi1 global data structure defined within the SPI driver.\r
+ \r
+ \r
+ @param rx_handler\r
+ The rx_handler parameter is a pointer to the frame receive handler that must\r
+ be called when a frame is received by the MSS SPI slave.\r
+ \r
+ Example:\r
+ @code\r
+ uint32_t g_slave_rx_frame = 0;\r
+\r
+ void slave_frame_handler( uint32_t rx_frame )\r
+ {\r
+ g_slave_rx_frame = rx_frame;\r
+ }\r
+\r
+ int setup_slave( void )\r
+ {\r
+ const uint16_t frame_size = 25;\r
+ MSS_SPI_init( &g_mss_spi1 );\r
+ MSS_SPI_configure_slave_mode\r
+ (\r
+ &g_mss_spi0,\r
+ MSS_SPI_MODE2,\r
+ MSS_SPI_PCLK_DIV_64,\r
+ frame_size\r
+ );\r
+ MSS_SPI_set_frame_rx_handler( &g_mss_spi1, slave_frame_handler );\r
+ }\r
+ @endcode\r
+ */\r
+void MSS_SPI_set_frame_rx_handler\r
+(\r
+ mss_spi_instance_t * this_spi,\r
+ mss_spi_frame_rx_handler_t rx_handler\r
+);\r
+\r
+/***************************************************************************//**\r
+ The MSS_SPI_set_slave_tx_frame() function is used by MSS SPI slaves to specify\r
+ the frame that will be transmitted when a transaction is initiated by the SPI\r
+ master.\r
+ \r
+ @param this_spi\r
+ The this_spi parameter is a pointer to an mss_spi_instance_t structure\r
+ identifying the MSS SPI hardware block to be initialized. There are two such\r
+ data structures, g_mss_spi0 and g_mss_spi1, associated with MSS SPI 0 and\r
+ MSS SPI 1 respectively. This parameter must point to either the g_mss_spi0\r
+ or g_mss_spi1 global data structure defined within the SPI driver.\r
+ \r
+ \r
+ @param frame_value\r
+ The frame_value parameter contains the value of the frame to be sent to the\r
+ master.\r
+ Note: The bit length of the value to be transmitted to the master must be\r
+ specified as the frame_bit_length parameter in a previous call to\r
+ the MSS_SPI_configure_slave() function.\r
+\r
+ Example:\r
+ @code\r
+ const uint16_t frame_size = 25;\r
+ const uint32_t slave_tx_frame = 0x0110F761;\r
+ uint32_t master_rx;\r
+\r
+ MSS_SPI_init( &g_mss_spi1 );\r
+ MSS_SPI_configure_slave_mode\r
+ (\r
+ &g_mss_spi0,\r
+ MSS_SPI_MODE2,\r
+ MSS_SPI_PCLK_DIV_64,\r
+ frame_size\r
+ );\r
+ MSS_SPI_set_slave_tx_frame( &g_mss_spi1, slave_tx_frame );\r
+ @endcode\r
+ */\r
+void MSS_SPI_set_slave_tx_frame\r
+(\r
+ mss_spi_instance_t * this_spi,\r
+ uint32_t frame_value\r
+);\r
+\r
+/***************************************************************************//**\r
+ The MSS_SPI_set_slave_block_buffers() function is used to configure an MSS\r
+ SPI slave for block transfer operations. It specifies one or more of the\r
+ following:\r
+ \95 The data that will be transmitted when accessed by a master.\r
+ \95 The buffer where data received from a master will be stored.\r
+ \95 The handler function that must be called after the receive buffer has been\r
+ filled.\r
+ \95 The number of bytes that must be received from the master before the receive\r
+ handler function is called.\r
+ These parameters allow the following use cases:\r
+ \95 Slave performing an action after receiving a block of data from a master\r
+ containing a command. The action will be performed by the receive handling\r
+ based on the content of the receive data buffer.\r
+ \95 Slave returning a block of data to the master. The type of information is\r
+ always the same but the actual values change over time. For example,\r
+ returning the voltage of a predefined set of analog inputs.\r
+ \95 Slave returning data based on a command contained in the first part of the\r
+ SPI transaction. For example, reading the voltage of the analog input\r
+ specified by the first data byte by the master. This is achieved by setting\r
+ the rx_buff_size parameter to the number of received bytes making up the\r
+ command.\r
+ \r
+ @param this_spi\r
+ The this_spi parameter is a pointer to an mss_spi_instance_t structure\r
+ identifying the MSS SPI hardware block to be initialized. There are two such\r
+ data structures, g_mss_spi0 and g_mss_spi1, associated with MSS SPI 0 and\r
+ MSS SPI 1 respectively. This parameter must point to either the g_mss_spi0\r
+ or g_mss_spi1 global data structure defined within the SPI driver.\r
+ \r
+ \r
+ @param tx_buffer\r
+ The tx_buffer parameter is a pointer to a buffer containing the data that\r
+ will be sent to the master. This parameter can be set to 0 if the MSS SPI\r
+ slave is not intended to be the target of SPI read transactions or if DMA\r
+ is used to transfer SPI read data into the MSS SPI slave.\r
+ \r
+ @param tx_buff_size\r
+ The tx_buff_size parameter specifies the number of bytes contained in the\r
+ tx_buffer. This parameter can be set to 0 if the MSS SPI slave is not\r
+ intended to be the target of SPI read transactions or if DMA is used to\r
+ transfer SPI read data into the MSS SPI slave.\r
+ \r
+ @param rx_buffer\r
+ The rx_buffer parameter is a pointer to the buffer where data received from\r
+ the master will be stored. This parameter can be set to 0 if the MSS SPI\r
+ slave is not intended to be the target of SPI write or write-read\r
+ transactions. It can also set to 0 if the MSS SPI slave uses DMA to handle\r
+ data written to it.\r
+ \r
+ @param rx_buff_size\r
+ The rx_buff_size parameter specifies the size of the receive buffer. It is\r
+ also the number of bytes that must be received before the receive handler\r
+ is called, if a receive handler is specified using the block_rx_handler\r
+ parameter. This parameter can be set to 0 if the MSS SPI slave is not\r
+ intended to be the target of SPI write or write-read transactions. It can\r
+ also set to 0 if the MSS SPI slave uses DMA to handle data written to it.\r
+ \r
+ @param block_rx_handler\r
+ The block_rx_handler parameter is a pointer to a function that will be\r
+ called when the receive buffer has been filled. This parameter can be set\r
+ to 0 if the MSS SPI slave is not intended to be the target of SPI write or\r
+ write-read transactions. It can also set to 0 if the MSS SPI slave uses DMA\r
+ to handle data written to it.\r
+ \r
+ Slave performing operation based on master command:\r
+ In this example the SPI slave is configured to receive 10 bytes of data or\r
+ command from the SPI slave and process the data received from the master.\r
+ @code\r
+ uint32_t nb_of_rx_handler_calls = 0;\r
+ \r
+ void spi1_block_rx_handler_b\r
+ (\r
+ uint8_t * rx_buff,\r
+ uint16_t rx_size\r
+ )\r
+ {\r
+ ++nb_of_rx_handler_calls;\r
+ }\r
+ \r
+ void setup_slave( void )\r
+ {\r
+ uint8_t slave_rx_buffer[10] = \r
+ {\r
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00\r
+ };\r
+ \r
+ MSS_SPI_init( &g_mss_spi1 );\r
+ MSS_SPI_configure_slave_mode\r
+ ( \r
+ &g_mss_spi0,\r
+ MSS_SPI_MODE2,\r
+ MSS_SPI_PCLK_DIV_64,\r
+ MSS_SPI_BLOCK_TRANSFER_FRAME_SIZE\r
+ );\r
+ \r
+ MSS_SPI_set_slave_block_buffers\r
+ (\r
+ &g_mss_spi1,\r
+ 0,\r
+ 0,\r
+ slave_rx_buffer,\r
+ sizeof(master_tx_buffer),\r
+ spi1_block_rx_handler_b\r
+ );\r
+ }\r
+ @endcode\r
+ \r
+ Slave responding to command example:\r
+ In this example the slave will return data based on a command sent by the\r
+ master. The first part of the transaction is handled using polled mode where\r
+ each byte returned to the master is written as part of the interrupt service\r
+ routine. The second part of the transaction, where the slave returns data\r
+ based on the command value, is sent using a DMA transfer initiated by the\r
+ receive handler. \r
+ @code\r
+ static uint8_t g_spi1_tx_buffer_b[SLAVE_TX_BUFFER_SIZE] =\r
+ {\r
+ 5, 6, 7, 8, 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5\r
+ };\r
+ \r
+ void spi1_block_rx_handler\r
+ (\r
+ uint8_t * rx_buff,\r
+ uint16_t rx_size\r
+ )\r
+ {\r
+ if ( rx_buff[2] == 0x99 )\r
+ {\r
+ PDMA_start\r
+ (\r
+ PDMA_CHANNEL_0,\r
+ (uint32_t)g_spi1_tx_buffer_b,\r
+ 0x40011014,\r
+ sizeof(g_spi1_tx_buffer_b)\r
+ ); \r
+ }\r
+ }\r
+ \r
+ void setup_slave( void )\r
+ {\r
+ uint8_t slave_preamble[8] = { 9, 10, 11, 12, 13, 14, 16, 16 };\r
+\r
+ MSS_SPI_init( &g_mss_spi1 );\r
+ MSS_SPI_configure_slave_mode\r
+ (\r
+ &g_mss_spi0,\r
+ MSS_SPI_MODE2,\r
+ MSS_SPI_PCLK_DIV_64,\r
+ MSS_SPI_BLOCK_TRANSFER_FRAME_SIZE\r
+ );\r
+ \r
+ PDMA_init();\r
+ PDMA_configure\r
+ (\r
+ PDMA_CHANNEL_0, \r
+ TO_SPI_1,\r
+ LOW_PRIORITY | BYTE_TRANSFER | INC_SRC_ONE_BYTE\r
+ );\r
+ \r
+ MSS_SPI_set_slave_block_buffers\r
+ (\r
+ &g_mss_spi1,\r
+ slave_preamble,\r
+ 4,\r
+ g_spi1_rx_buffer,\r
+ sizeof(g_spi1_rx_buffer),\r
+ spi1_block_rx_handler\r
+ );\r
+ }\r
+ @endcode\r
+ */\r
+void MSS_SPI_set_slave_block_buffers\r
+(\r
+ mss_spi_instance_t * this_spi,\r
+ const uint8_t * tx_buffer,\r
+ uint32_t tx_buff_size,\r
+ uint8_t * rx_buffer,\r
+ uint32_t rx_buff_size,\r
+ mss_spi_block_rx_handler_t block_rx_handler\r
+);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* MSS_SPI_H_*/\r
--- /dev/null
+/*******************************************************************************\r
+ * (c) Copyright 2007 Actel Corporation. All rights reserved.\r
+ *\r
+ * SmartFusion Microcontroller Subsystem UART bare metal software driver\r
+ * implementation.\r
+ *\r
+ * SVN $Revision: 1898 $\r
+ * SVN $Date: 2009-12-21 17:27:57 +0000 (Mon, 21 Dec 2009) $\r
+ */\r
+#include "mss_uart.h"\r
+#include "../../CMSIS/mss_assert.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif \r
+\r
+/*******************************************************************************\r
+ * defines\r
+ */\r
+#define TX_READY 0x01U\r
+#define TX_COMPLETE 0U\r
+\r
+#define TX_FIFO_SIZE 16U\r
+\r
+#define FCR_TRIG_LEVEL_MASK 0xC0U\r
+\r
+#define IIRF_MASK 0x0FU\r
+\r
+/*******************************************************************************\r
+ * Possible values for Interrupt Identification Register Field.\r
+ */\r
+#define IIRF_MODEM_STATUS 0x00U \r
+#define IIRF_THRE 0x02U\r
+#define IIRF_RX_DATA 0x04U\r
+#define IIRF_RX_LINE_STATUS 0x06U\r
+#define IIRF_DATA_TIMEOUT 0x0CU\r
+\r
+/*******************************************************************************\r
+ * Cortex-M3 interrupt handler functions implemented as part of the MSS UART\r
+ * driver.\r
+ */\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void UART0_IRQHandler( void );\r
+#else\r
+void UART0_IRQHandler( void );\r
+#endif\r
+\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void UART1_IRQHandler( void );\r
+#else\r
+void UART1_IRQHandler( void );\r
+#endif\r
+\r
+/*******************************************************************************\r
+ * Local functions.\r
+ */\r
+static void MSS_UART_isr( mss_uart_instance_t * this_uart );\r
+\r
+/*******************************************************************************\r
+ *\r
+ */\r
+mss_uart_instance_t g_mss_uart0;\r
+mss_uart_instance_t g_mss_uart1;\r
+\r
+/***************************************************************************//**\r
+ * UART_init.\r
+ * Initialises the UART with default configuration.\r
+ */\r
+void \r
+MSS_UART_init\r
+(\r
+ mss_uart_instance_t* this_uart, \r
+ uint32_t baud_rate,\r
+ uint8_t line_config\r
+)\r
+{\r
+ uint16_t baud_value;\r
+ uint32_t pclk_freq;\r
+\r
+ /* The driver expects g_mss_uart0 and g_mss_uart1 to be the only \r
+ * mss_uart_instance_t instances used to identfy UART0 and UART1. */\r
+ ASSERT( (this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1) );\r
+ \r
+ /* Force the value of the CMSIS global variables holding the various system\r
+ * clock frequencies to be updated. */\r
+ SystemCoreClockUpdate();\r
+ \r
+ if ( this_uart == &g_mss_uart0 )\r
+ {\r
+ this_uart->hw_reg = UART0;\r
+ this_uart->hw_reg_bit = UART0_BITBAND;\r
+ this_uart->irqn = UART0_IRQn;\r
+\r
+ pclk_freq = g_FrequencyPCLK0;\r
+ \r
+ /* reset UART0 */\r
+ SYSREG->SOFT_RST_CR |= SYSREG_UART0_SOFTRESET_MASK;\r
+ /* Clear any previously pended UART0 interrupt */\r
+ NVIC_ClearPendingIRQ( UART0_IRQn );\r
+ /* Take UART0 out of reset. */\r
+ SYSREG->SOFT_RST_CR &= ~SYSREG_UART0_SOFTRESET_MASK;\r
+ }\r
+ else\r
+ {\r
+ this_uart->hw_reg = UART1;\r
+ this_uart->hw_reg_bit = UART1_BITBAND;\r
+ this_uart->irqn = UART1_IRQn;\r
+\r
+ pclk_freq = g_FrequencyPCLK1;\r
+ \r
+ /* Reset UART1 */\r
+ SYSREG->SOFT_RST_CR |= SYSREG_UART1_SOFTRESET_MASK;\r
+ /* Clear any previously pended UART1 interrupt */\r
+ NVIC_ClearPendingIRQ( UART1_IRQn );\r
+ /* Take UART1 out of reset. */\r
+ SYSREG->SOFT_RST_CR &= ~SYSREG_UART1_SOFTRESET_MASK;\r
+ }\r
+ \r
+ /* disable interrupts */\r
+ this_uart->hw_reg->IER = 0U;\r
+\r
+ /*\r
+ * Compute baud value based on requested baud rate and PCLK frequency.\r
+ * The baud value is computed using the following equation:\r
+ * baud_value = PCLK_Frequency / (baud_rate * 16)\r
+ * The baud value is rounded up or down depending on what would be the remainder\r
+ * of the divide by 16 operation.\r
+ */\r
+ baud_value = (uint16_t)(pclk_freq / baud_rate);\r
+ if ( baud_value & 0x00000008U )\r
+ {\r
+ /* remainder above 0.5 */\r
+ baud_value = (baud_value >> 4U) + 1U;\r
+ }\r
+ else\r
+ {\r
+ /* remainder below 0.5 */\r
+ baud_value = (baud_value >> 4U);\r
+ }\r
+\r
+ /* set divisor latch */\r
+ this_uart->hw_reg_bit->LCR_DLAB = (uint32_t)1;\r
+\r
+ /* msb of baud value */\r
+ this_uart->hw_reg->DMR = (uint8_t)(baud_value >> 8);\r
+ /* lsb of baud value */\r
+ this_uart->hw_reg->DLR = (uint8_t)baud_value;\r
+\r
+ /* reset divisor latch */\r
+ this_uart->hw_reg_bit->LCR_DLAB = (uint32_t)0;\r
+\r
+ /* set the line control register (bit length, stop bits, parity) */\r
+ this_uart->hw_reg->LCR = line_config;\r
+ \r
+ /* FIFO configuration */\r
+ this_uart->hw_reg->FCR = (uint8_t)MSS_UART_FIFO_SINGLE_BYTE;\r
+ \r
+ /* disable loopback */\r
+ this_uart->hw_reg_bit->MCR_LOOP = (uint32_t)0;\r
+\r
+ /* Instance setup */\r
+ this_uart->tx_buff_size = TX_COMPLETE;\r
+ this_uart->tx_buffer = (const uint8_t *)0;\r
+ this_uart->tx_idx = 0U;\r
+ \r
+ this_uart->rx_handler = (mss_uart_rx_handler_t)0;\r
+}\r
+\r
+/***************************************************************************//**\r
+ * See mss_uart.h for details of how to use this function.\r
+ */\r
+void \r
+MSS_UART_polled_tx\r
+( \r
+ mss_uart_instance_t * this_uart, \r
+ const uint8_t * pbuff,\r
+ uint32_t tx_size\r
+)\r
+{\r
+ uint32_t char_idx;\r
+ uint32_t status;\r
+\r
+ ASSERT( (this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1) );\r
+ \r
+ for ( char_idx = 0U; char_idx < tx_size; char_idx++ )\r
+ {\r
+ /* Wait for UART to become ready to transmit. */\r
+ do {\r
+ status = this_uart->hw_reg_bit->LSR_THRE;\r
+ } while ( (status & TX_READY) == 0U );\r
+ /* Send next character in the buffer. */\r
+ this_uart->hw_reg->THR = pbuff[char_idx];\r
+ }\r
+}\r
+\r
+/***************************************************************************//**\r
+ * See mss_uart.h for details of how to use this function.\r
+ */\r
+void \r
+MSS_UART_polled_tx_string\r
+( \r
+ mss_uart_instance_t * this_uart, \r
+ const uint8_t * p_sz_string\r
+)\r
+{\r
+ uint32_t char_idx;\r
+ uint32_t status;\r
+\r
+ ASSERT( (this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1) );\r
+ \r
+ char_idx = 0U;\r
+ \r
+ while ( p_sz_string[char_idx] != 0U )\r
+ {\r
+ /* Wait for UART to become ready to transmit. */\r
+ do {\r
+ status = this_uart->hw_reg_bit->LSR_THRE;\r
+ } while ( (status & TX_READY) == 0U);\r
+ /* Send next character in the buffer. */\r
+ this_uart->hw_reg->THR = p_sz_string[char_idx];\r
+ ++char_idx;\r
+ }\r
+}\r
+\r
+/***************************************************************************//**\r
+ * See mss_uart.h for details of how to use this function.\r
+ */\r
+void \r
+MSS_UART_irq_tx\r
+( \r
+ mss_uart_instance_t * this_uart, \r
+ const uint8_t * pbuff,\r
+ uint32_t tx_size\r
+)\r
+{\r
+ ASSERT( (this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1) );\r
+ \r
+ if ( tx_size > 0U )\r
+ {\r
+ /*Initialise the transmit info for the UART instance with the arguments.*/\r
+ this_uart->tx_buffer = pbuff;\r
+ this_uart->tx_buff_size = tx_size;\r
+ this_uart->tx_idx = (uint16_t)0;\r
+ \r
+ /* enables TX interrupt */\r
+ this_uart->hw_reg_bit->IER_ETBEI = (uint32_t)1;\r
+ \r
+ /* Enable UART instance interrupt in Cortex-M3 NVIC. */\r
+ NVIC_EnableIRQ( this_uart->irqn );\r
+ }\r
+}\r
+\r
+/***************************************************************************//**\r
+ * See mss_uart.h for details of how to use this function.\r
+ */\r
+int8_t \r
+MSS_UART_tx_complete\r
+( \r
+ mss_uart_instance_t * this_uart \r
+)\r
+{\r
+ int8_t ret_value = 0;\r
+ uint32_t transmit_empty = this_uart->hw_reg_bit->LSR_TEMT;\r
+ \r
+ ASSERT( (this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1) );\r
+\r
+ if ( ( TX_COMPLETE == this_uart->tx_buff_size ) && transmit_empty )\r
+ {\r
+ ret_value = 1;\r
+ }\r
+ \r
+ return ret_value;\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * See mss_uart.h for details of how to use this function.\r
+ */\r
+size_t\r
+MSS_UART_get_rx\r
+(\r
+ mss_uart_instance_t * this_uart,\r
+ uint8_t * rx_buff,\r
+ size_t buff_size\r
+)\r
+{\r
+ size_t rx_size = 0U;\r
+ \r
+ ASSERT( (this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1) );\r
+\r
+ while (( this_uart->hw_reg_bit->LSR_DR != 0U) && ( rx_size < buff_size ) )\r
+ {\r
+ rx_buff[rx_size] = this_uart->hw_reg->RBR;\r
+ ++rx_size;\r
+ }\r
+ \r
+ return rx_size;\r
+}\r
+\r
+/***************************************************************************//**\r
+ * Interrupt service routine triggered by the Transmitter Holding Register\r
+ * Empty (THRE) interrupt or Received Data Available (RDA). \r
+ * On THRE irq this routine will transmit the data from the transmit buffer. \r
+ * When all bytes are transmitted, this routine disables the THRE interrupt\r
+ * and resets the transmit counter.\r
+ * On RDA irq this routine will call the user's receive handler routine previously\r
+ * registered with the UART driver through a call to UART_set_rx_handler().\r
+ */\r
+static void \r
+MSS_UART_isr\r
+( \r
+ mss_uart_instance_t * this_uart \r
+)\r
+{\r
+ uint8_t iirf;\r
+ uint32_t tx_empty;\r
+ \r
+ ASSERT( (this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1) );\r
+\r
+ iirf = this_uart->hw_reg->IIR & IIRF_MASK;\r
+ \r
+ switch ( iirf )\r
+ {\r
+ case IIRF_MODEM_STATUS:\r
+ break;\r
+ \r
+ case IIRF_THRE: /* Transmitter Holding Register Empty */\r
+ tx_empty = this_uart->hw_reg_bit->LSR_TEMT;\r
+ \r
+ if ( tx_empty )\r
+ {\r
+ uint32_t i;\r
+ uint32_t fill_size = TX_FIFO_SIZE;\r
+ uint32_t tx_remain = this_uart->tx_buff_size - this_uart->tx_idx;\r
+ if ( tx_remain < TX_FIFO_SIZE )\r
+ {\r
+ fill_size = tx_remain;\r
+ }\r
+ /* Fill up FIFO */\r
+ for ( i = 0U; i < fill_size; ++i )\r
+ {\r
+ this_uart->hw_reg->THR = this_uart->tx_buffer[this_uart->tx_idx];\r
+ ++this_uart->tx_idx;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ this_uart->hw_reg->THR = this_uart->tx_buffer[this_uart->tx_idx];\r
+ ++this_uart->tx_idx;\r
+ }\r
+ \r
+ if ( this_uart->tx_idx == this_uart->tx_buff_size )\r
+ {\r
+ this_uart->tx_buff_size = TX_COMPLETE;\r
+ /* disables TX interrupt */\r
+ this_uart->hw_reg_bit->IER_ETBEI = 0U;\r
+ }\r
+ break;\r
+ \r
+ case IIRF_RX_DATA: /* Received Data Available */\r
+ case IIRF_DATA_TIMEOUT:\r
+ if (this_uart->rx_handler != 0)\r
+ {\r
+ (*(this_uart->rx_handler))();\r
+ }\r
+ break;\r
+ \r
+ case IIRF_RX_LINE_STATUS:\r
+ break;\r
+ \r
+ default:\r
+ /* Disable other interrupts */\r
+ this_uart->hw_reg_bit->IER_ELSI = 0U;\r
+ this_uart->hw_reg_bit->IER_EDSSI = 0U;\r
+ break;\r
+ }\r
+}\r
+\r
+/***************************************************************************//**\r
+ * See mss_uart.h for details of how to use this function.\r
+ */\r
+void\r
+MSS_UART_set_rx_handler\r
+(\r
+ mss_uart_instance_t * this_uart,\r
+ mss_uart_rx_handler_t handler,\r
+ mss_uart_rx_trig_level_t trigger_level\r
+)\r
+{\r
+ ASSERT( (this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1) );\r
+ \r
+ this_uart->rx_handler = handler;\r
+ \r
+ /* Set the receive interrupt trigger level. */\r
+ this_uart->hw_reg->FCR = (this_uart->hw_reg->FCR & (uint8_t)(~((uint8_t)FCR_TRIG_LEVEL_MASK))) | (uint8_t)trigger_level;\r
+ \r
+ /* Enable receive interrupt. */\r
+ this_uart->hw_reg_bit->IER_ERBFI = 1U;\r
+ \r
+ /* Enable UART instance interrupt in Cortex-M3 NVIC. */\r
+ NVIC_EnableIRQ( this_uart->irqn );\r
+}\r
+\r
+/***************************************************************************//**\r
+ * See mss_uart.h for details of how to use this function.\r
+ */\r
+void\r
+MSS_UART_set_loopback\r
+(\r
+ mss_uart_instance_t * this_uart,\r
+ mss_uart_loopback_t loopback\r
+)\r
+{\r
+ ASSERT( (this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1) );\r
+ \r
+ if ( loopback == MSS_UART_LOOPBACK_OFF )\r
+ {\r
+ this_uart->hw_reg_bit->MCR_LOOP = 0U;\r
+ }\r
+ else\r
+ {\r
+ this_uart->hw_reg_bit->MCR_LOOP = 1U;\r
+ }\r
+}\r
+\r
+/***************************************************************************//**\r
+ * UART0 interrupt service routine.\r
+ * UART0_IRQHandler is included within the Cortex-M3 vector table as part of the\r
+ * Fusion 2 CMSIS.\r
+ */\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void UART0_IRQHandler( void )\r
+#else\r
+void UART0_IRQHandler( void )\r
+#endif\r
+{\r
+ MSS_UART_isr( &g_mss_uart0 );\r
+ NVIC_ClearPendingIRQ( UART0_IRQn );\r
+}\r
+\r
+/***************************************************************************//**\r
+ * UART1 interrupt service routine.\r
+ * UART2_IRQHandler is included within the Cortex-M3 vector table as part of the\r
+ * Fusion 2 CMSIS.\r
+ */\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void UART1_IRQHandler( void )\r
+#else\r
+void UART1_IRQHandler( void )\r
+#endif\r
+{\r
+ MSS_UART_isr( &g_mss_uart1 );\r
+ NVIC_ClearPendingIRQ( UART1_IRQn );\r
+}\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
--- /dev/null
+/*******************************************************************************\r
+ * (c) Copyright 2007 Actel Corporation. All rights reserved.\r
+ *\r
+ * SmartFusion Microcontroller Subsystem UART bare metal software driver public API.\r
+ *\r
+ * SVN $Revision: 1942 $\r
+ * SVN $Date: 2009-12-22 17:48:07 +0000 (Tue, 22 Dec 2009) $\r
+ */\r
+/*=========================================================================*//**\r
+ @mainpage SmartFusion MSS UART Bare Metal Driver.\r
+\r
+ @section intro_sec Introduction\r
+ The SmartFusion MicroController Subsystem (MSS) includes two UART peripherals\r
+ for serial communications.\r
+ This driver provides a set of functions for controlling the MSS UARTs as part\r
+ of a bare metal system where no operating system is available. These drivers\r
+ can be adapted for use as part of an operating system but the implementation\r
+ of the adaptation layer between this driver and the operating system's driver\r
+ model is outside the scope of this driver.\r
+ \r
+ @section hw_dependencies Hardware Flow Dependencies\r
+ The configuration of all features of the MSS UARTs is covered by this driver\r
+ with the exception of the SmartFusion IOMUX configuration. SmartFusion allows\r
+ multiple non-concurrent uses of some external pins through IOMUX configuration.\r
+ This feature allows optimization of external pin usage by assigning external\r
+ pins for use by either the microcontroller subsystem or the FPGA fabric. The\r
+ MSS UARTs serial signals are routed through IOMUXes to the SmartFusion device\r
+ external pins. These IOMUXes are configured automatically by the MSS\r
+ configurator tool in the hardware flow correctly when the MSS UARTs are enabled\r
+ in that tool. You must ensure that the MSS UARTs are enabled by the MSS\r
+ configurator tool in the hardware flow; otherwise the serial inputs and outputs\r
+ will not be connected to the chip's external pins. For more information on\r
+ IOMUX, refer to the IOMUX section of the SmartFusion Datasheet.\r
+ The base address, register addresses and interrupt number assignment for the MSS\r
+ UART blocks are defined as constants in the SmartFusion CMSIS-PAL You must ensure\r
+ that the SmartFusion CMSIS-PAL is either included in the software tool chain used\r
+ to build your project or is included in your project.\r
+\r
+ \r
+ @section theory_op Theory of Operation\r
+ The MSS UART driver uses the SmartFusion "Cortex Microcontroler Software\r
+ Interface Standard - Peripheral Access Layer" (CMSIS-PAL) to access hadware\r
+ registers. You must ensure that the SmartFusion CMSIS-PAL is either included\r
+ in the software toolchain used to build your project or is included in your\r
+ project. The most up to date SmartFusion CMSIS-PAL files can be obtained using\r
+ the Actel Firmware Catalog.\r
+ \r
+ The MSS UART driver functions are logically grouped into three groups:\r
+ - Initialization functions\r
+ - Polled transmit and receive functions\r
+ - Interrupt driven transmit and receive functions\r
+ \r
+ The MSS UART driver is initialized through a call to the UART_init() function.\r
+ This function takes the UART's configuration as parameters. The UART_init()\r
+ function must be called before any other UART driver functions can be called.\r
+ The first parameter of the UART_init() function is a pointer to one of two\r
+ global data structures used to store state information for each UART driver.\r
+ A pointer to these data structures is also used as first parameter to any of\r
+ the driver functions to identify which UART will be used by the called\r
+ function. The name of these two data structures are g_mss_uart0 and\r
+ g_mss_uart1. Therefore any call to a MSS UART function should be of the form\r
+ UART_function_name( &g_mss_uart0, ... ) or UART_function_name( &g_mss_uart1, ... ).\r
+ The two SmartFusion MSS UARTs can also be configured to loop back to each\r
+ other using the MSS_set_loopback() function for debugging purposes.\r
+ \r
+ Polled operations where the processor constantly poll the UART registers state\r
+ in order to control data transmit or data receive is performed using functions:\r
+ - MSS_UART_polled_tx()\r
+ - MSS_UART_get_rx()\r
+ \r
+ Interrupt driven operations where the processor sets up transmit or receive\r
+ then returns to performing some other operation until an interrupts occurs\r
+ indicating that its attention is required is performed using functions:\r
+ - MSS_UART_irq_tx()\r
+ - MSS_UART_tx_complete()\r
+ - MSS_UART_set_rx_handler()\r
+ - MSS_UART_get_rx()\r
+ Interrupt driven transmit is initiated by a call to MSS_UART_irq_tx() specifying\r
+ the block of data to transmit. The processor can then perform some other\r
+ operation and later inquire whether transmit has completed by calling the\r
+ MSS_UART_tx_complete() function.\r
+ Interrupt driven receive is performed by first registering a receive handler\r
+ function that will be called by the driver whenever receive data is available.\r
+ This receive handler function in turns calls the MSS_UART_get_rx() function to\r
+ actually read the received data.\r
+ \r
+ *//*=========================================================================*/\r
+#ifndef __MSS_UART_H_\r
+#define __MSS_UART_H_ 1\r
+\r
+#include "../../CMSIS/a2fxxxm3.h"\r
+#include <stddef.h>\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif \r
+\r
+/***************************************************************************//**\r
+ Baud rates.\r
+ The following definitions are used to specify standard baud rates as a\r
+ parameter to the MSS_UART_init() function.\r
+ */\r
+#define MSS_UART_110_BAUD 110\r
+#define MSS_UART_300_BAUD 300\r
+#define MSS_UART_1200_BAUD 1200\r
+#define MSS_UART_2400_BAUD 2400\r
+#define MSS_UART_4800_BAUD 4800\r
+#define MSS_UART_9600_BAUD 9600\r
+#define MSS_UART_19200_BAUD 19200\r
+#define MSS_UART_38400_BAUD 38400\r
+#define MSS_UART_57600_BAUD 57600\r
+#define MSS_UART_115200_BAUD 115200\r
+#define MSS_UART_230400_BAUD 230400\r
+#define MSS_UART_460800_BAUD 460800\r
+#define MSS_UART_921600_BAUD 921600\r
+\r
+/***************************************************************************//**\r
+ Data bits length values.\r
+ \r
+ The following defines are used to build the value of the MSS_UART_init()\r
+ function line_config parameter.\r
+ */\r
+#define MSS_UART_DATA_5_BITS 0x00\r
+#define MSS_UART_DATA_6_BITS 0x01\r
+#define MSS_UART_DATA_7_BITS 0x02\r
+#define MSS_UART_DATA_8_BITS 0x03\r
+\r
+/***************************************************************************//**\r
+ Parity values\r
+ The following defines are used to build the value of the MSS_UART_init()\r
+ function line_config parameter.\r
+ */\r
+#define MSS_UART_NO_PARITY 0x00\r
+#define MSS_UART_ODD_PARITY 0x08\r
+#define MSS_UART_EVEN_PARITY 0x18\r
+#define MSS_UART_STICK_PARITY_0 0x38\r
+#define MSS_UART_STICK_PARITY_1 0x28\r
+\r
+/***************************************************************************//**\r
+ Stop bit values\r
+ The following defines are used to build the value of the MSS_UART_init()\r
+ function line_config parameter.\r
+ */\r
+#define MSS_UART_ONE_STOP_BIT 0x00\r
+#define MSS_UART_ONEHALF_STOP_BIT 0x04\r
+#define MSS_UART_TWO_STOP_BITS 0x04\r
+\r
+/***************************************************************************//**\r
+ FIFO trigger sizes\r
+ This enumeration specifies the number of bytes that must be received before a\r
+ receive interrupt is generated. This enumeration provides the allowed values for\r
+ the MSS_UART_set_rx_handler() function trigger_level parameter.\r
+ */\r
+typedef enum __mss_uart_rx_trig_level_t {\r
+ MSS_UART_FIFO_SINGLE_BYTE = 0x00,\r
+ MSS_UART_FIFO_FOUR_BYTES = 0x40,\r
+ MSS_UART_FIFO_EIGHT_BYTES = 0x80,\r
+ MSS_UART_FIFO_FOURTEEN_BYTES = 0xC0\r
+} mss_uart_rx_trig_level_t;\r
+\r
+/***************************************************************************//**\r
+ Loopback.\r
+ This enumeration is used as parameter to function MSS_UART_set_loopback(). It\r
+ specifies the loopback configuration of the UARTs. Using MSS_UART_LOOPBACK_ON\r
+ as parameter to function MSS_UART_set_loopback() will set up the UART to locally\r
+ loopback its Tx and Rx lines.\r
+ */\r
+typedef enum __mss_uart_loopback_t {\r
+ MSS_UART_LOOPBACK_OFF = 0,\r
+ MSS_UART_LOOPBACK_ON = 1\r
+} mss_uart_loopback_t;\r
+\r
+/***************************************************************************//**\r
+ Receive handler prototype.\r
+ This typedef specifies the prototype of functions that can be registered with\r
+ this driver as receive handler functions.\r
+ */\r
+typedef void (*mss_uart_rx_handler_t)(void);\r
+\r
+/***************************************************************************//**\r
+ mss_uart_instance_t.\r
+ \r
+ There is one instance of this structure for each instance of the Microcontroller\r
+ Subsystem's UARTs. Instances of this structure are used to identify a specific\r
+ UART. A pointer to an instance of the mss_uart_instance_t structure is passed\r
+ as the first parameter to MSS UART driver functions to identify which UART\r
+ should perform the requested operation.\r
+ */\r
+typedef struct {\r
+ /* CMSIS related defines identifying the UART hardware. */\r
+ UART_TypeDef * hw_reg; /*!< Pointer to UART registers. */\r
+ UART_BitBand_TypeDef * hw_reg_bit; /*!< Pointer to UART registers bit band area. */\r
+ IRQn_Type irqn; /*!< UART's Cortex-M3 NVIC interrupt number. */\r
+ \r
+ /* transmit related info (used with interrupt driven trnasmit): */\r
+ const uint8_t * tx_buffer; /*!< Pointer to transmit buffer. */\r
+ uint32_t tx_buff_size; /*!< Transmit buffer size. */\r
+ uint32_t tx_idx; /*!< Index within trnamit buffer of next byte to transmit.*/\r
+ \r
+ /* receive interrupt handler:*/\r
+ mss_uart_rx_handler_t rx_handler; /*!< Pointer to user registered received handler. */\r
+} mss_uart_instance_t;\r
+\r
+/***************************************************************************//**\r
+ This instance of mss_uart_instance_t holds all data related to the operations\r
+ performed by UART0. A pointer to g_mss_uart0 is passed as the first parameter\r
+ to MSS UART driver functions to indicate that UART0 should perform the requested\r
+ operation.\r
+ */\r
+extern mss_uart_instance_t g_mss_uart0;\r
+\r
+/***************************************************************************//**\r
+ This instance of mss_uart_instance_t holds all data related to the operations\r
+ performed by UART1. A pointer to g_mss_uart1 is passed as the first parameter\r
+ to MSS UART driver functions to indicate that UART1 should perform the requested\r
+ operation.\r
+ */\r
+extern mss_uart_instance_t g_mss_uart1;\r
+\r
+/***************************************************************************//**\r
+ The MSS_UART_init() function initializes and configures one of the SmartFusion\r
+ MSS UARTs with the configuration passed as a parameter. The configuration\r
+ parameters are the baud_rate which is used to generate the baud value and the\r
+ line_config which is used to specify the line configuration (bit length, stop\r
+ bits and parity).\r
+ \r
+ Example:\r
+ @code\r
+ #include "mss_uart.h"\r
+ \r
+ int main(void)\r
+ {\r
+ MSS_UART_init\r
+ (\r
+ &g_mss_uart0,\r
+ MSS_UART_57600_BAUD,\r
+ MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT\r
+ );\r
+ return(0);\r
+ }\r
+ @endcode\r
+ \r
+ @param this_uart\r
+ The this_uart parameter is a pointer to an mss_uart_instance_t structure\r
+ identifying the MSS UART hardware block to be initialized. There are two\r
+ such data structures, g_mss_uart0 and g_mss_uart1, associated with MSS UART0\r
+ and MSS UART1 respectively. This parameter must point to either the\r
+ g_mss_uart0 or g_mss_uart1 global data structure defined within the UART\r
+ driver.\r
+ \r
+ \r
+ @param baud_rate\r
+ The baud_rate parameter specifies the baud rate. It can be specified for\r
+ common baud rates' using the following defines:\r
+ - MSS_UART_110_BAUD\r
+ - MSS_UART_300_BAUD\r
+ - MSS_UART_1200_BAUD\r
+ - MSS_UART_2400_BAUD\r
+ - MSS_UART_4800_BAUD\r
+ - MSS_UART_9600_BAUD\r
+ - MSS_UART_19200_BAUD\r
+ - MSS_UART_38400_BAUD\r
+ - MSS_UART_57600_BAUD\r
+ - MSS_UART_115200_BAUD\r
+ - MSS_UART_230400_BAUD\r
+ - MSS_UART_460800_BAUD\r
+ - MSS_UART_921600_BAUD \r
+ Alternatively, any non standard baud rate can be specified by simply passing\r
+ the actual required baud rate as value for this parameter.\r
+ \r
+ @param line_config\r
+ The line_config parameter is the line configuration specifying the bit length,\r
+ number of stop bits and parity settings. This is a logical OR of one of the\r
+ following to specify the transmit/receive data bit length: \r
+ - MSS_UART_DATA_5_BITS\r
+ - MSS_UART_DATA_6_BITS,\r
+ - MSS_UART_DATA_7_BITS\r
+ - MSS_UART_DATA_8_BITS\r
+ with one of the following to specify the parity setting:\r
+ - MSS_UART_NO_PARITY\r
+ - MSS_UART_EVEN_PARITY\r
+ - MSS_UART_ODD_PARITY\r
+ - MSS_UART_STICK_PARITY_0\r
+ - MSS_UART_STICK_PARITY_1\r
+ with one of the following to specify the number of stop bits:\r
+ - MSS_UART_ONE_STOP_BIT\r
+ - MSS_UART_ONEHALF_STOP_BIT\r
+ - MSS_UART_TWO_STOP_BITS\r
+ \r
+ @return\r
+ This function does not return a value.\r
+ */\r
+void\r
+MSS_UART_init\r
+(\r
+ mss_uart_instance_t* this_uart,\r
+ uint32_t baud_rate,\r
+ uint8_t line_config\r
+);\r
+\r
+/***************************************************************************//**\r
+ The function MSS_UART_polled_tx() is used to transmit data. It transfers the\r
+ contents of the transmitter data buffer, passed as a function parameter, into\r
+ the UART's hardware transmitter FIFO. It returns when the full content of the\r
+ transmit data buffer has been transferred to the UART's transmit FIFO. \r
+ \r
+ @param this_uart\r
+ The this_uart parameter is a pointer to an mss_uart_instance_t structure\r
+ identifying the MSS UART hardware block that will perform the requested\r
+ function. There are two such data structures, g_mss_uart0 and g_mss_uart1,\r
+ associated with MSS UART0 and MSS UART1. This parameter must point to either\r
+ the g_mss_uart0 or g_mss_uart1 global data structure defined within the UART\r
+ driver.\r
+ \r
+ @param pbuff\r
+ The pbuff parameter is a pointer to a buffer containing the data to be\r
+ transmitted.\r
+ \r
+ @param tx_size\r
+ The tx_size parameter specifies the size, in bytes, of the data to be\r
+ transmitted.\r
+ \r
+ @return This function does not return a value.\r
+ */\r
+void \r
+MSS_UART_polled_tx\r
+( \r
+ mss_uart_instance_t * this_uart, \r
+ const uint8_t * pbuff,\r
+ uint32_t tx_size\r
+);\r
+\r
+/***************************************************************************//**\r
+ The function MSS_UART_polled_tx_string() is used to transmit a zero-terminated\r
+ string. It transfers the text found starting at the address pointed to by\r
+ p_sz_string into the UART's hardware transmitter FIFO. It returns when the\r
+ complete string has been transferred to the UART's transmit FIFO. \r
+ \r
+ @param this_uart\r
+ The this_uart parameter is a pointer to an mss_uart_instance_t structure\r
+ identifying the MSS UART hardware block that will perform the requested\r
+ function. There are two such data structures, g_mss_uart0 and g_mss_uart1,\r
+ associated with MSS UART0 and MSS UART1. This parameter must point to either\r
+ the g_mss_uart0 or g_mss_uart1 global data structure defined within the UART\r
+ driver.\r
+ \r
+ @param p_sz_string\r
+ The p_sz_string parameter is a pointer to a buffer containing the\r
+ zero-terminated string to be transmitted.\r
+ \r
+ @return This function does not return a value.\r
+ */\r
+void \r
+MSS_UART_polled_tx_string\r
+( \r
+ mss_uart_instance_t * this_uart, \r
+ const uint8_t * p_sz_string\r
+);\r
+\r
+\r
+/***************************************************************************//**\r
+ The function MSS_UART_irq_tx() is used to initiate interrupt driven transmit. It\r
+ returns immediately after making a note of the transmit buffer location and\r
+ enabling transmit interrupts both at the UART and Cortex-M3 NVIC level.\r
+ This function takes a pointer to a memory buffer containing the data to\r
+ transmit as parameter. The memory buffer specified through this pointer\r
+ should remain allocated and contain the data to transmit until the transmit\r
+ completion has been detected through calls to function MSS_UART_tx_complete().\r
+ NOTE: The MSS_UART_irq_tx() function also enables the Transmitter Holding\r
+ Register Empty (THRE) interrupt and the UART instance interrupt in the\r
+ Cortex-M3 NVIC as part of its implementation.\r
+ \r
+ Example:\r
+ @code\r
+ #include "mss_uart.h"\r
+ \r
+ int main(void)\r
+ {\r
+ uint8_t tx_buff[10] = "abcdefghi";\r
+ MSS_UART_init( &g_mss_uart0, MSS_UART_57600_BAUD, MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT );\r
+ MSS_UART_irq_tx( &g_mss_uart0, tx_buff, sizeof(tx_buff));\r
+ while ( 0 == MSS_UART_tx_complete( &g_mss_uart0 ) )\r
+ {\r
+ ;\r
+ }\r
+ return(0);\r
+ }\r
+ @endcode\r
+ \r
+ @param this_uart\r
+ The this_uart parameter is a pointer to an mss_uart_instance_t structure\r
+ identifying the MSS UART hardware block that will perform the requested\r
+ function. There are two such data structures, g_mss_uart0 and g_mss_uart1,\r
+ associated with MSS UART0 and MSS UART1. This parameter must point to either\r
+ the g_mss_uart0 or g_mss_uart1 global data structure defined within the UART\r
+ driver.\r
+ \r
+ @param pbuff\r
+ The pbuff parameter is a pointer to a buffer containing the data to be\r
+ transmitted.\r
+ \r
+ @param tx_size\r
+ The tx_size parameter specifies the size, in bytes, of the data to be\r
+ transmitted.\r
+ \r
+ @return\r
+ This function does not return a value.\r
+ */\r
+void \r
+MSS_UART_irq_tx\r
+( \r
+ mss_uart_instance_t * this_uart, \r
+ const uint8_t * pbuff,\r
+ uint32_t tx_size\r
+);\r
+\r
+/***************************************************************************//**\r
+ The MSS_UART_tx_complete() function is used to find out if interrupt driven\r
+ transmit previously initiated through a call to MSS_UART_irq_tx() is complete.\r
+ This is typically used to find out when it is safe to reuse or release the\r
+ memory buffer holding transmit data.\r
+ \r
+ @param this_uart\r
+ The this_uart parameter is a pointer to an mss_uart_instance_t structure\r
+ identifying the MSS UART hardware block that will perform the requested\r
+ function. There are two such data structures, g_mss_uart0 and g_mss_uart1,\r
+ associated with MSS UART0 and MSS UART1. This parameter must point to either\r
+ the g_mss_uart0 or g_mss_uart1 global data structure defined within the UART\r
+ driver.\r
+ \r
+ @return\r
+ This function return a non-zero value if transmit has completed, otherwise\r
+ it returns zero.\r
+ \r
+ Example:\r
+ See the MSS_UART_irq_tx() function for an example that uses the\r
+ MSS_UART_tx_complete() function.\r
+ */\r
+int8_t\r
+MSS_UART_tx_complete\r
+(\r
+ mss_uart_instance_t * this_uart\r
+);\r
+\r
+/***************************************************************************//**\r
+ The MSS_UART_get_rx() function is used to read the content of a UART's receive\r
+ FIFO. It can be used in polled mode where it is called at regular interval\r
+ to find out if any data has been received or in interrupt driven mode where\r
+ it is called as part of a receive handler called by the driver as a result of\r
+ data being received. This function is non-blocking and will return 0\r
+ immediately if no data has been received.\r
+ NOTE: In interrupt driven mode you should call the MSS_UART_get_rx() function\r
+ as part of the receive handler function that you register with the MSS UART\r
+ driver through a call to MSS_UART_set_rx_handler().\r
+ \r
+ @param this_uart\r
+ The this_uart parameter is a pointer to an mss_uart_instance_t structure\r
+ identifying the MSS UART hardware block that will perform the requested\r
+ function. There are two such data structures, g_mss_uart0 and g_mss_uart1,\r
+ associated with MSS UART0 and MSS UART1. This parameter must point to either\r
+ the g_mss_uart0 or g_mss_uart1 global data structure defined within the UART\r
+ driver.\r
+ \r
+ @param rx_buff\r
+ The rx_buff parameter is a pointer to a buffer where the received data will\r
+ be copied.\r
+ \r
+ @param buff_size\r
+ The buff_size parameter specifies the size of the receive buffer in bytes.\r
+ \r
+ @return\r
+ This function return the number of bytes that were copied into the rx_buff\r
+ buffer. It returns 0 if no data has been received.\r
+ \r
+ Polled mode example:\r
+ @code\r
+ int main( void )\r
+ {\r
+ uint8_t rx_buff[RX_BUFF_SIZE];\r
+ uint32_t rx_idx = 0;\r
+ \r
+ MSS_UART_init( &g_mss_uart0, MSS_UART_57600_BAUD, MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT );\r
+ \r
+ while( 1 )\r
+ {\r
+ rx_size = MSS_UART_get_rx( &g_mss_uart0, rx_buff, sizeof(rx_buff) );\r
+ if (rx_size > 0)\r
+ {\r
+ process_rx_data( rx_buff, rx_size );\r
+ }\r
+ task_a();\r
+ task_b();\r
+ }\r
+ return 0;\r
+ }\r
+ @endcode\r
+ \r
+ Interrupt driven example:\r
+ @code\r
+ int main( void )\r
+ {\r
+ MSS_UART_init( &g_mss_uart1, MSS_UART_57600_BAUD, MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT );\r
+ MSS_UART_set_rx_handler( &g_mss_uart1, uart1_rx_handler, MSS_UART_FIFO_SINGLE_BYTE );\r
+ \r
+ while( 1 )\r
+ {\r
+ task_a();\r
+ task_b();\r
+ }\r
+ return 0;\r
+ }\r
+ \r
+ void uart1_rx_handler( void )\r
+ {\r
+ uint8_t rx_buff[RX_BUFF_SIZE];\r
+ uint32_t rx_idx = 0;\r
+ rx_size = MSS_UART_get_rx( &g_mss_uart1, rx_buff, sizeof(rx_buff) );\r
+ process_rx_data( rx_buff, rx_size );\r
+ }\r
+ @endcode\r
+ */\r
+size_t\r
+MSS_UART_get_rx\r
+(\r
+ mss_uart_instance_t * this_uart,\r
+ uint8_t * rx_buff,\r
+ size_t buff_size\r
+);\r
+\r
+/***************************************************************************//**\r
+ The MSS_UART_set_rx_handler() function is used to register a receive handler\r
+ function which will be called by the driver when a UART Received Data Available\r
+ (RDA) interrupt occurs. You must create and register the handler function to\r
+ suit your application. The MSS_UART_set_rx_handler() function also enables the UART\r
+ Received Data Available interrupt and the UART instance interrupt in the\r
+ Cortex-M3 NVIC as part of its implementation.\r
+ \r
+ @param this_uart\r
+ The this_uart parameter is a pointer to an mss_uart_instance_t structure\r
+ identifying the MSS UART hardware block that will perform the requested\r
+ function. There are two such data structures, g_mss_uart0 and g_mss_uart1,\r
+ associated with MSS UART0 and MSS UART1. This parameter must point to either\r
+ the g_mss_uart0 or g_mss_uart1 global data structure defined within the UART\r
+ driver.\r
+ \r
+ @param handler\r
+ The handler parameter is a pointer to a receive handler function provided\r
+ by your application which will be called as a result of a UART Received\r
+ Data Available interrupt.\r
+ \r
+ @param trigger_level\r
+ The trigger_level parameter is the receive FIFO trigger level. This specifies\r
+ the number of bytes that must be received before the UART triggers a Received\r
+ Data Available interrupt. \r
+ \r
+ @return\r
+ This function does not return a value.\r
+ \r
+ Example:\r
+ @code\r
+ #include "mss_uart.h"\r
+ \r
+ #define RX_BUFF_SIZE 64\r
+ \r
+ uint8_t g_rx_buff[RX_BUFF_SIZE];\r
+ \r
+ void uart0_rx_handler( void )\r
+ {\r
+ MSS_UART_get_rx( &g_mss_uart, &g_rx_buff[g_rx_idx], sizeof(g_rx_buff) );\r
+ }\r
+ \r
+ int main(void)\r
+ {\r
+ MSS_UART_init( &g_mss_uart0, MSS_UART_57600_BAUD, MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT );\r
+ MSS_UART_set_rx_handler( &g_mss_uart0, uart0_rx_handler, MSS_UART_FIFO_SINGLE_BYTE );\r
+ \r
+ while ( 1 )\r
+ {\r
+ ;\r
+ }\r
+ return(0);\r
+ }\r
+ @endcode\r
+ */\r
+void\r
+MSS_UART_set_rx_handler\r
+(\r
+ mss_uart_instance_t * this_uart,\r
+ mss_uart_rx_handler_t handler,\r
+ mss_uart_rx_trig_level_t trigger_level\r
+);\r
+\r
+/***************************************************************************//**\r
+ The MSS_UART_set_loopback() function is used to locally loopback the Tx and Rx\r
+ lines of a UART.\r
+ This is not to be confused with the loopback of UART0 to UART1 which can be\r
+ achieved through the microcontroller subsystem's system registers\r
+ \r
+ @param this_uart\r
+ The this_uart parameter is a pointer to an mss_uart_instance_t structure\r
+ identifying the MSS UART hardware block that will perform the requested\r
+ function. There are two such data structures, g_mss_uart0 and g_mss_uart1,\r
+ associated with MSS UART0 and MSS UART1. This parameter must point to either\r
+ the g_mss_uart0 or g_mss_uart1 global data structure defined within the UART\r
+ driver.\r
+ \r
+ @param loopback\r
+ The loopback parameter indicates whether or not the UART's transmit and receive lines\r
+ should be looped back. Allowed values are:\r
+ - MSS_UART_LOOPBACK_ON\r
+ - MSS_UART_LOOPBACK_OFF\r
+ @return\r
+ This function does not return a value.\r
+ */\r
+void\r
+MSS_UART_set_loopback\r
+(\r
+ mss_uart_instance_t * this_uart,\r
+ mss_uart_loopback_t loopback\r
+);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __MSS_UART_H_ */\r
--- /dev/null
+/*******************************************************************************\r
+ * (c) Copyright 2009 Actel Corporation. All rights reserved.\r
+ * \r
+ * SmartFusion Microcontroller Subsystem (MSS) Watchdog bare metal software\r
+ * driver.\r
+ *\r
+ * SVN $Revision: 1888 $\r
+ * SVN $Date: 2009-12-18 10:58:42 +0000 (Fri, 18 Dec 2009) $\r
+ */\r
+/*=========================================================================*//**\r
+ @section intro_sec Introduction\r
+ The SmartFusion microcontroller subsystem (MSS) includes a watchdog timer used\r
+ to detect system lockups.\r
+ This driver provides a set of functions for controlling the MSS watchdog as\r
+ part of a bare metal system where no operating system is available. These\r
+ drivers can be adapted for use as part of an operating system but the\r
+ implementation of the adaptation layer between this driver and the operating\r
+ system's driver model is outside the scope of this driver.\r
+ \r
+ @section hw_dependencies Hardware Flow Dependencies\r
+ The configuration of all features of the MSS watchdog is covered by this\r
+ driver. There are no dependencies on the hardware flow for configuring the\r
+ SmartFusion MSS watchdog timer.\r
+ \r
+ @section theory_op Theory of Operation\r
+ The watchdog driver uses the SmartFusion "Cortex Microcontroler Software\r
+ Interface Standard - Peripheral Access Layer" (CMSIS-PAL) to access hadware\r
+ registers. You must ensure that the SmartFusion CMSIS-PAL is either included\r
+ in the software toolchain used to build your project or is included in your\r
+ project. The most up-to-date SmartFusion CMSIS-PAL files can be obtained using\r
+ the Actel Firmware Catalog.\r
+ \r
+ The watchdog driver functions are grouped into the following categories:\r
+ - Initialization and cnfiguration\r
+ - Reading the watchdog timer current value and status\r
+ - Refreshing the watchdog timer value\r
+ - Time-out and wake-up interrupts control\r
+ \r
+ The watchdog driver is initialized and configured through a call to the\r
+ MSS_WD_init() function. The parameters passed to MSS_WD_init() function\r
+ specify the watchdog timer configuration. The configuration parameters include\r
+ the value that will be reloaded into the watchdog timer down counter every\r
+ time the watchdog is refreshed. Also included as part of the configuration\r
+ parameters is the optional allowed refresh window. The allowed refresh window\r
+ specifies the maximum allowed current value of the watchdog timer at the time\r
+ of the watchdog is relaoded. Attempting to reload the watchdog timer when its\r
+ value is larger than the allowed refresh window will cause a reset or\r
+ interrupt depending on the watchdog configuration. The allowed refresh window\r
+ can be disabled by specifying an allowed refesh window equal or higher than\r
+ the watchdog reload value.\r
+ The MSS_WD_init() function must be called before any other watchdog driver\r
+ functions can be called with the exception of the MSS_WD_disable() function.\r
+ \r
+ The watchdog timer can be disabled using the MSS_WD_disable() function. Once\r
+ disabled, the watchdog timer can only be reenabled by a power-on reset.\r
+ \r
+ The watchdog timer current value can be read using the MSS_WD_current_value()\r
+ function. The watchdog status can be read using the MSS_WD_status() function.\r
+ These functions are typically required when using the watchdog configured with\r
+ an allowed refresh window to check if a watchdog reload is currently allowed.\r
+ \r
+ The watchdog timer value is reloaded using the MSS_WD_reload() function. The\r
+ value reloaded into the watchdog timer down counter is the value specified as\r
+ parameter to the MSS_WD_init() function.\r
+ \r
+ The watchdog timer can generate interrupts instead of resetting the system\r
+ when its down-counter timer expires. These time-out interrupts are controlled\r
+ using the following functions:\r
+ - MSS_WD_enable_timeout_irq\r
+ - MSS_WD_disable_timeout_irq\r
+ - MSS_WD_clear_timeout_irq\r
+ \r
+ The watchdog timer is external to the Cortex-M3 processor core and operates\r
+ even when the Cortex-M3 is in sleep mode. A wakeup interrupt can be generated\r
+ by the watchdog timer to wakeup the Cortext-M3 when the watchdog timer value\r
+ reaches the allowed refresh window while the Cortex-M3 is in sleep mode. The\r
+ watchdog driver provides the following functions to control wakeup interrupts:\r
+ - MSS_WD_enable_wakeup_irq\r
+ - MSS_WD_disable_wakeup_irq\r
+ - MSS_WD_clear_wakeup_irq\r
+ \r
+ *//*=========================================================================*/\r
+\r
+#ifndef MSS_WATCHDOG_H_\r
+#define MSS_WATCHDOG_H_\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif \r
+\r
+#include "../../CMSIS/a2fxxxm3.h"\r
+\r
+/***************************************************************************//**\r
+ * The MSS_WDOG_RESET_ON_TIMEOUT_MODE macro is one of the possible values for the\r
+ * mode parameter of the WD_init() function. It is used to specify that a reset\r
+ * should occur when the watchdog down counter times out.\r
+ */\r
+#define MSS_WDOG_RESET_ON_TIMEOUT_MODE (uint32_t)0x00000000U\r
+\r
+/***************************************************************************//**\r
+ * The MSS_WDOG_INTERRUPT_ON_TIMEOUT_MODE macro is one of the possible values for\r
+ * the mode parameter of function the WD_init() function. It is used to specify\r
+ * that a time out interrupt should occur when the watchdog down counter expires.\r
+ */\r
+#define MSS_WDOG_INTERRUPT_ON_TIMEOUT_MODE (uint32_t)0x00000004U\r
+\r
+/***************************************************************************//**\r
+ * The MSS_WDOG_NO_WINDOW macro can be used as the value for the reload_window\r
+ * parameter of the WD_init() function. It is used to specify that no forbidden\r
+ * window will exist for the reload of the watchdog down counter.\r
+ */\r
+#define MSS_WDOG_NO_WINDOW (uint32_t)0xFFFFFFFFU\r
+\r
+/***************************************************************************//**\r
+ * The MSS_WDOG_CTRL_MODE_BIT_MASK macro is a bit mask specifying the bit used to\r
+ * set the watchdog's operating mode within the wathcdog's WDOGCONTROL register.\r
+ */\r
+#define MSS_WDOG_CTRL_MODE_BIT_MASK (uint32_t)0x00000004U\r
+\r
+/***************************************************************************//**\r
+ * The MSS_WDOG_TIMEOUT_IRQ_ENABLE_BIT_MASK macro is a bit mask specifying the bit\r
+ * used to enable the time out interrupt within the watchdog's WDOGCONTROL\r
+ * register.\r
+ */\r
+#define MSS_WDOG_TIMEOUT_IRQ_ENABLE_BIT_MASK (uint32_t)0x00000001U\r
+\r
+/***************************************************************************//**\r
+ The MSS_WDOG_WAKEUP_IRQ_ENABLE_BIT_MASK macro is a bit mask specifying the bit\r
+ used to enable the wake up interrupt within the watchdog's WDOGCONTROL\r
+ register.\r
+ */\r
+#define MSS_WDOG_WAKEUP_IRQ_ENABLE_BIT_MASK (uint32_t)0x00000002U\r
+\r
+/***************************************************************************//**\r
+ The MSS_WDOG_TIMEOUT_IRQ_CLEAR_BIT_MASK macro is a bit mask specifying the bit\r
+ used to clear the time out interrupt within the watchdog's WDOGRIS register.\r
+ */\r
+#define MSS_WDOG_TIMEOUT_IRQ_CLEAR_BIT_MASK (uint32_t)0x00000001U\r
+\r
+/***************************************************************************//**\r
+ The MSS_WDOG_WAKEUP_IRQ_CLEAR_BIT_MASK macro is a bit mask specifying the bit\r
+ used to clear the wake up interrupt within the watchdog's WDOGRIS register.\r
+ */\r
+#define MSS_WDOG_WAKEUP_IRQ_CLEAR_BIT_MASK (uint32_t)0x00000002U\r
+\r
+/***************************************************************************//**\r
+ The MSS_WDOG_REFRESH_KEY macro holds the magic value which will cause a reload\r
+ of the watchdog's down counter when written to the watchdog's WDOGREFRESH\r
+ register.\r
+ */\r
+#define MSS_WDOG_REFRESH_KEY (uint32_t)0xAC15DE42U\r
+\r
+/***************************************************************************//**\r
+ The MSS_WDOG_DISABLE_KEY macro holds the magic value which will disable the\r
+ watchdog if written to the watchdog's WDOGENABLE register.\r
+ */\r
+#define MSS_WDOG_DISABLE_KEY (uint32_t)0x4C6E55FAU\r
+\r
+/***************************************************************************//**\r
+ The MSS_WD_init() function initializes and configures the watchdog timer.\r
+ \r
+ @param load_value\r
+ The load_value parameter specifies the value that will be loaded into the\r
+ watchdog's down counter when the reload command is issued through a call to\r
+ MSS_WD_reload().\r
+ \r
+ @param reload_window\r
+ The reload_window parameter specifies the time window during which a reload\r
+ of the watchdog counter is allowed. A reload of the watchdog counter should\r
+ only be performed when the watchdog counter value is below the value of the\r
+ reload_window. Reloading the watchdog down counter value before it has\r
+ reached the reload_window will result in an interrupt or reset depending on\r
+ the watchdog's mode.\r
+ The reload window can be disabled by using WDOG_NO_WINDOW for this parameter.\r
+ \r
+ @param mode\r
+ The mode parameter specifies the watchdog's operating mode. It can be either\r
+ MSS_WDOG_RESET_ON_TIMEOUT_MODE or MSS_WDOG_INTERRUPT_ON_TIMEOUT_MODE.\r
+ MSS_WDOG_RESET_ON_TIMEOUT_MODE: a reset will occur if the watchdog timer\r
+ expires.\r
+ MSS_WDOG_INTERRUPT_ON_TIMEOUT_MODE: an NMI interrupt will occur if the\r
+ watchdog timer expires.\r
+ \r
+ @return\r
+ This function does not return a value.\r
+ */\r
+static __INLINE void MSS_WD_init\r
+(\r
+ uint32_t load_value,\r
+ uint32_t reload_window,\r
+ uint32_t mode\r
+)\r
+{\r
+ /* Disable interrupts. */\r
+ WATCHDOG->WDOGCONTROL &= ~(MSS_WDOG_TIMEOUT_IRQ_ENABLE_BIT_MASK | MSS_WDOG_WAKEUP_IRQ_CLEAR_BIT_MASK);\r
+ \r
+ /* Clear any existing interrupts. */\r
+ WATCHDOG->WDOGRIS = MSS_WDOG_TIMEOUT_IRQ_CLEAR_BIT_MASK | MSS_WDOG_WAKEUP_IRQ_CLEAR_BIT_MASK;\r
+ \r
+ /* Configure watchdog with new configuration passed as parameter. */\r
+ WATCHDOG->WDOGMVRP = MSS_WDOG_NO_WINDOW;\r
+ WATCHDOG->WDOGLOAD = load_value;\r
+ WATCHDOG->WDOGCONTROL = (WATCHDOG->WDOGCONTROL & ~MSS_WDOG_CTRL_MODE_BIT_MASK) | (mode & MSS_WDOG_CTRL_MODE_BIT_MASK);\r
+ \r
+ /* Reload watchdog with new load value. */\r
+ WATCHDOG->WDOGREFRESH = MSS_WDOG_REFRESH_KEY;\r
+ \r
+ /* Set allowed window. */\r
+ WATCHDOG->WDOGMVRP = reload_window;\r
+}\r
+\r
+/***************************************************************************//**\r
+ The MSS_WD_reload() function causes the watchdog to reload its down counter timer\r
+ with the load value configured through the call to WD_init(). This function \r
+ must be called regularly to avoid a system reset.\r
+ \r
+ @return\r
+ This function does not return a value.\r
+ */\r
+static __INLINE void MSS_WD_reload( void )\r
+{\r
+ WATCHDOG->WDOGREFRESH = MSS_WDOG_REFRESH_KEY;\r
+}\r
+\r
+/***************************************************************************//**\r
+ The MSS_WD_disable() function disables the watchdog.\r
+ Please note that the watchdog can only be reenabled as a result of a power-on\r
+ reset.\r
+ \r
+ @return\r
+ This function does not return a value.\r
+ */\r
+static __INLINE void MSS_WD_disable( void )\r
+{\r
+ WATCHDOG->WDOGENABLE = MSS_WDOG_DISABLE_KEY;\r
+}\r
+\r
+/***************************************************************************//**\r
+ The MSS_WD_current_value() function returns the current value of the watchdog's\r
+ down counter.\r
+ \r
+ @return\r
+ This function returns the current value of the watchdog down counter.\r
+ */\r
+static __INLINE uint32_t MSS_WD_current_value( void )\r
+{\r
+ return WATCHDOG->WDOGVALUE;\r
+}\r
+\r
+/***************************************************************************//**\r
+ The MSS_WD_status() function returns the status of the watchdog.\r
+ \r
+ @return \r
+ The MSS_WD_status() function returns the status of the watchdog. A value of\r
+ 0 indicates that watchdog counter has reached the forbidden window and that\r
+ a reload should not be done. A value of 1 indicates that the watchdog counter\r
+ is within the permitted window and that a reload is allowed.\r
+ */\r
+static __INLINE uint32_t MSS_WD_status( void )\r
+{\r
+ return WATCHDOG->WDOGSTATUS;\r
+}\r
+\r
+/***************************************************************************//**\r
+ The MSS_WD_enable_timeout_irq() function enables the watchdog\92s time out\r
+ interrupt which is connected to the Cortex-M3 NMI interrupt.\r
+ The NMI_Handler() function will be called when a watchdog time out occurs. You\r
+ must provide the implementation of the NMI_Handler() function to suit your\r
+ application.\r
+ \r
+ @return\r
+ This function does not return a value.\r
+ \r
+ Example:\r
+ @code\r
+ #include "mss_watchdog.h"\r
+ int main( void )\r
+ {\r
+ MSS_WD_init( 0x10000000, MSS_WDOG_NO_WINDOW, MSS_WDOG_INTERRUPT_ON_TIMEOUT_MODE );\r
+ MSS_WD_enable_timeout_irq();\r
+ for (;;)\r
+ {\r
+ main_task();\r
+ }\r
+ }\r
+ \r
+ void NMI_Handler( void )\r
+ {\r
+ process_timeout();\r
+ MSS_WD_clear_timeout_irq();\r
+ }\r
+ @endcode\r
+ */\r
+static __INLINE void MSS_WD_enable_timeout_irq( void )\r
+{\r
+ WATCHDOG->WDOGCONTROL |= MSS_WDOG_TIMEOUT_IRQ_ENABLE_BIT_MASK;\r
+}\r
+\r
+/***************************************************************************//**\r
+ The WD_disable_timeout_irq() function disables the generation of the NMI\r
+ interrupt when the watchdog times out.\r
+ \r
+ @return\r
+ This function does not return a value.\r
+ */\r
+static __INLINE void MSS_WD_disable_timeout_irq( void )\r
+{\r
+ WATCHDOG->WDOGCONTROL &= ~MSS_WDOG_TIMEOUT_IRQ_ENABLE_BIT_MASK;\r
+}\r
+\r
+/***************************************************************************//**\r
+ The MSS_WD_enable_wakeup_irq() function enables the SmartFusion wakeup\r
+ interrupt. The WdogWakeup_IRQHandler() function will be called when a wake up\r
+ interrupt occurs. You must provide the implementation of the WdogWakeup_IRQHandler()\r
+ function to suit your application.\r
+ \r
+ @return\r
+ This function does not return a value.\r
+ \r
+ Example:\r
+ @code\r
+ #include "mss_watchdog.h"\r
+ int main( void )\r
+ {\r
+ MSS_WD_init( 0x10000000, MSS_WDOG_NO_WINDOW, MSS_WDOG_INTERRUPT_ON_TIMEOUT_MODE );\r
+ MSS_WD_enable_wakeup_irq();\r
+ for (;;)\r
+ {\r
+ main_task();\r
+ cortex_sleep();\r
+ }\r
+ }\r
+ \r
+ void WdogWakeup_IRQHandler( void )\r
+ {\r
+ process_wakeup();\r
+ MSS_WD_clear_wakeup_irq();\r
+ }\r
+ @endcode\r
+ */\r
+static __INLINE void MSS_WD_enable_wakeup_irq( void )\r
+{\r
+ WATCHDOG->WDOGCONTROL |= MSS_WDOG_WAKEUP_IRQ_ENABLE_BIT_MASK;\r
+ NVIC_EnableIRQ( WdogWakeup_IRQn );\r
+}\r
+\r
+/***************************************************************************//**\r
+ The MSS_WD_disable_wakeup_irq() function disables the SmartFusion wakeup\r
+ interrupt. \r
+ \r
+ @return\r
+ This function does not return a value.\r
+ */\r
+static __INLINE void MSS_WD_disable_wakeup_irq( void )\r
+{\r
+ WATCHDOG->WDOGCONTROL &= ~MSS_WDOG_WAKEUP_IRQ_ENABLE_BIT_MASK;\r
+}\r
+\r
+/***************************************************************************//**\r
+ The MSS_WD_clear_timeout_irq() function clears the watchdog\92s time out\r
+ interrupt which is connected to the Cortex-M3 NMI interrupt.\r
+ Calling MSS_WD_clear_timeout_irq() results in clearing the Cortex-M3 NMI interrupt.\r
+ Note: The MSS_WD_clear_timeout_irq() function must be called as part of the\r
+ timeout interrupt service routine (ISR) in order to prevent the same interrupt\r
+ event retriggering a call to the wakeup ISR.\r
+ \r
+ @return\r
+ The example below demonstrates the use of the MSS_WD_clear_timeout_irq()\r
+ function as part of the NMI interrupt service routine.\r
+\r
+ Example:\r
+ @code\r
+ void NMI_Handler( void )\r
+ {\r
+ process_timeout();\r
+ MSS_WD_clear_timeout_irq();\r
+ }\r
+ @endcode\r
+ */\r
+static __INLINE void MSS_WD_clear_timeout_irq( void )\r
+{\r
+ WATCHDOG->WDOGRIS = MSS_WDOG_TIMEOUT_IRQ_CLEAR_BIT_MASK;\r
+ /*\r
+ * Perform a second write to ensure that the first write completed before \r
+ * returning from this function. This is to account for posted writes across\r
+ * the AHB matrix. The second write ensures that the first write has\r
+ * completed and that the interrupt line has been de-asserted by the time\r
+ * the function returns. Omitting the second write may result in a delay\r
+ * in the de-assertion of the interrupt line going to the Cortex-M3 and a\r
+ * retriggering of the interrupt.\r
+ */\r
+ WATCHDOG->WDOGRIS = MSS_WDOG_TIMEOUT_IRQ_CLEAR_BIT_MASK;\r
+}\r
+\r
+/***************************************************************************//**\r
+ The MSS_WD_clear_wakeup_irq() function clears the wakeup interrupt.\r
+ Note: The MSS_WD_clear_wakeup_irq() function must be called as part of the\r
+ wakeup interrupt service routine (ISR) in order to prevent the same interrupt\r
+ event retriggering a call to the wakeup ISR. This function also clears the\r
+ interrupt in the Cortex-M3 interrupt controller through a call to\r
+ NVIC_ClearPendingIRQ().\r
+ \r
+ @return\r
+ This function does not return a value.\r
+\r
+ Example:\r
+ The example below demonstrates the use of the MSS_WD_clear_wakeup_irq() function\r
+ as part of the wakeup interrupt service routine. \r
+ @code\r
+ void WdogWakeup_IRQHandler( void )\r
+ {\r
+ do_interrupt_processing();\r
+ \r
+ MSS_WD_clear_wakeup_irq();\r
+ }\r
+ @endcode\r
+*/\r
+static __INLINE void MSS_WD_clear_wakeup_irq( void )\r
+{\r
+ WATCHDOG->WDOGRIS = MSS_WDOG_WAKEUP_IRQ_CLEAR_BIT_MASK;\r
+ NVIC_ClearPendingIRQ( WdogWakeup_IRQn );\r
+}\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* MSS_WATCHDOG_H_ */\r
--- /dev/null
+/*\r
+ FreeRTOS V6.1.1 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * If you are: *\r
+ * *\r
+ * + New to FreeRTOS, *\r
+ * + Wanting to learn FreeRTOS or multitasking in general quickly *\r
+ * + Looking for basic training, *\r
+ * + Wanting to improve your FreeRTOS skills and productivity *\r
+ * *\r
+ * then take a look at the FreeRTOS books - available as PDF or paperback *\r
+ * *\r
+ * "Using the FreeRTOS Real Time Kernel - a Practical Guide" *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ * A pdf reference manual is also available. Both are usually delivered *\r
+ * to your inbox within 20 minutes to two hours when purchased between 8am *\r
+ * and 8pm GMT (although please allow up to 24 hours in case of *\r
+ * exceptional circumstances). Thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ ***NOTE*** The exception to the GPL is included to allow you to distribute\r
+ a combined work that includes FreeRTOS without being obliged to provide the\r
+ source code for proprietary components outside of the FreeRTOS kernel.\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT\r
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+/*\r
+This simple demo project runs on the STM32 Discovery board, which is\r
+populated with an STM32F100RB Cortex-M3 microcontroller. The discovery board \r
+makes an ideal low cost evaluation platform, but the 8K of RAM provided on the\r
+STM32F100RB does not allow the simple application to demonstrate all of all the \r
+FreeRTOS kernel features. Therefore, this simple demo only actively \r
+demonstrates task, queue, timer and interrupt functionality. In addition, the \r
+demo is configured to include malloc failure, idle and stack overflow hook \r
+functions.\r
+\r
+The idle hook function:\r
+The idle hook function queries the amount of FreeRTOS heap space that is\r
+remaining (see vApplicationIdleHook() defined in this file). The demo \r
+application is configured use 7K or the available 8K of RAM as the FreeRTOS heap.\r
+Memory is only allocated from this heap during initialisation, and this demo \r
+only actually uses 1.6K bytes of the configured 7K available - leaving 5.4K \r
+bytes of heap space unallocated.\r
+\r
+The main() Function:\r
+main() creates one software timer, one queue, and two tasks. It then starts the\r
+scheduler.\r
+\r
+The Queue Send Task:\r
+The queue send task is implemented by the prvQueueSendTask() function in this \r
+file. prvQueueSendTask() sits in a loop that causes it to repeatedly block for \r
+200 milliseconds, before sending the value 100 to the queue that was created \r
+within main(). Once the value is sent, the task loops back around to block for\r
+another 200 milliseconds.\r
+\r
+The Queue Receive Task:\r
+The queue receive task is implemented by the prvQueueReceiveTask() function\r
+in this file. prvQueueReceiveTask() sits in a loop that causes repeatedly \r
+attempt to read data from the queue that was created within main(). When data \r
+is received, the task checks the value of the data, and if the value equals \r
+the expected 100, toggles the green LED. The 'block time' parameter passed to \r
+the queue receive function specifies that the task should be held in the Blocked \r
+state indefinitely to wait for data to be available on the queue. The queue \r
+receive task will only leave the Blocked state when the queue send task writes \r
+to the queue. As the queue send task writes to the queue every 200 \r
+milliseconds, the queue receive task leaves the Blocked state every 200 \r
+milliseconds, and therefore toggles the green LED every 200 milliseconds.\r
+\r
+The LED Software Timer and the Button Interrupt:\r
+The user button B1 is configured to generate an interrupt each time it is\r
+pressed. The interrupt service routine switches the red LED on, and resets the \r
+LED software timer. The LED timer has a 5000 millisecond (5 second) period, and\r
+uses a callback function that is defined to just turn the red LED off. \r
+Therefore, pressing the user button will turn the red LED on, and the LED will \r
+remain on until a full five seconds pass without the button being pressed.\r
+*/\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "queue.h"\r
+#include "timers.h"\r
+\r
+/* Microsemi drivers/libraries. */\r
+#include "mss_gpio.h"\r
+#include "mss_watchdog.h"\r
+\r
+\r
+/* Priorities at which the tasks are created. */\r
+#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+\r
+/* The rate at which data is sent to the queue, specified in milliseconds, and\r
+converted to ticks using the portTICK_RATE_MS constant. */\r
+#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_RATE_MS )\r
+\r
+/* The number of items the queue can hold. This is 1 as the receive task\r
+will remove items as they are added, meaning the send task should always find\r
+the queue empty. */\r
+#define mainQUEUE_LENGTH ( 1 )\r
+\r
+#define mainTASK_CONTROLLED_LED 0x01UL\r
+#define mainTIMER_CONTROLLED_LED 0x02UL\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Setup the NVIC, LED outputs, and button inputs.\r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+/*\r
+ * The tasks as described in the comments at the top of this file.\r
+ */\r
+static void prvQueueReceiveTask( void *pvParameters );\r
+static void prvQueueSendTask( void *pvParameters );\r
+\r
+/*\r
+ * The LED timer callback function. This does nothing but switch the red LED \r
+ * off.\r
+ */\r
+static void vLEDTimerCallback( xTimerHandle xTimer );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The queue used by both tasks. */\r
+static xQueueHandle xQueue = NULL;\r
+\r
+/* The LED software timer. This uses vLEDTimerCallback() as its callback\r
+function. */\r
+static xTimerHandle xLEDTimer = NULL;\r
+\r
+volatile unsigned long ulGPIOState = 0UL;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+int main(void)\r
+{\r
+ /* Configure the NVIC, LED outputs and button inputs. */\r
+ prvSetupHardware();\r
+\r
+ /* Create the queue. */\r
+ xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) );\r
+\r
+ if( xQueue != NULL )\r
+ {\r
+ /* Start the two tasks as described in the comments at the top of this\r
+ file. */\r
+ xTaskCreate( prvQueueReceiveTask, ( signed char * ) "Rx", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_RECEIVE_TASK_PRIORITY, NULL );\r
+ xTaskCreate( prvQueueSendTask, ( signed char * ) "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL );\r
+\r
+ /* Create the software timer that is responsible for turning off the LED \r
+ if the button is not pushed within 5000ms, as described at the top of \r
+ this file. */\r
+ xLEDTimer = xTimerCreate( ( const signed char * ) "LEDTimer", /* A text name, purely to help debugging. */\r
+ ( 5000 / portTICK_RATE_MS ), /* The timer period, in this case 5000ms (5s). */\r
+ pdFALSE, /* This is a one shot timer, so xAutoReload is set to pdFALSE. */\r
+ ( void * ) 0, /* The ID is not used, so can be set to anything. */\r
+ vLEDTimerCallback /* The callback function that switches the LED off. */\r
+ );\r
+\r
+ /* Start the tasks and timer running. */\r
+ vTaskStartScheduler();\r
+ }\r
+\r
+ /* If all is well, the scheduler will now be running, and the following line\r
+ will never be reached. If the following line does execute, then there was\r
+ insufficient FreeRTOS heap memory available for the idle and/or timer tasks\r
+ to be created. See the memory management section on the FreeRTOS web site\r
+ for more details. */\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vLEDTimerCallback( xTimerHandle xTimer )\r
+{\r
+ /* The timer has expired - so no button pushes have occurred in the last\r
+ five seconds - turn the LED off. NOTE - accessing the LED port should use\r
+ a critical section because it is accessed from multiple tasks, and the\r
+ button interrupt - in this trivial case, for simplicity, the critical\r
+ section is omitted. */\r
+ ulGPIOState |= mainTIMER_CONTROLLED_LED;\r
+ MSS_GPIO_set_outputs( ulGPIOState );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The ISR executed when the user button is pushed. */\r
+void GPIO8_IRQHandler( void )\r
+{\r
+portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;\r
+\r
+ /* The button was pushed, so ensure the LED is on before resetting the\r
+ LED timer. The LED timer will turn the LED off if the button is not\r
+ pushed within 5000ms. */\r
+ ulGPIOState &= ~mainTIMER_CONTROLLED_LED;\r
+ MSS_GPIO_set_outputs( ulGPIOState );\r
+\r
+ /* This interrupt safe FreeRTOS function can be called from this interrupt\r
+ because the interrupt priority is below the\r
+ configMAX_SYSCALL_INTERRUPT_PRIORITY setting in FreeRTOSConfig.h. */\r
+ xTimerResetFromISR( xLEDTimer, &xHigherPriorityTaskWoken );\r
+\r
+ /* Clear the interrupt before leaving. */\r
+ MSS_GPIO_clear_irq( MSS_GPIO_8 );\r
+\r
+ /* If calling xTimerResetFromISR() caused a task (in this case the timer\r
+ service/daemon task) to unblock, and the unblocked task has a priority\r
+ higher than or equal to the task that was interrupted, then\r
+ xHigherPriorityTaskWoken will now be set to pdTRUE, and calling\r
+ portEND_SWITCHING_ISR() will ensure the unblocked task runs next. */\r
+ portEND_SWITCHING_ISR( xHigherPriorityTaskWoken );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvQueueSendTask( void *pvParameters )\r
+{\r
+portTickType xNextWakeTime;\r
+const unsigned long ulValueToSend = 100UL;\r
+\r
+ /* Initialise xNextWakeTime - this only needs to be done once. */\r
+ xNextWakeTime = xTaskGetTickCount();\r
+\r
+ for( ;; )\r
+ {\r
+ /* Place this task in the blocked state until it is time to run again.\r
+ The block time is specified in ticks, the constant used converts ticks\r
+ to ms. While in the Blocked state this task will not consume any CPU\r
+ time. */\r
+ vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS );\r
+\r
+ /* Send to the queue - causing the queue receive task to unblock and\r
+ toggle an LED. 0 is used as the block time so the sending operation\r
+ will not block - it shouldn't need to block as the queue should always\r
+ be empty at this point in the code. */\r
+ xQueueSend( xQueue, &ulValueToSend, 0 );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvQueueReceiveTask( void *pvParameters )\r
+{\r
+unsigned long ulReceivedValue;\r
+\r
+ for( ;; )\r
+ {\r
+ /* Wait until something arrives in the queue - this task will block\r
+ indefinitely provided INCLUDE_vTaskSuspend is set to 1 in\r
+ FreeRTOSConfig.h. */\r
+ xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );\r
+\r
+ /* To get here something must have been received from the queue, but\r
+ is it the expected value? If it is, toggle the green LED. */\r
+ if( ulReceivedValue == 100UL )\r
+ {\r
+ /* NOTE - accessing the LED port should use a critical section\r
+ because it is accessed from multiple tasks, and the button interrupt \r
+ - in this trivial case, for simplicity, the critical section is \r
+ omitted. */\r
+ if( ( ulGPIOState & mainTASK_CONTROLLED_LED ) != 0 )\r
+ {\r
+ ulGPIOState &= ~mainTASK_CONTROLLED_LED;\r
+ }\r
+ else\r
+ {\r
+ ulGPIOState |= mainTASK_CONTROLLED_LED;\r
+ }\r
+ MSS_GPIO_set_outputs( ulGPIOState );\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupHardware( void )\r
+{\r
+ /* Disable the Watch Dog Timer */\r
+ MSS_WD_disable( );\r
+\r
+ /* Initialise the GPIO */\r
+ MSS_GPIO_init();\r
+\r
+ /* Set up GPIO for the LEDs. */\r
+ MSS_GPIO_config( MSS_GPIO_0 , MSS_GPIO_OUTPUT_MODE );\r
+ MSS_GPIO_config( MSS_GPIO_1 , MSS_GPIO_OUTPUT_MODE );\r
+ MSS_GPIO_config( MSS_GPIO_2 , MSS_GPIO_OUTPUT_MODE );\r
+ MSS_GPIO_config( MSS_GPIO_3 , MSS_GPIO_OUTPUT_MODE );\r
+ MSS_GPIO_config( MSS_GPIO_4 , MSS_GPIO_OUTPUT_MODE );\r
+ MSS_GPIO_config( MSS_GPIO_5 , MSS_GPIO_OUTPUT_MODE );\r
+ MSS_GPIO_config( MSS_GPIO_6 , MSS_GPIO_OUTPUT_MODE );\r
+ MSS_GPIO_config( MSS_GPIO_7 , MSS_GPIO_OUTPUT_MODE );\r
+\r
+ /* All LEDs start off. */\r
+ ulGPIOState = 0xffffffffUL;\r
+ MSS_GPIO_set_outputs( ulGPIOState );\r
+\r
+ /* Setup the GPIO and the NVIC for the switch used in this simple demo. */\r
+ NVIC_EnableIRQ( GPIO8_IRQn );\r
+ MSS_GPIO_config( MSS_GPIO_8, MSS_GPIO_INPUT_MODE | MSS_GPIO_IRQ_EDGE_NEGATIVE );\r
+ MSS_GPIO_enable_irq( MSS_GPIO_8 );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationMallocFailedHook( void )\r
+{\r
+ /* Called if a call to pvPortMalloc() fails because there is insufficient\r
+ free memory available in the FreeRTOS heap. pvPortMalloc() is called\r
+ internally by FreeRTOS API functions that create tasks, queues, software \r
+ timers, and semaphores. The size of the FreeRTOS heap is set by the\r
+ configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationStackOverflowHook( xTaskHandle *pxTask, signed char *pcTaskName )\r
+{\r
+ ( void ) pcTaskName;\r
+ ( void ) pxTask;\r
+\r
+ /* Run time stack overflow checking is performed if\r
+ configconfigCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook\r
+ function is called if a stack overflow is detected. */\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationIdleHook( void )\r
+{\r
+volatile size_t xFreeStackSpace;\r
+\r
+ /* This function is called on each cycle of the idle task. In this case it\r
+ does nothing useful, other than report the amout of FreeRTOS heap that \r
+ remains unallocated. */\r
+ xFreeStackSpace = xPortGetFreeHeapSize();\r
+\r
+ if( xFreeStackSpace > 100 )\r
+ {\r
+ /* By now, the kernel has allocated everything it is going to, so\r
+ if there is a lot of heap remaining unallocated then\r
+ the value of configTOTAL_HEAP_SIZE in FreeRTOSConfig.h can be\r
+ reduced accordingly. */\r
+ }\r
+}\r
projects / freertos / commitdiff