\r
\r
/*--------------------------------------------------------------------------\r
- Now try querying the previus value while notifying a task. */\r
+ Now try querying the previous value while notifying a task. */\r
xTaskNotifyAndQuery( xTaskToNotify, 0x00, eSetBits, &ulPreviousValue );\r
configASSERT( ulNotifiedValue == ( ULONG_MAX & ~( ulBit0 | ulBit1 ) ) );\r
\r
ulExpectedValue |= ulLoop;\r
}\r
\r
+\r
+\r
+ /* -------------------------------------------------------------------------\r
+ /* Clear the previous notifications. */\r
+ xTaskNotifyWait( ULONG_MAX, 0, &ulNotifiedValue, 0 );\r
+\r
+ /* The task should not have any notifications pending, so an attempt to clear\r
+ the notification state should fail. */\r
+ configASSERT( xTaskNotifyStateClear( NULL ) == pdFALSE );\r
+\r
+ /* Get the task to notify itself. This is not a normal thing to do, and is\r
+ only done here for test purposes. */\r
+ xTaskNotifyAndQuery( xTaskToNotify, ulFirstNotifiedConst, eSetValueWithoutOverwrite, &ulPreviousValue );\r
+\r
+ /* Now the notification state should be eNotified, so it should now be\r
+ possible to clear the notification state. */\r
+ configASSERT( xTaskNotifyStateClear( NULL ) == pdTRUE );\r
+ configASSERT( xTaskNotifyStateClear( NULL ) == pdFALSE );\r
+\r
+\r
+\r
+\r
/* Incremented to show the task is still running. */\r
ulNotifyCycleCount++;\r
\r
break;\r
\r
default:/* Should never get here!. */\r
- break; \r
+ break;\r
}\r
- \r
+\r
ulTimerNotificationsSent++;\r
}\r
}\r
#\r
-#Thu Oct 15 21:03:35 BST 2015\r
+#Fri Oct 16 11:40:45 BST 2015\r
default.com-microchip-mplab-nbide-toolchainXC16-XC16LanguageToolchain.md5=7b5555b9f3fac10bdeeaa71fff22c072\r
default.languagetoolchain.dir=C\:\\DevTools\\Microchip\\xc16\\v1.25\\bin\r
configurations-xml=e1668378027c43cfe57bea932c980e61\r
endif
${MAKE} -f nbproject/Makefile-PIC32MZ2048_SK.mk dist/${CND_CONF}/${IMAGE_TYPE}/RTOSDemo.X.${IMAGE_TYPE}.${OUTPUT_SUFFIX}
-MP_PROCESSOR_OPTION=32MZ2048ECM144
+MP_PROCESSOR_OPTION=32MZ2048ECH144
MP_LINKER_FILE_OPTION=
# ------------------------------------------------------------------------------------
# Rules for buildStep: assemble
#\r
-#Thu Oct 15 18:30:50 BST 2015\r
+#Fri Oct 16 11:52:06 BST 2015\r
PIC32MZ2048_SK.com-microchip-mplab-nbide-toolchainXC32-XC32LanguageToolchain.md5=dcb36c7e6928d5535e26dd359786192b\r
PIC32MZ2048EF_SK_SOFT_FLOAT.languagetoolchain.dir=C\:\\DevTools\\Microchip\\xc32\\v1.40\\bin\r
conf.ids=PIC32MZ2048_SK,PIC32MZ2048EF_SK_SOFT_FLOAT,PIC32MZ2048EF_SK_HARD_FLOAT\r
-configurations-xml=b89c82494ccd01c641a679d02e4a20c2\r
+configurations-xml=5494ca7739a1fe76ccf1dd947214ff1b\r
PIC32MZ2048EF_SK_HARD_FLOAT.languagetoolchain.dir=C\:\\DevTools\\Microchip\\xc32\\v1.40\\bin\r
PIC32MZ2048EF_SK_SOFT_FLOAT.com-microchip-mplab-nbide-toolchainXC32-XC32LanguageToolchain.md5=dcb36c7e6928d5535e26dd359786192b\r
PIC32MZ2048EF_SK_HARD_FLOAT.languagetoolchain.version=1.40\r
PROJECTNAME=RTOSDemo.X
# Active Configuration
-DEFAULTCONF=PIC32MZ2048EF_SK_HARD_FLOAT
+DEFAULTCONF=PIC32MZ2048_SK
CONF=${DEFAULTCONF}
# All Configurations
<conf name="PIC32MZ2048_SK" type="2">\r
<toolsSet>\r
<developmentServer>localhost</developmentServer>\r
- <targetDevice>PIC32MZ2048ECM144</targetDevice>\r
+ <targetDevice>PIC32MZ2048ECH144</targetDevice>\r
<targetHeader></targetHeader>\r
<targetPluginBoard></targetPluginBoard>\r
<platformTool>PKOBSKDEPlatformTool</platformTool>\r
<property key="ToolFirmwareFilePath"\r
value="Press to browse for a specific firmware version"/>\r
<property key="ToolFirmwareOption.UseLatestFirmware" value="true"/>\r
- <property key="firmware.download.all" value="false"/>\r
<property key="memories.configurationmemory" value="false"/>\r
<property key="memories.dataflash" value="true"/>\r
<property key="memories.eeprom" value="false"/>\r
<?xml version="1.0" encoding="UTF-8"?>\r
<configurationDescriptor version="62">\r
<projectmakefile>Makefile</projectmakefile>\r
- <defaultConf>2</defaultConf>\r
+ <defaultConf>0</defaultConf>\r
<confs>\r
<conf name="PIC32MZ2048_SK" type="2">\r
- <platformToolSN>:=MPLABComm-USB-Microchip:=<vid>04D8:=<pid>8107:=<rev>0002:=<man>Microchip Technology Incorporated:=<prod>PIC32MZ EF Family:=<sn>BUR153124004:=<drv>x:=<xpt>h:=end</platformToolSN>\r
+ <platformToolSN>:=MPLABComm-USB-Microchip:=<vid>04D8:=<pid>8107:=<rev>0002:=<man>Microchip Technology Incorporated:=<prod>PIC32MZ EC Family:=<sn>MTI132990155:=<drv>x:=<xpt>h:=end</platformToolSN>\r
<languageToolchainDir>C:\DevTools\Microchip\xc32\v1.40\bin</languageToolchainDir>\r
<mdbdebugger version="1">\r
<placeholder1>place holder 1</placeholder1>\r
</group>\r
<group name="Masters19024">\r
<file>file:/C:/E/Dev/FreeRTOS/WorkingCopy/FreeRTOS/Demo/PIC32MZ_MPLAB/main.c</file>\r
+ <file>file:/C:/E/Dev/FreeRTOS/WorkingCopy/FreeRTOS/Demo/PIC32MZ_MPLAB/flop_mz.c</file>\r
</group>\r
</open-files>\r
</project-private>\r
#pragma config EJTAGBEN = NORMAL, DBGPER = PG_ALL, FSLEEP = OFF, FECCCON = OFF_UNLOCKED\r
#pragma config BOOTISA = MIPS32, TRCEN = ON, ICESEL = ICS_PGx2, JTAGEN = OFF, DEBUG = ON\r
#pragma config CP = OFF\r
- #pragma config_alt FWDTEN=OFF\r
- #pragma config_alt USERID = 0x1234u\r
#elif defined(__32MZ2048EFM144) || defined(__32MZ2048EFH144)\r
#pragma config FMIIEN = OFF, FETHIO = OFF, PGL1WAY = OFF, PMDL1WAY = OFF, IOL1WAY = OFF, FUSBIDIO = OFF\r
#pragma config FNOSC = SPLL, FSOSCEN = OFF, IESO = OFF, POSCMOD = EC\r
}\r
/*-----------------------------------------------------------*/\r
\r
-void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName )\r
-{\r
- ( void ) pcTaskName;\r
- ( void ) pxTask;\r
-\r
- /* Run time stack overflow checking is performed if\r
- configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook\r
- function is called if a stack overflow is detected. */\r
- taskDISABLE_INTERRUPTS();\r
- for( ;; );\r
-}\r
#define configUSE_PREEMPTION 1\r
#define configTICK_RATE_HZ ( ( unsigned short ) 1000 )\r
#define configMAX_PRIORITIES ( 4 )\r
-#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 80 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 75 )\r
#define configMAX_TASK_NAME_LEN ( 10 )\r
#define configUSE_TRACE_FACILITY 0\r
#define configUSE_16_BIT_TICKS 1\r
</option>\r
<option>\r
<name>DynDriver</name>\r
- <state>TKRL78</state>\r
+ <state>SIMRL78</state>\r
</option>\r
<option>\r
<name>DebugDDFOverride</name>\r
</option>\r
<option>\r
<name>DynDriver</name>\r
- <state>SIMRL78</state>\r
+ <state>E1RL78</state>\r
</option>\r
<option>\r
<name>DebugDDFOverride</name>\r
<debug>1</debug>\r
<settings>\r
<name>General</name>\r
- <archiveVersion>5</archiveVersion>\r
+ <archiveVersion>6</archiveVersion>\r
<data>\r
<version>1</version>\r
<wantNonLocal>1</wantNonLocal>\r
</settings>\r
<settings>\r
<name>ICCRL78</name>\r
- <archiveVersion>5</archiveVersion>\r
+ <archiveVersion>6</archiveVersion>\r
<data>\r
<version>7</version>\r
<wantNonLocal>1</wantNonLocal>\r
</settings>\r
<settings>\r
<name>ARL78</name>\r
- <archiveVersion>5</archiveVersion>\r
+ <archiveVersion>6</archiveVersion>\r
<data>\r
- <version>2</version>\r
+ <version>3</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
<name>PreInclude</name>\r
<state></state>\r
</option>\r
+ <option>\r
+ <name>AsmListIncludeHeaderSource</name>\r
+ <state>0</state>\r
+ </option>\r
</data>\r
</settings>\r
<settings>\r
<data>\r
<extensions></extensions>\r
<cmdline></cmdline>\r
+ <hasPrio>0</hasPrio>\r
</data>\r
</settings>\r
<settings>\r
</settings>\r
<settings>\r
<name>XLINK</name>\r
- <archiveVersion>5</archiveVersion>\r
+ <archiveVersion>6</archiveVersion>\r
<data>\r
<version>14</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
+ <option>\r
+ <name>XlinkHugeHeap</name>\r
+ <state>1</state>\r
+ </option>\r
<option>\r
<name>XOutOverride</name>\r
<state>0</state>\r
</settings>\r
<settings>\r
<name>XAR</name>\r
- <archiveVersion>5</archiveVersion>\r
+ <archiveVersion>6</archiveVersion>\r
<data>\r
<version>0</version>\r
<wantNonLocal>1</wantNonLocal>\r
</settings>\r
<settings>\r
<name>INTERNAL_HWSUPPORT</name>\r
- <archiveVersion>5</archiveVersion>\r
+ <archiveVersion>6</archiveVersion>\r
<data/>\r
</settings>\r
<settings>\r
<debug>1</debug>\r
<settings>\r
<name>General</name>\r
- <archiveVersion>5</archiveVersion>\r
+ <archiveVersion>6</archiveVersion>\r
<data>\r
<version>1</version>\r
<wantNonLocal>1</wantNonLocal>\r
</settings>\r
<settings>\r
<name>ICCRL78</name>\r
- <archiveVersion>5</archiveVersion>\r
+ <archiveVersion>6</archiveVersion>\r
<data>\r
<version>7</version>\r
<wantNonLocal>1</wantNonLocal>\r
</settings>\r
<settings>\r
<name>ARL78</name>\r
- <archiveVersion>5</archiveVersion>\r
+ <archiveVersion>6</archiveVersion>\r
<data>\r
- <version>2</version>\r
+ <version>3</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
<name>PreInclude</name>\r
<state></state>\r
</option>\r
+ <option>\r
+ <name>AsmListIncludeHeaderSource</name>\r
+ <state>0</state>\r
+ </option>\r
</data>\r
</settings>\r
<settings>\r
<data>\r
<extensions></extensions>\r
<cmdline></cmdline>\r
+ <hasPrio>0</hasPrio>\r
</data>\r
</settings>\r
<settings>\r
</settings>\r
<settings>\r
<name>XLINK</name>\r
- <archiveVersion>5</archiveVersion>\r
+ <archiveVersion>6</archiveVersion>\r
<data>\r
<version>14</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
+ <option>\r
+ <name>XlinkHugeHeap</name>\r
+ <state>1</state>\r
+ </option>\r
<option>\r
<name>XOutOverride</name>\r
<state>0</state>\r
</settings>\r
<settings>\r
<name>XAR</name>\r
- <archiveVersion>5</archiveVersion>\r
+ <archiveVersion>6</archiveVersion>\r
<data>\r
<version>0</version>\r
<wantNonLocal>1</wantNonLocal>\r
</settings>\r
<settings>\r
<name>INTERNAL_HWSUPPORT</name>\r
- <archiveVersion>5</archiveVersion>\r
+ <archiveVersion>6</archiveVersion>\r
<data/>\r
</settings>\r
<settings>\r
<debug>1</debug>\r
<settings>\r
<name>General</name>\r
- <archiveVersion>5</archiveVersion>\r
+ <archiveVersion>6</archiveVersion>\r
<data>\r
<version>1</version>\r
<wantNonLocal>1</wantNonLocal>\r
</settings>\r
<settings>\r
<name>ICCRL78</name>\r
- <archiveVersion>5</archiveVersion>\r
+ <archiveVersion>6</archiveVersion>\r
<data>\r
<version>7</version>\r
<wantNonLocal>1</wantNonLocal>\r
</settings>\r
<settings>\r
<name>ARL78</name>\r
- <archiveVersion>5</archiveVersion>\r
+ <archiveVersion>6</archiveVersion>\r
<data>\r
- <version>2</version>\r
+ <version>3</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
<name>PreInclude</name>\r
<state></state>\r
</option>\r
+ <option>\r
+ <name>AsmListIncludeHeaderSource</name>\r
+ <state>0</state>\r
+ </option>\r
</data>\r
</settings>\r
<settings>\r
<data>\r
<extensions></extensions>\r
<cmdline></cmdline>\r
+ <hasPrio>0</hasPrio>\r
</data>\r
</settings>\r
<settings>\r
</settings>\r
<settings>\r
<name>XLINK</name>\r
- <archiveVersion>5</archiveVersion>\r
+ <archiveVersion>6</archiveVersion>\r
<data>\r
<version>14</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
+ <option>\r
+ <name>XlinkHugeHeap</name>\r
+ <state>1</state>\r
+ </option>\r
<option>\r
<name>XOutOverride</name>\r
<state>0</state>\r
</settings>\r
<settings>\r
<name>XAR</name>\r
- <archiveVersion>5</archiveVersion>\r
+ <archiveVersion>6</archiveVersion>\r
<data>\r
<version>0</version>\r
<wantNonLocal>1</wantNonLocal>\r
</settings>\r
<settings>\r
<name>INTERNAL_HWSUPPORT</name>\r
- <archiveVersion>5</archiveVersion>\r
+ <archiveVersion>6</archiveVersion>\r
<data/>\r
</settings>\r
<settings>\r
<debug>1</debug>\r
<settings>\r
<name>General</name>\r
- <archiveVersion>5</archiveVersion>\r
+ <archiveVersion>6</archiveVersion>\r
<data>\r
<version>1</version>\r
<wantNonLocal>1</wantNonLocal>\r
<option>\r
<name>GenCodeModel</name>\r
<version>0</version>\r
- <state>1</state>\r
+ <state>0</state>\r
</option>\r
<option>\r
<name>GenDataModel</name>\r
<version>0</version>\r
- <state>1</state>\r
+ <state>0</state>\r
</option>\r
<option>\r
<name>GenNearConstLocation</name>\r
</option>\r
<option>\r
<name>GenRTConfigPath</name>\r
- <state>$TOOLKIT_DIR$\LIB\dlrl78ff1n.h</state>\r
+ <state>$TOOLKIT_DIR$\LIB\dlrl78nn1n.h</state>\r
</option>\r
<option>\r
<name>GenRTLibraryPath</name>\r
- <state>$TOOLKIT_DIR$\LIB\dlrl78ff1n.r87</state>\r
+ <state>$TOOLKIT_DIR$\LIB\dlrl78fn1n.r87</state>\r
</option>\r
<option>\r
<name>GenHwSupport</name>\r
</option>\r
<option>\r
<name>GenLibInFormatterDescription</name>\r
- <state>No specifier n, no float, no scan set, no assignment suppressing.</state>\r
+ <state>No specifier n, no float or long long, no scan set, no assignment suppressing.</state>\r
</option>\r
<option>\r
<name>GenLibOutFormatter</name>\r
</option>\r
<option>\r
<name>GenLibOutFormatterDescription</name>\r
- <state>No specifier a or A, no specifier n, no float, no flags.</state>\r
+ <state>No specifier a or A, no specifier n, no float or long long, no flags.</state>\r
</option>\r
<option>\r
<name>GenStackSize</name>\r
</settings>\r
<settings>\r
<name>ICCRL78</name>\r
- <archiveVersion>5</archiveVersion>\r
+ <archiveVersion>6</archiveVersion>\r
<data>\r
<version>7</version>\r
<wantNonLocal>1</wantNonLocal>\r
</settings>\r
<settings>\r
<name>ARL78</name>\r
- <archiveVersion>5</archiveVersion>\r
+ <archiveVersion>6</archiveVersion>\r
<data>\r
- <version>2</version>\r
+ <version>3</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
<option>\r
<name>AsmDefines</name>\r
<state>RSKRL78L13</state>\r
- <state>__FAR_DATA_MODEL__</state>\r
+ <state>__NEAR_DATA_MODEL__</state>\r
</option>\r
<option>\r
<name>AsmPreprocOutput</name>\r
<name>PreInclude</name>\r
<state></state>\r
</option>\r
+ <option>\r
+ <name>AsmListIncludeHeaderSource</name>\r
+ <state>0</state>\r
+ </option>\r
</data>\r
</settings>\r
<settings>\r
<data>\r
<extensions></extensions>\r
<cmdline></cmdline>\r
+ <hasPrio>0</hasPrio>\r
</data>\r
</settings>\r
<settings>\r
</settings>\r
<settings>\r
<name>XLINK</name>\r
- <archiveVersion>5</archiveVersion>\r
+ <archiveVersion>6</archiveVersion>\r
<data>\r
<version>14</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
+ <option>\r
+ <name>XlinkHugeHeap</name>\r
+ <state>1</state>\r
+ </option>\r
<option>\r
<name>XOutOverride</name>\r
<state>0</state>\r
</settings>\r
<settings>\r
<name>XAR</name>\r
- <archiveVersion>5</archiveVersion>\r
+ <archiveVersion>6</archiveVersion>\r
<data>\r
<version>0</version>\r
<wantNonLocal>1</wantNonLocal>\r
</settings>\r
<settings>\r
<name>INTERNAL_HWSUPPORT</name>\r
- <archiveVersion>5</archiveVersion>\r
+ <archiveVersion>6</archiveVersion>\r
<data/>\r
</settings>\r
<settings>\r
<debug>1</debug>\r
<settings>\r
<name>General</name>\r
- <archiveVersion>5</archiveVersion>\r
+ <archiveVersion>6</archiveVersion>\r
<data>\r
<version>1</version>\r
<wantNonLocal>1</wantNonLocal>\r
</settings>\r
<settings>\r
<name>ICCRL78</name>\r
- <archiveVersion>5</archiveVersion>\r
+ <archiveVersion>6</archiveVersion>\r
<data>\r
<version>7</version>\r
<wantNonLocal>1</wantNonLocal>\r
</settings>\r
<settings>\r
<name>ARL78</name>\r
- <archiveVersion>5</archiveVersion>\r
+ <archiveVersion>6</archiveVersion>\r
<data>\r
- <version>2</version>\r
+ <version>3</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
<name>PreInclude</name>\r
<state></state>\r
</option>\r
+ <option>\r
+ <name>AsmListIncludeHeaderSource</name>\r
+ <state>0</state>\r
+ </option>\r
</data>\r
</settings>\r
<settings>\r
<data>\r
<extensions></extensions>\r
<cmdline></cmdline>\r
+ <hasPrio>0</hasPrio>\r
</data>\r
</settings>\r
<settings>\r
</settings>\r
<settings>\r
<name>XLINK</name>\r
- <archiveVersion>5</archiveVersion>\r
+ <archiveVersion>6</archiveVersion>\r
<data>\r
<version>14</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
+ <option>\r
+ <name>XlinkHugeHeap</name>\r
+ <state>1</state>\r
+ </option>\r
<option>\r
<name>XOutOverride</name>\r
<state>0</state>\r
</settings>\r
<settings>\r
<name>XAR</name>\r
- <archiveVersion>5</archiveVersion>\r
+ <archiveVersion>6</archiveVersion>\r
<data>\r
<version>0</version>\r
<wantNonLocal>1</wantNonLocal>\r
</settings>\r
<settings>\r
<name>INTERNAL_HWSUPPORT</name>\r
- <archiveVersion>5</archiveVersion>\r
+ <archiveVersion>6</archiveVersion>\r
<data/>\r
</settings>\r
<settings>\r
<debug>1</debug>\r
<settings>\r
<name>General</name>\r
- <archiveVersion>5</archiveVersion>\r
+ <archiveVersion>6</archiveVersion>\r
<data>\r
<version>1</version>\r
<wantNonLocal>1</wantNonLocal>\r
</settings>\r
<settings>\r
<name>ICCRL78</name>\r
- <archiveVersion>5</archiveVersion>\r
+ <archiveVersion>6</archiveVersion>\r
<data>\r
<version>7</version>\r
<wantNonLocal>1</wantNonLocal>\r
</settings>\r
<settings>\r
<name>ARL78</name>\r
- <archiveVersion>5</archiveVersion>\r
+ <archiveVersion>6</archiveVersion>\r
<data>\r
- <version>2</version>\r
+ <version>3</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
<name>PreInclude</name>\r
<state></state>\r
</option>\r
+ <option>\r
+ <name>AsmListIncludeHeaderSource</name>\r
+ <state>0</state>\r
+ </option>\r
</data>\r
</settings>\r
<settings>\r
<data>\r
<extensions></extensions>\r
<cmdline></cmdline>\r
+ <hasPrio>0</hasPrio>\r
</data>\r
</settings>\r
<settings>\r
</settings>\r
<settings>\r
<name>XLINK</name>\r
- <archiveVersion>5</archiveVersion>\r
+ <archiveVersion>6</archiveVersion>\r
<data>\r
<version>14</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
+ <option>\r
+ <name>XlinkHugeHeap</name>\r
+ <state>1</state>\r
+ </option>\r
<option>\r
<name>XOutOverride</name>\r
<state>0</state>\r
</settings>\r
<settings>\r
<name>XAR</name>\r
- <archiveVersion>5</archiveVersion>\r
+ <archiveVersion>6</archiveVersion>\r
<data>\r
<version>0</version>\r
<wantNonLocal>1</wantNonLocal>\r
</settings>\r
<settings>\r
<name>INTERNAL_HWSUPPORT</name>\r
- <archiveVersion>5</archiveVersion>\r
+ <archiveVersion>6</archiveVersion>\r
<data/>\r
</settings>\r
<settings>\r
\r
\r
\r
- <Column0>154</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>\r
+ <Column0>255</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>\r
</Workspace>\r
<Disassembly>\r
\r
\r
\r
<PreferedWindows><Position>2</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows><MixedMode>1</MixedMode><CodeCovShow>1</CodeCovShow><InstrProfShow>1</InstrProfShow><col-names><item>Disassembly</item><item>_I0</item></col-names><col-widths><item>500</item><item>20</item></col-widths><DisasmHistory/><ShowCodeCoverage>0</ShowCodeCoverage><ShowInstrProfiling>0</ShowInstrProfiling></Disassembly>\r
- <STACK2><PreferedWindows><Position>1</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows></STACK2><Register><PreferedWindows><Position>2</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows></Register><WATCH_1><PreferedWindows><Position>2</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows><expressions><item/></expressions><col-names><item>Expression</item><item>Location</item><item>Type</item><item>Value</item></col-names><col-widths><item>1
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\r <Windows>\r
\r
\r
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<Tabs>\r
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<Factory>Workspace</Factory>\r
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<Workspace>\r
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\r
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<Desktop>\r
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<Factory>Workspace</Factory>\r
<Session>\r
\r
- <NodeDict><ExpandedNode>RTOSDemo</ExpandedNode><ExpandedNode>RTOSDemo/Demo Source</ExpandedNode></NodeDict></Session>\r
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\r
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</Desktop>\r
</Workspace>\r
\r
\r
/**\r
* task. h\r
- * <PRE>void vTaskNotifyClear( TaskHandle_t xTask );</pre>\r
+ * <PRE>BaseType_t xTaskNotifyStateClear( TaskHandle_t xTask );</pre>\r
*\r
- * Clear the notification state of the task referenced by the handle xTask. The\r
- * task's notification value is not altered. Set xTask to NULL to clear the\r
+ * If the notification state of the task referenced by the handle xTask is \r
+ * eNotified, then set the task's notification state to eNotWaitingNotification. \r
+ * The task's notification value is not altered. Set xTask to NULL to clear the\r
* notification state of the calling task.\r
+ *\r
+ * @return pdTRUE if the task's notification state was set to \r
+ * eNotWaitingNotification, otherwise pdFALSE.\r
* \defgroup vTaskNotifyClear vTaskNotifyClear\r
* \ingroup TaskNotifications\r
*/\r
-void vTaskNotifyStateClear( TaskHandle_t xTask );\r
+BaseType_t xTaskNotifyStateClear( TaskHandle_t xTask );\r
\r
/*-----------------------------------------------------------\r
* SCHEDULER INTERNALS AVAILABLE FOR PORTING PURPOSES\r
--- /dev/null
+/*\r
+ FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+/* Standard includes. */\r
+#include <stdlib.h>\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+#ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS\r
+ #error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined. Refer to Cortex-A equivalent: http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html\r
+#endif\r
+\r
+#ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET\r
+ #error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined. Refer to Cortex-A equivalent: http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html\r
+#endif\r
+\r
+#ifndef configUNIQUE_INTERRUPT_PRIORITIES\r
+ #error configUNIQUE_INTERRUPT_PRIORITIES must be defined. Refer to Cortex-A equivalent: http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html\r
+#endif\r
+\r
+#ifndef configSETUP_TICK_INTERRUPT\r
+ #error configSETUP_TICK_INTERRUPT() must be defined. Refer to Cortex-A equivalent: http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html\r
+#endif /* configSETUP_TICK_INTERRUPT */\r
+\r
+#ifndef configMAX_API_CALL_INTERRUPT_PRIORITY\r
+ #error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. Refer to Cortex-A equivalent: http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html\r
+#endif\r
+\r
+#if configMAX_API_CALL_INTERRUPT_PRIORITY == 0\r
+ #error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0\r
+#endif\r
+\r
+#if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES\r
+ #error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority\r
+#endif\r
+\r
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1\r
+ /* Check the configuration. */\r
+ #if( configMAX_PRIORITIES > 32 )\r
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.\r
+ #endif\r
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */\r
+\r
+/* In case security extensions are implemented. */\r
+#if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )\r
+ #error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )\r
+#endif\r
+\r
+/* Some vendor specific files default configCLEAR_TICK_INTERRUPT() in\r
+portmacro.h. */\r
+#ifndef configCLEAR_TICK_INTERRUPT\r
+ #define configCLEAR_TICK_INTERRUPT()\r
+#endif\r
+\r
+/* A critical section is exited when the critical section nesting count reaches\r
+this value. */\r
+#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )\r
+\r
+/* In all GICs 255 can be written to the priority mask register to unmask all\r
+(but the lowest) interrupt priority. */\r
+#define portUNMASK_VALUE ( 0xFFUL )\r
+\r
+/* Tasks are not created with a floating point context, but can be given a\r
+floating point context after they have been created. A variable is stored as\r
+part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task\r
+does not have an FPU context, or any other value if the task does have an FPU\r
+context. */\r
+#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 )\r
+\r
+/* Constants required to setup the initial task context. */\r
+#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, IRQ enabled FIQ enabled. */\r
+#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )\r
+#define portINTERRUPT_ENABLE_BIT ( 0x80UL )\r
+#define portTHUMB_MODE_ADDRESS ( 0x01UL )\r
+\r
+/* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary\r
+point is zero. */\r
+#define portBINARY_POINT_BITS ( ( uint8_t ) 0x03 )\r
+\r
+/* Masks all bits in the APSR other than the mode bits. */\r
+#define portAPSR_MODE_BITS_MASK ( 0x1F )\r
+\r
+/* The value of the mode bits in the APSR when the CPU is executing in user\r
+mode. */\r
+#define portAPSR_USER_MODE ( 0x10 )\r
+\r
+/* The critical section macros only mask interrupts up to an application\r
+determined priority level. Sometimes it is necessary to turn interrupt off in\r
+the CPU itself before modifying certain hardware registers. */\r
+#define portCPU_IRQ_DISABLE() \\r
+ __asm volatile ( "CPSID i" ); \\r
+ __asm volatile ( "DSB" ); \\r
+ __asm volatile ( "ISB" );\r
+\r
+#define portCPU_IRQ_ENABLE() \\r
+ __asm volatile ( "CPSIE i" ); \\r
+ __asm volatile ( "DSB" ); \\r
+ __asm volatile ( "ISB" );\r
+\r
+\r
+/* Macro to unmask all interrupt priorities. */\r
+#define portCLEAR_INTERRUPT_MASK() \\r
+{ \\r
+ portCPU_IRQ_DISABLE(); \\r
+ portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \\r
+ __asm( "DSB \n" \\r
+ "ISB \n" ); \\r
+ portCPU_IRQ_ENABLE(); \\r
+}\r
+\r
+#define portINTERRUPT_PRIORITY_REGISTER_OFFSET 0x400UL\r
+#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )\r
+#define portBIT_0_SET ( ( uint8_t ) 0x01 )\r
+\r
+/* Let the user override the pre-loading of the initial LR with the address of\r
+prvTaskExitError() in case is messes up unwinding of the stack in the\r
+debugger. */\r
+#ifdef configTASK_RETURN_ADDRESS\r
+ #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS\r
+#else\r
+ #define portTASK_RETURN_ADDRESS prvTaskExitError\r
+#endif\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Starts the first task executing. This function is necessarily written in\r
+ * assembly code so is implemented in portASM.s.\r
+ */\r
+extern void vPortRestoreTaskContext( void );\r
+\r
+/*\r
+ * Used to catch tasks that attempt to return from their implementing function.\r
+ */\r
+static void prvTaskExitError( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* A variable is used to keep track of the critical section nesting. This\r
+variable has to be stored as part of the task context and must be initialised to\r
+a non zero value to ensure interrupts don't inadvertently become unmasked before\r
+the scheduler starts. As it is stored as part of the task context it will\r
+automatically be set to 0 when the first task is started. */\r
+volatile uint32_t ulCriticalNesting = 9999UL;\r
+\r
+/* Saved as part of the task context. If ulPortTaskHasFPUContext is non-zero then\r
+a floating point context must be saved and restored for the task. */\r
+uint32_t ulPortTaskHasFPUContext = pdFALSE;\r
+\r
+/* Set to 1 to pend a context switch from an ISR. */\r
+uint32_t ulPortYieldRequired = pdFALSE;\r
+\r
+/* Counts the interrupt nesting depth. A context switch is only performed if\r
+if the nesting depth is 0. */\r
+uint32_t ulPortInterruptNesting = 0UL;\r
+\r
+/* Used in asm code. */\r
+__attribute__(( used )) const uint32_t ulICCIAR = portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS;\r
+__attribute__(( used )) const uint32_t ulICCEOIR = portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS;\r
+__attribute__(( used )) const uint32_t ulICCPMR = portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS;\r
+__attribute__(( used )) const uint32_t ulMaxAPIPriorityMask = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * See header file for description.\r
+ */\r
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )\r
+{\r
+ /* Setup the initial stack of the task. The stack is set exactly as\r
+ expected by the portRESTORE_CONTEXT() macro.\r
+\r
+ The fist real value on the stack is the status register, which is set for\r
+ system mode, with interrupts enabled. A few NULLs are added first to ensure\r
+ GDB does not try decoding a non-existent return address. */\r
+ *pxTopOfStack = ( StackType_t ) NULL;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) NULL;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) NULL;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;\r
+\r
+ if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL )\r
+ {\r
+ /* The task will start in THUMB mode. */\r
+ *pxTopOfStack |= portTHUMB_MODE_BIT;\r
+ }\r
+\r
+ pxTopOfStack--;\r
+\r
+ /* Next the return address, which in this case is the start of the task. */\r
+ *pxTopOfStack = ( StackType_t ) pxCode;\r
+ pxTopOfStack--;\r
+\r
+ /* Next all the registers other than the stack pointer. */\r
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* R14 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\r
+ pxTopOfStack--;\r
+\r
+ /* The task will start with a critical nesting count of 0 as interrupts are\r
+ enabled. */\r
+ *pxTopOfStack = portNO_CRITICAL_NESTING;\r
+ pxTopOfStack--;\r
+\r
+ /* The task will start without a floating point context. A task that uses\r
+ the floating point hardware must call vPortTaskUsesFPU() before executing\r
+ any floating point instructions. */\r
+ *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;\r
+\r
+ return pxTopOfStack;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvTaskExitError( void )\r
+{\r
+ /* A function that implements a task must not exit or attempt to return to\r
+ its caller as there is nothing to return to. If a task wants to exit it\r
+ should instead call vTaskDelete( NULL ).\r
+\r
+ Artificially force an assert() to be triggered if configASSERT() is\r
+ defined, then stop here so application writers can catch the error. */\r
+ configASSERT( ulPortInterruptNesting == ~0UL );\r
+ portDISABLE_INTERRUPTS();\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+BaseType_t xPortStartScheduler( void )\r
+{\r
+uint32_t ulAPSR, ulCycles = 8; /* 8 bits per byte. */\r
+\r
+ #if( configASSERT_DEFINED == 1 )\r
+ {\r
+ volatile uint32_t ulOriginalPriority;\r
+ volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + portINTERRUPT_PRIORITY_REGISTER_OFFSET );\r
+ volatile uint8_t ucMaxPriorityValue;\r
+\r
+ /* Determine how many priority bits are implemented in the GIC.\r
+\r
+ Save the interrupt priority value that is about to be clobbered. */\r
+ ulOriginalPriority = *pucFirstUserPriorityRegister;\r
+\r
+ /* Determine the number of priority bits available. First write to\r
+ all possible bits. */\r
+ *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;\r
+\r
+ /* Read the value back to see how many bits stuck. */\r
+ ucMaxPriorityValue = *pucFirstUserPriorityRegister;\r
+\r
+ /* Shift to the least significant bits. */\r
+ while( ( ucMaxPriorityValue & portBIT_0_SET ) != portBIT_0_SET )\r
+ {\r
+ ucMaxPriorityValue >>= ( uint8_t ) 0x01;\r
+\r
+ /* If ulCycles reaches 0 then ucMaxPriorityValue must have been\r
+ read as 0, indicating a misconfiguration. */\r
+ ulCycles--;\r
+ if( ulCycles == 0 )\r
+ {\r
+ break;\r
+ }\r
+ }\r
+\r
+ /* Sanity check configUNIQUE_INTERRUPT_PRIORITIES matches the read\r
+ value. */\r
+// configASSERT( ucMaxPriorityValue == portLOWEST_INTERRUPT_PRIORITY );\r
+\r
+ /* Restore the clobbered interrupt priority register to its original\r
+ value. */\r
+ *pucFirstUserPriorityRegister = ulOriginalPriority;\r
+ }\r
+ #endif /* conifgASSERT_DEFINED */\r
+\r
+ /* Only continue if the CPU is not in User mode. The CPU must be in a\r
+ Privileged mode for the scheduler to start. */\r
+ __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) );\r
+ ulAPSR &= portAPSR_MODE_BITS_MASK;\r
+ configASSERT( ulAPSR != portAPSR_USER_MODE );\r
+\r
+ if( ulAPSR != portAPSR_USER_MODE )\r
+ {\r
+ /* Only continue if the binary point value is set to its lowest possible\r
+ setting. See the comments in vPortValidateInterruptPriority() below for\r
+ more information. */\r
+ configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );\r
+\r
+ if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE )\r
+ {\r
+ /* Interrupts are turned off in the CPU itself to ensure tick does\r
+ not execute while the scheduler is being started. Interrupts are\r
+ automatically turned back on in the CPU when the first task starts\r
+ executing. */\r
+ portCPU_IRQ_DISABLE();\r
+\r
+ /* Start the timer that generates the tick ISR. */\r
+ configSETUP_TICK_INTERRUPT();\r
+\r
+ /* Start the first task executing. */\r
+ vPortRestoreTaskContext();\r
+ }\r
+ }\r
+\r
+ /* Will only get here if xTaskStartScheduler() was called with the CPU in\r
+ a non-privileged mode or the binary point register was not set to its lowest\r
+ possible value. prvTaskExitError() is referenced to prevent a compiler\r
+ warning about it being defined but not referenced in the case that the user\r
+ defines their own exit address. */\r
+ ( void ) prvTaskExitError;\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEndScheduler( void )\r
+{\r
+ /* Not implemented in ports where there is nothing to return to.\r
+ Artificially force an assert. */\r
+ configASSERT( ulCriticalNesting == 1000UL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEnterCritical( void )\r
+{\r
+ /* Mask interrupts up to the max syscall interrupt priority. */\r
+ ulPortSetInterruptMask();\r
+\r
+ /* Now interrupts are disabled ulCriticalNesting can be accessed\r
+ directly. Increment ulCriticalNesting to keep a count of how many times\r
+ portENTER_CRITICAL() has been called. */\r
+ ulCriticalNesting++;\r
+\r
+ /* This is not the interrupt safe version of the enter critical function so\r
+ assert() if it is being called from an interrupt context. Only API\r
+ functions that end in "FromISR" can be used in an interrupt. Only assert if\r
+ the critical nesting count is 1 to protect against recursive calls if the\r
+ assert function also uses a critical section. */\r
+ if( ulCriticalNesting == 1 )\r
+ {\r
+ configASSERT( ulPortInterruptNesting == 0 );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortExitCritical( void )\r
+{\r
+ if( ulCriticalNesting > portNO_CRITICAL_NESTING )\r
+ {\r
+ /* Decrement the nesting count as the critical section is being\r
+ exited. */\r
+ ulCriticalNesting--;\r
+\r
+ /* If the nesting level has reached zero then all interrupt\r
+ priorities must be re-enabled. */\r
+ if( ulCriticalNesting == portNO_CRITICAL_NESTING )\r
+ {\r
+ /* Critical nesting has reached zero so all interrupt priorities\r
+ should be unmasked. */\r
+ portCLEAR_INTERRUPT_MASK();\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void FreeRTOS_Tick_Handler( void )\r
+{\r
+ /* Set interrupt mask before altering scheduler structures. The tick\r
+ handler runs at the lowest priority, so interrupts cannot already be masked,\r
+ so there is no need to save and restore the current mask value. It is\r
+ necessary to turn off interrupts in the CPU itself while the ICCPMR is being\r
+ updated. */\r
+ portCPU_IRQ_DISABLE();\r
+ portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );\r
+ __asm volatile ( "dsb \n"\r
+ "isb \n" );\r
+ portCPU_IRQ_ENABLE();\r
+\r
+ /* Increment the RTOS tick. */\r
+ if( xTaskIncrementTick() != pdFALSE )\r
+ {\r
+ ulPortYieldRequired = pdTRUE;\r
+ }\r
+\r
+ /* Ensure all interrupt priorities are active again. */\r
+ portCLEAR_INTERRUPT_MASK();\r
+ configCLEAR_TICK_INTERRUPT();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortTaskUsesFPU( void )\r
+{\r
+uint32_t ulInitialFPSCR = 0;\r
+\r
+ /* A task is registering the fact that it needs an FPU context. Set the\r
+ FPU flag (which is saved as part of the task context). */\r
+ ulPortTaskHasFPUContext = pdTRUE;\r
+\r
+ /* Initialise the floating point status register. */\r
+ __asm volatile ( "FMXR FPSCR, %0" :: "r" (ulInitialFPSCR) );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortClearInterruptMask( uint32_t ulNewMaskValue )\r
+{\r
+ if( ulNewMaskValue == pdFALSE )\r
+ {\r
+ portCLEAR_INTERRUPT_MASK();\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+uint32_t ulPortSetInterruptMask( void )\r
+{\r
+uint32_t ulReturn;\r
+\r
+ /* Interrupt in the CPU must be turned off while the ICCPMR is being\r
+ updated. */\r
+ portCPU_IRQ_DISABLE();\r
+ if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )\r
+ {\r
+ /* Interrupts were already masked. */\r
+ ulReturn = pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ ulReturn = pdFALSE;\r
+ portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );\r
+ __asm volatile ( "dsb \n"\r
+ "isb \n" );\r
+ }\r
+ portCPU_IRQ_ENABLE();\r
+\r
+ return ulReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configASSERT_DEFINED == 1 )\r
+\r
+ void vPortValidateInterruptPriority( void )\r
+ {\r
+ /* The following assertion will fail if a service routine (ISR) for\r
+ an interrupt that has been assigned a priority above\r
+ configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API\r
+ function. ISR safe FreeRTOS API functions must *only* be called\r
+ from interrupts that have been assigned a priority at or below\r
+ configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
+\r
+ Numerically low interrupt priority numbers represent logically high\r
+ interrupt priorities, therefore the priority of the interrupt must\r
+ be set to a value equal to or numerically *higher* than\r
+ configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
+\r
+ FreeRTOS maintains separate thread and ISR API functions to ensure\r
+ interrupt entry is as fast and simple as possible. */\r
+\r
+ configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );\r
+\r
+ /* Priority grouping: The interrupt controller (GIC) allows the bits\r
+ that define each interrupt's priority to be split between bits that\r
+ define the interrupt's pre-emption priority bits and bits that define\r
+ the interrupt's sub-priority. For simplicity all bits must be defined\r
+ to be pre-emption priority bits. The following assertion will fail if\r
+ this is not the case (if some bits represent a sub-priority).\r
+\r
+ The priority grouping is configured by the GIC's binary point register\r
+ (ICCBPR). Writting 0 to ICCBPR will ensure it is set to its lowest\r
+ possible value (which may be above 0). */\r
+ configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );\r
+ }\r
+\r
+#endif /* configASSERT_DEFINED */\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+ .text\r
+ .arm\r
+\r
+ .set SYS_MODE, 0x1f\r
+ .set SVC_MODE, 0x13\r
+ .set IRQ_MODE, 0x12\r
+\r
+ /* Hardware registers. */\r
+ .extern ulICCIAR\r
+ .extern ulICCEOIR\r
+ .extern ulICCPMR\r
+\r
+ /* Variables and functions. */\r
+ .extern ulMaxAPIPriorityMask\r
+ .extern _freertos_vector_table\r
+ .extern pxCurrentTCB\r
+ .extern vTaskSwitchContext\r
+ .extern vApplicationIRQHandler\r
+ .extern ulPortInterruptNesting\r
+ .extern ulPortTaskHasFPUContext\r
+\r
+ .global FreeRTOS_IRQ_Handler\r
+ .global FreeRTOS_SWI_Handler\r
+ .global vPortRestoreTaskContext\r
+ .global vPortInstallFreeRTOSVectorTable\r
+\r
+\r
+\r
+\r
+.macro portSAVE_CONTEXT\r
+\r
+ /* Save the LR and SPSR onto the system mode stack before switching to\r
+ system mode to save the remaining system mode registers. */\r
+ SRSDB sp!, #SYS_MODE\r
+ CPS #SYS_MODE\r
+ PUSH {R0-R12, R14}\r
+\r
+ /* Push the critical nesting count. */\r
+ LDR R2, ulCriticalNestingConst\r
+ LDR R1, [R2]\r
+ PUSH {R1}\r
+\r
+ /* Does the task have a floating point context that needs saving? If\r
+ ulPortTaskHasFPUContext is 0 then no. */\r
+ LDR R2, ulPortTaskHasFPUContextConst\r
+ LDR R3, [R2]\r
+ CMP R3, #0\r
+\r
+ /* Save the floating point context, if any. */\r
+ FMRXNE R1, FPSCR\r
+ VPUSHNE {D0-D15}\r
+ /*VPUSHNE {D16-D31}*/\r
+ PUSHNE {R1}\r
+\r
+ /* Save ulPortTaskHasFPUContext itself. */\r
+ PUSH {R3}\r
+\r
+ /* Save the stack pointer in the TCB. */\r
+ LDR R0, pxCurrentTCBConst\r
+ LDR R1, [R0]\r
+ STR SP, [R1]\r
+\r
+ .endm\r
+\r
+; /**********************************************************************/\r
+\r
+.macro portRESTORE_CONTEXT\r
+\r
+ /* Set the SP to point to the stack of the task being restored. */\r
+ LDR R0, pxCurrentTCBConst\r
+ LDR R1, [R0]\r
+ LDR SP, [R1]\r
+\r
+ /* Is there a floating point context to restore? If the restored\r
+ ulPortTaskHasFPUContext is zero then no. */\r
+ LDR R0, ulPortTaskHasFPUContextConst\r
+ POP {R1}\r
+ STR R1, [R0]\r
+ CMP R1, #0\r
+\r
+ /* Restore the floating point context, if any. */\r
+ POPNE {R0}\r
+ /*VPOPNE {D16-D31}*/\r
+ VPOPNE {D0-D15}\r
+ VMSRNE FPSCR, R0\r
+\r
+ /* Restore the critical section nesting depth. */\r
+ LDR R0, ulCriticalNestingConst\r
+ POP {R1}\r
+ STR R1, [R0]\r
+\r
+ /* Ensure the priority mask is correct for the critical nesting depth. */\r
+ LDR R2, ulICCPMRConst\r
+ LDR R2, [R2]\r
+ CMP R1, #0\r
+ MOVEQ R4, #255\r
+ LDRNE R4, ulMaxAPIPriorityMaskConst\r
+ LDRNE R4, [R4]\r
+ STR R4, [R2]\r
+\r
+ /* Restore all system mode registers other than the SP (which is already\r
+ being used). */\r
+ POP {R0-R12, R14}\r
+\r
+ /* Return to the task code, loading CPSR on the way. */\r
+ RFEIA sp!\r
+\r
+ .endm\r
+\r
+\r
+\r
+\r
+/******************************************************************************\r
+ * SVC handler is used to start the scheduler.\r
+ *****************************************************************************/\r
+.align 4\r
+.type FreeRTOS_SWI_Handler, %function\r
+FreeRTOS_SWI_Handler:\r
+ /* Save the context of the current task and select a new task to run. */\r
+ portSAVE_CONTEXT\r
+ LDR R0, vTaskSwitchContextConst\r
+ BLX R0\r
+ portRESTORE_CONTEXT\r
+\r
+\r
+/******************************************************************************\r
+ * vPortRestoreTaskContext is used to start the scheduler.\r
+ *****************************************************************************/\r
+.type vPortRestoreTaskContext, %function\r
+vPortRestoreTaskContext:\r
+ /* Switch to system mode. */\r
+ CPS #SYS_MODE\r
+ portRESTORE_CONTEXT\r
+\r
+.align 4\r
+.type FreeRTOS_IRQ_Handler, %function\r
+FreeRTOS_IRQ_Handler:\r
+\r
+ /* Return to the interrupted instruction. */\r
+ SUB lr, lr, #4\r
+\r
+ /* Push the return address and SPSR. */\r
+ PUSH {lr}\r
+ MRS lr, SPSR\r
+ PUSH {lr}\r
+\r
+ /* Change to supervisor mode to allow reentry. */\r
+ CPS #SVC_MODE\r
+\r
+ /* Push used registers. */\r
+ PUSH {r0-r4, r12}\r
+\r
+ /* Increment nesting count. r3 holds the address of ulPortInterruptNesting\r
+ for future use. r1 holds the original ulPortInterruptNesting value for\r
+ future use. */\r
+ LDR r3, ulPortInterruptNestingConst\r
+ LDR r1, [r3]\r
+ ADD r4, r1, #1\r
+ STR r4, [r3]\r
+\r
+ /* Read value from the interrupt acknowledge register, which is stored in r0\r
+ for future parameter and interrupt clearing use. */\r
+ LDR r2, ulICCIARConst\r
+ LDR r2, [r2]\r
+ LDR r0, [r2]\r
+\r
+ /* Ensure bit 2 of the stack pointer is clear. r2 holds the bit 2 value for\r
+ future use. */\r
+ MOV r2, sp\r
+ AND r2, r2, #4\r
+ SUB sp, sp, r2\r
+\r
+ /* Call the interrupt handler. */\r
+ PUSH {r0-r3, lr}\r
+ LDR r1, vApplicationIRQHandlerConst\r
+ BLX r1\r
+ POP {r0-r3, lr}\r
+ ADD sp, sp, r2\r
+\r
+ CPSID i\r
+ DSB\r
+ ISB\r
+\r
+ /* Write the value read from ICCIAR to ICCEOIR. */\r
+ LDR r4, ulICCEOIRConst\r
+ LDR r4, [r4]\r
+ STR r0, [r4]\r
+\r
+ /* Restore the old nesting count. */\r
+ STR r1, [r3]\r
+\r
+ /* A context switch is never performed if the nesting count is not 0. */\r
+ CMP r1, #0\r
+ BNE exit_without_switch\r
+\r
+ /* Did the interrupt request a context switch? r1 holds the address of\r
+ ulPortYieldRequired and r0 the value of ulPortYieldRequired for future\r
+ use. */\r
+ LDR r1, =ulPortYieldRequired\r
+ LDR r0, [r1]\r
+ CMP r0, #0\r
+ BNE switch_before_exit\r
+\r
+exit_without_switch:\r
+ /* No context switch. Restore used registers, LR_irq and SPSR before\r
+ returning. */\r
+ POP {r0-r4, r12}\r
+ CPS #IRQ_MODE\r
+ POP {LR}\r
+ MSR SPSR_cxsf, LR\r
+ POP {LR}\r
+ MOVS PC, LR\r
+\r
+switch_before_exit:\r
+ /* A context swtich is to be performed. Clear the context switch pending\r
+ flag. */\r
+ MOV r0, #0\r
+ STR r0, [r1]\r
+\r
+ /* Restore used registers, LR-irq and SPSR before saving the context\r
+ to the task stack. */\r
+ POP {r0-r4, r12}\r
+ CPS #IRQ_MODE\r
+ POP {LR}\r
+ MSR SPSR_cxsf, LR\r
+ POP {LR}\r
+ portSAVE_CONTEXT\r
+\r
+ /* Call the function that selects the new task to execute.\r
+ vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD\r
+ instructions, or 8 byte aligned stack allocated data. LR does not need\r
+ saving as a new LR will be loaded by portRESTORE_CONTEXT anyway. */\r
+ LDR R0, vTaskSwitchContextConst\r
+ BLX R0\r
+\r
+ /* Restore the context of, and branch to, the task selected to execute\r
+ next. */\r
+ portRESTORE_CONTEXT\r
+\r
+ulICCIARConst: .word ulICCIAR\r
+ulICCEOIRConst: .word ulICCEOIR\r
+ulICCPMRConst: .word ulICCPMR\r
+pxCurrentTCBConst: .word pxCurrentTCB\r
+ulCriticalNestingConst: .word ulCriticalNesting\r
+ulPortTaskHasFPUContextConst: .word ulPortTaskHasFPUContext\r
+ulMaxAPIPriorityMaskConst: .word ulMaxAPIPriorityMask\r
+vTaskSwitchContextConst: .word vTaskSwitchContext\r
+vApplicationIRQHandlerConst: .word vApplicationIRQHandler\r
+ulPortInterruptNestingConst: .word ulPortInterruptNesting\r
+\r
+.end\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+#ifndef PORTMACRO_H\r
+#define PORTMACRO_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/*-----------------------------------------------------------\r
+ * Port specific definitions.\r
+ *\r
+ * The settings in this file configure FreeRTOS correctly for the given hardware\r
+ * and compiler.\r
+ *\r
+ * These settings should not be altered.\r
+ *-----------------------------------------------------------\r
+ */\r
+\r
+/* Type definitions. */\r
+#define portCHAR char\r
+#define portFLOAT float\r
+#define portDOUBLE double\r
+#define portLONG long\r
+#define portSHORT short\r
+#define portSTACK_TYPE uint32_t\r
+#define portBASE_TYPE long\r
+\r
+typedef portSTACK_TYPE StackType_t;\r
+typedef long BaseType_t;\r
+typedef unsigned long UBaseType_t;\r
+\r
+typedef uint32_t TickType_t;\r
+#define portMAX_DELAY ( TickType_t ) 0xffffffffUL\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Hardware specifics. */\r
+#define portSTACK_GROWTH ( -1 )\r
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\r
+#define portBYTE_ALIGNMENT 8\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Task utilities. */\r
+\r
+/* Called at the end of an ISR that can cause a context switch. */\r
+#define portEND_SWITCHING_ISR( xSwitchRequired )\\r
+{ \\r
+extern uint32_t ulPortYieldRequired; \\r
+ \\r
+ if( xSwitchRequired != pdFALSE ) \\r
+ { \\r
+ ulPortYieldRequired = pdTRUE; \\r
+ } \\r
+}\r
+\r
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\r
+#define portYIELD() __asm volatile ( "SWI 0" );\r
+\r
+\r
+/*-----------------------------------------------------------\r
+ * Critical section control\r
+ *----------------------------------------------------------*/\r
+\r
+extern void vPortEnterCritical( void );\r
+extern void vPortExitCritical( void );\r
+extern uint32_t ulPortSetInterruptMask( void );\r
+extern void vPortClearInterruptMask( uint32_t ulNewMaskValue );\r
+extern void vPortInstallFreeRTOSVectorTable( void );\r
+\r
+/* These macros do not globally disable/enable interrupts. They do mask off\r
+interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */\r
+#define portENTER_CRITICAL() vPortEnterCritical();\r
+#define portEXIT_CRITICAL() vPortExitCritical();\r
+#define portDISABLE_INTERRUPTS() ulPortSetInterruptMask()\r
+#define portENABLE_INTERRUPTS() vPortClearInterruptMask( 0 )\r
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetInterruptMask()\r
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortClearInterruptMask(x)\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Task function macros as described on the FreeRTOS.org WEB site. These are\r
+not required for this port but included in case common demo code that uses these\r
+macros is used. */\r
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+\r
+/* Prototype of the FreeRTOS tick handler. This must be installed as the\r
+handler for whichever peripheral is used to generate the RTOS tick. */\r
+void FreeRTOS_Tick_Handler( void );\r
+\r
+/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()\r
+before any floating point instructions are executed. */\r
+void vPortTaskUsesFPU( void );\r
+#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()\r
+\r
+#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )\r
+#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )\r
+\r
+/* Architecture specific optimisations. */\r
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION\r
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1\r
+#endif\r
+\r
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1\r
+\r
+ /* Store/clear the ready priorities in a bit map. */\r
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )\r
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )\r
+\r
+ /*-----------------------------------------------------------*/\r
+\r
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __builtin_clz( uxReadyPriorities ) )\r
+\r
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */\r
+\r
+#ifdef configASSERT\r
+ void vPortValidateInterruptPriority( void );\r
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()\r
+#endif /* configASSERT */\r
+\r
+#define portNOP() __asm volatile( "NOP" )\r
+\r
+\r
+#ifdef __cplusplus\r
+ } /* extern C */\r
+#endif\r
+\r
+\r
+/* The number of bits to shift for an interrupt priority is dependent on the\r
+number of bits implemented by the interrupt controller. */\r
+#if configUNIQUE_INTERRUPT_PRIORITIES == 16\r
+ #define portPRIORITY_SHIFT 4\r
+ #define portMAX_BINARY_POINT_VALUE 3\r
+#elif configUNIQUE_INTERRUPT_PRIORITIES == 32\r
+ #define portPRIORITY_SHIFT 3\r
+ #define portMAX_BINARY_POINT_VALUE 2\r
+#elif configUNIQUE_INTERRUPT_PRIORITIES == 64\r
+ #define portPRIORITY_SHIFT 2\r
+ #define portMAX_BINARY_POINT_VALUE 1\r
+#elif configUNIQUE_INTERRUPT_PRIORITIES == 128\r
+ #define portPRIORITY_SHIFT 1\r
+ #define portMAX_BINARY_POINT_VALUE 0\r
+#elif configUNIQUE_INTERRUPT_PRIORITIES == 256\r
+ #define portPRIORITY_SHIFT 0\r
+ #define portMAX_BINARY_POINT_VALUE 0\r
+#else\r
+ #error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting. configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware\r
+#endif\r
+\r
+/* Interrupt controller access addresses. */\r
+#define portICCPMR_PRIORITY_MASK_OFFSET ( 0x04 )\r
+#define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ( 0x0C )\r
+#define portICCEOIR_END_OF_INTERRUPT_OFFSET ( 0x10 )\r
+#define portICCBPR_BINARY_POINT_OFFSET ( 0x08 )\r
+#define portICCRPR_RUNNING_PRIORITY_OFFSET ( 0x14 )\r
+\r
+#define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET )\r
+#define portICCPMR_PRIORITY_MASK_REGISTER ( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) )\r
+#define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET )\r
+#define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET )\r
+#define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET )\r
+#define portICCBPR_BINARY_POINT_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) )\r
+#define portICCRPR_RUNNING_PRIORITY_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) )\r
+\r
+#endif /* PORTMACRO_H */\r
+\r
\r
PUSH AX ; Save AX Register to stack.\r
PUSH HL\r
-#if configMEMORY_MODE == 1\r
MOV A, CS ; Save CS register.\r
XCH A, X\r
MOV A, ES ; Save ES register.\r
PUSH AX\r
-#else\r
- MOV A, CS ; Save CS register.\r
- PUSH AX\r
-#endif\r
PUSH DE ; Save the remaining general purpose registers.\r
PUSH BC\r
MOVW AX, usCriticalNesting ; Save the usCriticalNesting value.\r
MOVW usCriticalNesting, AX\r
POP BC ; Restore the necessary general purpose registers.\r
POP DE\r
-#if configMEMORY_MODE == 1\r
POP AX ; Restore the ES register.\r
MOV ES, A\r
XCH A, X ; Restore the CS register.\r
MOV CS, A\r
-#else\r
- POP AX\r
- MOV CS, A ; Restore CS register.\r
-#endif\r
POP HL ; Restore general purpose register HL.\r
POP AX ; Restore AX.\r
ENDM\r
\r
PUSH AX ; Save AX Register to stack.\r
PUSH HL\r
-#if __DATA_MODEL__ == __DATA_MODEL_FAR__\r
MOV A, CS ; Save CS register.\r
XCH A, X\r
MOV A, ES ; Save ES register.\r
PUSH AX\r
-#else\r
- MOV A, CS ; Save CS register.\r
- PUSH AX\r
-#endif\r
PUSH DE ; Save the remaining general purpose registers.\r
PUSH BC\r
MOVW AX, usCriticalNesting ; Save the usCriticalNesting value.\r
MOVW usCriticalNesting, AX\r
POP BC ; Restore the necessary general purpose registers.\r
POP DE\r
-#if __DATA_MODEL__ == __DATA_MODEL_FAR__\r
POP AX ; Restore the ES register.\r
MOV ES, A\r
XCH A, X ; Restore the CS register.\r
MOV CS, A\r
-#else\r
- POP AX\r
- MOV CS, A ; Restore CS register.\r
-#endif\r
POP HL ; Restore general purpose register HL.\r
POP AX ; Restore AX.\r
ENDM\r
void vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions )\r
{\r
BlockLink_t *pxFirstFreeBlockInRegion = NULL, *pxPreviousFreeBlock;\r
-uint8_t *pucAlignedHeap;\r
+size_t xAlignedHeap;\r
size_t xTotalRegionSize, xTotalHeapSize = 0;\r
BaseType_t xDefinedRegions = 0;\r
size_t xAddress;\r
xTotalRegionSize -= xAddress - ( size_t ) pxHeapRegion->pucStartAddress;\r
}\r
\r
- pucAlignedHeap = ( uint8_t * ) xAddress;\r
+ xAlignedHeap = xAddress;\r
\r
/* Set xStart if it has not already been set. */\r
if( xDefinedRegions == 0 )\r
{\r
/* xStart is used to hold a pointer to the first item in the list of\r
free blocks. The void cast is used to prevent compiler warnings. */\r
- xStart.pxNextFreeBlock = ( BlockLink_t * ) pucAlignedHeap;\r
+ xStart.pxNextFreeBlock = ( BlockLink_t * ) xAlignedHeap;\r
xStart.xBlockSize = ( size_t ) 0;\r
}\r
else\r
\r
/* pxEnd is used to mark the end of the list of free blocks and is\r
inserted at the end of the region space. */\r
- xAddress = ( ( size_t ) pucAlignedHeap ) + xTotalRegionSize;\r
+ xAddress = xAlignedHeap + xTotalRegionSize;\r
xAddress -= xHeapStructSize;\r
xAddress &= ~portBYTE_ALIGNMENT_MASK;\r
pxEnd = ( BlockLink_t * ) xAddress;\r
/* To start with there is a single free block in this region that is\r
sized to take up the entire heap region minus the space taken by the\r
free block structure. */\r
- pxFirstFreeBlockInRegion = ( BlockLink_t * ) pucAlignedHeap;\r
+ pxFirstFreeBlockInRegion = ( BlockLink_t * ) xAlignedHeap;\r
pxFirstFreeBlockInRegion->xBlockSize = xAddress - ( size_t ) pxFirstFreeBlockInRegion;\r
pxFirstFreeBlockInRegion->pxNextFreeBlock = pxEnd;\r
\r
#endif /* configGENERATE_RUN_TIME_STATS */\r
\r
/* Check for stack overflow, if configured. */\r
- taskFIRST_CHECK_FOR_STACK_OVERFLOW();\r
- taskSECOND_CHECK_FOR_STACK_OVERFLOW();\r
+ taskCHECK_FOR_STACK_OVERFLOW();\r
\r
/* Select a new task to run using either the generic C or port\r
optimised asm code. */\r
#endif /* INCLUDE_vTaskSuspend */\r
\r
traceTASK_NOTIFY_WAIT_BLOCK();\r
- \r
+\r
/* All ports are written to allow a yield in a critical\r
section (some will yield immediately, others wait until the\r
critical section exits) - but it is not something that\r
taskENTER_CRITICAL();\r
{\r
traceTASK_NOTIFY_WAIT();\r
- \r
+\r
if( pulNotificationValue != NULL )\r
{\r
/* Output the current notification value, which may or may not\r
}\r
\r
traceTASK_NOTIFY_FROM_ISR();\r
- \r
+\r
/* If the task is in the blocked state specifically to wait for a\r
notification then unblock it now. */\r
if( eOriginalNotifyState == eWaitingNotification )\r
/* 'Giving' is equivalent to incrementing a count in a counting\r
semaphore. */\r
( pxTCB->ulNotifiedValue )++;\r
- \r
+\r
traceTASK_NOTIFY_GIVE_FROM_ISR();\r
\r
/* If the task is in the blocked state specifically to wait for a\r
\r
/*-----------------------------------------------------------*/\r
\r
+#if( configUSE_TASK_NOTIFICATIONS == 1 )\r
+\r
+ BaseType_t xTaskNotifyStateClear( TaskHandle_t xTask )\r
+ {\r
+ TCB_t *pxTCB;\r
+ BaseType_t xReturn;\r
+\r
+ pxTCB = ( TCB_t * ) xTask;\r
+\r
+ /* If null is passed in here then it is the calling task that is having\r
+ its notification state cleared. */\r
+ pxTCB = prvGetTCBFromHandle( pxTCB );\r
+\r
+ taskENTER_CRITICAL();\r
+ {\r
+ if( pxTCB->eNotifyState == eNotified )\r
+ {\r
+ pxTCB->eNotifyState = eNotWaitingNotification;\r
+ xReturn = pdPASS;\r
+ }\r
+ else\r
+ {\r
+ xReturn = pdFAIL;\r
+ }\r
+ }\r
+ taskEXIT_CRITICAL();\r
+\r
+ return xReturn;\r
+ }\r
+\r
+#endif /* configUSE_TASK_NOTIFICATIONS */\r
\r
#ifdef FREERTOS_MODULE_TEST\r
#include "tasks_test_access_functions.h"\r
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