--- /dev/null
+/*\r
+ FreeRTOS V7.0.1 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+\r
+\r
+ FreeRTOS supports many tools and architectures. V7.0.0 is sponsored by:\r
+ Atollic AB - Atollic provides professional embedded systems development\r
+ tools for C/C++ development, code analysis and test automation.\r
+ See http://www.atollic.com\r
+\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\r
+ *\r
+ * See http://www.freertos.org/a00110.html.\r
+ *----------------------------------------------------------*/\r
+\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 1\r
+#define configUSE_TICK_HOOK 1\r
+#define configCPU_CLOCK_HZ ( 75000000UL )\r
+#define configTICK_RATE_HZ ( ( portTickType ) 1000 )\r
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 90 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 60 * 1024 ) )\r
+#define configMAX_TASK_NAME_LEN ( 10 )\r
+#define configUSE_TRACE_FACILITY 1\r
+#define configUSE_16_BIT_TICKS 0\r
+#define configIDLE_SHOULD_YIELD 1\r
+#define configUSE_MUTEXES 1\r
+#define configQUEUE_REGISTRY_SIZE 0\r
+#define configGENERATE_RUN_TIME_STATS 0\r
+#define configCHECK_FOR_STACK_OVERFLOW 2\r
+#define configUSE_RECURSIVE_MUTEXES 1\r
+#define configUSE_MALLOC_FAILED_HOOK 1\r
+#define configUSE_APPLICATION_TASK_TAG 0\r
+#define configUSE_COUNTING_SEMAPHORES 1\r
+\r
+/* Co-routine definitions. */\r
+#define configUSE_CO_ROUTINES 0\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Software timer definitions. */\r
+#define configUSE_TIMERS 1\r
+#define configTIMER_TASK_PRIORITY ( 2 )\r
+#define configTIMER_QUEUE_LENGTH 10\r
+#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 1\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskCleanUpResources 1\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+\r
+/* Use the system definition, if there is one */\r
+#ifdef __NVIC_PRIO_BITS\r
+ #define configPRIO_BITS __NVIC_PRIO_BITS\r
+#else\r
+ #define configPRIO_BITS 4 /* 15 priority levels */\r
+#endif\r
+\r
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0xf\r
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5\r
+\r
+/* The lowest priority. */\r
+#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )\r
+/* Priority 5, or 160 as only the top three bits are implemented. */\r
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )\r
+ \r
+#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); } \r
+ \r
+#define vPortSVCHandler SVC_Handler\r
+#define xPortPendSVHandler PendSV_Handler\r
+#define xPortSysTickHandler SysTick_Handler\r
+\r
+/* MAC address configuration. */\r
+#define configMAC_ADDR0 0x00\r
+#define configMAC_ADDR1 0x12\r
+#define configMAC_ADDR2 0x13\r
+#define configMAC_ADDR3 0x10\r
+#define configMAC_ADDR4 0x15\r
+#define configMAC_ADDR5 0x11\r
+\r
+/* IP address configuration. */\r
+#define configIP_ADDR0 192\r
+#define configIP_ADDR1 168\r
+#define configIP_ADDR2 0\r
+#define configIP_ADDR3 200\r
+\r
+/* Netmask configuration. */\r
+#define configNET_MASK0 255\r
+#define configNET_MASK1 255\r
+#define configNET_MASK2 255\r
+#define configNET_MASK3 0\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
+\r
--- /dev/null
+/*###ICF### Section handled by ICF editor, don't touch! ****/\r
+/*-Editor annotation file-*/\r
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */\r
+/*-Specials-*/\r
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;\r
+/*-Memory Regions-*/\r
+define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;\r
+define symbol __ICFEDIT_region_ROM_end__ = 0x00080000;\r
+define symbol __ICFEDIT_region_RAM_start__ = 0x1FFF0410;\r
+define symbol __ICFEDIT_region_RAM_end__ = 0x20000000;\r
+/*-Sizes-*/\r
+define symbol __ICFEDIT_size_cstack__ = 0x1000;\r
+define symbol __ICFEDIT_size_heap__ = 0x200;\r
+/**** End of ICF editor section. ###ICF###*/\r
+\r
+define symbol __region_RAM2_start__ = 0x20000000;\r
+define symbol __region_RAM2_end__ = 0x20010000;\r
+\r
+define exported symbol __VECTOR_TABLE = 0x00000000;\r
+define exported symbol __VECTOR_RAM = 0x1fff0000;\r
+\r
+define exported symbol __BOOT_STACK_ADDRESS = __region_RAM2_end__ - 8; //0x2000FFF8;\r
+\r
+define symbol __code_start__ = 0x00000410;\r
+\r
+define memory mem with size = 4G;\r
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];\r
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__] | mem:[from __region_RAM2_start__ to __region_RAM2_end__];\r
+\r
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };\r
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };\r
+\r
+initialize manually { readwrite };\r
+initialize manually { section .data};\r
+initialize manually { section .textrw };\r
+do not initialize { section .noinit };\r
+\r
+define block CodeRelocate { section .textrw_init };\r
+define block CodeRelocateRam { section .textrw };\r
+\r
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };\r
+place at address mem:__code_start__ { readonly section .noinit };\r
+\r
+place in ROM_region { readonly, block CodeRelocate};\r
+\r
+place in RAM_region { readwrite, block CodeRelocateRam,\r
+ block CSTACK, block HEAP };\r
+
\ No newline at end of file
--- /dev/null
+/*\r
+ * File: assert.h\r
+ * Purpose: Provide macro for software assertions\r
+ *\r
+ * Notes: assert_failed() defined in assert.c\r
+ */\r
+\r
+#ifndef _ASSERT_H_\r
+#define _ASSERT_H_\r
+\r
+/********************************************************************/\r
+\r
+void assert_failed(char *, int);\r
+\r
+#ifdef DEBUG_PRINT\r
+#define ASSERT(expr) \\r
+ if (!(expr)) \\r
+ assert_failed(__FILE__, __LINE__)\r
+#else\r
+#define ASSERT(expr)\r
+#endif\r
+\r
+/********************************************************************/\r
+#endif /* _ASSERT_H_ */\r
+\r
--- /dev/null
+/*\r
+ * File: common.h\r
+ * Purpose: File to be included by all project files\r
+ *\r
+ * Notes:\r
+ */\r
+\r
+#ifndef _COMMON_H_\r
+#define _COMMON_H_\r
+\r
+/********************************************************************/\r
+\r
+/*\r
+ * Debug prints ON (#define) or OFF (#undef)\r
+ */\r
+#define DEBUG\r
+#define DEBUG_PRINT\r
+\r
+/*\r
+ * Include the generic CPU header file\r
+ */\r
+#include "arm_cm4.h"\r
+\r
+/*\r
+ * Include the platform specific header file\r
+ */\r
+#if (defined(TWR_K40X256))\r
+ #include "k40_tower.h"\r
+#elif (defined(TWR_K53N512))\r
+ #include "k53_tower.h"\r
+#elif (defined(TWR_K60N512))\r
+ #include "k60_tower.h"\r
+#else\r
+ #error "No valid platform defined"\r
+#endif\r
+\r
+/*\r
+ * Include the cpu specific header file\r
+ */\r
+#if (defined(CPU_MK40N512VMD100))\r
+ #include <freescale/MK40N512VMD100.h>\r
+#elif (defined(CPU_MK53N512VMD100))\r
+ #include <freescale/MK53N512CMD100.h>\r
+#elif (defined(CPU_MK60N512VMD100))\r
+ #include <freescale/MK60N512VMD100.h>\r
+#else\r
+ #error "No valid CPU defined"\r
+#endif\r
+\r
+\r
+/*\r
+ * Include any toolchain specfic header files\r
+ */\r
+#if (defined(CW))\r
+ #include "cw.h"\r
+#elif (defined(IAR))\r
+ #include "iar.h"\r
+#else\r
+#warning "No toolchain specific header included"\r
+#endif\r
+\r
+/*\r
+ * Include common utilities\r
+ */\r
+#include "assert.h"\r
+#include "io.h"\r
+#include "startup.h"\r
+#include "stdlib.h"\r
+\r
+#if (defined(IAR))\r
+ #include "intrinsics.h"\r
+#endif\r
+\r
+/********************************************************************/\r
+\r
+#endif /* _COMMON_H_ */\r
--- /dev/null
+/*\r
+ * File: iar.h\r
+ * Purpose: Define constants used by IAR toolchain\r
+ *\r
+ * Notes: \r
+ *\r
+ */\r
+\r
+#ifndef _IAR_H_\r
+#define _IAR_H_\r
+\r
+/********************************************************************/\r
+\r
+/********************************************************************/\r
+\r
+#endif /* _IAR_H_ */\r
--- /dev/null
+/*\r
+ * File: io.h\r
+ * Purpose: Serial Input/Output routines\r
+ *\r
+ */\r
+\r
+#ifndef _IO_H\r
+#define _IO_H\r
+\r
+/********************************************************************/\r
+\r
+char \r
+in_char(void);\r
+\r
+void\r
+out_char(char);\r
+\r
+int\r
+char_present(void);\r
+\r
+int \r
+printf(const char *, ... );\r
+\r
+int\r
+sprintf(char *, const char *, ... );\r
+\r
+/********************************************************************/\r
+\r
+#endif\r
--- /dev/null
+/*\r
+ * File: queue.h\r
+ * Purpose: Implement a first in, first out linked list\r
+ *\r
+ * Notes:\r
+ */\r
+\r
+#ifndef _QUEUE_H_\r
+#define _QUEUE_H_\r
+\r
+/********************************************************************/\r
+\r
+/* \r
+ * Individual queue node\r
+ */\r
+typedef struct NODE\r
+{\r
+ struct NODE *next;\r
+} QNODE;\r
+\r
+/* \r
+ * Queue Struture - linked list of qentry items \r
+ */\r
+typedef struct\r
+{\r
+ QNODE *head;\r
+ QNODE *tail;\r
+} QUEUE;\r
+\r
+/*\r
+ * Functions provided by queue.c\r
+ */\r
+void\r
+queue_init(QUEUE *);\r
+\r
+int\r
+queue_isempty(QUEUE *);\r
+\r
+void\r
+queue_add(QUEUE *, QNODE *);\r
+\r
+QNODE*\r
+queue_remove(QUEUE *);\r
+\r
+QNODE*\r
+queue_peek(QUEUE *);\r
+\r
+void\r
+queue_move(QUEUE *, QUEUE *);\r
+\r
+/********************************************************************/\r
+\r
+#endif /* _QUEUE_H_ */\r
--- /dev/null
+/*\r
+ * File: startup.c\r
+ * Purpose: Generic Kinetis startup code\r
+ *\r
+ * Notes:\r
+ */\r
+\r
+#include "common.h"\r
+\r
+#if (defined(IAR))\r
+ #pragma section = ".data"\r
+ #pragma section = ".data_init"\r
+ #pragma section = ".bss"\r
+ #pragma section = "CodeRelocate"\r
+ #pragma section = "CodeRelocateRam"\r
+#endif\r
+\r
+/********************************************************************/\r
+void\r
+common_startup(void)\r
+{\r
+\r
+#if (defined(CW)) \r
+ extern char __START_BSS[];\r
+ extern char __END_BSS[];\r
+ extern uint32 __DATA_ROM[];\r
+ extern uint32 __DATA_RAM[];\r
+ extern char __DATA_END[];\r
+#endif\r
+\r
+ /* Declare a counter we'll use in all of the copy loops */\r
+ uint32 n;\r
+\r
+ /* Declare pointers for various data sections. These pointers\r
+ * are initialized using values pulled in from the linker file\r
+ */\r
+ uint8 * data_ram, * data_rom, * data_rom_end;\r
+ uint8 * bss_start, * bss_end;\r
+\r
+\r
+ /* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */\r
+ extern uint32 __VECTOR_TABLE[];\r
+ extern uint32 __VECTOR_RAM[];\r
+\r
+ /* Copy the vector table to RAM */\r
+ if (__VECTOR_RAM != __VECTOR_TABLE)\r
+ {\r
+ for (n = 0; n < 0x410; n++)\r
+ __VECTOR_RAM[n] = __VECTOR_TABLE[n];\r
+ }\r
+ /* Point the VTOR to the new copy of the vector table */\r
+ write_vtor((uint32)__VECTOR_RAM);\r
+\r
+ /* Get the addresses for the .data section (initialized data section) */\r
+ #if (defined(CW))\r
+ data_ram = (uint8 *)__DATA_RAM;\r
+ data_rom = (uint8 *)__DATA_ROM;\r
+ data_rom_end = (uint8 *)__DATA_END; /* This is actually a RAM address in CodeWarrior */\r
+ n = data_rom_end - data_ram;\r
+ #elif (defined(IAR))\r
+ data_ram = __section_begin(".data");\r
+ data_rom = __section_begin(".data_init");\r
+ data_rom_end = __section_end(".data_init");\r
+ n = data_rom_end - data_rom;\r
+ #endif \r
+ \r
+ /* Copy initialized data from ROM to RAM */\r
+ while (n--)\r
+ *data_ram++ = *data_rom++;\r
+ \r
+ \r
+ /* Get the addresses for the .bss section (zero-initialized data) */\r
+ #if (defined(CW))\r
+ bss_start = (uint8 *)__START_BSS;\r
+ bss_end = (uint8 *)__END_BSS;\r
+ #elif (defined(IAR))\r
+ bss_start = __section_begin(".bss");\r
+ bss_end = __section_end(".bss");\r
+ #endif\r
+ \r
+ \r
+ \r
+\r
+ /* Clear the zero-initialized data section */\r
+ n = bss_end - bss_start;\r
+ while(n--)\r
+ *bss_start++ = 0;\r
+\r
+ /* Get addresses for any code sections that need to be copied from ROM to RAM.\r
+ * The IAR tools have a predefined keyword that can be used to mark individual\r
+ * functions for execution from RAM. Add "__ramfunc" before the return type in\r
+ * the function prototype for any routines you need to execute from RAM instead\r
+ * of ROM. ex: __ramfunc void foo(void);\r
+ */\r
+ #if (defined(IAR))\r
+ uint8* code_relocate_ram = __section_begin("CodeRelocateRam");\r
+ uint8* code_relocate = __section_begin("CodeRelocate");\r
+ uint8* code_relocate_end = __section_end("CodeRelocate");\r
+\r
+ /* Copy functions from ROM to RAM */\r
+ n = code_relocate_end - code_relocate;\r
+ while (n--)\r
+ *code_relocate_ram++ = *code_relocate++;\r
+ #endif\r
+}\r
+/********************************************************************/\r
--- /dev/null
+/*\r
+ * File: startup.h\r
+ * Purpose: Determine cause of Reset and which processor is running\r
+ *\r
+ * Notes: \r
+ */\r
+\r
+#ifndef _STARTUP_H_\r
+#define _STARTUP_H_\r
+\r
+/********************************************************************/\r
+\r
+void common_startup(void);\r
+\r
+/********************************************************************/\r
+\r
+#endif /* _STARTUP_H_ */\r
--- /dev/null
+/*\r
+ * File: arm_cm4.c\r
+ * Purpose: Generic high-level routines for ARM Cortex M4 processors\r
+ *\r
+ * Notes:\r
+ */\r
+\r
+#include "common.h"\r
+\r
+/***********************************************************************/\r
+/*\r
+ * Configures the ARM system control register for STOP (deep sleep) mode\r
+ * and then executes the WFI instruction to enter the mode.\r
+ *\r
+ * Parameters:\r
+ * none\r
+ *\r
+ * Note: Might want to change this later to allow for passing in a parameter\r
+ * to optionally set the sleep on exit bit.\r
+ */\r
+\r
+void stop (void)\r
+{\r
+ /* Set the SLEEPDEEP bit to enable deep sleep mode (STOP) */\r
+ SCB_SCR |= SCB_SCR_SLEEPDEEP_MASK; \r
+\r
+ /* WFI instruction will start entry into STOP mode */\r
+ asm("WFI");\r
+}\r
+/***********************************************************************/\r
+/*\r
+ * Configures the ARM system control register for WAIT (sleep) mode\r
+ * and then executes the WFI instruction to enter the mode.\r
+ *\r
+ * Parameters:\r
+ * none\r
+ *\r
+ * Note: Might want to change this later to allow for passing in a parameter\r
+ * to optionally set the sleep on exit bit.\r
+ */\r
+\r
+void wait (void)\r
+{\r
+ /* Clear the SLEEPDEEP bit to make sure we go into WAIT (sleep) mode instead\r
+ * of deep sleep.\r
+ */\r
+ SCB_SCR &= ~SCB_SCR_SLEEPDEEP_MASK; \r
+\r
+ /* WFI instruction will start entry into WAIT mode */\r
+ asm("WFI");\r
+}\r
+/***********************************************************************/\r
+/*\r
+ * Change the value of the vector table offset register to the specified value.\r
+ *\r
+ * Parameters:\r
+ * vtor new value to write to the VTOR\r
+ */\r
+\r
+void write_vtor (int vtor)\r
+{\r
+ /* Write the VTOR with the new value */\r
+ SCB_VTOR = vtor; \r
+}\r
+/***********************************************************************/\r
+/*\r
+ * Initialize the NVIC to enable the specified IRQ.\r
+ * \r
+ * NOTE: The function only initializes the NVIC to enable a single IRQ. \r
+ * Interrupts will also need to be enabled in the ARM core. This can be \r
+ * done using the EnableInterrupts macro.\r
+ *\r
+ * Parameters:\r
+ * irq irq number to be enabled (the irq number NOT the vector number)\r
+ */\r
+\r
+void enable_irq (int irq)\r
+{\r
+ int div;\r
+ \r
+ /* Make sure that the IRQ is an allowable number. Right now up to 91 is \r
+ * used.\r
+ */\r
+ if (irq > 91)\r
+ printf("\nERR! Invalid IRQ value passed to enable irq function!\n");\r
+ \r
+ /* Determine which of the NVICISERs corresponds to the irq */\r
+ div = irq/32;\r
+ \r
+ switch (div)\r
+ {\r
+ case 0x0:\r
+ NVICICPR0 = 1 << (irq%32);\r
+ NVICISER0 = 1 << (irq%32);\r
+ break;\r
+ case 0x1:\r
+ NVICICPR1 = 1 << (irq%32);\r
+ NVICISER1 = 1 << (irq%32);\r
+ break;\r
+ case 0x2:\r
+ NVICICPR2 = 1 << (irq%32);\r
+ NVICISER2 = 1 << (irq%32);\r
+ break;\r
+ } \r
+}\r
+/***********************************************************************/\r
+/*\r
+ * Initialize the NVIC to disable the specified IRQ.\r
+ * \r
+ * NOTE: The function only initializes the NVIC to disable a single IRQ. \r
+ * If you want to disable all interrupts, then use the DisableInterrupts\r
+ * macro instead. \r
+ *\r
+ * Parameters:\r
+ * irq irq number to be disabled (the irq number NOT the vector number)\r
+ */\r
+\r
+void disable_irq (int irq)\r
+{\r
+ int div;\r
+ \r
+ /* Make sure that the IRQ is an allowable number. Right now up to 91 is \r
+ * used.\r
+ */\r
+ if (irq > 91)\r
+ printf("\nERR! Invalid IRQ value passed to disable irq function!\n");\r
+ \r
+ /* Determine which of the NVICICERs corresponds to the irq */\r
+ div = irq/32;\r
+ \r
+ switch (div)\r
+ {\r
+ case 0x0:\r
+ NVICICER0 = 1 << (irq%32);\r
+ break;\r
+ case 0x1:\r
+ NVICICER1 = 1 << (irq%32);\r
+ break;\r
+ case 0x2:\r
+ NVICICER2 = 1 << (irq%32);\r
+ break;\r
+ } \r
+}\r
+/***********************************************************************/\r
+/*\r
+ * Initialize the NVIC to set specified IRQ priority.\r
+ * \r
+ * NOTE: The function only initializes the NVIC to set a single IRQ priority. \r
+ * Interrupts will also need to be enabled in the ARM core. This can be \r
+ * done using the EnableInterrupts macro.\r
+ *\r
+ * Parameters:\r
+ * irq irq number to be enabled (the irq number NOT the vector number)\r
+ * prio irq priority. 0-15 levels. 0 max priority\r
+ */\r
+\r
+void set_irq_priority (int irq, int prio)\r
+{\r
+ /*irq priority pointer*/\r
+ uint8 *prio_reg;\r
+ \r
+ /* Make sure that the IRQ is an allowable number. Right now up to 91 is \r
+ * used.\r
+ */\r
+ if (irq > 91)\r
+ printf("\nERR! Invalid IRQ value passed to priority irq function!\n");\r
+\r
+ if (prio > 15)\r
+ printf("\nERR! Invalid priority value passed to priority irq function!\n");\r
+ \r
+ /* Determine which of the NVICIPx corresponds to the irq */\r
+ prio_reg = (uint8 *)(((uint32)&NVICIP0) + irq);\r
+ /* Assign priority to IRQ */\r
+ *prio_reg = ( (prio&0xF) << (8 - ARM_INTERRUPT_LEVEL_BITS) ); \r
+}\r
+/***********************************************************************/\r
+\r
--- /dev/null
+/*\r
+ * File: arm_cm4.h\r
+ * Purpose: Definitions common to all ARM Cortex M4 processors\r
+ *\r
+ * Notes:\r
+ */\r
+\r
+#ifndef _CPU_ARM_CM4_H\r
+#define _CPU_ARM_CM4_H\r
+\r
+#include "common.h"\r
+\r
+/*ARM Cortex M4 implementation for interrupt priority shift*/\r
+#define ARM_INTERRUPT_LEVEL_BITS 4\r
+\r
+/***********************************************************************/\r
+// function prototypes for arm_cm4.c\r
+void stop (void);\r
+void wait (void);\r
+void write_vtor (int);\r
+void enable_irq (int);\r
+void disable_irq (int);\r
+void set_irq_priority (int, int);\r
+\r
+/***********************************************************************/\r
+ /*!< Macro to enable all interrupts. */\r
+#define EnableInterrupts asm(" CPSIE i");\r
+\r
+ /*!< Macro to disable all interrupts. */\r
+#define DisableInterrupts asm(" CPSID i");\r
+/***********************************************************************/\r
+\r
+\r
+/*\r
+ * Misc. Defines\r
+ */\r
+#ifdef FALSE\r
+#undef FALSE\r
+#endif\r
+#define FALSE (0)\r
+\r
+#ifdef TRUE\r
+#undef TRUE\r
+#endif\r
+#define TRUE (1)\r
+\r
+#ifdef NULL\r
+#undef NULL\r
+#endif\r
+#define NULL (0)\r
+\r
+#ifdef ON\r
+#undef ON\r
+#endif\r
+#define ON (1)\r
+\r
+#ifdef OFF\r
+#undef OFF\r
+#endif\r
+#define OFF (0)\r
+\r
+/***********************************************************************/\r
+/*\r
+ * The basic data types\r
+ */\r
+typedef unsigned char uint8; /* 8 bits */\r
+typedef unsigned short int uint16; /* 16 bits */\r
+typedef unsigned long int uint32; /* 32 bits */\r
+\r
+typedef char int8; /* 8 bits */\r
+typedef short int int16; /* 16 bits */\r
+typedef int int32; /* 32 bits */\r
+\r
+typedef volatile int8 vint8; /* 8 bits */\r
+typedef volatile int16 vint16; /* 16 bits */\r
+typedef volatile int32 vint32; /* 32 bits */\r
+\r
+typedef volatile uint8 vuint8; /* 8 bits */\r
+typedef volatile uint16 vuint16; /* 16 bits */\r
+typedef volatile uint32 vuint32; /* 32 bits */\r
+\r
+// function prototype for main function\r
+void main(void);\r
+\r
+/***********************************************************************/\r
+#endif /* _CPU_ARM_CM4_H */\r
+\r
--- /dev/null
+/*\r
+ * File: crt0.s\r
+ * Purpose: Lowest level routines for Kinetis.\r
+ *\r
+ * Notes: \r
+ *\r
+ */\r
+\r
+; AREA Crt0, CODE, READONLY ; name this block of code\r
+\r
+\r
+\r
+ SECTION .noinit : CODE\r
+ EXPORT __startup\r
+__startup\r
+\r
+ MOV r0,#0 ; Initialize the GPRs\r
+ MOV r1,#0\r
+ MOV r2,#0\r
+ MOV r3,#0\r
+ MOV r4,#0\r
+ MOV r5,#0\r
+ MOV r6,#0\r
+ MOV r7,#0\r
+ MOV r8,#0\r
+ MOV r9,#0\r
+ MOV r10,#0\r
+ MOV r11,#0\r
+ MOV r12,#0\r
+ CPSIE i ; Unmask interrupts\r
+ import start\r
+ BL start ; call the C code\r
+__done\r
+ B __done\r
+\r
+\r
+ END\r
--- /dev/null
+/*\r
+ * File: dma_channels.h\r
+ * Purpose: DMA request macros for use on Kinetis processors.\r
+ * This file gives default DMA channel assignments\r
+ * for all of the possible Kinetis module DMA requests.\r
+ *\r
+ *\r
+ * Notes: There are more DMA requests than DMA channels, so\r
+ * care should be taken to make sure that DMA channel\r
+ * assignments are unique for the modules that are \r
+ * being used at any time. \r
+ */\r
+\r
+#ifndef _DMA_CHANNELS_H\r
+#define _DMA_CHANNELS_H\r
+\r
+/********************************************************************/\r
+/* NOTE: There are more DMA requests than DMA channels, so\r
+ * care should be taken to make sure that DMA channel\r
+ * assignments are unique for the modules that are \r
+ * being used at any time. \r
+ * \r
+ * It is recommended that you read the appropriate DMAMUX_CHCFGn\r
+ * register before updating it to verify it is 0x0. If the\r
+ * DMAMUX_CHCFGn register is not zero, then that indicates the \r
+ * selected DMA channel might already be in use by another peripheral\r
+ * (a more specific test would be to look for DMAMUX_CHCFGn[ENBL] set).\r
+ * The module's DMA configuration routine can return an error\r
+ * when this situation is detected.\r
+ */\r
+ \r
+ \r
+/* Default DMA channel assignments and module request macros */\r
+\r
+/* UARTs */\r
+#define DMA_UART0RX_CH 0\r
+#define DMA_UART0TX_CH 1\r
+\r
+#define DMA_UART1RX_CH 2\r
+#define DMA_UART1TX_CH 3\r
+\r
+#define DMA_UART2RX_CH 10\r
+#define DMA_UART2TX_CH 11\r
+\r
+#define DMA_UART3RX_CH 12\r
+#define DMA_UART3TX_CH 13\r
+\r
+#define DMA_UART4RX_CH 6\r
+#define DMA_UART4TX_CH 7\r
+\r
+#define DMA_UART5RX_CH 8\r
+#define DMA_UART5TX_CH 9\r
+\r
+/* SSI/SAI */\r
+#define DMA_SSI0RX_CH 4\r
+#define DMA_SSI0TX_CH 5\r
+\r
+/* DSPIs */\r
+#define DMA_DSPI0RX_CH 6\r
+#define DMA_DSPI0TX_CH 7\r
+\r
+#define DMA_DSPI1RX_CH 8\r
+#define DMA_DSPI1TX_CH 9\r
+\r
+#define DMA_DSPI2RX_CH 14\r
+#define DMA_DSPI2TX_CH 15\r
+\r
+/* I2Cs */\r
+#define DMA_I2C0_CH 7\r
+#define DMA_I2C1_CH 2\r
+\r
+/* FTMs */\r
+#define DMA_FTM0CH0_CH 5\r
+#define DMA_FTM0CH1_CH 6\r
+#define DMA_FTM0CH2_CH 3\r
+#define DMA_FTM0CH3_CH 4\r
+#define DMA_FTM0CH4_CH 12\r
+#define DMA_FTM0CH5_CH 13\r
+#define DMA_FTM0CH6_CH 14\r
+#define DMA_FTM0CH7_CH 15\r
+\r
+#define DMA_FTM1CH0_CH 10\r
+#define DMA_FTM1CH1_CH 11\r
+\r
+#define DMA_FTM2CH0_CH 0\r
+#define DMA_FTM2CH1_CH 1\r
+\r
+/* Ethernet timers */\r
+#define DMA_ENETTMR0_CH 4\r
+#define DMA_ENETTMR1_CH 8\r
+#define DMA_ENETTMR2_CH 0\r
+#define DMA_ENETTMR3_CH 15\r
+\r
+/* ADCs */\r
+#define DMA_ADC0_CH 12\r
+#define DMA_ADC1_CH 3\r
+\r
+/* HSCMPs */\r
+#define DMA_HSCMP0_CH 13\r
+#define DMA_HSCMP1_CH 2\r
+#define DMA_HSCMP2_CH 9\r
+\r
+/* 12-bit DAC */\r
+#define DMA_12bDAC0_CH 14\r
+\r
+/* CMT */\r
+#define DMA_CMT_CH 5\r
+\r
+/* PDB */\r
+#define DMA_PDB_CH 10\r
+\r
+/* GPIO Ports */\r
+#define DMA_GPIOPORTA_CH 15\r
+#define DMA_GPIOPORTB_CH 0\r
+#define DMA_GPIOPORTC_CH 1\r
+#define DMA_GPIOPORTD_CH 11\r
+#define DMA_GPIOPORTE_CH 8\r
+\r
+/********************************************************************/\r
+\r
+#endif /* _DMA_CHANNELS_H */\r
--- /dev/null
+/*\r
+ * File: k60_tower.h\r
+ * Purpose: Definitions for the Kinetis K60 tower card\r
+ *\r
+ * Notes:\r
+ */\r
+\r
+#ifndef __K60_TOWER_H__\r
+#define __K60_TOWER_H__\r
+\r
+#include "mcg.h"\r
+\r
+/********************************************************************/\r
+\r
+/* Global defines to use for all boards */\r
+#define DEBUG_PRINT\r
+\r
+\r
+\r
+/* Defines specific to the K60 tower board */\r
+\r
+\r
+/* Define for the CPU on the K60 board */\r
+#define CPU_MK60N512VMD100\r
+\r
+/*\r
+ * System Bus Clock Info\r
+ */\r
+#define K60_CLK 1\r
+#define REF_CLK XTAL8 /* value isn't used, but we still need something defined */\r
+#define CORE_CLK_MHZ PLL96 /* 96MHz is only freq tested for a clock input*/\r
+\r
+/*\r
+ * Serial Port Info\r
+ */\r
+\r
+/* \r
+ * Select the serial port that is being used below. Only one of the \r
+ * options should be uncommented at any time.\r
+ */\r
+//#define SERIAL_CARD // use this option for serial port on TWR-SER\r
+#define OSJTAG // use this option for serial port over the OS-JTAG circuit\r
+\r
+#if (defined(SERIAL_CARD))\r
+ #define TERM_PORT UART3_BASE_PTR\r
+ #define TERMINAL_BAUD 115200\r
+ #undef HW_FLOW_CONTROL\r
+#elif (defined(OSJTAG))\r
+ #define TERM_PORT UART5_BASE_PTR\r
+ #define TERMINAL_BAUD 115200\r
+ #undef HW_FLOW_CONTROL\r
+#else\r
+ #error "No valid serial port defined"\r
+#endif\r
+\r
+\r
+#endif /* __K60_TOWER_H__ */\r
--- /dev/null
+/********************************************************************************/\r
+/* FILENAME RegisterFile.h */\r
+/* The current release of the documentation and header files does not include\r
+ * the system register file or the VBAT register file. This header file\r
+ * adds support for accessing both register files. \r
+ * \r
+ * Once the manual is updated to include the register files, this file\r
+ * will become obsolete. \r
+ */\r
+/********************************************************************************/\r
+\r
+/* Register File - Peripheral instance base addresses */\r
+/* Peripheral System Register File base pointer */\r
+#define RFSYS_DATA_BASE_PTR ((RFDATA_MemMapPtr)0x40041000u)\r
+/* Peripheral VBAT Register File base pointer */\r
+#define RFVBAT_DATA_BASE_PTR ((RFDATA_MemMapPtr)0x4003E000u)\r
+\r
+ typedef struct RFDATA_MemMap {\r
+ uint32_t RFDATA [32]; /*!< Register file n, array offset: 0x0, array step: 0x4 */\r
+ \r
+ \r
+} volatile *RFDATA_MemMapPtr;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- Register file - Register accessor macros\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/* Register file - Register accessors */\r
+#define RFSYS_DATA_REG(base,index) ((base)->RFDATA[index])\r
+#define RFVBAT_DATA_REG(base,index) ((base)->RFDATA[index])\r
+\r
+#define RFSYS_DATA0 RFSYS_DATA_REG(RFSYS_DATA_BASE_PTR,0 )\r
+#define RFSYS_DATA1 RFSYS_DATA_REG(RFSYS_DATA_BASE_PTR,1 )\r
+#define RFSYS_DATA2 RFSYS_DATA_REG(RFSYS_DATA_BASE_PTR,2 )\r
+#define RFSYS_DATA3 RFSYS_DATA_REG(RFSYS_DATA_BASE_PTR,3 )\r
+#define RFSYS_DATA4 RFSYS_DATA_REG(RFSYS_DATA_BASE_PTR,4 )\r
+#define RFSYS_DATA5 RFSYS_DATA_REG(RFSYS_DATA_BASE_PTR,5 )\r
+#define RFSYS_DATA6 RFSYS_DATA_REG(RFSYS_DATA_BASE_PTR,6 )\r
+#define RFSYS_DATA7 RFSYS_DATA_REG(RFSYS_DATA_BASE_PTR,7 )\r
+\r
+#define RFVBAT_DATA0 RFVBAT_DATA_REG(RFVBAT_DATA_BASE_PTR,0 )\r
+#define RFVBAT_DATA1 RFVBAT_DATA_REG(RFVBAT_DATA_BASE_PTR,1 )\r
+#define RFVBAT_DATA2 RFVBAT_DATA_REG(RFVBAT_DATA_BASE_PTR,2 )\r
+#define RFVBAT_DATA3 RFVBAT_DATA_REG(RFVBAT_DATA_BASE_PTR,3 )\r
+#define RFVBAT_DATA4 RFVBAT_DATA_REG(RFVBAT_DATA_BASE_PTR,4 )\r
+#define RFVBAT_DATA5 RFVBAT_DATA_REG(RFVBAT_DATA_BASE_PTR,5 )\r
+#define RFVBAT_DATA6 RFVBAT_DATA_REG(RFVBAT_DATA_BASE_PTR,6 )\r
+#define RFVBAT_DATA7 RFVBAT_DATA_REG(RFVBAT_DATA_BASE_PTR,7 )\r
+ \r
+\r
+/* LL Bit Fields */\r
+#define RF_DATA_LL_MASK 0x000000FFu\r
+#define RF_DATA_LL_SHIFT 0\r
+#define RF_DATA_LL(x) (((x)<<RF_DATA_LL_SHIFT)&RF_DATA_LL_MASK)\r
+/* LH Bit Fields */ \r
+#define RF_DATA_LH_MASK 0x0000FF00u\r
+#define RF_DATA_LH_SHIFT 8\r
+#define RF_DATA_LH(x) (((x)<<RF_DATA_LH_SHIFT)&RF_DATA_LH_MASK)\r
+/* HL Bit Fields */\r
+#define RF_DATA_HL_MASK 0x00FF0000u\r
+#define RF_DATA_HL_SHIFT 16\r
+#define RF_DATA_HL(x) (((x)<<RF_DATA_HL_SHIFT)&RF_DATA_HL_MASK)\r
+/* HH Bit Fields */\r
+#define RF_DATA_HH_MASK 0xFF000000u\r
+#define RF_DATA_HH_SHIFT 24\r
+#define RF_DATA_HH(x) (((x)<<RF_DATA_HH_SHIFT)&RF_DATA_HH_MASK)\r
+\r
+\r
+/*! \} */ /* end of group Register_File_Register_Accessor_Macros */\r
--- /dev/null
+/*\r
+ * File: start.c\r
+ * Purpose: Kinetis start up routines. \r
+ *\r
+ * Notes: \r
+ */\r
+\r
+#include "start.h"\r
+#include "common.h"\r
+#include "wdog.h"\r
+#include "sysinit.h"\r
+\r
+/********************************************************************/\r
+/*!\r
+ * \brief Kinetis Start\r
+ * \return None\r
+ *\r
+ * This function calls all of the needed starup routines and then \r
+ * branches to the main process.\r
+ */\r
+void start(void)\r
+{\r
+ /* Disable the watchdog timer */\r
+ wdog_disable();\r
+\r
+ /* Copy any vector or data sections that need to be in RAM */\r
+ common_startup();\r
+\r
+ /* Perform processor initialization */\r
+ sysinit();\r
+ \r
+ printf("\n\n");\r
+ \r
+ /* Determine the last cause(s) of reset */\r
+ if (MC_SRSH & MC_SRSH_SW_MASK)\r
+ printf("Software Reset\n");\r
+ if (MC_SRSH & MC_SRSH_LOCKUP_MASK)\r
+ printf("Core Lockup Event Reset\n");\r
+ if (MC_SRSH & MC_SRSH_JTAG_MASK)\r
+ printf("JTAG Reset\n");\r
+ \r
+ if (MC_SRSL & MC_SRSL_POR_MASK)\r
+ printf("Power-on Reset\n");\r
+ if (MC_SRSL & MC_SRSL_PIN_MASK)\r
+ printf("External Pin Reset\n");\r
+ if (MC_SRSL & MC_SRSL_COP_MASK)\r
+ printf("Watchdog(COP) Reset\n");\r
+ if (MC_SRSL & MC_SRSL_LOC_MASK)\r
+ printf("Loss of Clock Reset\n");\r
+ if (MC_SRSL & MC_SRSL_LVD_MASK)\r
+ printf("Low-voltage Detect Reset\n");\r
+ if (MC_SRSL & MC_SRSL_WAKEUP_MASK)\r
+ printf("LLWU Reset\n"); \r
+ \r
+\r
+ /* Determine specific Kinetis device and revision */\r
+ cpu_identify();\r
+ \r
+ /* Jump to main process */\r
+ main();\r
+\r
+ /* No actions to perform after this so wait forever */\r
+ while(1);\r
+}\r
+/********************************************************************/\r
+/*!\r
+ * \brief Kinetis Identify\r
+ * \return None\r
+ *\r
+ * This is primarly a reporting function that displays information\r
+ * about the specific CPU to the default terminal including:\r
+ * - Kinetis family\r
+ * - package\r
+ * - die revision\r
+ * - P-flash size\r
+ * - Ram size\r
+ */\r
+void cpu_identify (void)\r
+{\r
+ /* Determine the Kinetis family */\r
+ switch((SIM_SDID & SIM_SDID_FAMID(0x7))>>SIM_SDID_FAMID_SHIFT) \r
+ { \r
+ case 0x0:\r
+ printf("\nK10-");\r
+ break;\r
+ case 0x1:\r
+ printf("\nK20-");\r
+ break;\r
+ case 0x2:\r
+ printf("\nK30-");\r
+ break;\r
+ case 0x3:\r
+ printf("\nK40-");\r
+ break;\r
+ case 0x4:\r
+ printf("\nK60-");\r
+ break;\r
+ case 0x5:\r
+ printf("\nK70-");\r
+ break;\r
+ case 0x6:\r
+ printf("\nK50-");\r
+ break;\r
+ case 0x7:\r
+ printf("\nK53-");\r
+ break;\r
+ default:\r
+ printf("\nUnrecognized Kinetis family device.\n"); \r
+ break; \r
+ }\r
+\r
+ /* Determine the package size */\r
+ switch((SIM_SDID & SIM_SDID_PINID(0xF))>>SIM_SDID_PINID_SHIFT) \r
+ { \r
+ case 0x2:\r
+ printf("32pin ");\r
+ break;\r
+ case 0x4:\r
+ printf("48pin ");\r
+ break;\r
+ case 0x5:\r
+ printf("64pin ");\r
+ break;\r
+ case 0x6:\r
+ printf("80pin ");\r
+ break;\r
+ case 0x7:\r
+ printf("81pin ");\r
+ break;\r
+ case 0x8:\r
+ printf("100pin ");\r
+ break;\r
+ case 0x9:\r
+ printf("104pin ");\r
+ break;\r
+ case 0xA:\r
+ printf("144pin ");\r
+ break;\r
+ case 0xC:\r
+ printf("196pin ");\r
+ break;\r
+ case 0xE:\r
+ printf("256pin ");\r
+ break;\r
+ default:\r
+ printf("\nUnrecognized Kinetis package code. "); \r
+ break; \r
+ } \r
+\r
+ /* Determine the revision ID */\r
+ printf("Silicon rev %d \n", (SIM_SDID & SIM_SDID_REVID(0xF))>>SIM_SDID_REVID_SHIFT);\r
+ \r
+ \r
+ /* Determine the flash revision */\r
+ flash_identify(); \r
+ \r
+ /* Determine the P-flash size */\r
+ switch((SIM_FCFG1 & SIM_FCFG1_FSIZE(0xFF))>>SIM_FCFG1_FSIZE_SHIFT)\r
+ {\r
+ case 0x0:\r
+ printf("12 kBytes of P-flash ");\r
+ break;\r
+ case 0x1:\r
+ printf("16 kBytes of P-flash ");\r
+ break;\r
+ case 0x2:\r
+ printf("32 kBytes of P-flash ");\r
+ break;\r
+ case 0x3:\r
+ printf("48 kBytes of P-flash ");\r
+ break;\r
+ case 0x4:\r
+ printf("64 kBytes of P-flash ");\r
+ break;\r
+ case 0x5:\r
+ printf("96 kBytes of P-flash ");\r
+ break;\r
+ case 0x6:\r
+ printf("128 kBytes of P-flash ");\r
+ break;\r
+ case 0x7:\r
+ printf("192 kBytes of P-flash ");\r
+ break;\r
+ case 0x8:\r
+ printf("256 kBytes of P-flash ");\r
+ break;\r
+ case 0x9:\r
+ printf("320 kBytes of P-flash ");\r
+ break;\r
+ case 0xA:\r
+ printf("384 kBytes of P-flash ");\r
+ break;\r
+ case 0xB:\r
+ printf("448 kBytes of P-flash ");\r
+ break;\r
+ case 0xC:\r
+ printf("512 kBytes of P-flash ");\r
+ break;\r
+ case 0xFF:\r
+ printf("Full size P-flash ");\r
+ break;\r
+ default:\r
+ printf("ERR!! Undefined P-flash size\n"); \r
+ break; \r
+ }\r
+\r
+ /* Determine the RAM size */\r
+ switch((SIM_SOPT1 & SIM_SOPT1_RAMSIZE(0xF))>>SIM_SOPT1_RAMSIZE_SHIFT)\r
+ {\r
+ case 0x5:\r
+ printf(" 32 kBytes of RAM\n\n");\r
+ break;\r
+ case 0x7:\r
+ printf(" 64 kBytes of RAM\n\n");\r
+ break;\r
+ case 0x8:\r
+ printf(" 96 kBytes of RAM\n\n");\r
+ break;\r
+ case 0x9:\r
+ printf(" 128 kBytes of RAM\n\n");\r
+ break;\r
+ default:\r
+ printf(" ERR!! Undefined RAM size\n\n"); \r
+ break; \r
+ }\r
+}\r
+/********************************************************************/\r
+/*!\r
+ * \brief flash Identify\r
+ * \return None\r
+ *\r
+ * This is primarly a reporting function that displays information\r
+ * about the specific flash parameters and flash version ID for \r
+ * the current device. These parameters are obtained using a special\r
+ * flash command call "read resource." The first four bytes returned\r
+ * are the flash parameter revision, and the second four bytes are\r
+ * the flash version ID.\r
+ */\r
+void flash_identify (void)\r
+{\r
+ /* Get the flash parameter version */\r
+\r
+ /* Write the flash FCCOB registers with the values for a read resource command */\r
+ FTFL_FCCOB0 = 0x03;\r
+ FTFL_FCCOB1 = 0x00;\r
+ FTFL_FCCOB2 = 0x00;\r
+ FTFL_FCCOB3 = 0x00;\r
+ FTFL_FCCOB8 = 0x01;\r
+\r
+ /* All required FCCOBx registers are written, so launch the command */\r
+ FTFL_FSTAT = FTFL_FSTAT_CCIF_MASK;\r
+\r
+ /* Wait for the command to complete */\r
+ while(!(FTFL_FSTAT & FTFL_FSTAT_CCIF_MASK));\r
+ \r
+ printf("Flash parameter version %d.%d.%d.%d\n",FTFL_FCCOB4,FTFL_FCCOB5,FTFL_FCCOB6,FTFL_FCCOB7);\r
+\r
+ /* Get the flash version ID */ \r
+\r
+ /* Write the flash FCCOB registers with the values for a read resource command */\r
+ FTFL_FCCOB0 = 0x03;\r
+ FTFL_FCCOB1 = 0x00;\r
+ FTFL_FCCOB2 = 0x00;\r
+ FTFL_FCCOB3 = 0x04;\r
+ FTFL_FCCOB8 = 0x01;\r
+\r
+ /* All required FCCOBx registers are written, so launch the command */\r
+ FTFL_FSTAT = FTFL_FSTAT_CCIF_MASK;\r
+\r
+ /* Wait for the command to complete */\r
+ while(!(FTFL_FSTAT & FTFL_FSTAT_CCIF_MASK));\r
+\r
+ printf("Flash version ID %d.%d.%d.%d\n",FTFL_FCCOB4,FTFL_FCCOB5,FTFL_FCCOB6,FTFL_FCCOB7); \r
+}\r
+/********************************************************************/\r
+\r
--- /dev/null
+/*\r
+ * File: start.h\r
+ * Purpose: Kinetis start up routines. \r
+ *\r
+ * Notes: \r
+ */\r
+\r
+\r
+// Function prototypes\r
+void _start(void);\r
+void cpu_identify(void);\r
+void flash_identify(void);\r
--- /dev/null
+/*\r
+ * File: sysinit.c\r
+ * Purpose: Kinetis Configuration\r
+ * Initializes processor to a default state\r
+ *\r
+ * Notes:\r
+ *\r
+ */\r
+\r
+#include "common.h"\r
+#include "sysinit.h"\r
+#include "uart.h"\r
+\r
+/********************************************************************/\r
+\r
+/* Actual system clock frequency */\r
+int core_clk_khz;\r
+int core_clk_mhz;\r
+int periph_clk_khz;\r
+\r
+/********************************************************************/\r
+void sysinit (void)\r
+{\r
+ /*\r
+ * Enable all of the port clocks. These have to be enabled to configure\r
+ * pin muxing options, so most code will need all of these on anyway.\r
+ */\r
+ SIM_SCGC5 |= (SIM_SCGC5_PORTA_MASK\r
+ | SIM_SCGC5_PORTB_MASK\r
+ | SIM_SCGC5_PORTC_MASK\r
+ | SIM_SCGC5_PORTD_MASK\r
+ | SIM_SCGC5_PORTE_MASK );\r
+\r
+ /* Ramp up the system clock */\r
+ core_clk_mhz = pll_init(CORE_CLK_MHZ, REF_CLK);\r
+\r
+ /*\r
+ * Use the value obtained from the pll_init function to define variables\r
+ * for the core clock in kHz and also the peripheral clock. These\r
+ * variables can be used by other functions that need awareness of the\r
+ * system frequency.\r
+ */\r
+ core_clk_khz = core_clk_mhz * 1000;\r
+ periph_clk_khz = core_clk_khz / (((SIM_CLKDIV1 & SIM_CLKDIV1_OUTDIV2_MASK) >> 24)+ 1);\r
+\r
+ /* For debugging purposes, enable the trace clock and/or FB_CLK so that\r
+ * we'll be able to monitor clocks and know the PLL is at the frequency\r
+ * that we expect.\r
+ */\r
+ trace_clk_init();\r
+ fb_clk_init();\r
+\r
+ /* Enable the pins for the selected UART */\r
+ if (TERM_PORT == UART0_BASE_PTR)\r
+ {\r
+ /* Enable the UART0_TXD function on PTD6 */\r
+ PORTD_PCR6 = PORT_PCR_MUX(0x3); // UART is alt3 function for this pin\r
+\r
+ /* Enable the UART0_RXD function on PTD7 */\r
+ PORTD_PCR7 = PORT_PCR_MUX(0x3); // UART is alt3 function for this pin\r
+ }\r
+\r
+ if (TERM_PORT == UART1_BASE_PTR)\r
+ {\r
+ /* Enable the UART1_TXD function on PTC4 */\r
+ PORTC_PCR4 = PORT_PCR_MUX(0x3); // UART is alt3 function for this pin\r
+\r
+ /* Enable the UART1_RXD function on PTC3 */\r
+ PORTC_PCR3 = PORT_PCR_MUX(0x3); // UART is alt3 function for this pin\r
+ }\r
+\r
+ if (TERM_PORT == UART2_BASE_PTR)\r
+ {\r
+ /* Enable the UART2_TXD function on PTD3 */\r
+ PORTD_PCR3 = PORT_PCR_MUX(0x3); // UART is alt3 function for this pin\r
+\r
+ /* Enable the UART2_RXD function on PTD2 */\r
+ PORTD_PCR2 = PORT_PCR_MUX(0x3); // UART is alt3 function for this pin\r
+ }\r
+\r
+ if (TERM_PORT == UART3_BASE_PTR)\r
+ {\r
+ /* Enable the UART3_TXD function on PTC17 */\r
+ PORTC_PCR17 = PORT_PCR_MUX(0x3); // UART is alt3 function for this pin\r
+\r
+ /* Enable the UART3_RXD function on PTC16 */\r
+ PORTC_PCR16 = PORT_PCR_MUX(0x3); // UART is alt3 function for this pin\r
+ }\r
+ if (TERM_PORT == UART4_BASE_PTR)\r
+ {\r
+ /* Enable the UART3_TXD function on PTC17 */\r
+ PORTE_PCR24 = PORT_PCR_MUX(0x3); // UART is alt3 function for this pin\r
+\r
+ /* Enable the UART3_RXD function on PTC16 */\r
+ PORTE_PCR25 = PORT_PCR_MUX(0x3); // UART is alt3 function for this pin\r
+ }\r
+ if (TERM_PORT == UART5_BASE_PTR)\r
+ {\r
+ /* Enable the UART3_TXD function on PTC17 */\r
+ PORTE_PCR8 = PORT_PCR_MUX(0x3); // UART is alt3 function for this pin\r
+\r
+ /* Enable the UART3_RXD function on PTC16 */\r
+ PORTE_PCR9 = PORT_PCR_MUX(0x3); // UART is alt3 function for this pin\r
+ }\r
+ /* UART0 and UART1 are clocked from the core clock, but all other UARTs are\r
+ * clocked from the peripheral clock. So we have to determine which clock\r
+ * to send to the uart_init function.\r
+ */\r
+ if ((TERM_PORT == UART0_BASE_PTR) | (TERM_PORT == UART1_BASE_PTR))\r
+ uart_init (TERM_PORT, core_clk_khz, TERMINAL_BAUD);\r
+ else\r
+ uart_init (TERM_PORT, periph_clk_khz, TERMINAL_BAUD);\r
+}\r
+/********************************************************************/\r
+void trace_clk_init(void)\r
+{\r
+ /* Set the trace clock to the core clock frequency */\r
+ SIM_SOPT2 |= SIM_SOPT2_TRACECLKSEL_MASK;\r
+\r
+ /* Enable the TRACE_CLKOUT pin function on PTA6 (alt7 function) */\r
+ PORTA_PCR6 = ( PORT_PCR_MUX(0x7));\r
+}\r
+/********************************************************************/\r
+void fb_clk_init(void)\r
+{\r
+ /* Enable the clock to the FlexBus module */\r
+ SIM_SCGC7 |= SIM_SCGC7_FLEXBUS_MASK;\r
+\r
+ /* Enable the FB_CLKOUT function on PTC3 (alt5 function) */\r
+ PORTC_PCR3 = ( PORT_PCR_MUX(0x5));\r
+}\r
+/********************************************************************/\r
--- /dev/null
+/*\r
+ * File: sysinit.h\r
+ * Purpose: Kinetis Configuration\r
+ * Initializes processor to a default state\r
+ *\r
+ * Notes:\r
+ *\r
+ */\r
+\r
+/********************************************************************/\r
+\r
+// function prototypes\r
+void sysinit (void);\r
+void trace_clk_init(void);\r
+void fb_clk_init(void);\r
+void enable_abort_button(void);\r
+/********************************************************************/\r
--- /dev/null
+/******************************************************************************\r
+* File: vectors.c\r
+*\r
+* Purpose: Configure interrupt vector table for Kinetis.\r
+******************************************************************************/\r
+\r
+#include "vectors.h"\r
+#include "common.h"\r
+\r
+extern void SVC_Handler( void );\r
+extern void PendSV_Handler( void );\r
+extern void SysTick_Handler( void );\r
+\r
+\r
+/******************************************************************************\r
+* Vector Table\r
+******************************************************************************/\r
+typedef void (*vector_entry)(void);\r
+\r
+#if defined(IAR)\r
+ #pragma location = ".intvec"\r
+ const vector_entry __vector_table[] = //@ ".intvec" =\r
+#elif defined(CW)\r
+ #pragma define_section vectortable ".vectortable" ".vectortable" ".vectortable" far_abs R\r
+ #define VECTOR __declspec(vectortable)\r
+ const VECTOR vector_entry __vector_table[] = //@ ".intvec" =\r
+#endif\r
+\r
+{\r
+ VECTOR_000, /* Initial SP */\r
+ VECTOR_001, /* Initial PC */\r
+ VECTOR_002,\r
+ VECTOR_003,\r
+ VECTOR_004,\r
+ VECTOR_005,\r
+ VECTOR_006,\r
+ VECTOR_007,\r
+ VECTOR_008,\r
+ VECTOR_009,\r
+ VECTOR_010,\r
+ SVC_Handler,\r
+ VECTOR_012,\r
+ VECTOR_013,\r
+ PendSV_Handler,\r
+ SysTick_Handler,\r
+\r
+ VECTOR_016,\r
+ VECTOR_017,\r
+ VECTOR_018,\r
+ VECTOR_019,\r
+ VECTOR_020,\r
+ VECTOR_021,\r
+ VECTOR_022,\r
+ VECTOR_023,\r
+ VECTOR_024,\r
+ VECTOR_025,\r
+ VECTOR_026,\r
+ VECTOR_027,\r
+ VECTOR_028,\r
+ VECTOR_029,\r
+ VECTOR_030,\r
+ VECTOR_031,\r
+ VECTOR_032,\r
+ VECTOR_033,\r
+ VECTOR_034,\r
+ VECTOR_035,\r
+ VECTOR_036,\r
+ VECTOR_037,\r
+ VECTOR_038,\r
+ VECTOR_039,\r
+ VECTOR_040,\r
+ VECTOR_041,\r
+ VECTOR_042,\r
+ VECTOR_043,\r
+ VECTOR_044,\r
+ VECTOR_045,\r
+ VECTOR_046,\r
+ VECTOR_047,\r
+ VECTOR_048,\r
+ VECTOR_049,\r
+ VECTOR_050,\r
+ VECTOR_051,\r
+ VECTOR_052,\r
+ VECTOR_053,\r
+ VECTOR_054,\r
+ VECTOR_055,\r
+ VECTOR_056,\r
+ VECTOR_057,\r
+ VECTOR_058,\r
+ VECTOR_059,\r
+ VECTOR_060,\r
+ VECTOR_061,\r
+ VECTOR_062,\r
+ VECTOR_063,\r
+ VECTOR_064,\r
+ VECTOR_065,\r
+ VECTOR_066,\r
+ VECTOR_067,\r
+ VECTOR_068,\r
+ VECTOR_069,\r
+ VECTOR_070,\r
+ VECTOR_071,\r
+ VECTOR_072,\r
+ VECTOR_073,\r
+ VECTOR_074,\r
+ VECTOR_075,\r
+ VECTOR_076,\r
+ VECTOR_077,\r
+ VECTOR_078,\r
+ VECTOR_079,\r
+ VECTOR_080,\r
+ VECTOR_081,\r
+ VECTOR_082,\r
+ VECTOR_083,\r
+ VECTOR_084,\r
+ VECTOR_085,\r
+ VECTOR_086,\r
+ VECTOR_087,\r
+ VECTOR_088,\r
+ VECTOR_089,\r
+ VECTOR_090,\r
+ VECTOR_091,\r
+ VECTOR_092,\r
+ VECTOR_093,\r
+ VECTOR_094,\r
+ VECTOR_095,\r
+ VECTOR_096,\r
+ VECTOR_097,\r
+ VECTOR_098,\r
+ VECTOR_099,\r
+ VECTOR_100,\r
+ VECTOR_101,\r
+ VECTOR_102,\r
+ VECTOR_103, /* Port A */\r
+ VECTOR_104,\r
+ VECTOR_105, /* Port C */\r
+ VECTOR_106,\r
+ VECTOR_107, /* Port E */\r
+ VECTOR_108,\r
+ VECTOR_109,\r
+ VECTOR_110,\r
+ VECTOR_111,\r
+ VECTOR_112,\r
+ VECTOR_113,\r
+ VECTOR_114,\r
+ VECTOR_115,\r
+ VECTOR_116,\r
+ VECTOR_117,\r
+ VECTOR_118,\r
+ VECTOR_119,\r
+ VECTOR_120,\r
+ VECTOR_121,\r
+ VECTOR_122,\r
+ VECTOR_123,\r
+ VECTOR_124,\r
+ VECTOR_125,\r
+ VECTOR_126,\r
+ VECTOR_127,\r
+ VECTOR_128,\r
+ VECTOR_129,\r
+ VECTOR_130,\r
+ VECTOR_131,\r
+ VECTOR_132,\r
+ VECTOR_133,\r
+ VECTOR_134,\r
+ VECTOR_135,\r
+ VECTOR_136,\r
+ VECTOR_137,\r
+ VECTOR_138,\r
+ VECTOR_139,\r
+ VECTOR_140,\r
+ VECTOR_141,\r
+ VECTOR_142,\r
+ VECTOR_143,\r
+ VECTOR_144,\r
+ VECTOR_145,\r
+ VECTOR_146,\r
+ VECTOR_147,\r
+ VECTOR_148,\r
+ VECTOR_149,\r
+ VECTOR_150,\r
+ VECTOR_151,\r
+ VECTOR_152,\r
+ VECTOR_153,\r
+ VECTOR_154,\r
+ VECTOR_155,\r
+ VECTOR_156,\r
+ VECTOR_157,\r
+ VECTOR_158,\r
+ VECTOR_159,\r
+ VECTOR_160,\r
+ VECTOR_161,\r
+ VECTOR_162,\r
+ VECTOR_163,\r
+ VECTOR_164,\r
+ VECTOR_165,\r
+ VECTOR_166,\r
+ VECTOR_167,\r
+ VECTOR_168,\r
+ VECTOR_169,\r
+ VECTOR_170,\r
+ VECTOR_171,\r
+ VECTOR_172,\r
+ VECTOR_173,\r
+ VECTOR_174,\r
+ VECTOR_175,\r
+ VECTOR_176,\r
+ VECTOR_177,\r
+ VECTOR_178,\r
+ VECTOR_179,\r
+ VECTOR_180,\r
+ VECTOR_181,\r
+ VECTOR_182,\r
+ VECTOR_183,\r
+ VECTOR_184,\r
+ VECTOR_185,\r
+ VECTOR_186,\r
+ VECTOR_187,\r
+ VECTOR_188,\r
+ VECTOR_189,\r
+ VECTOR_190,\r
+ VECTOR_191,\r
+ VECTOR_192,\r
+ VECTOR_193,\r
+ VECTOR_194,\r
+ VECTOR_195,\r
+ VECTOR_196,\r
+ VECTOR_197,\r
+ VECTOR_198,\r
+ VECTOR_199,\r
+ VECTOR_200,\r
+ VECTOR_201,\r
+ VECTOR_202,\r
+ VECTOR_203,\r
+ VECTOR_204,\r
+ VECTOR_205,\r
+ VECTOR_206,\r
+ VECTOR_207,\r
+ VECTOR_208,\r
+ VECTOR_209,\r
+ VECTOR_210,\r
+ VECTOR_211,\r
+ VECTOR_212,\r
+ VECTOR_213,\r
+ VECTOR_214,\r
+ VECTOR_215,\r
+ VECTOR_216,\r
+ VECTOR_217,\r
+ VECTOR_218,\r
+ VECTOR_219,\r
+ VECTOR_220,\r
+ VECTOR_221,\r
+ VECTOR_222,\r
+ VECTOR_223,\r
+ VECTOR_224,\r
+ VECTOR_225,\r
+ VECTOR_226,\r
+ VECTOR_227,\r
+ VECTOR_228,\r
+ VECTOR_229,\r
+ VECTOR_230,\r
+ VECTOR_231,\r
+ VECTOR_232,\r
+ VECTOR_233,\r
+ VECTOR_234,\r
+ VECTOR_235,\r
+ VECTOR_236,\r
+ VECTOR_237,\r
+ VECTOR_238,\r
+ VECTOR_239,\r
+ VECTOR_240,\r
+ VECTOR_241,\r
+ VECTOR_242,\r
+ VECTOR_243,\r
+ VECTOR_244,\r
+ VECTOR_245,\r
+ VECTOR_246,\r
+ VECTOR_247,\r
+ VECTOR_248,\r
+ VECTOR_249,\r
+ VECTOR_250,\r
+ VECTOR_251,\r
+ VECTOR_252,\r
+ VECTOR_253,\r
+ VECTOR_254,\r
+ VECTOR_255,\r
+ CONFIG_1,\r
+ CONFIG_2,\r
+ CONFIG_3,\r
+ CONFIG_4,\r
+\r
+};\r
+// VECTOR_TABLE end\r
+/******************************************************************************\r
+* default_isr(void)\r
+*\r
+* Default ISR definition.\r
+*\r
+* In: n/a\r
+* Out: n/a\r
+******************************************************************************/\r
+//#if (defined(CW))\r
+//__declspec(interrupt)\r
+//#endif\r
+\r
+void default_isr(void)\r
+{\r
+ #define VECTORNUM (*(volatile uint8_t*)(0xE000ED04))\r
+\r
+ printf("\n****default_isr entered on vector %d*****\r\n\n",VECTORNUM);\r
+ return;\r
+}\r
+/******************************************************************************/\r
+/* End of "vectors.c" */\r
--- /dev/null
+/******************************************************************************\r
+* File: vectors.h\r
+*\r
+* Purpose: Provide custom interrupt service routines for Kinetis. \r
+*\r
+* NOTE: This vector table is a superset table, so interrupt sources might be \r
+* listed that are not available on the specific Kinetis device you are \r
+* using.\r
+******************************************************************************/\r
+\r
+#ifndef __VECTORS_H\r
+#define __VECTORS_H 1\r
+\r
+// function prototype for default_isr in vectors.c\r
+void default_isr(void);\r
+void abort_isr(void);\r
+\r
+void hard_fault_handler_c(unsigned int * hardfault_args);\r
+\r
+/* Interrupt Vector Table Function Pointers */\r
+typedef void pointer(void);\r
+\r
+extern void __startup(void);\r
+\r
+extern unsigned long __BOOT_STACK_ADDRESS[];\r
+extern void __iar_program_start(void);\r
+ // Address Vector IRQ Source module Source description\r
+#define VECTOR_000 (pointer*)__BOOT_STACK_ADDRESS // ARM core Initial Supervisor SP\r
+#define VECTOR_001 __startup // 0x0000_0004 1 - ARM core Initial Program Counter\r
+#define VECTOR_002 default_isr // 0x0000_0008 2 - ARM core Non-maskable Interrupt (NMI)\r
+#define VECTOR_003 default_isr // 0x0000_000C 3 - ARM core Hard Fault\r
+#define VECTOR_004 default_isr // 0x0000_0010 4 -\r
+#define VECTOR_005 default_isr // 0x0000_0014 5 - ARM core Bus Fault\r
+#define VECTOR_006 default_isr // 0x0000_0018 6 - ARM core Usage Fault\r
+#define VECTOR_007 default_isr // 0x0000_001C 7 - \r
+#define VECTOR_008 default_isr // 0x0000_0020 8 - \r
+#define VECTOR_009 default_isr // 0x0000_0024 9 -\r
+#define VECTOR_010 default_isr // 0x0000_0028 10 -\r
+#define VECTOR_011 default_isr // 0x0000_002C 11 - ARM core Supervisor call (SVCall)\r
+#define VECTOR_012 default_isr // 0x0000_0030 12 - ARM core Debug Monitor\r
+#define VECTOR_013 default_isr // 0x0000_0034 13 - \r
+#define VECTOR_014 default_isr // 0x0000_0038 14 - ARM core Pendable request for system service (PendableSrvReq)\r
+#define VECTOR_015 default_isr // 0x0000_003C 15 - ARM core System tick timer (SysTick)\r
+#define VECTOR_016 default_isr // 0x0000_0040 16 0 DMA DMA Channel 0 transfer complete\r
+#define VECTOR_017 default_isr // 0x0000_0044 17 1 DMA DMA Channel 1 transfer complete\r
+#define VECTOR_018 default_isr // 0x0000_0048 18 2 DMA DMA Channel 2 transfer complete\r
+#define VECTOR_019 default_isr // 0x0000_004C 19 3 DMA DMA Channel 3 transfer complete\r
+#define VECTOR_020 default_isr // 0x0000_0050 20 4 DMA DMA Channel 4 transfer complete\r
+#define VECTOR_021 default_isr // 0x0000_0054 21 5 DMA DMA Channel 5 transfer complete\r
+#define VECTOR_022 default_isr // 0x0000_0058 22 6 DMA DMA Channel 6 transfer complete\r
+#define VECTOR_023 default_isr // 0x0000_005C 23 7 DMA DMA Channel 7 transfer complete\r
+#define VECTOR_024 default_isr // 0x0000_0060 24 8 DMA DMA Channel 8 transfer complete\r
+#define VECTOR_025 default_isr // 0x0000_0064 25 9 DMA DMA Channel 9 transfer complete\r
+#define VECTOR_026 default_isr // 0x0000_0068 26 10 DMA DMA Channel 10 transfer complete\r
+#define VECTOR_027 default_isr // 0x0000_006C 27 11 DMA DMA Channel 11 transfer complete\r
+#define VECTOR_028 default_isr // 0x0000_0070 28 12 DMA DMA Channel 12 transfer complete\r
+#define VECTOR_029 default_isr // 0x0000_0074 29 13 DMA DMA Channel 13 transfer complete\r
+#define VECTOR_030 default_isr // 0x0000_0078 30 14 DMA DMA Channel 14 transfer complete\r
+#define VECTOR_031 default_isr // 0x0000_007C 31 15 DMA DMA Channel 15 transfer complete\r
+#define VECTOR_032 default_isr // 0x0000_0080 32 16 DMA DMA Error Interrupt Channels 0-15\r
+#define VECTOR_033 default_isr // 0x0000_0084 33 17 MCM Normal interrupt\r
+#define VECTOR_034 default_isr // 0x0000_0088 34 18 Flash memory Command Complete\r
+#define VECTOR_035 default_isr // 0x0000_008C 35 19 Flash memory Read Collision\r
+#define VECTOR_036 default_isr // 0x0000_0090 36 20 Mode Controller Low Voltage Detect,Low Voltage Warning, Low Leakage Wakeup\r
+#define VECTOR_037 default_isr // 0x0000_0094 37 21 LLWU\r
+#define VECTOR_038 default_isr // 0x0000_0098 38 22 WDOG\r
+#define VECTOR_039 default_isr // 0x0000_009C 39 23 RNGB\r
+#define VECTOR_040 default_isr // 0x0000_00A0 40 24 I2C0\r
+#define VECTOR_041 default_isr // 0x0000_00A4 41 25 I2C1\r
+#define VECTOR_042 default_isr // 0x0000_00A8 42 26 SPI0 Single interrupt vector for all sources\r
+#define VECTOR_043 default_isr // 0x0000_00AC 43 27 SPI1 Single interrupt vector for all sources\r
+#define VECTOR_044 default_isr // 0x0000_00B0 44 28 SPI2 Single interrupt vector for all sources\r
+#define VECTOR_045 default_isr // 0x0000_00B4 45 29 CAN0 OR'ed Message buffer (0-15)\r
+#define VECTOR_046 default_isr // 0x0000_00B8 46 30 CAN0 Bus Off\r
+#define VECTOR_047 default_isr // 0x0000_00BC 47 31 CAN0 Error\r
+#define VECTOR_048 default_isr // 0x0000_00C0 48 32 CAN0 Transmit Warning\r
+#define VECTOR_049 default_isr // 0x0000_00C4 49 33 CAN0 Receive Warning\r
+#define VECTOR_050 default_isr // 0x0000_00C8 50 34 CAN0 Wake Up\r
+#define VECTOR_051 default_isr // 0x0000_00CC 51 35 CAN0 Individual Matching Elements Update (IMEU)\r
+#define VECTOR_052 default_isr // 0x0000_00D0 52 36 CAN0 Lost receive\r
+#define VECTOR_053 default_isr // 0x0000_00D4 53 37 CAN1 OR'ed Message buffer (0-15)\r
+#define VECTOR_054 default_isr // 0x0000_00D8 54 38 CAN1 Bus off\r
+#define VECTOR_055 default_isr // 0x0000_00DC 55 39 CAN1 Error\r
+#define VECTOR_056 default_isr // 0x0000_00E0 56 40 CAN1 Transmit Warning\r
+#define VECTOR_057 default_isr // 0x0000_00E4 57 41 CAN1 Receive Warning\r
+#define VECTOR_058 default_isr // 0x0000_00E8 58 42 CAN1 Wake Up\r
+#define VECTOR_059 default_isr // 0x0000_00EC 59 43 CAN1 Individual Matching Elements Update (IMEU)\r
+#define VECTOR_060 default_isr // 0x0000_00F0 60 44 CAN1 Lost receive \r
+#define VECTOR_061 default_isr // 0x0000_00F4 61 45 UART0 Single interrupt vector for UART status sources\r
+#define VECTOR_062 default_isr // 0x0000_00F8 62 46 UART0 Single interrupt vector for UART error sources\r
+#define VECTOR_063 default_isr // 0x0000_00FC 63 47 UART1 Single interrupt vector for UART status sources\r
+#define VECTOR_064 default_isr // 0x0000_0100 64 48 UART1 Single interrupt vector for UART error sources\r
+#define VECTOR_065 default_isr // 0x0000_0104 65 49 UART2 Single interrupt vector for UART status sources\r
+#define VECTOR_066 default_isr // 0x0000_0108 66 50 UART2 Single interrupt vector for UART error sources\r
+#define VECTOR_067 default_isr // 0x0000_010C 67 51 UART3 Single interrupt vector for UART status sources\r
+#define VECTOR_068 default_isr // 0x0000_0110 68 52 UART3 Single interrupt vector for UART error sources\r
+#define VECTOR_069 default_isr // 0x0000_0114 69 53 UART4 Single interrupt vector for UART status sources\r
+#define VECTOR_070 default_isr // 0x0000_0118 70 54 UART4 Single interrupt vector for UART error sources\r
+#define VECTOR_071 default_isr // 0x0000_011C 71 55 UART5 Single interrupt vector for UART status sources\r
+#define VECTOR_072 default_isr // 0x0000_0120 72 56 UART5 Single interrupt vector for UART error sources\r
+#define VECTOR_073 default_isr // 0x0000_0124 73 57 ADC0\r
+#define VECTOR_074 default_isr // 0x0000_0128 74 58 ADC1\r
+#define VECTOR_075 default_isr // 0x0000_012C 75 59 CMP0 High-speed comparator \r
+#define VECTOR_076 default_isr // 0x0000_0130 76 60 CMP1\r
+#define VECTOR_077 default_isr // 0x0000_0134 77 61 CMP2\r
+#define VECTOR_078 default_isr // 0x0000_0138 78 62 FTM0 Single interrupt vector for all sources\r
+#define VECTOR_079 default_isr // 0x0000_013C 79 63 FTM1 Single interrupt vector for all sources\r
+#define VECTOR_080 default_isr // 0x0000_0140 80 64 FTM2 Single interrupt vector for all sources\r
+#define VECTOR_081 default_isr // 0x0000_0144 81 65 CMT\r
+#define VECTOR_082 default_isr // 0x0000_0148 82 66 RTC Timer interrupt\r
+#define VECTOR_083 default_isr // 0x0000_014C 83 67\r
+#define VECTOR_084 default_isr // 0x0000_0150 84 68 PIT Channel 0\r
+#define VECTOR_085 default_isr // 0x0000_0154 85 69 PIT Channel 1\r
+#define VECTOR_086 default_isr // 0x0000_0158 86 70 PIT Channel 2\r
+#define VECTOR_087 default_isr // 0x0000_015C 87 71 PIT Channel 3\r
+#define VECTOR_088 default_isr // 0x0000_0160 88 72 PDB\r
+#define VECTOR_089 default_isr // 0x0000_0164 89 73 USB OTG\r
+#define VECTOR_090 default_isr // 0x0000_0168 90 74 USB Charger Detect\r
+#define VECTOR_091 default_isr // 0x0000_016C 91 75 ENET IEEE 1588 Timer interrupt \r
+#define VECTOR_092 default_isr // 0x0000_0170 92 76 ENET Transmit interrupt\r
+#define VECTOR_093 default_isr // 0x0000_0174 93 77 ENET Receive interrupt\r
+#define VECTOR_094 default_isr // 0x0000_0178 94 78 ENET Error and miscellaneous interrupt\r
+#define VECTOR_095 default_isr // 0x0000_017C 95 79 I2S\r
+#define VECTOR_096 default_isr // 0x0000_0180 96 80 SDHC\r
+#define VECTOR_097 default_isr // 0x0000_0184 97 81 DAC0\r
+#define VECTOR_098 default_isr // 0x0000_0188 98 82 DAC1\r
+#define VECTOR_099 default_isr // 0x0000_018C 99 83 TSI Single interrupt vector for all sources\r
+#define VECTOR_100 default_isr // 0x0000_0190 100 84 MCG\r
+#define VECTOR_101 default_isr // 0x0000_0194 101 85 Low Power Timer\r
+#define VECTOR_102 default_isr // 0x0000_0198 102 86 Segment LCD Single interrupt vector for all sources\r
+#define VECTOR_103 default_isr // 0x0000_019C 103 87 Port control module Pin Detect (Port A)\r
+#define VECTOR_104 default_isr // 0x0000_01A0 104 88 Port control module Pin Detect (Port B)\r
+#define VECTOR_105 default_isr // 0x0000_01A4 105 89 Port control module Pin Detect (Port C)\r
+#define VECTOR_106 default_isr // 0x0000_01A8 106 90 Port control module Pin Detect (Port D)\r
+#define VECTOR_107 default_isr // 0x0000_01AC 107 91 Port control module Pin Detect (Port E)\r
+#define VECTOR_108 default_isr // 0x0000_01B0 108 92 \r
+#define VECTOR_109 default_isr // 0x0000_01B4 109 93 \r
+#define VECTOR_110 default_isr // 0x0000_01B8 110 94 \r
+#define VECTOR_111 default_isr // 0x0000_01BC 111 95 \r
+#define VECTOR_112 default_isr // 0x0000_01C0 112 96 \r
+#define VECTOR_113 default_isr // 0x0000_01C4 113 97 \r
+#define VECTOR_114 default_isr // 0x0000_01C8 114 98 \r
+#define VECTOR_115 default_isr // 0x0000_01CC 115 99 \r
+#define VECTOR_116 default_isr // 0x0000_01D0 116 100\r
+#define VECTOR_117 default_isr // 0x0000_01D4 117 101\r
+#define VECTOR_118 default_isr // 0x0000_01D8 118 102\r
+#define VECTOR_119 default_isr // 0x0000_01DC 119 103\r
+#define VECTOR_120 default_isr // \r
+#define VECTOR_121 default_isr // \r
+#define VECTOR_122 default_isr // \r
+#define VECTOR_123 default_isr // \r
+#define VECTOR_124 default_isr // \r
+#define VECTOR_125 default_isr // \r
+#define VECTOR_126 default_isr // \r
+#define VECTOR_127 default_isr // \r
+#define VECTOR_128 default_isr // \r
+#define VECTOR_129 default_isr // \r
+#define VECTOR_130 default_isr // \r
+#define VECTOR_131 default_isr // \r
+#define VECTOR_132 default_isr // \r
+#define VECTOR_133 default_isr // \r
+#define VECTOR_134 default_isr // \r
+#define VECTOR_135 default_isr // \r
+#define VECTOR_136 default_isr // \r
+#define VECTOR_137 default_isr // \r
+#define VECTOR_138 default_isr // \r
+#define VECTOR_139 default_isr // \r
+#define VECTOR_140 default_isr // \r
+#define VECTOR_141 default_isr // \r
+#define VECTOR_142 default_isr // \r
+#define VECTOR_143 default_isr // \r
+#define VECTOR_144 default_isr // \r
+#define VECTOR_145 default_isr // \r
+#define VECTOR_146 default_isr // \r
+#define VECTOR_147 default_isr // \r
+#define VECTOR_148 default_isr // \r
+#define VECTOR_149 default_isr // \r
+#define VECTOR_150 default_isr // \r
+#define VECTOR_151 default_isr // \r
+#define VECTOR_152 default_isr // \r
+#define VECTOR_153 default_isr // \r
+#define VECTOR_154 default_isr // \r
+#define VECTOR_155 default_isr // \r
+#define VECTOR_156 default_isr // \r
+#define VECTOR_157 default_isr // \r
+#define VECTOR_158 default_isr // \r
+#define VECTOR_159 default_isr // \r
+#define VECTOR_160 default_isr // \r
+#define VECTOR_161 default_isr // \r
+#define VECTOR_162 default_isr // \r
+#define VECTOR_163 default_isr // \r
+#define VECTOR_164 default_isr // \r
+#define VECTOR_165 default_isr // \r
+#define VECTOR_166 default_isr // \r
+#define VECTOR_167 default_isr // \r
+#define VECTOR_168 default_isr // \r
+#define VECTOR_169 default_isr // \r
+#define VECTOR_170 default_isr // \r
+#define VECTOR_171 default_isr // \r
+#define VECTOR_172 default_isr // \r
+#define VECTOR_173 default_isr // \r
+#define VECTOR_174 default_isr // \r
+#define VECTOR_175 default_isr // \r
+#define VECTOR_176 default_isr // \r
+#define VECTOR_177 default_isr // \r
+#define VECTOR_178 default_isr // \r
+#define VECTOR_179 default_isr // \r
+#define VECTOR_180 default_isr // \r
+#define VECTOR_181 default_isr // \r
+#define VECTOR_182 default_isr // \r
+#define VECTOR_183 default_isr // \r
+#define VECTOR_184 default_isr // \r
+#define VECTOR_185 default_isr // \r
+#define VECTOR_186 default_isr // \r
+#define VECTOR_187 default_isr // \r
+#define VECTOR_188 default_isr // \r
+#define VECTOR_189 default_isr // \r
+#define VECTOR_190 default_isr // \r
+#define VECTOR_191 default_isr // \r
+#define VECTOR_192 default_isr // \r
+#define VECTOR_193 default_isr // \r
+#define VECTOR_194 default_isr // \r
+#define VECTOR_195 default_isr // \r
+#define VECTOR_196 default_isr // \r
+#define VECTOR_197 default_isr // \r
+#define VECTOR_198 default_isr // \r
+#define VECTOR_199 default_isr // \r
+#define VECTOR_200 default_isr // \r
+#define VECTOR_201 default_isr // \r
+#define VECTOR_202 default_isr // \r
+#define VECTOR_203 default_isr // \r
+#define VECTOR_204 default_isr // \r
+#define VECTOR_205 default_isr // \r
+#define VECTOR_206 default_isr // \r
+#define VECTOR_207 default_isr // \r
+#define VECTOR_208 default_isr // \r
+#define VECTOR_209 default_isr // \r
+#define VECTOR_210 default_isr // \r
+#define VECTOR_211 default_isr // \r
+#define VECTOR_212 default_isr // \r
+#define VECTOR_213 default_isr // \r
+#define VECTOR_214 default_isr // \r
+#define VECTOR_215 default_isr // \r
+#define VECTOR_216 default_isr // \r
+#define VECTOR_217 default_isr // \r
+#define VECTOR_218 default_isr // \r
+#define VECTOR_219 default_isr // \r
+#define VECTOR_220 default_isr // \r
+#define VECTOR_221 default_isr // \r
+#define VECTOR_222 default_isr // \r
+#define VECTOR_223 default_isr // \r
+#define VECTOR_224 default_isr // \r
+#define VECTOR_225 default_isr // \r
+#define VECTOR_226 default_isr // \r
+#define VECTOR_227 default_isr // \r
+#define VECTOR_228 default_isr // \r
+#define VECTOR_229 default_isr // \r
+#define VECTOR_230 default_isr // \r
+#define VECTOR_231 default_isr // \r
+#define VECTOR_232 default_isr // \r
+#define VECTOR_233 default_isr // \r
+#define VECTOR_234 default_isr // \r
+#define VECTOR_235 default_isr // \r
+#define VECTOR_236 default_isr // \r
+#define VECTOR_237 default_isr // \r
+#define VECTOR_238 default_isr // \r
+#define VECTOR_239 default_isr // \r
+#define VECTOR_240 default_isr // \r
+#define VECTOR_241 default_isr // \r
+#define VECTOR_242 default_isr // \r
+#define VECTOR_243 default_isr // \r
+#define VECTOR_244 default_isr // \r
+#define VECTOR_245 default_isr // \r
+#define VECTOR_246 default_isr // \r
+#define VECTOR_247 default_isr // \r
+#define VECTOR_248 default_isr // \r
+#define VECTOR_249 default_isr // \r
+#define VECTOR_250 default_isr // \r
+#define VECTOR_251 default_isr // \r
+#define VECTOR_252 default_isr // \r
+#define VECTOR_253 default_isr // \r
+#define VECTOR_254 default_isr // \r
+#define VECTOR_255 default_isr // \r
+#define CONFIG_1 (pointer*)0xffffffff \r
+#define CONFIG_2 (pointer*)0xffffffff \r
+#define CONFIG_3 (pointer*)0xffffffff\r
+#define CONFIG_4 (pointer*)0xfffffffe\r
+\r
+#endif /*__VECTORS_H*/\r
+\r
+/* End of "vectors.h" */\r
--- /dev/null
+/*\r
+ * File: mcg.c\r
+ * Purpose: Driver for enabling the PLL in 1 of 4 options\r
+ *\r
+ * Notes:\r
+ * Assumes the MCG mode is in the default FEI mode out of reset\r
+ * One of 4 clocking oprions can be selected.\r
+ * One of 16 crystal values can be used\r
+ */\r
+\r
+#include "common.h"\r
+#include "mcg.h"\r
+\r
+extern int core_clk_khz;\r
+extern int core_clk_mhz;\r
+extern int periph_clk_khz;\r
+\r
+unsigned char pll_init(unsigned char clk_option, unsigned char crystal_val)\r
+{\r
+ unsigned char pll_freq;\r
+\r
+ if (clk_option > 3) {return 0;} //return 0 if one of the available options is not selected\r
+ if (crystal_val > 15) {return 1;} // return 1 if one of the available crystal options is not available\r
+//This assumes that the MCG is in default FEI mode out of reset.\r
+\r
+// First move to FBE mode\r
+#if (defined(K60_CLK) || defined(K53_CLK) || defined(ASB817))\r
+ MCG_C2 = 0;\r
+#else\r
+// Enable external oscillator, RANGE=2, HGO=1, EREFS=1, LP=0, IRCS=0\r
+ MCG_C2 = MCG_C2_RANGE(2) | MCG_C2_HGO_MASK | MCG_C2_EREFS_MASK;\r
+#endif\r
+\r
+// after initialization of oscillator release latched state of oscillator and GPIO\r
+ SIM_SCGC4 |= SIM_SCGC4_LLWU_MASK;\r
+ LLWU_CS |= LLWU_CS_ACKISO_MASK;\r
+\r
+// Select external oscilator and Reference Divider and clear IREFS to start ext osc\r
+// CLKS=2, FRDIV=3, IREFS=0, IRCLKEN=0, IREFSTEN=0\r
+ MCG_C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3);\r
+\r
+ /* if we aren't using an osc input we don't need to wait for the osc to init */\r
+#if (!defined(K60_CLK) && !defined(K53_CLK) && !defined(ASB817))\r
+ while (!(MCG_S & MCG_S_OSCINIT_MASK)){}; // wait for oscillator to initialize\r
+#endif\r
+\r
+ while (MCG_S & MCG_S_IREFST_MASK){}; // wait for Reference clock Status bit to clear\r
+\r
+ while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x2){}; // Wait for clock status bits to show clock source is ext ref clk\r
+\r
+// Now in FBE\r
+\r
+#if (defined(K60_CLK) || defined(K53_CLK))\r
+ MCG_C5 = MCG_C5_PRDIV(0x18);\r
+#else\r
+// Configure PLL Ref Divider, PLLCLKEN=0, PLLSTEN=0, PRDIV=5\r
+// The crystal frequency is used to select the PRDIV value. Only even frequency crystals are supported\r
+// that will produce a 2MHz reference clock to the PLL.\r
+ MCG_C5 = MCG_C5_PRDIV(crystal_val); // Set PLL ref divider to match the crystal used\r
+#endif\r
+\r
+ // Ensure MCG_C6 is at the reset default of 0. LOLIE disabled, PLL disabled, clk monitor disabled, PLL VCO divider is clear\r
+ MCG_C6 = 0x0;\r
+// Select the PLL VCO divider and system clock dividers depending on clocking option\r
+ switch (clk_option) {\r
+ case 0:\r
+ // Set system options dividers\r
+ //MCG=PLL, core = MCG, bus = MCG, FlexBus = MCG, Flash clock= MCG/2\r
+ set_sys_dividers(0,0,0,1);\r
+ // Set the VCO divider and enable the PLL for 50MHz, LOLIE=0, PLLS=1, CME=0, VDIV=1\r
+ MCG_C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV(1); //VDIV = 1 (x25)\r
+ pll_freq = 50;\r
+ break;\r
+ case 1:\r
+ // Set system options dividers\r
+ //MCG=PLL, core = MCG, bus = MCG/2, FlexBus = MCG/2, Flash clock= MCG/4\r
+ set_sys_dividers(0,1,1,3);\r
+ // Set the VCO divider and enable the PLL for 100MHz, LOLIE=0, PLLS=1, CME=0, VDIV=26\r
+ MCG_C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV(26); //VDIV = 26 (x50)\r
+ pll_freq = 100;\r
+ break;\r
+ case 2:\r
+ // Set system options dividers\r
+ //MCG=PLL, core = MCG, bus = MCG/2, FlexBus = MCG/2, Flash clock= MCG/4\r
+ set_sys_dividers(0,1,1,3);\r
+ // Set the VCO divider and enable the PLL for 96MHz, LOLIE=0, PLLS=1, CME=0, VDIV=24\r
+ MCG_C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV(24); //VDIV = 24 (x48)\r
+ pll_freq = 96;\r
+ break;\r
+ case 3:\r
+ // Set system options dividers\r
+ //MCG=PLL, core = MCG, bus = MCG, FlexBus = MCG, Flash clock= MCG/2\r
+ set_sys_dividers(0,0,0,1);\r
+ // Set the VCO divider and enable the PLL for 48MHz, LOLIE=0, PLLS=1, CME=0, VDIV=0\r
+ MCG_C6 = MCG_C6_PLLS_MASK; //VDIV = 0 (x24)\r
+ pll_freq = 48;\r
+ break;\r
+ }\r
+ while (!(MCG_S & MCG_S_PLLST_MASK)){}; // wait for PLL status bit to set\r
+\r
+ while (!(MCG_S & MCG_S_LOCK_MASK)){}; // Wait for LOCK bit to set\r
+\r
+// Now running PBE Mode\r
+\r
+// Transition into PEE by setting CLKS to 0\r
+// CLKS=0, FRDIV=3, IREFS=0, IRCLKEN=0, IREFSTEN=0\r
+ MCG_C1 &= ~MCG_C1_CLKS_MASK;\r
+\r
+// Wait for clock status bits to update\r
+ while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x3){};\r
+\r
+// Now running PEE Mode\r
+\r
+return pll_freq;\r
+} //pll_init\r
+\r
+\r
+ /*\r
+ * This routine must be placed in RAM. It is a workaround for errata e2448.\r
+ * Flash prefetch must be disabled when the flash clock divider is changed.\r
+ * This cannot be performed while executing out of flash.\r
+ * There must be a short delay after the clock dividers are changed before prefetch\r
+ * can be re-enabled.\r
+ */\r
+#if (defined(IAR))\r
+ __ramfunc void set_sys_dividers(uint32 outdiv1, uint32 outdiv2, uint32 outdiv3, uint32 outdiv4)\r
+#elif (defined(CW))\r
+__relocate_code__\r
+void set_sys_dividers(uint32 outdiv1, uint32 outdiv2, uint32 outdiv3, uint32 outdiv4)\r
+#endif\r
+{\r
+ uint32 temp_reg;\r
+ uint8 i;\r
+\r
+ temp_reg = FMC_PFAPR; // store present value of FMC_PFAPR\r
+\r
+ // set M0PFD through M7PFD to 1 to disable prefetch\r
+ FMC_PFAPR |= FMC_PFAPR_M7PFD_MASK | FMC_PFAPR_M6PFD_MASK | FMC_PFAPR_M5PFD_MASK\r
+ | FMC_PFAPR_M4PFD_MASK | FMC_PFAPR_M3PFD_MASK | FMC_PFAPR_M2PFD_MASK\r
+ | FMC_PFAPR_M1PFD_MASK | FMC_PFAPR_M0PFD_MASK;\r
+\r
+ // set clock dividers to desired value\r
+ SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(outdiv1) | SIM_CLKDIV1_OUTDIV2(outdiv2)\r
+ | SIM_CLKDIV1_OUTDIV3(outdiv3) | SIM_CLKDIV1_OUTDIV4(outdiv4);\r
+\r
+ // wait for dividers to change\r
+ for (i = 0 ; i < outdiv4 ; i++)\r
+ {}\r
+\r
+ FMC_PFAPR = temp_reg; // re-store original value of FMC_PFAPR\r
+\r
+ return;\r
+} // set_sys_dividers\r
+\r
+\r
+/********************************************************************/\r
+void mcg_pee_2_blpi(void)\r
+{\r
+ uint8 temp_reg;\r
+ // Transition from PEE to BLPI: PEE -> PBE -> FBE -> FBI -> BLPI\r
+\r
+ // Step 1: PEE -> PBE\r
+ MCG_C1 |= MCG_C1_CLKS(2); // System clock from external reference OSC, not PLL.\r
+ while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x2){}; // Wait for clock status to update.\r
+\r
+ // Step 2: PBE -> FBE\r
+ MCG_C6 &= ~MCG_C6_PLLS_MASK; // Clear PLLS to select FLL, still running system from ext OSC.\r
+ while (MCG_S & MCG_S_PLLST_MASK){}; // Wait for PLL status flag to reflect FLL selected.\r
+\r
+ // Step 3: FBE -> FBI\r
+ MCG_C2 &= ~MCG_C2_LP_MASK; // FLL remains active in bypassed modes.\r
+ MCG_C2 |= MCG_C2_IRCS_MASK; // Select fast (1MHz) internal reference\r
+ temp_reg = MCG_C1;\r
+ temp_reg &= ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK);\r
+ temp_reg |= (MCG_C1_CLKS(1) | MCG_C1_IREFS_MASK); // Select internal reference (fast IREF clock @ 1MHz) as MCG clock source.\r
+ MCG_C1 = temp_reg;\r
+\r
+ while (MCG_S & MCG_S_IREFST_MASK){}; // Wait for Reference Status bit to update.\r
+ while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x1){}; // Wait for clock status bits to update\r
+\r
+ // Step 4: FBI -> BLPI\r
+ MCG_C1 |= MCG_C1_IREFSTEN_MASK; // Keep internal reference clock running in STOP modes.\r
+ MCG_C2 |= MCG_C2_LP_MASK; // FLL remains disabled in bypassed modes.\r
+ while (!(MCG_S & MCG_S_IREFST_MASK)){}; // Wait for Reference Status bit to update.\r
+ while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x1){}; // Wait for clock status bits to update.\r
+\r
+} // end MCG PEE to BLPI\r
+/********************************************************************/\r
+void mcg_blpi_2_pee(void)\r
+{\r
+ uint8 temp_reg;\r
+ // Transition from BLPI to PEE: BLPI -> FBI -> FEI -> FBE -> PBE -> PEE\r
+\r
+ // Step 1: BLPI -> FBI\r
+ MCG_C2 &= ~MCG_C2_LP_MASK; // FLL remains active in bypassed modes.\r
+ while (!(MCG_S & MCG_S_IREFST_MASK)){}; // Wait for Reference Status bit to update.\r
+ while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x1){}; // Wait for clock status bits to update\r
+\r
+ // Step 2: FBI -> FEI\r
+ MCG_C2 &= ~MCG_C2_LP_MASK; // FLL remains active in bypassed modes.\r
+ temp_reg = MCG_C2; // assign temporary variable of MCG_C2 contents\r
+ temp_reg &= ~MCG_C2_RANGE_MASK; // set RANGE field location to zero\r
+ temp_reg |= (0x2 << 0x4); // OR in new values\r
+ MCG_C2 = temp_reg; // store new value in MCG_C2\r
+ MCG_C4 = 0x0E; // Low-range DCO output (~10MHz bus). FCTRIM=%0111.\r
+ MCG_C1 = 0x04; // Select internal clock as MCG source, FRDIV=%000, internal reference selected.\r
+\r
+ while (!(MCG_S & MCG_S_IREFST_MASK)){}; // Wait for Reference Status bit to update\r
+ while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x0){}; // Wait for clock status bits to update\r
+\r
+ // Handle FEI to PEE transitions using standard clock initialization routine.\r
+ core_clk_mhz = pll_init(CORE_CLK_MHZ, REF_CLK);\r
+\r
+ /* Use the value obtained from the pll_init function to define variables\r
+ * for the core clock in kHz and also the peripheral clock. These\r
+ * variables can be used by other functions that need awareness of the\r
+ * system frequency.\r
+ */\r
+ core_clk_khz = core_clk_mhz * 1000;\r
+ periph_clk_khz = core_clk_khz / (((SIM_CLKDIV1 & SIM_CLKDIV1_OUTDIV2_MASK) >> 24)+ 1);\r
+} // end MCG BLPI to PEE\r
+/********************************************************************/\r
+\r
+void mcg_pbe_2_pee(void)\r
+{\r
+ MCG_C1 &= ~MCG_C1_CLKS_MASK; // select PLL as MCG_OUT\r
+ // Wait for clock status bits to update\r
+ while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x3){};\r
+\r
+ switch (CORE_CLK_MHZ) {\r
+ case PLL50:\r
+ core_clk_khz = 50000;\r
+ break;\r
+ case PLL100:\r
+ core_clk_khz = 100000;\r
+ break;\r
+ case PLL96:\r
+ core_clk_khz = 96000;\r
+ break;\r
+ case PLL48:\r
+ core_clk_khz = 48000;\r
+ break;\r
+ }\r
+}\r
--- /dev/null
+/*\r
+ * File: pll_init.h\r
+ * Purpose: pll_driver specific declarations\r
+ *\r
+ * Notes:\r
+ */\r
+#ifndef __MCG_H__\r
+#define __MCG_H__\r
+/********************************************************************/\r
+\r
+/* For some reason CW needs to have cw.h explicitly included here for\r
+ * the code relocation of set_sys_dividers() to work correctly even\r
+ * though common.h should pull in cw.h.\r
+ */\r
+#if (defined(CW))\r
+ #include "cw.h"\r
+#endif\r
+\r
+unsigned char pll_init(unsigned char, unsigned char);\r
+\r
+void mcg_pee_2_blpi(void);\r
+void mcg_blpi_2_pee(void);\r
+void mcg_pbe_2_pee(void);\r
+\r
+#if (defined(IAR))\r
+ __ramfunc void set_sys_dividers(uint32 outdiv1, uint32 outdiv2, uint32 outdiv3, uint32 outdiv4);\r
+#elif (defined(CW))\r
+ __relocate_code__ \r
+ void set_sys_dividers(uint32 outdiv1, uint32 outdiv2, uint32 outdiv3, uint32 outdiv4);\r
+#endif \r
+\r
+enum clk_option\r
+{\r
+ PLL50,\r
+ PLL100,\r
+ PLL96,\r
+ PLL48\r
+};\r
+\r
+enum crystal_val\r
+{\r
+ XTAL2,\r
+ XTAL4,\r
+ XTAL6,\r
+ XTAL8,\r
+ XTAL10,\r
+ XTAL12,\r
+ XTAL14,\r
+ XTAL16,\r
+ XTAL18,\r
+ XTAL20,\r
+ XTAL22,\r
+ XTAL24,\r
+ XTAL26,\r
+ XTAL28,\r
+ XTAL30,\r
+ XTAL32\r
+};\r
+\r
+/********************************************************************/\r
+#endif /* __MCG_H__ */\r
--- /dev/null
+/*\r
+ * File: uart.c\r
+ * Purpose: Provide common UART routines for serial IO\r
+ *\r
+ * Notes: \r
+ * \r
+ */\r
+\r
+#include "common.h"\r
+#include "uart.h"\r
+\r
+/********************************************************************/\r
+/*\r
+ * Initialize the UART for 8N1 operation, interrupts disabled, and\r
+ * no hardware flow-control\r
+ *\r
+ * NOTE: Since the UARTs are pinned out in multiple locations on most\r
+ * Kinetis devices, this driver does not enable UART pin functions.\r
+ * The desired pins should be enabled before calling this init function.\r
+ *\r
+ * Parameters:\r
+ * uartch UART channel to initialize\r
+ * sysclk UART module Clock in kHz(used to calculate baud)\r
+ * baud UART baud rate\r
+ */\r
+void uart_init (UART_MemMapPtr uartch, int sysclk, int baud)\r
+{\r
+ register uint16 sbr, brfa;\r
+ uint8 temp;\r
+ \r
+ /* Enable the clock to the selected UART */ \r
+ if(uartch == UART0_BASE_PTR)\r
+ SIM_SCGC4 |= SIM_SCGC4_UART0_MASK;\r
+ else\r
+ if (uartch == UART1_BASE_PTR)\r
+ SIM_SCGC4 |= SIM_SCGC4_UART1_MASK;\r
+ else\r
+ if (uartch == UART2_BASE_PTR)\r
+ SIM_SCGC4 |= SIM_SCGC4_UART2_MASK;\r
+ else\r
+ if(uartch == UART3_BASE_PTR)\r
+ SIM_SCGC4 |= SIM_SCGC4_UART3_MASK;\r
+ else\r
+ if(uartch == UART4_BASE_PTR)\r
+ SIM_SCGC1 |= SIM_SCGC1_UART4_MASK;\r
+ else\r
+ SIM_SCGC1 |= SIM_SCGC1_UART5_MASK;\r
+ \r
+ /* Make sure that the transmitter and receiver are disabled while we \r
+ * change settings.\r
+ */\r
+ UART_C2_REG(uartch) &= ~(UART_C2_TE_MASK\r
+ | UART_C2_RE_MASK );\r
+\r
+ /* Configure the UART for 8-bit mode, no parity */\r
+ UART_C1_REG(uartch) = 0; /* We need all default settings, so entire register is cleared */\r
+ \r
+ /* Calculate baud settings */\r
+ sbr = (uint16)((sysclk*1000)/(baud * 16));\r
+ \r
+ /* Save off the current value of the UARTx_BDH except for the SBR field */\r
+ temp = UART_BDH_REG(uartch) & ~(UART_BDH_SBR(0x1F));\r
+ \r
+ UART_BDH_REG(uartch) = temp | UART_BDH_SBR(((sbr & 0x1F00) >> 8));\r
+ UART_BDL_REG(uartch) = (uint8)(sbr & UART_BDL_SBR_MASK);\r
+ \r
+ /* Determine if a fractional divider is needed to get closer to the baud rate */\r
+ brfa = (((sysclk*32000)/(baud * 16)) - (sbr * 32));\r
+ \r
+ /* Save off the current value of the UARTx_C4 register except for the BRFA field */\r
+ temp = UART_C4_REG(uartch) & ~(UART_C4_BRFA(0x1F));\r
+ \r
+ UART_C4_REG(uartch) = temp | UART_C4_BRFA(brfa); \r
+\r
+ /* Enable receiver and transmitter */\r
+ UART_C2_REG(uartch) |= (UART_C2_TE_MASK\r
+ | UART_C2_RE_MASK );\r
+}\r
+/********************************************************************/\r
+/*\r
+ * Wait for a character to be received on the specified UART\r
+ *\r
+ * Parameters:\r
+ * channel UART channel to read from\r
+ *\r
+ * Return Values:\r
+ * the received character\r
+ */\r
+char uart_getchar (UART_MemMapPtr channel)\r
+{\r
+ /* Wait until character has been received */\r
+ while (!(UART_S1_REG(channel) & UART_S1_RDRF_MASK));\r
+ \r
+ /* Return the 8-bit data from the receiver */\r
+ return UART_D_REG(channel);\r
+}\r
+/********************************************************************/\r
+/*\r
+ * Wait for space in the UART Tx FIFO and then send a character\r
+ *\r
+ * Parameters:\r
+ * channel UART channel to send to\r
+ * ch character to send\r
+ */ \r
+void uart_putchar (UART_MemMapPtr channel, char ch)\r
+{\r
+ /* Wait until space is available in the FIFO */\r
+ while(!(UART_S1_REG(channel) & UART_S1_TDRE_MASK));\r
+ \r
+ /* Send the character */\r
+ UART_D_REG(channel) = (uint8)ch;\r
+ }\r
+/********************************************************************/\r
+/*\r
+ * Check to see if a character has been received\r
+ *\r
+ * Parameters:\r
+ * channel UART channel to check for a character\r
+ *\r
+ * Return values:\r
+ * 0 No character received\r
+ * 1 Character has been received\r
+ */\r
+int uart_getchar_present (UART_MemMapPtr channel)\r
+{\r
+ return (UART_S1_REG(channel) & UART_S1_RDRF_MASK);\r
+}\r
+/********************************************************************/\r
+ \r
--- /dev/null
+/*\r
+ * File: uart.h\r
+ * Purpose: Provide common ColdFire UART routines for polled serial IO\r
+ *\r
+ * Notes:\r
+ */\r
+\r
+#ifndef __UART_H__\r
+#define __UART_H__\r
+\r
+/********************************************************************/\r
+\r
+void uart_init (UART_MemMapPtr, int, int);\r
+char uart_getchar (UART_MemMapPtr);\r
+void uart_putchar (UART_MemMapPtr, char);\r
+int uart_getchar_present (UART_MemMapPtr);\r
+\r
+/********************************************************************/\r
+\r
+#endif /* __UART_H__ */\r
--- /dev/null
+/*\r
+ * File: wdog.c\r
+ * Purpose: Provide common watchdog module routines\r
+ *\r
+ * Notes: Need to add more functionality. Right now it\r
+ * is just a disable routine since we know almost\r
+ * all projects will need that. \r
+ * \r
+ */\r
+\r
+#include "common.h"\r
+#include "wdog.h"\r
+ \r
+/********************************************************************/\r
+/*\r
+ * Watchdog timer disable routine\r
+ *\r
+ * Parameters:\r
+ * none\r
+ */\r
+void wdog_disable(void)\r
+{\r
+ /* First unlock the watchdog so that we can write to registers */\r
+ wdog_unlock();\r
+ \r
+ /* Clear the WDOGEN bit to disable the watchdog */\r
+ WDOG_STCTRLH &= ~WDOG_STCTRLH_WDOGEN_MASK;\r
+}\r
+/********************************************************************/\r
+/*\r
+ * Watchdog timer unlock routine. Writing 0xC520 followed by 0xD928\r
+ * will unlock the write once registers in the WDOG so they are writable\r
+ * within the WCT period.\r
+ *\r
+ * Parameters:\r
+ * none\r
+ */\r
+void wdog_unlock(void)\r
+{\r
+ /* NOTE: DO NOT SINGLE STEP THROUGH THIS FUNCTION!!! */\r
+ /* There are timing requirements for the execution of the unlock. If\r
+ * you single step through the code you will cause the CPU to reset.\r
+ */\r
+\r
+ /* This sequence must execute within 20 clock cycles, so disable\r
+ * interrupts will keep the code atomic and ensure the timing.\r
+ */\r
+ DisableInterrupts;\r
+ \r
+ /* Write 0xC520 to the unlock register */\r
+ WDOG_UNLOCK = 0xC520;\r
+ \r
+ /* Followed by 0xD928 to complete the unlock */\r
+ WDOG_UNLOCK = 0xD928;\r
+ \r
+ /* Re-enable interrupts now that we are done */ \r
+ EnableInterrupts;\r
+}\r
+/********************************************************************/\r
--- /dev/null
+/*\r
+ * File: wdog.h\r
+ * Purpose: Provide common watchdog module routines\r
+ *\r
+ * Notes:\r
+ */\r
+\r
+#ifndef __WDOG_H__\r
+#define __WDOG_H__\r
+\r
+/********************************************************************/\r
+\r
+// function prototypes\r
+void wdog_disable(void);\r
+void wdog_unlock(void);\r
+\r
+/********************************************************************/\r
+#endif /* __WDOG_H__ */\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<project>\r
+ <fileVersion>2</fileVersion>\r
+ <configuration>\r
+ <name>RTOSDemo</name>\r
+ <toolchain>\r
+ <name>ARM</name>\r
+ </toolchain>\r
+ <debug>1</debug>\r
+ <settings>\r
+ <name>C-SPY</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>22</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CInput</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CEndian</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCVariant</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MacOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MacFile</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>MemOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MemFile</name>\r
+ <state>$TOOLKIT_DIR$\CONFIG\debugger\Freescale\iok60xxxx.ddf</state>\r
+ </option>\r
+ <option>\r
+ <name>RunToEnable</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>RunToName</name>\r
+ <state>main</state>\r
+ </option>\r
+ <option>\r
+ <name>CExtraOptionsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CExtraOptions</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CFpuProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDDFArgumentProducer</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadSuppressDownload</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadVerifyAll</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCProductVersion</name>\r
+ <state>5.50.0.51907</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDynDriverList</name>\r
+ <state>JLINK_ID</state>\r
+ </option>\r
+ <option>\r
+ <name>OCLastSavedByProductVersion</name>\r
+ <state>6.21.1.52845</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadAttachToProgram</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>UseFlashLoader</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CLowLevel</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCBE8Slave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>MacFile2</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CDevice</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>FlashLoadersV3</name>\r
+ <state>$TOOLKIT_DIR$\config\flashloader\Freescale\FlashK60Xxxx.board</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesSuppressCheck1</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesPath1</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesSuppressCheck2</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesPath2</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesSuppressCheck3</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesPath3</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OverrideDefFlashBoard</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesOffset1</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesOffset2</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesOffset3</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesUse1</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesUse2</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesUse3</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>ARMSIM_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>1</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCSimDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCSimEnablePSP</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCSimPspOverrideConfig</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCSimPspConfigFile</name>\r
+ <state></state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>ANGEL_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CCAngelHeartbeat</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CAngelCommunication</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CAngelCommBaud</name>\r
+ <version>0</version>\r
+ <state>3</state>\r
+ </option>\r
+ <option>\r
+ <name>CAngelCommPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ANGELTCPIP</name>\r
+ <state>aaa.bbb.ccc.ddd</state>\r
+ </option>\r
+ <option>\r
+ <name>DoAngelLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AngelLogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>GDBSERVER_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>TCPIP</name>\r
+ <state>aaa.bbb.ccc.ddd</state>\r
+ </option>\r
+ <option>\r
+ <name>DoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>LogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJTagBreakpointRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJTagDoUpdateBreakpoints</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJTagUpdateBreakpoints</name>\r
+ <state>_call_main</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>IARROM_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>1</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CRomLogFileCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRomLogFileEditB</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CRomCommPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRomCommBaud</name>\r
+ <version>0</version>\r
+ <state>7</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>JLINK_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>13</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>JLinkSpeed</name>\r
+ <state>32</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkDoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkLogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkHWResetDelay</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>JLinkInitialSpeed</name>\r
+ <state>32</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDoJlinkMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCScanChainNonARMDevices</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkIRLength</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkCommRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkTCPIP</name>\r
+ <state>aaa.bbb.ccc.ddd</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkSpeedRadioV2</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCUSBDevice</name>\r
+ <version>1</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchUndef</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchSWI</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchData</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchPrefetch</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchIRQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchFIQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkBreakpointRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkDoUpdateBreakpoints</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkUpdateBreakpoints</name>\r
+ <state>_call_main</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkInterfaceRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCJLinkAttachSlave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkResetList</name>\r
+ <version>5</version>\r
+ <state>7</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchCORERESET</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchMMERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchNOCPERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchCHRERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchSTATERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchBUSERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchINTERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchHARDERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchDummy</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCJLinkScriptFile</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkUsbSerialNo</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCTcpIpAlt</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkTcpIpSerialNo</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCCpuClockEdit</name>\r
+ <state>72.0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockAuto</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockEdit</name>\r
+ <state>2000</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>LMIFTDI_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>2</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>LmiftdiSpeed</name>\r
+ <state>500</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiftdiDoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiftdiLogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiFtdiInterfaceRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiFtdiInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>MACRAIGOR_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>3</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>jtag</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>EmuSpeed</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>TCPIP</name>\r
+ <state>aaa.bbb.ccc.ddd</state>\r
+ </option>\r
+ <option>\r
+ <name>DoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>LogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>DoEmuMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>EmuMultiTarget</name>\r
+ <state>0@ARM7TDMI</state>\r
+ </option>\r
+ <option>\r
+ <name>EmuHWReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CEmuCommBaud</name>\r
+ <version>0</version>\r
+ <state>4</state>\r
+ </option>\r
+ <option>\r
+ <name>CEmuCommPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>jtago</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>UnusedAddr</name>\r
+ <state>0x00800000</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMacraigorHWResetDelay</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCJTagBreakpointRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJTagDoUpdateBreakpoints</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJTagUpdateBreakpoints</name>\r
+ <state>_call_main</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMacraigorInterfaceRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMacraigorInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>PEMICRO_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCPEMicroAttachSlave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroInterfaceList</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroResetDelay</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroJtagSpeed</name>\r
+ <state>1000</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJPEMicroShowSettings</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>DoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>LogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroUSBDevice</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroSerialPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJPEMicroTCPIPAutoScanNetwork</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroTCPIP</name>\r
+ <state>10.0.0.1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroCommCmdLineProducer</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>RDI_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>2</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CRDIDriverDll</name>\r
+ <state>###Uninitialized###</state>\r
+ </option>\r
+ <option>\r
+ <name>CRDILogFileCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRDILogFileEdit</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDIHWReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchUndef</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchSWI</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchData</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchPrefetch</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchIRQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchFIQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>STLINK_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>2</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkInterfaceRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkResetList</name>\r
+ <version>1</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCpuClockEdit</name>\r
+ <state>72.0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockAuto</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockEdit</name>\r
+ <state>2000</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>THIRDPARTY_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CThirdPartyDriverDll</name>\r
+ <state>###Uninitialized###</state>\r
+ </option>\r
+ <option>\r
+ <name>CThirdPartyLogFileCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CThirdPartyLogFileEditB</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>XDS100_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCXDS100AttachSlave</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <debuggerPlugins>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\FreeRTOS\FreeRTOSPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\OpenRTOS\OpenRTOSPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ </debuggerPlugins>\r
+ </configuration>\r
+</project>\r
+\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<project>\r
+ <fileVersion>2</fileVersion>\r
+ <configuration>\r
+ <name>RTOSDemo</name>\r
+ <toolchain>\r
+ <name>ARM</name>\r
+ </toolchain>\r
+ <debug>1</debug>\r
+ <settings>\r
+ <name>General</name>\r
+ <archiveVersion>3</archiveVersion>\r
+ <data>\r
+ <version>21</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>ExePath</name>\r
+ <state>RTOSDemo\Exe</state>\r
+ </option>\r
+ <option>\r
+ <name>ObjPath</name>\r
+ <state>RTOSDemo\Obj</state>\r
+ </option>\r
+ <option>\r
+ <name>ListPath</name>\r
+ <state>RTOSDemo\List</state>\r
+ </option>\r
+ <option>\r
+ <name>Variant</name>\r
+ <version>19</version>\r
+ <state>38</state>\r
+ </option>\r
+ <option>\r
+ <name>GEndianMode</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>Input variant</name>\r
+ <version>3</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>Input description</name>\r
+ <state>Full formatting.</state>\r
+ </option>\r
+ <option>\r
+ <name>Output variant</name>\r
+ <version>2</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>Output description</name>\r
+ <state>Full formatting.</state>\r
+ </option>\r
+ <option>\r
+ <name>GOutputBinary</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>FPU</name>\r
+ <version>2</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OGCoreOrChip</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GRuntimeLibSelect</name>\r
+ <version>0</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GRuntimeLibSelectSlave</name>\r
+ <version>0</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>RTDescription</name>\r
+ <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\r
+ </option>\r
+ <option>\r
+ <name>OGProductVersion</name>\r
+ <state>5.41.0.51757</state>\r
+ </option>\r
+ <option>\r
+ <name>OGLastSavedByProductVersion</name>\r
+ <state>6.21.1.52845</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralEnableMisra</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraVerbose</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OGChipSelectEditMenu</name>\r
+ <state>K60Xxxx Freescale K60Xxxx</state>\r
+ </option>\r
+ <option>\r
+ <name>GenLowLevelInterface</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GEndianModeBE</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OGBufferedTerminalOutput</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GenStdoutInterface</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraRules98</name>\r
+ <version>0</version>\r
+ <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraVer</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraRules04</name>\r
+ <version>0</version>\r
+ <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>RTConfigPath2</name>\r
+ <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Normal.h</state>\r
+ </option>\r
+ <option>\r
+ <name>GFPUCoreSlave</name>\r
+ <version>19</version>\r
+ <state>38</state>\r
+ </option>\r
+ <option>\r
+ <name>GBECoreSlave</name>\r
+ <version>19</version>\r
+ <state>38</state>\r
+ </option>\r
+ <option>\r
+ <name>OGUseCmsis</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OGUseCmsisDspLib</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>ICCARM</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>28</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CCDefines</name>\r
+ <state>IAR</state>\r
+ <state>TWR_K60N512</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPreprocFile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPreprocComments</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPreprocLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListCFile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListCMnemonics</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListCMessages</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListAssFile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListAssSource</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCEnableRemarks</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagSuppress</name>\r
+ <state>Pa082</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagRemark</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagWarning</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagError</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCObjPrefix</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCAllowList</name>\r
+ <version>1</version>\r
+ <state>0000000</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDebugInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IEndianMode</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IExtraOptionsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IExtraOptions</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCLangConformance</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSignedPlainChar</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRequirePrototypes</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMultibyteSupport</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagWarnAreErr</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCompilerRuntimeInfo</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IFpuProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OutputFile</name>\r
+ <state>$FILE_BNAME$.o</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLibConfigHeader</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>PreInclude</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CompilerMisraOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCIncludePath2</name>\r
+ <state>$PROJ_DIR$</state>\r
+ <state>$PROJ_DIR$\..\..\Source\include</state>\r
+ <state>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3</state>\r
+ <state>$PROJ_DIR$\..\Common\include</state>\r
+ <state>$PROJ_DIR$\Freescale_Code\common</state>\r
+ <state>$PROJ_DIR$\Freescale_Code\cpu</state>\r
+ <state>$PROJ_DIR$\Freescale_Code\drivers\uart</state>\r
+ <state>$PROJ_DIR$\Freescale_Code\drivers\mcg</state>\r
+ <state>$PROJ_DIR$\Freescale_Code\drivers\wdog</state>\r
+ <state>$PROJ_DIR$\Freescale_Code\drivers\adc16</state>\r
+ </option>\r
+ <option>\r
+ <name>CCStdIncCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCodeSection</name>\r
+ <state>.text</state>\r
+ </option>\r
+ <option>\r
+ <name>IInterwork2</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IProcessorMode2</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCOptLevel</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCOptStrategy</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCOptLevelSlave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CompilerMisraRules98</name>\r
+ <version>0</version>\r
+ <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>CompilerMisraRules04</name>\r
+ <version>0</version>\r
+ <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPosIndRopi</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPosIndRwpi</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPosIndNoDynInit</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IccLang</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IccCDialect</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccAllowVLA</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IccCppDialect</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccExceptions</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccRTTI</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
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+ </data>\r
+ </settings>\r
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+ <archiveVersion>2</archiveVersion>\r
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+ <version>8</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
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+ <name>AObjPrefix</name>\r
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+ <state></state>\r
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+ <state>0</state>\r
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+ <name>MultiLine</name>\r
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+ <name>ALimitErrorsEdit</name>\r
+ <state>100</state>\r
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+ <option>\r
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+ <state>0</state>\r
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+ <option>\r
+ <name>AUserIncludes</name>\r
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+ </option>\r
+ <option>\r
+ <name>AExtraOptionsV2</name>\r
+ <state></state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>OBJCOPY</name>\r
+ <archiveVersion>0</archiveVersion>\r
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+ <version>1</version>\r
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+ <debug>1</debug>\r
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+ <name>OOCOutputFormat</name>\r
+ <version>2</version>\r
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+ <option>\r
+ <name>OCOutputOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OOCOutputFile</name>\r
+ <state>RTOSDemo.srec</state>\r
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+ <option>\r
+ <name>OOCCommandLineProducer</name>\r
+ <state>1</state>\r
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+ <option>\r
+ <name>OOCObjCopyEnable</name>\r
+ <state>1</state>\r
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+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>CUSTOM</name>\r
+ <archiveVersion>3</archiveVersion>\r
+ <data>\r
+ <extensions></extensions>\r
+ <cmdline></cmdline>\r
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+ </settings>\r
+ <settings>\r
+ <name>BICOMP</name>\r
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+ <prebuild></prebuild>\r
+ <postbuild></postbuild>\r
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+ </settings>\r
+ <settings>\r
+ <name>ILINK</name>\r
+ <archiveVersion>0</archiveVersion>\r
+ <data>\r
+ <version>13</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>IlinkLibIOConfig</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>XLinkMisraHandler</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkInputFileSlave</name>\r
+ <state>0</state>\r
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+ <name>IlinkOutputFile</name>\r
+ <state>$PROJ_FNAME$.out</state>\r
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+ <name>IlinkDebugInfoEnable</name>\r
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+ <name>IlinkKeepSymbols</name>\r
+ <state></state>\r
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+ <name>IlinkRawBinaryFile</name>\r
+ <state></state>\r
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+ <name>IlinkRawBinarySymbol</name>\r
+ <state></state>\r
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+ <option>\r
+ <name>IlinkRawBinarySegment</name>\r
+ <state></state>\r
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+ <option>\r
+ <name>IlinkRawBinaryAlign</name>\r
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+ <option>\r
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+ <option>\r
+ <name>IlinkConfigDefines</name>\r
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+ <option>\r
+ <name>IlinkMapFile</name>\r
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+ <option>\r
+ <name>IlinkIcfOverride</name>\r
+ <state>1</state>\r
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+ <name>IlinkIcfFile</name>\r
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+ </option>\r
+ <option>\r
+ <name>IlinkIcfFileSlave</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkEnableRemarks</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkSuppressDiags</name>\r
+ <state>Lp012</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkTreatAsRem</name>\r
+ <state></state>\r
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+ <option>\r
+ <name>IlinkTreatAsWarn</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkTreatAsErr</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkWarningsAreErrors</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkUseExtraOptions</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkExtraOptions</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkLowLevelInterfaceSlave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkAutoLibEnable</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkAdditionalLibs</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOverrideProgramEntryLabel</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkProgramEntryLabelSelect</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkProgramEntryLabel</name>\r
+ <state>__iar_program_start</state>\r
+ </option>\r
+ <option>\r
+ <name>DoFill</name>\r
+ <state>0</state>\r
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+ <name>FillerByte</name>\r
+ <state>0xFF</state>\r
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+ <version>0</version>\r
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+ <name>CrcAlign</name>\r
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+ <state>1</state>\r
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+ <name>CrcFullSize</name>\r
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+ <state>0</state>\r
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+ <state>0</state>\r
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+ <option>\r
+ <name>IlinkLogRedirSymbols</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkLogUnusedFragments</name>\r
+ <state>0</state>\r
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+ <option>\r
+ <name>IlinkCrcReverseByteOrder</name>\r
+ <state>0</state>\r
+ </option>\r
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+ <name>IlinkCrcUseAsInput</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOptInline</name>\r
+ <state>0</state>\r
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+ <name>IlinkOptExceptionsAllow</name>\r
+ <state>1</state>\r
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+ <name>IlinkOptExceptionsForce</name>\r
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+ <state>1</state>\r
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+ <name>IlinkOptMergeDuplSections</name>\r
+ <state>0</state>\r
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+ <option>\r
+ <name>IlinkOptUseVfe</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOptForceVfe</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>IARCHIVE</name>\r
+ <archiveVersion>0</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>IarchiveInputs</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IarchiveOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IarchiveOutput</name>\r
+ <state>###Unitialized###</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>BILINK</name>\r
+ <archiveVersion>0</archiveVersion>\r
+ <data/>\r
+ </settings>\r
+ </configuration>\r
+ <group>\r
+ <name>FreeRTOS_Source</name>\r
+ <group>\r
+ <name>portable</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\portable\MemMang\heap_2.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\port.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\portasm.s</name>\r
+ </file>\r
+ </group>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\list.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\queue.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\tasks.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\timers.c</name>\r
+ </file>\r
+ </group>\r
+ <group>\r
+ <name>Freescale_Code</name>\r
+ <group>\r
+ <name>common</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\Freescale_Code\common\startup.c</name>\r
+ </file>\r
+ </group>\r
+ <group>\r
+ <name>cpu</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\Freescale_Code\cpu\arm_cm4.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\Freescale_Code\cpu\crt0.s</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\Freescale_Code\cpu\start.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\Freescale_Code\cpu\sysinit.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\Freescale_Code\cpu\vectors.c</name>\r
+ </file>\r
+ </group>\r
+ <group>\r
+ <name>drivers</name>\r
+ <group>\r
+ <name>mcg</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\Freescale_Code\drivers\mcg\mcg.c</name>\r
+ </file>\r
+ </group>\r
+ <group>\r
+ <name>uart</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\Freescale_Code\drivers\uart\uart.c</name>\r
+ </file>\r
+ </group>\r
+ <group>\r
+ <name>wdog</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\Freescale_Code\drivers\wdog\wdog.c</name>\r
+ </file>\r
+ </group>\r
+ </group>\r
+ </group>\r
+ <file>\r
+ <name>$PROJ_DIR$\main_blinky.c</name>\r
+ </file>\r
+</project>\r
+\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<workspace>\r
+ <project>\r
+ <path>$WS_DIR$\RTOSDemo.ewp</path>\r
+ </project>\r
+ <batchBuild>\r
+ <batchDefinition>\r
+ <name>All</name>\r
+ <member>\r
+ <project>gpio_k40_tower</project>\r
+ <configuration>FLASH_128KB_PFLASH</configuration>\r
+ </member>\r
+ <member>\r
+ <project>gpio_k40_tower</project>\r
+ <configuration>FLASH_64KB_PFLASH_64KB_DFLASH</configuration>\r
+ </member>\r
+ <member>\r
+ <project>gpio_k40_tower</project>\r
+ <configuration>RAM_128KB</configuration>\r
+ </member>\r
+ <member>\r
+ <project>RTOSDemo</project>\r
+ <configuration>FLASH_128KB_PFLASH</configuration>\r
+ </member>\r
+ <member>\r
+ <project>RTOSDemo</project>\r
+ <configuration>FLASH_64KB_PFLASH_64KB_DFLASH</configuration>\r
+ </member>\r
+ <member>\r
+ <project>RTOSDemo</project>\r
+ <configuration>RAM_128KB</configuration>\r
+ </member>\r
+ <member>\r
+ <project>gpio_k53_tower</project>\r
+ <configuration>FLASH_128KB_PFLASH</configuration>\r
+ </member>\r
+ <member>\r
+ <project>gpio_k53_tower</project>\r
+ <configuration>FLASH_64KB_PFLASH_64KB_DFLASH</configuration>\r
+ </member>\r
+ <member>\r
+ <project>gpio_k53_tower</project>\r
+ <configuration>RAM_128KB</configuration>\r
+ </member>\r
+ </batchDefinition>\r
+ </batchBuild>\r
+</workspace>\r
+\r
+\r
projects / freertos / commitdiff