mww_phys retired. Replaced by generic mww phys in target.c

diff --git a/doc/openocd.texi b/doc/openocd.texi
index de73bec71283630afccba088f960b47eb512be24..e04b83c82cce9c2fd1e6331b9f8de93efc43be73 100644 (file)
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -5431,23 +5431,6 @@ Display cp15 register @var{regnum};
 else if a @var{value} is provided, that value is written to that register.
 @end deffn
 
-@deffn Command {arm720t mdw_phys} addr [count]
-@deffnx Command {arm720t mdh_phys} addr [count]
-@deffnx Command {arm720t mdb_phys} addr [count]
-Display contents of physical address @var{addr}, as
-32-bit words (@command{mdw_phys}), 16-bit halfwords (@command{mdh_phys}),
-or 8-bit bytes (@command{mdb_phys}).
-If @var{count} is specified, displays that many units.
-@end deffn
-
-@deffn Command {arm720t mww_phys} addr word
-@deffnx Command {arm720t mwh_phys} addr halfword
-@deffnx Command {arm720t mwb_phys} addr byte
-Writes the specified @var{word} (32 bits),
-@var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
-at the specified physical address @var{addr}.
-@end deffn
-
 @subsection ARM9 specific commands
 @cindex ARM9
 
@@ -5508,23 +5491,6 @@ Else if that value is written using the specified @var{address},
 or using zero if no other address is not provided.
 @end deffn
 
-@deffn Command {arm920t mdw_phys} addr [count]
-@deffnx Command {arm920t mdh_phys} addr [count]
-@deffnx Command {arm920t mdb_phys} addr [count]
-Display contents of physical address @var{addr}, as
-32-bit words (@command{mdw_phys}), 16-bit halfwords (@command{mdh_phys}),
-or 8-bit bytes (@command{mdb_phys}).
-If @var{count} is specified, displays that many units.
-@end deffn
-
-@deffn Command {arm920t mww_phys} addr word
-@deffnx Command {arm920t mwh_phys} addr halfword
-@deffnx Command {arm920t mwb_phys} addr byte
-Writes the specified @var{word} (32 bits),
-@var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
-at the specified physical address @var{addr}.
-@end deffn
-
 @deffn Command {arm920t read_cache} filename
 Dump the content of ICache and DCache to a file named @file{filename}.
 @end deffn
@@ -5556,23 +5522,6 @@ If a @var{value} is provided, that value is written to that register.
 Else that register is read and displayed.
 @end deffn
 
-@deffn Command {arm926ejs mdw_phys} addr [count]
-@deffnx Command {arm926ejs mdh_phys} addr [count]
-@deffnx Command {arm926ejs mdb_phys} addr [count]
-Display contents of physical address @var{addr}, as
-32-bit words (@command{mdw_phys}), 16-bit halfwords (@command{mdh_phys}),
-or 8-bit bytes (@command{mdb_phys}).
-If @var{count} is specified, displays that many units.
-@end deffn
-
-@deffn Command {arm926ejs mww_phys} addr word
-@deffnx Command {arm926ejs mwh_phys} addr halfword
-@deffnx Command {arm926ejs mwb_phys} addr byte
-Writes the specified @var{word} (32 bits),
-@var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
-at the specified physical address @var{addr}.
-@end deffn
-
 @subsection ARM966E specific commands
 @cindex ARM966E
 

diff --git a/tcl/board/atmel_at91sam9260-ek.cfg b/tcl/board/atmel_at91sam9260-ek.cfg
index 099d93dff31b3aa41cff51f9016b28d132e521c7..06a54e232769925d00beeb76884d8998e5b3a58f 100644 (file)
--- a/tcl/board/atmel_at91sam9260-ek.cfg
+++ b/tcl/board/atmel_at91sam9260-ek.cfg
@@ -24,7 +24,7 @@ $_TARGETNAME configure -event reset-start {
         jtag_rclk 5
         halt
         # RSTC_MR : enable user reset, MMU may be enabled... use physical address
-        arm926ejs mww_phys 0xfffffd08 0xa5000501
+        arm926ejs mww phys 0xfffffd08 0xa5000501
 }
 
 $_TARGETNAME configure -event reset-init {

diff --git a/tcl/board/mini2440.cfg b/tcl/board/mini2440.cfg
index 277f61ff69b5e2e98458ea310dc7f52d81f45ac2..29819501ffffde6febdd57e340729665f86bc250 100644 (file)
--- a/tcl/board/mini2440.cfg
+++ b/tcl/board/mini2440.cfg
@@ -177,10 +177,10 @@ proc init_2440 { } {
     # usb clock are off 12mHz xtal
     #-----------------------------------------------
 
-    arm920t mww_phys 0x4C000014 0x00000005 #  Clock Divider control Reg
-    arm920t mww_phys 0x4C000000 0xFFFFFFFF #  LOCKTIME count register
-    arm920t mww_phys 0x4C000008 0x00038022 #  UPPLCON  USB clock config Reg
-    arm920t mww_phys 0x4C000004 0x0007F021 #  MPPLCON  Proc clock config Reg
+    arm920t mww phys 0x4C000014 0x00000005 #  Clock Divider control Reg
+    arm920t mww phys 0x4C000000 0xFFFFFFFF #  LOCKTIME count register
+    arm920t mww phys 0x4C000008 0x00038022 #  UPPLCON  USB clock config Reg
+    arm920t mww phys 0x4C000004 0x0007F021 #  MPPLCON  Proc clock config Reg
 
     #-----------------------------------------------
     # Configure Memory controller
@@ -188,45 +188,45 @@ proc init_2440 { } {
     # DRAM - 64MB - 32 bit bus, uses BANKCON6 BANKCON7
     #-----------------------------------------------
 
-    arm920t mww_phys 0x48000000 0x22111112 #  BWSCON - Bank and Bus Width
-    arm920t mww_phys 0x48000010 0x00001112 #  BANKCON4 - ?
-    arm920t mww_phys 0x4800001c 0x00018009 #  BANKCON6 - DRAM
-    arm920t mww_phys 0x48000020 0x00018009 #  BANKCON7 - DRAM
-    arm920t mww_phys 0x48000024 0x008E04EB #  REFRESH  - DRAM
-    arm920t mww_phys 0x48000028 0x000000B2 #  BANKSIZE - DRAM
-    arm920t mww_phys 0x4800002C 0x00000030 #  MRSRB6 - DRAM
-    arm920t mww_phys 0x48000030 0x00000030 #  MRSRB7 - DRAM
+    arm920t mww phys 0x48000000 0x22111112 #  BWSCON - Bank and Bus Width
+    arm920t mww phys 0x48000010 0x00001112 #  BANKCON4 - ?
+    arm920t mww phys 0x4800001c 0x00018009 #  BANKCON6 - DRAM
+    arm920t mww phys 0x48000020 0x00018009 #  BANKCON7 - DRAM
+    arm920t mww phys 0x48000024 0x008E04EB #  REFRESH  - DRAM
+    arm920t mww phys 0x48000028 0x000000B2 #  BANKSIZE - DRAM
+    arm920t mww phys 0x4800002C 0x00000030 #  MRSRB6 - DRAM
+    arm920t mww phys 0x48000030 0x00000030 #  MRSRB7 - DRAM
 
     #-----------------------------------------------
     # Now port configuration for enables for memory
     # and other stuff.
     #-----------------------------------------------
 
-    arm920t mww_phys 0x56000000        0x007FFFFF #  GPACON
+    arm920t mww phys 0x56000000        0x007FFFFF #  GPACON
 
-    arm920t mww_phys 0x56000010        0x00295559 #  GPBCON
-    arm920t mww_phys 0x56000018        0x000003FF #  GPBUP (PULLUP ENABLE)
-    arm920t mww_phys 0x56000014        0x000007C2 #  GPBDAT
+    arm920t mww phys 0x56000010        0x00295559 #  GPBCON
+    arm920t mww phys 0x56000018        0x000003FF #  GPBUP (PULLUP ENABLE)
+    arm920t mww phys 0x56000014        0x000007C2 #  GPBDAT
 
-    arm920t mww_phys 0x56000020        0xAAAAA6AA #  GPCCON
-    arm920t mww_phys 0x56000028        0x0000FFFF #  GPCUP
-    arm920t mww_phys 0x56000024        0x00000020 #  GPCDAT
+    arm920t mww phys 0x56000020        0xAAAAA6AA #  GPCCON
+    arm920t mww phys 0x56000028        0x0000FFFF #  GPCUP
+    arm920t mww phys 0x56000024        0x00000020 #  GPCDAT
 
-    arm920t mww_phys 0x56000030        0xAAAAAAAA #  GPDCON
-    arm920t mww_phys 0x56000038        0x0000FFFF #  GPDUP
+    arm920t mww phys 0x56000030        0xAAAAAAAA #  GPDCON
+    arm920t mww phys 0x56000038        0x0000FFFF #  GPDUP
 
-    arm920t mww_phys 0x56000040        0xAAAAAAAA #  GPECON
-    arm920t mww_phys 0x56000048        0x0000FFFF #  GPEUP
+    arm920t mww phys 0x56000040        0xAAAAAAAA #  GPECON
+    arm920t mww phys 0x56000048        0x0000FFFF #  GPEUP
 
-    arm920t mww_phys 0x56000050        0x00001555 #  GPFCON
-    arm920t mww_phys 0x56000058        0x0000007F #  GPFUP
-    arm920t mww_phys 0x56000054        0x00000000 #  GPFDAT
+    arm920t mww phys 0x56000050        0x00001555 #  GPFCON
+    arm920t mww phys 0x56000058        0x0000007F #  GPFUP
+    arm920t mww phys 0x56000054        0x00000000 #  GPFDAT
 
-    arm920t mww_phys 0x56000060        0x00150114 #  GPGCON
-    arm920t mww_phys 0x56000068        0x0000007F #  GPGUP
+    arm920t mww phys 0x56000060        0x00150114 #  GPGCON
+    arm920t mww phys 0x56000068        0x0000007F #  GPGUP
 
-    arm920t mww_phys 0x56000070        0x0015AAAA #  GPHCON
-    arm920t mww_phys 0x56000078        0x000003FF #  GPGUP
+    arm920t mww phys 0x56000070        0x0015AAAA #  GPHCON
+    arm920t mww phys 0x56000078        0x000003FF #  GPGUP
 
 }
 

diff --git a/tcl/board/olimex_sam9_l9260.cfg b/tcl/board/olimex_sam9_l9260.cfg
index b5cd10ec0303fb8335e55b07e3872de8e2dfded0..935d7cd56c1976de0d1b98fd70cf787d1602c136 100644 (file)
--- a/tcl/board/olimex_sam9_l9260.cfg
+++ b/tcl/board/olimex_sam9_l9260.cfg
@@ -26,7 +26,7 @@ $_TARGETNAME configure -event reset-start {
        
        # RSTC_MR : enable user reset, reset length is 64 slow clock cycles.  MMU may 
        # be enabled... use physical address.
-       arm926ejs mww_phys 0xfffffd08 0xa5000501
+       arm926ejs mww phys 0xfffffd08 0xa5000501
 }
 
 $_TARGETNAME configure -event reset-init {

diff --git a/tcl/board/unknown_at91sam9260.cfg b/tcl/board/unknown_at91sam9260.cfg
index 017f793f31f6468696656aacdbbd7514027df98b..7286a9670f5518a4bf329654e21268405ffb33b2 100644 (file)
--- a/tcl/board/unknown_at91sam9260.cfg
+++ b/tcl/board/unknown_at91sam9260.cfg
@@ -18,7 +18,7 @@ $_TARGETNAME configure -event reset-start {
         jtag_rclk 3
         halt
        # RSTC_MR : enable user reset, MMU may be enabled... use physical address
-        arm926ejs mww_phys 0xfffffd08 0xa5000501
+        arm926ejs mww phys 0xfffffd08 0xa5000501
 }
 
 

diff --git a/tcl/target/davinci.cfg b/tcl/target/davinci.cfg
index e1eb48f598285991233780e37a4150110bc871c3..c14c98ea8eb8f0cd31694b95c7376b88e1aa1990 100644 (file)
--- a/tcl/target/davinci.cfg
+++ b/tcl/target/davinci.cfg
@@ -204,34 +204,34 @@ proc davinci_wdog_reset {} {
        #
 
        # EMUMGT_CLKSPEED: write FREE bit to run despite emulation halt
-       arm926ejs mww_phys [expr $timer2_phys + 0x28] 0x00004000
+       arm926ejs mww phys [expr $timer2_phys + 0x28] 0x00004000
 
        #
        # Part II -- in case watchdog hasn't been set up
        #
 
        # TCR: disable, force internal clock source
-       arm926ejs mww_phys [expr $timer2_phys + 0x20] 0
+       arm926ejs mww phys [expr $timer2_phys + 0x20] 0
 
        # TGCR: reset, force to 64-bit wdog mode, un-reset ("initial" state)
-       arm926ejs mww_phys [expr $timer2_phys + 0x24] 0
-       arm926ejs mww_phys [expr $timer2_phys + 0x24] 0x110b
+       arm926ejs mww phys [expr $timer2_phys + 0x24] 0
+       arm926ejs mww phys [expr $timer2_phys + 0x24] 0x110b
 
        # clear counter (TIM12, TIM34) and period (PRD12, PRD34) registers
        # so watchdog triggers ASAP
-       arm926ejs mww_phys [expr $timer2_phys + 0x10] 0
-       arm926ejs mww_phys [expr $timer2_phys + 0x14] 0
-       arm926ejs mww_phys [expr $timer2_phys + 0x18] 0
-       arm926ejs mww_phys [expr $timer2_phys + 0x1c] 0
+       arm926ejs mww phys [expr $timer2_phys + 0x10] 0
+       arm926ejs mww phys [expr $timer2_phys + 0x14] 0
+       arm926ejs mww phys [expr $timer2_phys + 0x18] 0
+       arm926ejs mww phys [expr $timer2_phys + 0x1c] 0
 
        # WDTCR: put into pre-active state, then active
-       arm926ejs mww_phys [expr $timer2_phys + 0x28] 0xa5c64000
-       arm926ejs mww_phys [expr $timer2_phys + 0x28] 0xda7e4000
+       arm926ejs mww phys [expr $timer2_phys + 0x28] 0xa5c64000
+       arm926ejs mww phys [expr $timer2_phys + 0x28] 0xda7e4000
 
        #
        # Part III -- it's ready to rumble
        #
 
        # WDTCR: write invalid WDKEY to trigger reset
-       arm926ejs mww_phys [expr $timer2_phys + 0x28] 0x00004000
+       arm926ejs mww phys [expr $timer2_phys + 0x28] 0x00004000
 }