]> git.sur5r.net Git - openocd/commitdiff
SAM3X - Added support for at91sam3x8h-ES, fixed CIDR for ES2 and production
authorOlivier Schonken <olivier.schonken@gmail.com>
Thu, 19 Apr 2012 06:53:27 +0000 (08:53 +0200)
committerSpencer Oliver <spen@spen-soft.co.uk>
Thu, 26 Apr 2012 10:58:42 +0000 (10:58 +0000)
The first available devkits for the at91sam3x8h had the ES device populated.
The ES device had an error in the CIDR, specifically in the last byte of
which the upper 3 bits identifies the chip family - cortex-m3, arm7tdmi etc.

The problem was fixed on the ES2 devices - Thanks to Pat Hickey for giving me
the heads-up.

Change-Id: I13dd7fbe0cffaf76f948188c9459dc3cf4435570
Signed-off-by: Olivier Schonken <olivier.schonken@gmail.com>
Reviewed-on: http://openocd.zylin.com/575
Tested-by: jenkins
Reviewed-by: Jim Norris <u17263@att.net>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
src/flash/nor/at91sam3.c

index 01c962413a781e1522eefd24962991a3aef27634..37b6dd78b3a2d074abb88d180b0e7f84c3eb0d12 100644 (file)
@@ -1414,8 +1414,51 @@ static const struct sam3_chip_details all_sam3_details[] = {
        /*      else */
        /*         Bank1 is the boot rom */
        /*      endif */
+       /*at91sam3x8h - ES has an incorrect CIDR of 0x286E0A20*/
        {
                .chipid_cidr    = 0x286E0A20,
+               .name           = "at91sam3x8h - ES",
+               .total_flash_size     = 512 * 1024,
+               .total_sram_size      = 96 * 1024,
+               .n_gpnvms       = 3,
+               .n_banks        = 2,
+               {
+/*             .bank[0] = { */
+                 {
+                       .probed = 0,
+                       .pChip  = NULL,
+                       .pBank  = NULL,
+                       .bank_number = 0,
+                       .base_address = FLASH_BANK0_BASE_AX,
+                       .controller_address = 0x400e0a00,
+                       .flash_wait_states = 6, /* workaround silicon bug */
+                       .present = 1,
+                       .size_bytes =  256 * 1024,
+                       .nsectors   =  16,
+                       .sector_size = 16384,
+                       .page_size   = 256,
+                 },
+/*             .bank[1] = { */
+                 {
+                       .probed = 0,
+                       .pChip  = NULL,
+                       .pBank  = NULL,
+                       .bank_number = 1,
+                       .base_address = FLASH_BANK1_BASE_512K_AX,
+                       .controller_address = 0x400e0c00,
+                       .flash_wait_states = 6, /* workaround silicon bug */
+                       .present = 1,
+                       .size_bytes =  256 * 1024,
+                       .nsectors   =  16,
+                       .sector_size = 16384,
+                       .page_size   = 256,
+
+                 },
+               },
+       },
+       /*at91sam3x8h - ES2 and up uses the correct CIDR of 0x286E0A60*/
+       {
+               .chipid_cidr    = 0x286E0A60,
                .name           = "at91sam3x8h",
                .total_flash_size     = 512 * 1024,
                .total_sram_size      = 96 * 1024,