Replace the read back of the software interrupt register with barrier instructions...

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@1858 1d2547de-c912-0410-9cb9-b8ca96c0e9e2

diff --git a/FreeRTOS/Source/portable/CCS/ARM_Cortex-R4/portmacro.h b/FreeRTOS/Source/portable/CCS/ARM_Cortex-R4/portmacro.h
index 9d3aeceb582060a0b79e01425d918cecdfdb596d..3c665fc900cd97bed96e4bfb0b5b5f9dcb1f16ac 100644 (file)
--- a/FreeRTOS/Source/portable/CCS/ARM_Cortex-R4/portmacro.h
+++ b/FreeRTOS/Source/portable/CCS/ARM_Cortex-R4/portmacro.h
@@ -56,19 +56,19 @@
     ***************************************************************************\r
 \r
 \r
-    http://www.FreeRTOS.org - Documentation, books, training, latest versions, \r
+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
     license and Real Time Engineers Ltd. contact details.\r
 \r
     http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
     including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
     fully thread aware and reentrant UDP/IP stack.\r
 \r
-    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High \r
-    Integrity Systems, who sell the code with commercial support, \r
+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+    Integrity Systems, who sell the code with commercial support,\r
     indemnification and middleware, under the OpenRTOS brand.\r
-    \r
-    http://www.SafeRTOS.com - High Integrity Systems also provide a safety \r
-    engineered and independently SIL3 certified version for use in safety and \r
+\r
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+    engineered and independently SIL3 certified version for use in safety and\r
     mission critical applications that require provable dependability.\r
 */\r
 \r
@@ -105,7 +105,7 @@
 \r
 /* Architecture specifics. */\r
 #define portSTACK_GROWTH    (-1)\r
-#define portTICK_RATE_MS    ((portTickType) 1000 / configTICK_RATE_HZ)         \r
+#define portTICK_RATE_MS    ((portTickType) 1000 / configTICK_RATE_HZ)\r
 #define portBYTE_ALIGNMENT  8\r
 \r
 /* Critical section handling. */\r
@@ -122,7 +122,7 @@ extern void vPortYield( void );
 #define portYIELD()                    vPortYield()\r
 #define portSYS_SSIR1_REG                      ( * ( ( volatile unsigned long * ) 0xFFFFFFB0 ) )\r
 #define portSYS_SSIR1_SSKEY                    ( 0x7500UL )\r
-#define portYIELD_WITHIN_API()         { portSYS_SSIR1_REG = portSYS_SSIR1_SSKEY;  ( void ) portSYS_SSIR1_REG; }\r
+#define portYIELD_WITHIN_API()         { portSYS_SSIR1_REG = portSYS_SSIR1_SSKEY;  asm( " DSB " ); asm( " ISB " ); }\r
 #define portYIELD_FROM_ISR( x )                if( x != pdFALSE ){ portSYS_SSIR1_REG = portSYS_SSIR1_SSKEY;  ( void ) portSYS_SSIR1_REG; }\r
 \r
 /* Architecture specific optimisations. */\r