board: add TP-Link WDR4300 config

tested on TP-Link WDR4300 v1.7

Change-Id: If2b456afac835ab3a3987d434d20824c7ba75b93
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-on: http://openocd.zylin.com/4192
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>

diff --git a/tcl/board/tp-link_wdr4300.cfg b/tcl/board/tp-link_wdr4300.cfg
new file mode 100644 (file)
index 0000000..c317916
--- /dev/null
+++ b/tcl/board/tp-link_wdr4300.cfg
@@ -0,0 +1,160 @@
+source [find target/atheros_ar9344.cfg]
+
+reset_config trst_only separate
+
+proc ar9344_40mhz_pll_init {} {
+       # QCA_PLL_SRIF_CPU_DPLL2_REG
+       mww 0xb81161C4 0x13210f00
+       # QCA_PLL_SRIF_CPU_DPLL3_REG
+       mww 0xb81161C8 0x03000000
+       # QCA_PLL_SRIF_DDR_DPLL2_REG
+       mww 0xb8116244 0x13210f00
+       # QCA_PLL_SRIF_DDR_DPLL3_REG
+       mww 0xb8116248 0x03000000
+       # QCA_PLL_SRIF_BB_DPLL_BASE_REG
+       mww 0xb8116188 0x03000000
+
+       # QCA_PLL_CPU_DDR_CLK_CTRL_REG
+       mww 0xb8050008 0x0130001C
+       mww 0xb8050008 0x0130001C
+       mww 0xb8050008 0x0130001C
+
+       # QCA_PLL_CPU_PLL_CFG_REG
+       mww 0xb8050000 0x40021380
+       # QCA_PLL_DDR_PLL_CFG_REG
+       mww 0xb8050004 0x40815800
+       # QCA_PLL_CPU_DDR_CLK_CTRL_REG
+       mww 0xb8050008 0x0130801C
+
+       # QCA_PLL_SRIF_CPU_DPLL2_REG
+       mww 0xb81161C4 0x10810F00
+       mww 0xb81161C0 0x41C00000
+       # QCA_PLL_SRIF_CPU_DPLL2_REG
+       mww 0xb81161C4 0xD0810F00
+       # QCA_PLL_SRIF_CPU_DPLL3_REG
+       mww 0xb81161C8 0x03000000
+       # QCA_PLL_SRIF_CPU_DPLL2_REG
+       mww 0xb81161C4 0xD0800F00
+
+       # QCA_PLL_SRIF_CPU_DPLL3_REG
+       mww 0xb81161C8 0x03000000
+       # QCA_PLL_SRIF_CPU_DPLL3_REG
+       mww 0xb81161C8 0x43000000
+       # QCA_PLL_SRIF_CPU_DPLL3_REG
+       mww 0xb81161C8 0x030003E8
+
+       # QCA_PLL_SRIF_DDR_DPLL2_REG
+       mww 0xb8116244 0x10810F00
+       mww 0xb8116240 0x41680000
+       # QCA_PLL_SRIF_DDR_DPLL2_REG
+       mww 0xb8116244 0xD0810F00
+       # QCA_PLL_SRIF_DDR_DPLL3_REG
+       mww 0xb8116248 0x03000000
+       # QCA_PLL_SRIF_DDR_DPLL2_REG
+       mww 0xb8116244 0xD0800F00
+
+       # QCA_PLL_SRIF_DDR_DPLL3_REG
+       mww 0xb8116248 0x03000000
+       # QCA_PLL_SRIF_DDR_DPLL3_REG
+       mww 0xb8116248 0x43000000
+       # QCA_PLL_SRIF_DDR_DPLL3_REG
+       mww 0xb8116248 0x03000718
+
+       # QCA_PLL_CPU_DDR_CLK_CTRL_REG
+       mww 0xb8050008 0x01308018
+       mww 0xb8050008 0x01308010
+       mww 0xb8050008 0x01308000
+
+       # QCA_PLL_DDR_PLL_DITHER_REG
+       mww 0xb8050044 0x78180200
+       # QCA_PLL_CPU_PLL_DITHER_REG
+       mww 0xb8050048 0x41C00000
+
+}
+
+proc ar9344_ddr_init {} {
+       # QCA_DDR_CTRL_CFG_REG
+       mww 0xb8000108 0x40
+       # QCA_DDR_RD_DATA_THIS_CYCLE_REG
+       mww 0xb8000018 0xFF
+       # QCA_DDR_BURST_REG
+       mww 0xb80000C4 0x74444444
+       # QCA_DDR_BURST2_REG
+       mww 0xb80000C8 0x0222
+       # QCA_AHB_MASTER_TOUT_MAX_REG
+       mww 0xb80000CC 0xFFFFF
+
+       # QCA_DDR_CFG_REG
+       mww 0xb8000000 0xC7D48CD0
+       # QCA_DDR_CFG2_REG
+       mww 0xb8000004 0x9DD0E6A8
+
+       # QCA_DDR_DDR2_CFG_REG
+       mww 0xb80000B8 0x0E59
+       # QCA_DDR_CFG2_REG
+       mww 0xb8000004 0x9DD0E6A8
+
+       # QCA_DDR_CTRL_REG
+       mww 0xb8000010 0x08
+       mww 0xb8000010 0x08
+       mww 0xb8000010 0x10
+       mww 0xb8000010 0x20
+       # QCA_DDR_EMR_REG
+       mww 0xb800000C 0x02
+       # QCA_DDR_CTRL_REG
+       mww 0xb8000010 0x02
+
+       # QCA_DDR_MR_REG
+       mww 0xb8000008 0x0133
+       # QCA_DDR_CTRL_REG
+       mww 0xb8000010 0x1
+       mww 0xb8000010 0x8
+       mww 0xb8000010 0x8
+       mww 0xb8000010 0x4
+       mww 0xb8000010 0x4
+
+       # QCA_DDR_MR_REG
+       mww 0xb8000008 0x33
+       # QCA_DDR_CTRL_REG
+       mww 0xb8000010 0x1
+
+       # QCA_DDR_EMR_REG
+       mww 0xb800000C 0x0382
+       # QCA_DDR_CTRL_REG
+       mww 0xb8000010 0x2
+       # QCA_DDR_EMR_REG
+       mww 0xb800000C 0x0402
+       # QCA_DDR_CTRL_REG
+       mww 0xb8000010 0x2
+
+       # QCA_DDR_REFRESH_REG
+       mww 0xb8000014 0x4270
+
+       # QCA_DDR_TAP_CTRL_0_REG
+       mww 0xb800001C 0x0e
+       # QCA_DDR_TAP_CTRL_1_REG
+       mww 0xb8000020 0x0e
+       # QCA_DDR_TAP_CTRL_2_REG
+       mww 0xb8000024 0x0e
+       # QCA_DDR_TAP_CTRL_3_REG
+       mww 0xb8000028 0x0e
+}
+
+$_TARGETNAME configure -event reset-init {
+
+       # mww 0xb806001c 0x1000000
+       ar9344_40mhz_pll_init
+       sleep 100
+
+       # flash remap
+       # SPI_CONTROL_ADDR
+       mww 0xbF000004 0x43
+
+       ar9344_ddr_init
+       sleep 100
+}
+
+set ram_boot_address 0xa0000000
+$_TARGETNAME configure -work-area-phys 0x1d000000 -work-area-size 0x1000
+
+flash bank flash0 ath79 0 0 0 0 $_TARGETNAME cs0