Set ARM byte alignment to 8.

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@878 1d2547de-c912-0410-9cb9-b8ca96c0e9e2

diff --git a/Source/portable/GCC/ARM7_AT91FR40008/portmacro.h b/Source/portable/GCC/ARM7_AT91FR40008/portmacro.h
index 8ea6b8ef4f88b9fa2bf15dc66a90097bd8921012..1fb4c0a37bf6f2d94175ebd84a05c1cc01669019 100644 (file)
--- a/Source/portable/GCC/ARM7_AT91FR40008/portmacro.h
+++ b/Source/portable/GCC/ARM7_AT91FR40008/portmacro.h
@@ -106,7 +106,7 @@ extern "C" {
 /* Hardware specifics. */\r
 #define portSTACK_GROWTH                       ( -1 )\r
 #define portTICK_RATE_MS                       ( ( portTickType ) 1000 / configTICK_RATE_HZ )          \r
-#define portBYTE_ALIGNMENT                     4\r
+#define portBYTE_ALIGNMENT                     8\r
 #define portYIELD()                                    asm volatile ( "SWI" )\r
 #define portNOP()                                      asm volatile ( "NOP" )\r
 \r

diff --git a/Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h b/Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h
index 354fdaa5d851709f4ec814d94661aca97ce8b9f6..5d1e9e1a7cff58da6fab8f441b625aefb93cea9f 100644 (file)
--- a/Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h
+++ b/Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h
@@ -106,7 +106,7 @@ extern "C" {
 /* Architecture specifics. */\r
 #define portSTACK_GROWTH                       ( -1 )\r
 #define portTICK_RATE_MS                       ( ( portTickType ) 1000 / configTICK_RATE_HZ )          \r
-#define portBYTE_ALIGNMENT                     4\r
+#define portBYTE_ALIGNMENT                     8\r
 #define portNOP()                                      asm volatile ( "NOP" );\r
 /*-----------------------------------------------------------*/        \r
 \r

diff --git a/Source/portable/GCC/ARM7_LPC2000/port.c b/Source/portable/GCC/ARM7_LPC2000/port.c
index 07cf3f9c744673774d6580993a2f8f09abeef405..36310204e67bbcb8285d5c0d47347fa662f2d6e8 100644 (file)
--- a/Source/portable/GCC/ARM7_LPC2000/port.c
+++ b/Source/portable/GCC/ARM7_LPC2000/port.c
@@ -164,12 +164,11 @@ portSTACK_TYPE *pxOriginalTOS;
        system mode, with interrupts enabled. */\r
        *pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR;\r
 \r
-       #ifdef THUMB_INTERWORK\r
+       if( ( ( unsigned long ) pxCode & 0x01UL ) != 0x00 )\r
        {\r
                /* We want the task to start in thumb mode. */\r
                *pxTopOfStack |= portTHUMB_MODE_BIT;\r
        }\r
-       #endif\r
 \r
        pxTopOfStack--;\r
 \r

diff --git a/Source/portable/GCC/ARM7_LPC2000/portISR.c b/Source/portable/GCC/ARM7_LPC2000/portISR.c
index 04d58afe2ad7e9d392a02e7e7e4918a32ad0f3b2..81c0c294339ff4df83c2baeca57ee53df91c96f5 100644 (file)
--- a/Source/portable/GCC/ARM7_LPC2000/portISR.c
+++ b/Source/portable/GCC/ARM7_LPC2000/portISR.c
@@ -73,7 +73,6 @@
 \r
 /* Scheduler includes. */\r
 #include "FreeRTOS.h"\r
-#include "task.h"\r
 \r
 /* Constants required to handle interrupts. */\r
 #define portTIMER_MATCH_ISR_BIT                ( ( unsigned portCHAR ) 0x01 )\r
@@ -116,13 +115,13 @@ void vPortYieldProcessor( void )
        /* Within an IRQ ISR the link register has an offset from the true return \r
        address, but an SWI ISR does not.  Add the offset manually so the same \r
        ISR return code can be used in both cases. */\r
-       asm volatile ( "ADD             LR, LR, #4" );\r
+       __asm volatile ( "ADD           LR, LR, #4" );\r
 \r
        /* Perform the context switch.  First save the context of the current task. */\r
        portSAVE_CONTEXT();\r
 \r
        /* Find the highest priority task that is ready to run. */\r
-       vTaskSwitchContext();\r
+       __asm volatile ( "bl vTaskSwitchContext" );\r
 \r
        /* Restore the context of the new task. */\r
        portRESTORE_CONTEXT();  \r
@@ -140,10 +139,10 @@ void vTickISR( void )
 \r
        /* Increment the RTOS tick count, then look for the highest priority \r
        task that is ready to run. */\r
-       vTaskIncrementTick();\r
+       __asm volatile( "bl vTaskIncrementTick" );\r
 \r
        #if configUSE_PREEMPTION == 1\r
-               vTaskSwitchContext();\r
+               __asm volatile( "bl vTaskSwitchContext" );\r
        #endif\r
 \r
        /* Ready for the next interrupt. */\r
@@ -168,7 +167,7 @@ void vTickISR( void )
 \r
        void vPortDisableInterruptsFromThumb( void )\r
        {\r
-               asm volatile ( \r
+               __asm volatile ( \r
                        "STMDB  SP!, {R0}               \n\t"   /* Push R0.                                                                     */\r
                        "MRS    R0, CPSR                \n\t"   /* Get CPSR.                                                            */\r
                        "ORR    R0, R0, #0xC0   \n\t"   /* Disable IRQ, FIQ.                                            */\r
@@ -179,7 +178,7 @@ void vTickISR( void )
                        \r
        void vPortEnableInterruptsFromThumb( void )\r
        {\r
-               asm volatile ( \r
+               __asm volatile ( \r
                        "STMDB  SP!, {R0}               \n\t"   /* Push R0.                                                                     */      \r
                        "MRS    R0, CPSR                \n\t"   /* Get CPSR.                                                            */      \r
                        "BIC    R0, R0, #0xC0   \n\t"   /* Enable IRQ, FIQ.                                                     */      \r
@@ -197,7 +196,7 @@ in a variable, which is then saved as part of the stack context. */
 void vPortEnterCritical( void )\r
 {\r
        /* Disable interrupts as per portDISABLE_INTERRUPTS();                                                  */\r
-       asm volatile ( \r
+       __asm volatile ( \r
                "STMDB  SP!, {R0}                       \n\t"   /* Push R0.                                                             */\r
                "MRS    R0, CPSR                        \n\t"   /* Get CPSR.                                                    */\r
                "ORR    R0, R0, #0xC0           \n\t"   /* Disable IRQ, FIQ.                                    */\r
@@ -222,7 +221,7 @@ void vPortExitCritical( void )
                if( ulCriticalNesting == portNO_CRITICAL_NESTING )\r
                {\r
                        /* Enable interrupts as per portEXIT_CRITICAL().                                        */\r
-                       asm volatile ( \r
+                       __asm volatile ( \r
                                "STMDB  SP!, {R0}               \n\t"   /* Push R0.                                             */      \r
                                "MRS    R0, CPSR                \n\t"   /* Get CPSR.                                    */      \r
                                "BIC    R0, R0, #0xC0   \n\t"   /* Enable IRQ, FIQ.                             */      \r

diff --git a/Source/portable/GCC/ARM7_LPC2000/portmacro.h b/Source/portable/GCC/ARM7_LPC2000/portmacro.h
index 354fdaa5d851709f4ec814d94661aca97ce8b9f6..80455c386c1b6c317009d17bc5dc96f07bf6b9e3 100644 (file)
--- a/Source/portable/GCC/ARM7_LPC2000/portmacro.h
+++ b/Source/portable/GCC/ARM7_LPC2000/portmacro.h
@@ -45,29 +45,6 @@
        licensing and training services.\r
 */\r
 \r
-/*\r
-       Changes from V3.2.3\r
-       \r
-       + Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1.\r
-\r
-       Changes from V3.2.4\r
-\r
-       + Removed the use of the %0 parameter within the assembler macros and \r
-         replaced them with hard coded registers.  This will ensure the\r
-         assembler does not select the link register as the temp register as\r
-         was occasionally happening previously.\r
-\r
-       + The assembler statements are now included in a single asm block rather\r
-         than each line having its own asm block.\r
-\r
-       Changes from V4.5.0\r
-\r
-       + Removed the portENTER_SWITCHING_ISR() and portEXIT_SWITCHING_ISR() macros\r
-         and replaced them with portYIELD_FROM_ISR() macro.  Application code \r
-         should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT()\r
-         macros as per the V4.5.1 demo code.\r
-*/\r
-\r
 #ifndef PORTMACRO_H\r
 #define PORTMACRO_H\r
 \r
@@ -106,8 +83,8 @@ extern "C" {
 /* Architecture specifics. */\r
 #define portSTACK_GROWTH                       ( -1 )\r
 #define portTICK_RATE_MS                       ( ( portTickType ) 1000 / configTICK_RATE_HZ )          \r
-#define portBYTE_ALIGNMENT                     4\r
-#define portNOP()                                      asm volatile ( "NOP" );\r
+#define portBYTE_ALIGNMENT                     8\r
+#define portNOP()                                      __asm volatile ( "NOP" );\r
 /*-----------------------------------------------------------*/        \r
 \r
 \r
@@ -126,7 +103,7 @@ extern volatile void * volatile pxCurrentTCB;                                                       \
 extern volatile unsigned portLONG ulCriticalNesting;                                   \\r
                                                                                                                                                \\r
        /* Set the LR to the task stack. */                                                                     \\r
-       asm volatile (                                                                                                          \\r
+       __asm volatile (                                                                                                        \\r
        "LDR            R0, =pxCurrentTCB                                                               \n\t"   \\r
        "LDR            R0, [R0]                                                                                \n\t"   \\r
        "LDR            LR, [R0]                                                                                \n\t"   \\r
@@ -163,7 +140,7 @@ extern volatile void * volatile pxCurrentTCB;                                                       \
 extern volatile unsigned portLONG ulCriticalNesting;                                   \\r
                                                                                                                                                \\r
        /* Push R0 as we are going to use the register. */                                      \\r
-       asm volatile (                                                                                                          \\r
+       __asm volatile (                                                                                                        \\r
        "STMDB  SP!, {R0}                                                                                       \n\t"   \\r
                                                                                                                                                \\r
        /* Set R0 to point to the task stack pointer. */                                        \\r
@@ -203,9 +180,9 @@ extern volatile unsigned portLONG ulCriticalNesting;                                        \
        ( void ) pxCurrentTCB;                                                                                          \\r
 }\r
 \r
-\r
+extern void vTaskSwitchContext( void );\r
 #define portYIELD_FROM_ISR()           vTaskSwitchContext()\r
-#define portYIELD()                                    asm volatile ( "SWI" )\r
+#define portYIELD()                                    __asm volatile ( "SWI" )\r
 /*-----------------------------------------------------------*/\r
 \r
 \r
@@ -229,7 +206,7 @@ extern volatile unsigned portLONG ulCriticalNesting;                                        \
 #else\r
 \r
        #define portDISABLE_INTERRUPTS()                                                                                        \\r
-               asm volatile (                                                                                                                  \\r
+               __asm volatile (                                                                                                                \\r
                        "STMDB  SP!, {R0}               \n\t"   /* Push R0.                                             */      \\r
                        "MRS    R0, CPSR                \n\t"   /* Get CPSR.                                    */      \\r
                        "ORR    R0, R0, #0xC0   \n\t"   /* Disable IRQ, FIQ.                    */      \\r
@@ -237,7 +214,7 @@ extern volatile unsigned portLONG ulCriticalNesting;                                        \
                        "LDMIA  SP!, {R0}                       " )     /* Pop R0.                                              */\r
                        \r
        #define portENABLE_INTERRUPTS()                                                                                         \\r
-               asm volatile (                                                                                                                  \\r
+               __asm volatile (                                                                                                                \\r
                        "STMDB  SP!, {R0}               \n\t"   /* Push R0.                                             */      \\r
                        "MRS    R0, CPSR                \n\t"   /* Get CPSR.                                    */      \\r
                        "BIC    R0, R0, #0xC0   \n\t"   /* Enable IRQ, FIQ.                             */      \\r

diff --git a/Source/portable/GCC/ARM7_LPC23xx/portISR.c b/Source/portable/GCC/ARM7_LPC23xx/portISR.c
index 84937600dd06edad85c0fe336f2f5ce9d26ff5a9..66af1e7bb62eeba94059027675ab4ae801baffe9 100644 (file)
--- a/Source/portable/GCC/ARM7_LPC23xx/portISR.c
+++ b/Source/portable/GCC/ARM7_LPC23xx/portISR.c
@@ -97,13 +97,13 @@ void vPortYieldProcessor( void )
        /* Within an IRQ ISR the link register has an offset from the true return \r
        address, but an SWI ISR does not.  Add the offset manually so the same \r
        ISR return code can be used in both cases. */\r
-       asm volatile ( "ADD             LR, LR, #4" );\r
+       __asm volatile ( "ADD           LR, LR, #4" );\r
 \r
        /* Perform the context switch.  First save the context of the current task. */\r
        portSAVE_CONTEXT();\r
 \r
        /* Find the highest priority task that is ready to run. */\r
-       vTaskSwitchContext();\r
+       __asm volatile( "bl                     vTaskSwitchContext" );\r
 \r
        /* Restore the context of the new task. */\r
        portRESTORE_CONTEXT();  \r
@@ -140,8 +140,8 @@ void vPortYieldProcessor( void )
 \r
                /* Increment the RTOS tick count, then look for the highest priority \r
                task that is ready to run. */\r
-               vTaskIncrementTick();\r
-               vTaskSwitchContext();\r
+               __asm volatile( "bl vTaskIncrementTick" );\r
+               __asm volatile( "bl vTaskSwitchContext" );\r
 \r
                /* Ready for the next interrupt. */\r
                T0IR = 2;\r
@@ -167,7 +167,7 @@ void vPortYieldProcessor( void )
 \r
        void vPortDisableInterruptsFromThumb( void )\r
        {\r
-               asm volatile ( \r
+               __asm volatile ( \r
                        "STMDB  SP!, {R0}               \n\t"   /* Push R0.                                                                     */\r
                        "MRS    R0, CPSR                \n\t"   /* Get CPSR.                                                            */\r
                        "ORR    R0, R0, #0xC0   \n\t"   /* Disable IRQ, FIQ.                                            */\r
@@ -178,7 +178,7 @@ void vPortYieldProcessor( void )
                        \r
        void vPortEnableInterruptsFromThumb( void )\r
        {\r
-               asm volatile ( \r
+               __asm volatile ( \r
                        "STMDB  SP!, {R0}               \n\t"   /* Push R0.                                                                     */      \r
                        "MRS    R0, CPSR                \n\t"   /* Get CPSR.                                                            */      \r
                        "BIC    R0, R0, #0xC0   \n\t"   /* Enable IRQ, FIQ.                                                     */      \r
@@ -196,7 +196,7 @@ in a variable, which is then saved as part of the stack context. */
 void vPortEnterCritical( void )\r
 {\r
        /* Disable interrupts as per portDISABLE_INTERRUPTS();                                                  */\r
-       asm volatile ( \r
+       __asm volatile ( \r
                "STMDB  SP!, {R0}                       \n\t"   /* Push R0.                                                             */\r
                "MRS    R0, CPSR                        \n\t"   /* Get CPSR.                                                    */\r
                "ORR    R0, R0, #0xC0           \n\t"   /* Disable IRQ, FIQ.                                    */\r
@@ -221,7 +221,7 @@ void vPortExitCritical( void )
                if( ulCriticalNesting == portNO_CRITICAL_NESTING )\r
                {\r
                        /* Enable interrupts as per portEXIT_CRITICAL().                                        */\r
-                       asm volatile ( \r
+                       __asm volatile ( \r
                                "STMDB  SP!, {R0}               \n\t"   /* Push R0.                                             */      \r
                                "MRS    R0, CPSR                \n\t"   /* Get CPSR.                                    */      \r
                                "BIC    R0, R0, #0xC0   \n\t"   /* Enable IRQ, FIQ.                             */      \r

diff --git a/Source/portable/GCC/ARM7_LPC23xx/portmacro.h b/Source/portable/GCC/ARM7_LPC23xx/portmacro.h
index 354fdaa5d851709f4ec814d94661aca97ce8b9f6..4f0cd850a212a15bd7e0d4e2f18336c08a9aa0c3 100644 (file)
--- a/Source/portable/GCC/ARM7_LPC23xx/portmacro.h
+++ b/Source/portable/GCC/ARM7_LPC23xx/portmacro.h
@@ -106,8 +106,8 @@ extern "C" {
 /* Architecture specifics. */\r
 #define portSTACK_GROWTH                       ( -1 )\r
 #define portTICK_RATE_MS                       ( ( portTickType ) 1000 / configTICK_RATE_HZ )          \r
-#define portBYTE_ALIGNMENT                     4\r
-#define portNOP()                                      asm volatile ( "NOP" );\r
+#define portBYTE_ALIGNMENT                     8\r
+#define portNOP()                                      __asm volatile ( "NOP" );\r
 /*-----------------------------------------------------------*/        \r
 \r
 \r
@@ -126,7 +126,7 @@ extern volatile void * volatile pxCurrentTCB;                                                       \
 extern volatile unsigned portLONG ulCriticalNesting;                                   \\r
                                                                                                                                                \\r
        /* Set the LR to the task stack. */                                                                     \\r
-       asm volatile (                                                                                                          \\r
+       __asm volatile (                                                                                                        \\r
        "LDR            R0, =pxCurrentTCB                                                               \n\t"   \\r
        "LDR            R0, [R0]                                                                                \n\t"   \\r
        "LDR            LR, [R0]                                                                                \n\t"   \\r
@@ -163,7 +163,7 @@ extern volatile void * volatile pxCurrentTCB;                                                       \
 extern volatile unsigned portLONG ulCriticalNesting;                                   \\r
                                                                                                                                                \\r
        /* Push R0 as we are going to use the register. */                                      \\r
-       asm volatile (                                                                                                          \\r
+       __asm volatile (                                                                                                        \\r
        "STMDB  SP!, {R0}                                                                                       \n\t"   \\r
                                                                                                                                                \\r
        /* Set R0 to point to the task stack pointer. */                                        \\r
@@ -205,7 +205,7 @@ extern volatile unsigned portLONG ulCriticalNesting;                                        \
 \r
 \r
 #define portYIELD_FROM_ISR()           vTaskSwitchContext()\r
-#define portYIELD()                                    asm volatile ( "SWI" )\r
+#define portYIELD()                                    __asm volatile ( "SWI" )\r
 /*-----------------------------------------------------------*/\r
 \r
 \r
@@ -229,7 +229,7 @@ extern volatile unsigned portLONG ulCriticalNesting;                                        \
 #else\r
 \r
        #define portDISABLE_INTERRUPTS()                                                                                        \\r
-               asm volatile (                                                                                                                  \\r
+               __asm volatile (                                                                                                                        \\r
                        "STMDB  SP!, {R0}               \n\t"   /* Push R0.                                             */      \\r
                        "MRS    R0, CPSR                \n\t"   /* Get CPSR.                                    */      \\r
                        "ORR    R0, R0, #0xC0   \n\t"   /* Disable IRQ, FIQ.                    */      \\r
@@ -237,7 +237,7 @@ extern volatile unsigned portLONG ulCriticalNesting;                                        \
                        "LDMIA  SP!, {R0}                       " )     /* Pop R0.                                              */\r
                        \r
        #define portENABLE_INTERRUPTS()                                                                                         \\r
-               asm volatile (                                                                                                                  \\r
+               __asm volatile (                                                                                                                        \\r
                        "STMDB  SP!, {R0}               \n\t"   /* Push R0.                                             */      \\r
                        "MRS    R0, CPSR                \n\t"   /* Get CPSR.                                    */      \\r
                        "BIC    R0, R0, #0xC0   \n\t"   /* Enable IRQ, FIQ.                             */      \\r

diff --git a/Source/portable/GCC/ARM_CM3/portmacro.h b/Source/portable/GCC/ARM_CM3/portmacro.h
index e602122a99931fc335a0cecf414081de6401322a..99dca454d347c92416057bd551ce621ad77a3568 100644 (file)
--- a/Source/portable/GCC/ARM_CM3/portmacro.h
+++ b/Source/portable/GCC/ARM_CM3/portmacro.h
@@ -84,7 +84,7 @@ extern "C" {
 /* Architecture specifics. */\r
 #define portSTACK_GROWTH                       ( -1 )\r
 #define portTICK_RATE_MS                       ( ( portTickType ) 1000 / configTICK_RATE_HZ )          \r
-#define portBYTE_ALIGNMENT                     4\r
+#define portBYTE_ALIGNMENT                     8\r
 /*-----------------------------------------------------------*/        \r
 \r
 \r