BBRx, BBSx, RMBx, SMBx, WAI, and STP are unsupported
* BCD flag handling equals 6502 (unchecked if bug is simulated or wrong for
6502)
- * one cycle win for fetch-modify-write instructions ignored
- (e.g., ROL abs,x takes only 6 cycles if no page break occurs)
*/
#include "memory.h"
unsigned Val;
Cycles = 7;
Addr = MemReadWord (Regs.PC+1) + Regs.XR;
+ if (CPU != CPU_6502 && !PAGE_CROSS (Addr, Regs.XR))
+ --Cycles;
Val = MemReadByte (Addr) << 1;
MemWriteByte (Addr, (unsigned char) Val);
TEST_ZF (Val & 0xFF);
unsigned Val;
Cycles = 7;
Addr = MemReadWord (Regs.PC+1) + Regs.XR;
+ if (CPU != CPU_6502 && !PAGE_CROSS (Addr, Regs.XR))
+ --Cycles;
Val = MemReadByte (Addr);
ROL (Val);
MemWriteByte (Addr, Val);
unsigned char Val;
Cycles = 7;
Addr = MemReadWord (Regs.PC+1) + Regs.XR;
+ if (CPU != CPU_6502 && !PAGE_CROSS (Addr, Regs.XR))
+ --Cycles;
Val = MemReadByte (Addr);
SET_CF (Val & 0x01);
Val >>= 1;
unsigned Val;
Cycles = 7;
Addr = MemReadWord (Regs.PC+1) + Regs.XR;
+ if (CPU != CPU_6502 && !PAGE_CROSS (Addr, Regs.XR))
+ --Cycles;
Val = MemReadByte (Addr);
ROR (Val);
MemWriteByte (Addr, Val);
unsigned char Val;
Cycles = 7;
Addr = MemReadWord (Regs.PC+1) + Regs.XR;
+ if (CPU != CPU_6502 && !PAGE_CROSS (Addr, Regs.XR))
+ --Cycles;
Val = MemReadByte (Addr) - 1;
MemWriteByte (Addr, Val);
TEST_ZF (Val);
unsigned char Val;
Cycles = 7;
Addr = MemReadWord (Regs.PC+1) + Regs.XR;
+ if (CPU != CPU_6502 && !PAGE_CROSS (Addr, Regs.XR))
+ --Cycles;
Val = MemReadByte (Addr) + 1;
MemWriteByte (Addr, Val);
TEST_ZF (Val);