From: rtel <rtel@1d2547de-c912-0410-9cb9-b8ca96c0e9e2>
Date: Tue, 29 Jul 2014 21:31:04 +0000 (+0000)
Subject: Continue working on the GIC-less Cortex-A5 port for IAR:
X-Git-Tag: V8.1.0~9
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;ds=sidebyside;h=2b5594f2123069320c3e94cad1225f04655b3a9f;p=freertos

Continue working on the GIC-less Cortex-A5 port for IAR:
- Add in the assert when a task attempts to exit its implementing function without deleting itself.
- Remove obsolete code from the context switch asm code (obsoleted by the fact that there is no mask register).
- Attempt to make code more generic by using definitions for additional register addresses.

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2283 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
---

diff --git a/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/port.c b/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/port.c
index b8c1b6414..965d304f5 100644
--- a/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/port.c
+++ b/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/port.c
@@ -111,6 +111,11 @@ mode. */
  */
 extern void vPortRestoreTaskContext( void );
 
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
 /*-----------------------------------------------------------*/
 
 /* A variable is used to keep track of the critical section nesting.  This
@@ -137,7 +142,6 @@ uint32_t ulPortInterruptNesting = 0UL;
 #warning What about branch distance in asm file.
 #warning Does not support flop use in ISRs.
 #warning Level interrupts must be cleared in their handling function.
-#warning Can this be made generic by defining the vector address register externally?
 
 /*
  * See header file for description.
@@ -165,13 +169,13 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
 	}
 
 	pxTopOfStack--;
-#warning What about task exit error function?
+
 	/* Next the return address, which in this case is the start of the task. */
 	*pxTopOfStack = ( StackType_t ) pxCode;
 	pxTopOfStack--;
 
 	/* Next all the registers other than the stack pointer. */
-	*pxTopOfStack = ( StackType_t ) 0x00000000;	/* R14 */
+	*pxTopOfStack = ( StackType_t ) prvTaskExitError;	/* R14 */
 	pxTopOfStack--;
 	*pxTopOfStack = ( StackType_t ) 0x12121212;	/* R12 */
 	pxTopOfStack--;
@@ -214,6 +218,20 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
 }
 /*-----------------------------------------------------------*/
 
+static void prvTaskExitError( void )
+{
+	/* A function that implements a task must not exit or attempt to return to
+	its caller as there is nothing to return to.  If a task wants to exit it
+	should instead call vTaskDelete( NULL ).
+
+	Artificially force an assert() to be triggered if configASSERT() is
+	defined, then stop here so application writers can catch the error. */
+	configASSERT( ulPortInterruptNesting == ~0UL );
+	portDISABLE_INTERRUPTS();
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
 BaseType_t xPortStartScheduler( void )
 {
 uint32_t ulAPSR;
@@ -228,7 +246,6 @@ uint32_t ulAPSR;
 	{
 		/* Start the timer that generates the tick ISR. */
 		configSETUP_TICK_INTERRUPT();
-#warning Install spurious handler
 		__enable_irq();
 		vPortRestoreTaskContext();
 	}
diff --git a/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portASM.h b/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portASM.h
index 3af3284d3..fe6c74579 100644
--- a/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portASM.h
+++ b/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portASM.h
@@ -127,18 +127,12 @@ portRESTORE_CONTEXT macro
 	POP		{R1}
 	STR		R1, [R0]
 
-	; Ensure the priority mask is correct for the critical nesting depth
-;_RB_	LDR		R2, =portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS
-	CMP		R1, #0
-	MOVEQ	R4, #255
-;_RB_	LDRNE	R4, =( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT )
-	STR		R4, [r2]
-
 	; Restore all system mode registers other than the SP (which is already
 	; being used)
 	POP		{R0-R12, R14}
 
-	; Return to the task code, loading CPSR on the way.
+	; Return to the task code, loading CPSR on the way.  CPSR has the interrupt
+	; enable bit set appropriately for the task about to execute.
 	RFEIA	sp!
 
 	endm
diff --git a/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portASM.s b/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portASM.s
index b9086d486..c66146964 100644
--- a/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portASM.s
+++ b/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portASM.s
@@ -67,10 +67,6 @@ SYS_MODE			EQU		0x1f
 SVC_MODE			EQU		0x13
 IRQ_MODE			EQU		0x12
 
-; AIC register definitions.
-AIC_IVR				EQU		0xFFFFF010UL
-AIC_EOICR			EQU		0xFFFFF038UL
-
 	SECTION .text:CODE:ROOT(2)
 	ARM
 
@@ -93,7 +89,7 @@ vPortRestoreTaskContext
 
 
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; AIC interrupt handler
+; IRQ interrupt handler used when individual priorities cannot be masked
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 FreeRTOS_IRQ_Handler
 
@@ -127,7 +123,7 @@ FreeRTOS_IRQ_Handler
 
 	; Call the interrupt handler
 	PUSH	{r0-r3, lr}
-	LDR		r1, =AIC_IVR
+	LDR		r1, =configINTERRUPT_VECTOR_ADDRESS
 	LDR		r0, [r1]
 	STR		r1, [r1] ; Write to IVR in case protect mode is being used.
 	BLX		r0
@@ -137,7 +133,7 @@ FreeRTOS_IRQ_Handler
 	CPSID	i
 
 	; Write to the EOI register
-	LDR 	r4, =AIC_EOICR
+	LDR 	r4, =configEOI_ADDRESS
 	STR		r0, [r4]
 
 	; Restore the old nesting count