From: Gabriel Huau <contact@huau-gabriel.fr>
Date: Sat, 25 Apr 2015 20:16:03 +0000 (-0700)
Subject: x86: baytrail: fix the GPIOBASE address
X-Git-Tag: v2015.07-rc1~42
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;ds=sidebyside;h=4a34e4b86f75547ff2a546f02196cdfb9439eca4;p=u-boot

x86: baytrail: fix the GPIOBASE address

The correct GPIOBASE address on the baytrail is 0x48

Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
---

diff --git a/arch/x86/include/asm/arch-baytrail/gpio.h b/arch/x86/include/asm/arch-baytrail/gpio.h
index ab4e059131..4e8987ce5c 100644
--- a/arch/x86/include/asm/arch-baytrail/gpio.h
+++ b/arch/x86/include/asm/arch-baytrail/gpio.h
@@ -8,6 +8,6 @@
 #define _X86_ARCH_GPIO_H_
 
 /* Where in config space is the register that points to the GPIO registers? */
-#define PCI_CFG_GPIOBASE 0x44
+#define PCI_CFG_GPIOBASE 0x48
 
 #endif /* _X86_ARCH_GPIO_H_ */