From: Oleksij Rempel <linux@rempel-privat.de>
Date: Wed, 5 Feb 2014 22:11:15 +0000 (+0100)
Subject: mips32.c: cache debug caps and support EJTAG 2.0 specific changes
X-Git-Tag: v0.9.0-rc1~309
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=02ac60b0000977c707011abeac49c58de78bb9e5;p=openocd

mips32.c: cache debug caps and support EJTAG 2.0 specific changes

EJTAG v2.0 indicated some debug caps in IMP register.
V2.6 moved them to DCR register. To make it more universal,
convert this values and store them for later use.

Change-Id: Id6b9f47c9c2ea94d37281ebfcae5acf357261ddf
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-on: http://openocd.zylin.com/1932
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
---

diff --git a/src/target/mips32.c b/src/target/mips32.c
index 795efddf..d842705f 100644
--- a/src/target/mips32.c
+++ b/src/target/mips32.c
@@ -536,31 +536,36 @@ int mips32_configure_break_unit(struct target *target)
 	if (retval != ERROR_OK)
 		return retval;
 
-	/* EJTAG 2.0 defines IB and DB bits in IMP instead of DCR.
-	 * Since these DCR bits should be reserved on EJTAG 2.0, we can
-	 * just remap them. */
+	/* EJTAG 2.0 defines IB and DB bits in IMP instead of DCR. */
 	if (ejtag_info->ejtag_version == EJTAG_VERSION_20) {
+		ejtag_info->debug_caps = dcr & EJTAG_DCR_ENM;
 		if (!(ejtag_info->impcode & EJTAG_V20_IMP_NOIB))
-			dcr |= EJTAG_DCR_IB;
+			ejtag_info->debug_caps |= EJTAG_DCR_IB;
 		if (!(ejtag_info->impcode & EJTAG_V20_IMP_NODB))
-			dcr |= EJTAG_DCR_DB;
-	}
+			ejtag_info->debug_caps |= EJTAG_DCR_DB;
+	} else
+		/* keep  debug caps for later use */
+		ejtag_info->debug_caps = dcr & (EJTAG_DCR_ENM
+				| EJTAG_DCR_IB | EJTAG_DCR_DB);
+
 
-	if (dcr & EJTAG_DCR_IB) {
+	if (ejtag_info->debug_caps & EJTAG_DCR_IB) {
 		retval = mips32_configure_ibs(target);
 		if (retval != ERROR_OK)
 			return retval;
 	}
 
-	if (dcr & EJTAG_DCR_DB) {
+	if (ejtag_info->debug_caps & EJTAG_DCR_DB) {
 		retval = mips32_configure_dbs(target);
 		if (retval != ERROR_OK)
 			return retval;
 	}
 
 	/* check if target endianness settings matches debug control register */
-	if (((dcr & EJTAG_DCR_ENM) && (target->endianness == TARGET_LITTLE_ENDIAN)) ||
-			(!(dcr & EJTAG_DCR_ENM) && (target->endianness == TARGET_BIG_ENDIAN)))
+	if (((ejtag_info->debug_caps & EJTAG_DCR_ENM)
+			&& (target->endianness == TARGET_LITTLE_ENDIAN)) ||
+			(!(ejtag_info->debug_caps & EJTAG_DCR_ENM)
+			 && (target->endianness == TARGET_BIG_ENDIAN)))
 		LOG_WARNING("DCR endianness settings does not match target settings");
 
 	LOG_DEBUG("DCR 0x%" PRIx32 " numinst %i numdata %i", dcr, mips32->num_inst_bpoints,
diff --git a/src/target/mips_ejtag.h b/src/target/mips_ejtag.h
index 4c8933c7..3e0d8310 100644
--- a/src/target/mips_ejtag.h
+++ b/src/target/mips_ejtag.h
@@ -194,6 +194,7 @@ struct mips_ejtag {
 
 	/* Memory-Mapped Registers. This addresses are not same on different
 	 * EJTAG versions. */
+	uint32_t debug_caps;
 	uint32_t ejtag_ibs_addr;	/* Instruction Address Break Status */
 	uint32_t ejtag_iba0_addr;	/* IAB channel 0 */
 	uint32_t ejtag_ibc_offs;	/* IAB Control offset */