From: Michal Simek Date: Thu, 15 May 2014 07:40:14 +0000 (+0200) Subject: ARM: zynq: Show ECC status on the same line as DRAM size X-Git-Tag: v2014.10-rc1~38^2~14^2~1 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=03606ff42eb11a6beacc766a78819561abe930b1;p=u-boot ARM: zynq: Show ECC status on the same line as DRAM size Without this patch is DRAM size one line below DRAM: which is not nice Origin: I2C: ready DRAM: Memory: ECC disabled 1 GiB MMC: zynq_sdhci: 0 Fixed by this patch: I2C: ready DRAM: ECC disabled 1 GiB MMC: zynq_sdhci: 0 Signed-off-by: Michal Simek Tested-by: Masahiro Yamada --- diff --git a/arch/arm/cpu/armv7/zynq/ddrc.c b/arch/arm/cpu/armv7/zynq/ddrc.c index e0ed3bfb43..1ea086d520 100644 --- a/arch/arm/cpu/armv7/zynq/ddrc.c +++ b/arch/arm/cpu/armv7/zynq/ddrc.c @@ -34,7 +34,7 @@ void zynq_ddrc_init(void) /* ECC is enabled when memory is in 16bit mode and it is enabled */ if ((ecctype == ZYNQ_DDRC_ECC_SCRUBREG_ECCMODE_SECDED) && (width == ZYNQ_DDRC_CTRLREG_BUSWIDTH_16BIT)) { - puts("Memory: ECC enabled\n"); + puts("ECC enabled "); /* * Clear the first 1MB because it is not initialized from * first stage bootloader. To get ECC to work all memory has @@ -42,6 +42,6 @@ void zynq_ddrc_init(void) */ memset((void *)0, 0, 1 * 1024 * 1024); } else { - puts("Memory: ECC disabled\n"); + puts("ECC disabled "); } }