From: Andy Fleming <afleming@freescale.com>
Date: Mon, 23 Apr 2007 06:44:44 +0000 (-0500)
Subject: Some 85xx cpu cleanups
X-Git-Tag: v1.3.0-rc1~90^2~10
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=03b81b48eec0ad249ec97a4ae16c36fa2e014ff4;p=u-boot

Some 85xx cpu cleanups

* Cleaned up the TSR[WIS] clearing
* Cleaned up DMA initialization

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
---

diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c
index 2fe6bdf4b9..b701b477b1 100644
--- a/cpu/mpc85xx/cpu.c
+++ b/cpu/mpc85xx/cpu.c
@@ -198,9 +198,9 @@ reset_85xx_watchdog(void)
 	 * Clear TSR(WIS) bit by writing 1
 	 */
 	unsigned long val;
-	val = mfspr(tsr);
-	val |= 0x40000000;
-	mtspr(tsr, val);
+	val = mfspr(SPRN_TSR);
+	val |= TSR_WIS;
+	mtspr(SPRN_TSR, val);
 }
 #endif	/* CONFIG_WATCHDOG */
 
@@ -211,6 +211,7 @@ void dma_init(void) {
 
 	dma->satr0 = 0x02c40000;
 	dma->datr0 = 0x02c40000;
+	dma->sr0 = 0xfffffff; /* clear any errors */
 	asm("sync; isync; msync");
 	return;
 }
@@ -225,6 +226,10 @@ uint dma_check(void) {
 		status = dma->sr0;
 	}
 
+	/* clear MR0[CS] channel start bit */
+	dma->mr0 &= 0x00000001;
+	asm("sync;isync;msync");
+
 	if (status != 0) {
 		printf ("DMA Error: status = %x\n", status);
 	}