From: ntfreak Date: Thu, 24 Apr 2008 11:09:28 +0000 (+0000) Subject: - added svn props for newly added files X-Git-Tag: v0.1.0~674 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=040e25424314b49e35eb158eb88e287c76e50596;p=openocd - added svn props for newly added files git-svn-id: svn://svn.berlios.de/openocd/trunk@615 b42882b7-edfa-0310-969c-e2dbd0fdcd60 --- diff --git a/src/flash/ocl.c b/src/flash/ocl.c index befa4e10..4f3b506c 100644 --- a/src/flash/ocl.c +++ b/src/flash/ocl.c @@ -1,402 +1,402 @@ -/*************************************************************************** - * Copyright (C) 2007 by Pavel Chromy * - * chromy@asix.cz * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * - ***************************************************************************/ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - -#include "replacements.h" - -#include "ocl.h" - -#include "flash.h" -#include "target.h" -#include "log.h" -#include "binarybuffer.h" -#include "types.h" -#include "embeddedice.h" -#include "arm7_9_common.h" - -#include -#include -#include - -int ocl_register_commands(struct command_context_s *cmd_ctx); -int ocl_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank); -int ocl_erase(struct flash_bank_s *bank, int first, int last); -int ocl_protect(struct flash_bank_s *bank, int set, int first, int last); -int ocl_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count); -int ocl_probe(struct flash_bank_s *bank); -int ocl_erase_check(struct flash_bank_s *bank); -int ocl_protect_check(struct flash_bank_s *bank); -int ocl_info(struct flash_bank_s *bank, char *buf, int buf_size); -int ocl_auto_probe(struct flash_bank_s *bank); - -flash_driver_t ocl_flash = -{ - .name = "ocl", - .register_commands = ocl_register_commands, - .flash_bank_command = ocl_flash_bank_command, - .erase = ocl_erase, - .protect = ocl_protect, - .write = ocl_write, - .probe = ocl_probe, - .erase_check = ocl_erase_check, - .protect_check = ocl_protect_check, - .info = ocl_info, - .auto_probe = ocl_auto_probe -}; - - -typedef struct ocl_priv_s -{ - arm_jtag_t *jtag_info; - int buflen; - int bufalign; -} ocl_priv_t; - - -int ocl_register_commands(struct command_context_s *cmd_ctx) -{ - return ERROR_OK; -} - - -int ocl_erase_check(struct flash_bank_s *bank) -{ - return ERROR_OK; -} - - -int ocl_protect_check(struct flash_bank_s *bank) -{ - return ERROR_OK; -} - - -/* flash_bank ocl 0 0 0 0 */ -int ocl_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank) -{ - int retval; - armv4_5_common_t *armv4_5; - arm7_9_common_t *arm7_9; - ocl_priv_t *ocl; - - if (argc < 6) - { - LOG_WARNING("incomplete flash_bank ocl configuration"); - return ERROR_FLASH_BANK_INVALID; - } - - if ((retval = arm7_9_get_arch_pointers(bank->target, &armv4_5, &arm7_9)) != ERROR_OK) - return retval; - - ocl = bank->driver_priv = malloc(sizeof(ocl_priv_t)); - ocl->jtag_info = &arm7_9->jtag_info; - ocl->buflen = 0; - ocl->bufalign = 1; - - return ERROR_OK; -} - - -int ocl_erase(struct flash_bank_s *bank, int first, int last) -{ - ocl_priv_t *ocl = bank->driver_priv; - int retval; - u32 dcc_buffer[3]; - - /* check preconditions */ - if (bank->num_sectors == 0) - return ERROR_FLASH_BANK_NOT_PROBED; - - if (bank->target->state != TARGET_RUNNING) - { - LOG_ERROR("target has to be running to communicate with the loader"); - return ERROR_TARGET_NOT_RUNNING; - } - - if ((first == 0) && (last == bank->num_sectors - 1)) - { - dcc_buffer[0] = OCL_ERASE_ALL; - if ((retval = embeddedice_send(ocl->jtag_info, dcc_buffer, 1) != ERROR_OK)) - return retval; - } - else - { - dcc_buffer[0] = OCL_ERASE_BLOCK; - dcc_buffer[1] = first; - dcc_buffer[2] = last; - if ((retval = embeddedice_send(ocl->jtag_info, dcc_buffer, 3) != ERROR_OK)) - return retval; - } - - /* wait for response, fixed timeout of 1 s */ - if ((retval = embeddedice_handshake(ocl->jtag_info, EICE_COMM_CTRL_WBIT, 1000) != ERROR_OK)) - { - if (retval == ERROR_TARGET_TIMEOUT) - LOG_ERROR("loader not responding"); - return retval; - } - - /* receive response */ - if ((retval = embeddedice_receive(ocl->jtag_info, dcc_buffer+1, 1) != ERROR_OK)) - return retval; - - if (dcc_buffer[1] != OCL_CMD_DONE) - { - if (dcc_buffer[0] == OCL_ERASE_ALL) - LOG_ERROR("loader response to OCL_ERASE_ALL 0x%08lX", dcc_buffer[1]); - else - LOG_ERROR("loader response to OCL_ERASE_BLOCK 0x%08lX", dcc_buffer[1]); - return ERROR_FLASH_OPERATION_FAILED; - } - - return ERROR_OK; -} - - -int ocl_protect(struct flash_bank_s *bank, int set, int first, int last) -{ - return ERROR_OK; -} - - -int ocl_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count) -{ - ocl_priv_t *ocl = bank->driver_priv; - int retval; - u32 *dcc_buffer; - u32 *dcc_bufptr; - int byteofs; - int runlen; - u32 chksum; - - int i; - - /* check preconditions */ - if (ocl->buflen == 0 || ocl->bufalign==0) - return ERROR_FLASH_BANK_NOT_PROBED; - - if (bank->target->state != TARGET_RUNNING) - { - LOG_ERROR("target has to be running to communicate with the loader"); - return ERROR_TARGET_NOT_RUNNING; - } - - /* allocate buffer for max. ocl buffer + overhead */ - dcc_buffer = malloc(sizeof(u32)*(ocl->buflen/4+3)); - - while (count) - { - if (count + (offset % ocl->bufalign) > ocl->buflen) - runlen = ocl->buflen - (offset % ocl->bufalign); - else - runlen = count; - - dcc_buffer[0] = OCL_FLASH_BLOCK | runlen; - dcc_buffer[1] = offset; - dcc_bufptr = &dcc_buffer[2]; - - *dcc_bufptr = 0xffffffff; - byteofs = (offset % ocl->bufalign) % 4; - chksum = OCL_CHKS_INIT; - - /* copy data to DCC buffer in proper byte order and properly aligned */ - for (i=0; ijtag_info, dcc_buffer, dcc_bufptr-dcc_buffer)) != ERROR_OK) - { - free(dcc_buffer); - return retval; - } - - /* wait for response, fixed timeout of 1 s */ - if ((retval = embeddedice_handshake(ocl->jtag_info, EICE_COMM_CTRL_WBIT, 1000) != ERROR_OK)) - { - if (retval == ERROR_TARGET_TIMEOUT) - LOG_ERROR("loader not responding"); - free(dcc_buffer); - return retval; - } - - /* receive response */ - if ((retval = embeddedice_receive(ocl->jtag_info, dcc_buffer, 1) != ERROR_OK)) - { - free(dcc_buffer); - return retval; - } - - if (dcc_buffer[0] != OCL_CMD_DONE) - { - LOG_ERROR("loader response to OCL_FLASH_BLOCK 0x%08lX", dcc_buffer[0]); - free(dcc_buffer); - return ERROR_FLASH_OPERATION_FAILED; - } - - count -= runlen; - offset += runlen; - } - - free(dcc_buffer); - return ERROR_OK; -} - - -int ocl_probe(struct flash_bank_s *bank) -{ - ocl_priv_t *ocl = bank->driver_priv; - int retval; - u32 dcc_buffer[1]; - int sectsize; - int i; - - /* purge pending data in DCC */ - embeddedice_receive(ocl->jtag_info, dcc_buffer, 1); - - dcc_buffer[0] = OCL_PROBE; - if ((retval = embeddedice_send(ocl->jtag_info, dcc_buffer, 1) != ERROR_OK)) - return retval; - - /* wait for response, fixed timeout of 1 s */ - if ((retval = embeddedice_handshake(ocl->jtag_info, EICE_COMM_CTRL_WBIT, 1000) != ERROR_OK)) - { - if (retval == ERROR_TARGET_TIMEOUT) - LOG_ERROR("loader not responding"); - return retval; - } - - /* receive response */ - if ((retval = embeddedice_receive(ocl->jtag_info, dcc_buffer, 1) != ERROR_OK)) - return retval; - - if (dcc_buffer[0] != OCL_CMD_DONE) - { - LOG_ERROR("loader response to OCL_PROBE 0x%08lX", dcc_buffer[0]); - return ERROR_FLASH_OPERATION_FAILED; - } - - /* receive and fill in parameters, detection of loader is important, receive it one by one */ - if ((retval = embeddedice_handshake(ocl->jtag_info, EICE_COMM_CTRL_WBIT, 0) != ERROR_OK) - || (retval = embeddedice_receive(ocl->jtag_info, dcc_buffer, 1) != ERROR_OK)) - return retval; - bank->base = dcc_buffer[0]; - - if ((retval = embeddedice_handshake(ocl->jtag_info, EICE_COMM_CTRL_WBIT, 0) != ERROR_OK) - || (retval = embeddedice_receive(ocl->jtag_info, dcc_buffer, 1) != ERROR_OK)) - return retval; - bank->size = dcc_buffer[0]; - - if ((retval = embeddedice_handshake(ocl->jtag_info, EICE_COMM_CTRL_WBIT, 0) != ERROR_OK) - || (retval = embeddedice_receive(ocl->jtag_info, dcc_buffer, 1) != ERROR_OK)) - return retval; - bank->num_sectors = dcc_buffer[0]; - - if ((retval = embeddedice_handshake(ocl->jtag_info, EICE_COMM_CTRL_WBIT, 0) != ERROR_OK) - || (retval = embeddedice_receive(ocl->jtag_info, dcc_buffer, 1) != ERROR_OK)) - return retval; - ocl->buflen = dcc_buffer[0] & 0xffff; - ocl->bufalign = dcc_buffer[0] >> 16; - - bank->sectors = realloc(bank->sectors, sizeof(flash_sector_t)*bank->num_sectors); - if (bank->num_sectors == 0) - { - LOG_ERROR("number of sectors shall be non zero value"); - return ERROR_FLASH_BANK_INVALID; - } - if (bank->size % bank->num_sectors) { - LOG_ERROR("bank size not divisible by number of sectors"); - return ERROR_FLASH_BANK_INVALID; - } - sectsize = bank->size / bank->num_sectors; - for (i=0; inum_sectors; i++) - { - bank->sectors[i].offset = i * sectsize; - bank->sectors[i].size = sectsize; - bank->sectors[i].is_erased = -1; - bank->sectors[i].is_protected = -1; - } - - if (ocl->bufalign == 0) - ocl->bufalign = 1; - - if (ocl->buflen == 0) - { - LOG_ERROR("buflen shall be non zero value"); - return ERROR_FLASH_BANK_INVALID; - } - - if ((ocl->bufalign > ocl->buflen) || (ocl->buflen % ocl->bufalign)) - { - LOG_ERROR("buflen is not multiple of bufalign"); - return ERROR_FLASH_BANK_INVALID; - } - - if (ocl->buflen % 4) - { - LOG_ERROR("buflen shall be divisible by 4"); - return ERROR_FLASH_BANK_INVALID; - } - - return ERROR_OK; -} - - -int ocl_info(struct flash_bank_s *bank, char *buf, int buf_size) -{ - return ERROR_OK; -} - - -int ocl_auto_probe(struct flash_bank_s *bank) -{ - ocl_priv_t *ocl = bank->driver_priv; - - if (ocl->buflen == 0 || ocl->bufalign==0) - return ERROR_FLASH_BANK_NOT_PROBED; - - return ERROR_OK; -} +/*************************************************************************** + * Copyright (C) 2007 by Pavel Chromy * + * chromy@asix.cz * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, write to the * + * Free Software Foundation, Inc., * + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * + ***************************************************************************/ +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include "replacements.h" + +#include "ocl.h" + +#include "flash.h" +#include "target.h" +#include "log.h" +#include "binarybuffer.h" +#include "types.h" +#include "embeddedice.h" +#include "arm7_9_common.h" + +#include +#include +#include + +int ocl_register_commands(struct command_context_s *cmd_ctx); +int ocl_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank); +int ocl_erase(struct flash_bank_s *bank, int first, int last); +int ocl_protect(struct flash_bank_s *bank, int set, int first, int last); +int ocl_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count); +int ocl_probe(struct flash_bank_s *bank); +int ocl_erase_check(struct flash_bank_s *bank); +int ocl_protect_check(struct flash_bank_s *bank); +int ocl_info(struct flash_bank_s *bank, char *buf, int buf_size); +int ocl_auto_probe(struct flash_bank_s *bank); + +flash_driver_t ocl_flash = +{ + .name = "ocl", + .register_commands = ocl_register_commands, + .flash_bank_command = ocl_flash_bank_command, + .erase = ocl_erase, + .protect = ocl_protect, + .write = ocl_write, + .probe = ocl_probe, + .erase_check = ocl_erase_check, + .protect_check = ocl_protect_check, + .info = ocl_info, + .auto_probe = ocl_auto_probe +}; + + +typedef struct ocl_priv_s +{ + arm_jtag_t *jtag_info; + int buflen; + int bufalign; +} ocl_priv_t; + + +int ocl_register_commands(struct command_context_s *cmd_ctx) +{ + return ERROR_OK; +} + + +int ocl_erase_check(struct flash_bank_s *bank) +{ + return ERROR_OK; +} + + +int ocl_protect_check(struct flash_bank_s *bank) +{ + return ERROR_OK; +} + + +/* flash_bank ocl 0 0 0 0 */ +int ocl_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank) +{ + int retval; + armv4_5_common_t *armv4_5; + arm7_9_common_t *arm7_9; + ocl_priv_t *ocl; + + if (argc < 6) + { + LOG_WARNING("incomplete flash_bank ocl configuration"); + return ERROR_FLASH_BANK_INVALID; + } + + if ((retval = arm7_9_get_arch_pointers(bank->target, &armv4_5, &arm7_9)) != ERROR_OK) + return retval; + + ocl = bank->driver_priv = malloc(sizeof(ocl_priv_t)); + ocl->jtag_info = &arm7_9->jtag_info; + ocl->buflen = 0; + ocl->bufalign = 1; + + return ERROR_OK; +} + + +int ocl_erase(struct flash_bank_s *bank, int first, int last) +{ + ocl_priv_t *ocl = bank->driver_priv; + int retval; + u32 dcc_buffer[3]; + + /* check preconditions */ + if (bank->num_sectors == 0) + return ERROR_FLASH_BANK_NOT_PROBED; + + if (bank->target->state != TARGET_RUNNING) + { + LOG_ERROR("target has to be running to communicate with the loader"); + return ERROR_TARGET_NOT_RUNNING; + } + + if ((first == 0) && (last == bank->num_sectors - 1)) + { + dcc_buffer[0] = OCL_ERASE_ALL; + if ((retval = embeddedice_send(ocl->jtag_info, dcc_buffer, 1) != ERROR_OK)) + return retval; + } + else + { + dcc_buffer[0] = OCL_ERASE_BLOCK; + dcc_buffer[1] = first; + dcc_buffer[2] = last; + if ((retval = embeddedice_send(ocl->jtag_info, dcc_buffer, 3) != ERROR_OK)) + return retval; + } + + /* wait for response, fixed timeout of 1 s */ + if ((retval = embeddedice_handshake(ocl->jtag_info, EICE_COMM_CTRL_WBIT, 1000) != ERROR_OK)) + { + if (retval == ERROR_TARGET_TIMEOUT) + LOG_ERROR("loader not responding"); + return retval; + } + + /* receive response */ + if ((retval = embeddedice_receive(ocl->jtag_info, dcc_buffer+1, 1) != ERROR_OK)) + return retval; + + if (dcc_buffer[1] != OCL_CMD_DONE) + { + if (dcc_buffer[0] == OCL_ERASE_ALL) + LOG_ERROR("loader response to OCL_ERASE_ALL 0x%08lX", dcc_buffer[1]); + else + LOG_ERROR("loader response to OCL_ERASE_BLOCK 0x%08lX", dcc_buffer[1]); + return ERROR_FLASH_OPERATION_FAILED; + } + + return ERROR_OK; +} + + +int ocl_protect(struct flash_bank_s *bank, int set, int first, int last) +{ + return ERROR_OK; +} + + +int ocl_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count) +{ + ocl_priv_t *ocl = bank->driver_priv; + int retval; + u32 *dcc_buffer; + u32 *dcc_bufptr; + int byteofs; + int runlen; + u32 chksum; + + int i; + + /* check preconditions */ + if (ocl->buflen == 0 || ocl->bufalign==0) + return ERROR_FLASH_BANK_NOT_PROBED; + + if (bank->target->state != TARGET_RUNNING) + { + LOG_ERROR("target has to be running to communicate with the loader"); + return ERROR_TARGET_NOT_RUNNING; + } + + /* allocate buffer for max. ocl buffer + overhead */ + dcc_buffer = malloc(sizeof(u32)*(ocl->buflen/4+3)); + + while (count) + { + if (count + (offset % ocl->bufalign) > ocl->buflen) + runlen = ocl->buflen - (offset % ocl->bufalign); + else + runlen = count; + + dcc_buffer[0] = OCL_FLASH_BLOCK | runlen; + dcc_buffer[1] = offset; + dcc_bufptr = &dcc_buffer[2]; + + *dcc_bufptr = 0xffffffff; + byteofs = (offset % ocl->bufalign) % 4; + chksum = OCL_CHKS_INIT; + + /* copy data to DCC buffer in proper byte order and properly aligned */ + for (i=0; ijtag_info, dcc_buffer, dcc_bufptr-dcc_buffer)) != ERROR_OK) + { + free(dcc_buffer); + return retval; + } + + /* wait for response, fixed timeout of 1 s */ + if ((retval = embeddedice_handshake(ocl->jtag_info, EICE_COMM_CTRL_WBIT, 1000) != ERROR_OK)) + { + if (retval == ERROR_TARGET_TIMEOUT) + LOG_ERROR("loader not responding"); + free(dcc_buffer); + return retval; + } + + /* receive response */ + if ((retval = embeddedice_receive(ocl->jtag_info, dcc_buffer, 1) != ERROR_OK)) + { + free(dcc_buffer); + return retval; + } + + if (dcc_buffer[0] != OCL_CMD_DONE) + { + LOG_ERROR("loader response to OCL_FLASH_BLOCK 0x%08lX", dcc_buffer[0]); + free(dcc_buffer); + return ERROR_FLASH_OPERATION_FAILED; + } + + count -= runlen; + offset += runlen; + } + + free(dcc_buffer); + return ERROR_OK; +} + + +int ocl_probe(struct flash_bank_s *bank) +{ + ocl_priv_t *ocl = bank->driver_priv; + int retval; + u32 dcc_buffer[1]; + int sectsize; + int i; + + /* purge pending data in DCC */ + embeddedice_receive(ocl->jtag_info, dcc_buffer, 1); + + dcc_buffer[0] = OCL_PROBE; + if ((retval = embeddedice_send(ocl->jtag_info, dcc_buffer, 1) != ERROR_OK)) + return retval; + + /* wait for response, fixed timeout of 1 s */ + if ((retval = embeddedice_handshake(ocl->jtag_info, EICE_COMM_CTRL_WBIT, 1000) != ERROR_OK)) + { + if (retval == ERROR_TARGET_TIMEOUT) + LOG_ERROR("loader not responding"); + return retval; + } + + /* receive response */ + if ((retval = embeddedice_receive(ocl->jtag_info, dcc_buffer, 1) != ERROR_OK)) + return retval; + + if (dcc_buffer[0] != OCL_CMD_DONE) + { + LOG_ERROR("loader response to OCL_PROBE 0x%08lX", dcc_buffer[0]); + return ERROR_FLASH_OPERATION_FAILED; + } + + /* receive and fill in parameters, detection of loader is important, receive it one by one */ + if ((retval = embeddedice_handshake(ocl->jtag_info, EICE_COMM_CTRL_WBIT, 0) != ERROR_OK) + || (retval = embeddedice_receive(ocl->jtag_info, dcc_buffer, 1) != ERROR_OK)) + return retval; + bank->base = dcc_buffer[0]; + + if ((retval = embeddedice_handshake(ocl->jtag_info, EICE_COMM_CTRL_WBIT, 0) != ERROR_OK) + || (retval = embeddedice_receive(ocl->jtag_info, dcc_buffer, 1) != ERROR_OK)) + return retval; + bank->size = dcc_buffer[0]; + + if ((retval = embeddedice_handshake(ocl->jtag_info, EICE_COMM_CTRL_WBIT, 0) != ERROR_OK) + || (retval = embeddedice_receive(ocl->jtag_info, dcc_buffer, 1) != ERROR_OK)) + return retval; + bank->num_sectors = dcc_buffer[0]; + + if ((retval = embeddedice_handshake(ocl->jtag_info, EICE_COMM_CTRL_WBIT, 0) != ERROR_OK) + || (retval = embeddedice_receive(ocl->jtag_info, dcc_buffer, 1) != ERROR_OK)) + return retval; + ocl->buflen = dcc_buffer[0] & 0xffff; + ocl->bufalign = dcc_buffer[0] >> 16; + + bank->sectors = realloc(bank->sectors, sizeof(flash_sector_t)*bank->num_sectors); + if (bank->num_sectors == 0) + { + LOG_ERROR("number of sectors shall be non zero value"); + return ERROR_FLASH_BANK_INVALID; + } + if (bank->size % bank->num_sectors) { + LOG_ERROR("bank size not divisible by number of sectors"); + return ERROR_FLASH_BANK_INVALID; + } + sectsize = bank->size / bank->num_sectors; + for (i=0; inum_sectors; i++) + { + bank->sectors[i].offset = i * sectsize; + bank->sectors[i].size = sectsize; + bank->sectors[i].is_erased = -1; + bank->sectors[i].is_protected = -1; + } + + if (ocl->bufalign == 0) + ocl->bufalign = 1; + + if (ocl->buflen == 0) + { + LOG_ERROR("buflen shall be non zero value"); + return ERROR_FLASH_BANK_INVALID; + } + + if ((ocl->bufalign > ocl->buflen) || (ocl->buflen % ocl->bufalign)) + { + LOG_ERROR("buflen is not multiple of bufalign"); + return ERROR_FLASH_BANK_INVALID; + } + + if (ocl->buflen % 4) + { + LOG_ERROR("buflen shall be divisible by 4"); + return ERROR_FLASH_BANK_INVALID; + } + + return ERROR_OK; +} + + +int ocl_info(struct flash_bank_s *bank, char *buf, int buf_size) +{ + return ERROR_OK; +} + + +int ocl_auto_probe(struct flash_bank_s *bank) +{ + ocl_priv_t *ocl = bank->driver_priv; + + if (ocl->buflen == 0 || ocl->bufalign==0) + return ERROR_FLASH_BANK_NOT_PROBED; + + return ERROR_OK; +} diff --git a/src/flash/ocl.h b/src/flash/ocl.h index 8c677b0e..d5c430be 100644 --- a/src/flash/ocl.h +++ b/src/flash/ocl.h @@ -1,40 +1,40 @@ -/*************************************************************************** - * Copyright (C) 2007 by Pavel Chromy * - * chromy@asix.cz * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * - ***************************************************************************/ -#ifndef OCL_H -#define OCL_H - -/* command/response mask */ -#define OCL_CMD_MASK 0xFFFF0000L - -/* commads */ -#define OCL_FLASH_BLOCK 0x0CFB0000L -#define OCL_ERASE_BLOCK 0x0CEB0000L -#define OCL_ERASE_ALL 0x0CEA0000L -#define OCL_PROBE 0x0CBE0000L - -/* responses */ -#define OCL_CMD_DONE 0x0ACD0000L -#define OCL_CMD_ERR 0x0ACE0000L -#define OCL_CHKS_FAIL 0x0ACF0000L -#define OCL_BUFF_OVER 0x0AB00000L - -#define OCL_CHKS_INIT 0xC100CD0CL - -#endif /* OCL_H */ +/*************************************************************************** + * Copyright (C) 2007 by Pavel Chromy * + * chromy@asix.cz * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, write to the * + * Free Software Foundation, Inc., * + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * + ***************************************************************************/ +#ifndef OCL_H +#define OCL_H + +/* command/response mask */ +#define OCL_CMD_MASK 0xFFFF0000L + +/* commads */ +#define OCL_FLASH_BLOCK 0x0CFB0000L +#define OCL_ERASE_BLOCK 0x0CEB0000L +#define OCL_ERASE_ALL 0x0CEA0000L +#define OCL_PROBE 0x0CBE0000L + +/* responses */ +#define OCL_CMD_DONE 0x0ACD0000L +#define OCL_CMD_ERR 0x0ACE0000L +#define OCL_CHKS_FAIL 0x0ACF0000L +#define OCL_BUFF_OVER 0x0AB00000L + +#define OCL_CHKS_INIT 0xC100CD0CL + +#endif /* OCL_H */ diff --git a/src/flash/ocl/at91sam7x/at91sam7x_ocl_flash.script b/src/flash/ocl/at91sam7x/at91sam7x_ocl_flash.script index dbc40a0c..85450c14 100644 --- a/src/flash/ocl/at91sam7x/at91sam7x_ocl_flash.script +++ b/src/flash/ocl/at91sam7x/at91sam7x_ocl_flash.script @@ -1,4 +1,4 @@ -soft_reset_halt -load_image at91sam7x_ocl.bin 0x200000 -resume 0x200000 -flash probe 0 +soft_reset_halt +load_image at91sam7x_ocl.bin 0x200000 +resume 0x200000 +flash probe 0 diff --git a/src/flash/ocl/at91sam7x/at91sam7x_ram.ld b/src/flash/ocl/at91sam7x/at91sam7x_ram.ld index 106d2180..24c5c2b5 100644 --- a/src/flash/ocl/at91sam7x/at91sam7x_ram.ld +++ b/src/flash/ocl/at91sam7x/at91sam7x_ram.ld @@ -1,132 +1,132 @@ -/**************************************************************************** -* Copyright (c) 2006 by Michael Fischer. All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* 1. Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* 2. Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* 3. Neither the name of the author nor the names of its contributors may -* be used to endorse or promote products derived from this software -* without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL -* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -* SUCH DAMAGE. -* -**************************************************************************** -* -* History: -* -* 30.03.06 mifi First Version -****************************************************************************/ - - -ENTRY(ResetHandler) -SEARCH_DIR(.) - -/* - * Define stack size here - */ -FIQ_STACK_SIZE = 0x0100; -IRQ_STACK_SIZE = 0x0100; -ABT_STACK_SIZE = 0x0100; -UND_STACK_SIZE = 0x0100; -SVC_STACK_SIZE = 0x0100; - - -MEMORY -{ - ram : org = 0x00200000, len = 64k -} - -/* - * Do not change the next code - */ -SECTIONS -{ - .text : - { - *(.vectors); - . = ALIGN(4); - *(.init); - . = ALIGN(4); - *(.text); - . = ALIGN(4); - *(.rodata); - . = ALIGN(4); - *(.rodata*); - . = ALIGN(4); - *(.glue_7t); - . = ALIGN(4); - *(.glue_7); - . = ALIGN(4); - etext = .; - } > ram - - .data : - { - PROVIDE (__data_start = .); - *(.data) - . = ALIGN(4); - edata = .; - _edata = .; - PROVIDE (__data_end = .); - } > ram - - .bss : - { - PROVIDE (__bss_start = .); - *(.bss) - *(COMMON) - . = ALIGN(4); - PROVIDE (__bss_end = .); - - . = ALIGN(256); - - PROVIDE (__stack_start = .); - - PROVIDE (__stack_fiq_start = .); - . += FIQ_STACK_SIZE; - . = ALIGN(4); - PROVIDE (__stack_fiq_end = .); - - PROVIDE (__stack_irq_start = .); - . += IRQ_STACK_SIZE; - . = ALIGN(4); - PROVIDE (__stack_irq_end = .); - - PROVIDE (__stack_abt_start = .); - . += ABT_STACK_SIZE; - . = ALIGN(4); - PROVIDE (__stack_abt_end = .); - - PROVIDE (__stack_und_start = .); - . += UND_STACK_SIZE; - . = ALIGN(4); - PROVIDE (__stack_und_end = .); - - PROVIDE (__stack_svc_start = .); - . += SVC_STACK_SIZE; - . = ALIGN(4); - PROVIDE (__stack_svc_end = .); - PROVIDE (__stack_end = .); - PROVIDE (__heap_start = .); - } > ram - -} -/*** EOF ***/ - +/**************************************************************************** +* Copyright (c) 2006 by Michael Fischer. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* 1. Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* 3. Neither the name of the author nor the names of its contributors may +* be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL +* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +* SUCH DAMAGE. +* +**************************************************************************** +* +* History: +* +* 30.03.06 mifi First Version +****************************************************************************/ + + +ENTRY(ResetHandler) +SEARCH_DIR(.) + +/* + * Define stack size here + */ +FIQ_STACK_SIZE = 0x0100; +IRQ_STACK_SIZE = 0x0100; +ABT_STACK_SIZE = 0x0100; +UND_STACK_SIZE = 0x0100; +SVC_STACK_SIZE = 0x0100; + + +MEMORY +{ + ram : org = 0x00200000, len = 64k +} + +/* + * Do not change the next code + */ +SECTIONS +{ + .text : + { + *(.vectors); + . = ALIGN(4); + *(.init); + . = ALIGN(4); + *(.text); + . = ALIGN(4); + *(.rodata); + . = ALIGN(4); + *(.rodata*); + . = ALIGN(4); + *(.glue_7t); + . = ALIGN(4); + *(.glue_7); + . = ALIGN(4); + etext = .; + } > ram + + .data : + { + PROVIDE (__data_start = .); + *(.data) + . = ALIGN(4); + edata = .; + _edata = .; + PROVIDE (__data_end = .); + } > ram + + .bss : + { + PROVIDE (__bss_start = .); + *(.bss) + *(COMMON) + . = ALIGN(4); + PROVIDE (__bss_end = .); + + . = ALIGN(256); + + PROVIDE (__stack_start = .); + + PROVIDE (__stack_fiq_start = .); + . += FIQ_STACK_SIZE; + . = ALIGN(4); + PROVIDE (__stack_fiq_end = .); + + PROVIDE (__stack_irq_start = .); + . += IRQ_STACK_SIZE; + . = ALIGN(4); + PROVIDE (__stack_irq_end = .); + + PROVIDE (__stack_abt_start = .); + . += ABT_STACK_SIZE; + . = ALIGN(4); + PROVIDE (__stack_abt_end = .); + + PROVIDE (__stack_und_start = .); + . += UND_STACK_SIZE; + . = ALIGN(4); + PROVIDE (__stack_und_end = .); + + PROVIDE (__stack_svc_start = .); + . += SVC_STACK_SIZE; + . = ALIGN(4); + PROVIDE (__stack_svc_end = .); + PROVIDE (__stack_end = .); + PROVIDE (__heap_start = .); + } > ram + +} +/*** EOF ***/ + diff --git a/src/flash/ocl/at91sam7x/crt.s b/src/flash/ocl/at91sam7x/crt.s index 9ea8a7fc..b0bae0d6 100644 --- a/src/flash/ocl/at91sam7x/crt.s +++ b/src/flash/ocl/at91sam7x/crt.s @@ -1,225 +1,223 @@ -/**************************************************************************** -* Copyright (c) 2006 by Michael Fischer. All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* 1. Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* 2. Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* 3. Neither the name of the author nor the names of its contributors may -* be used to endorse or promote products derived from this software -* without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL -* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -* SUCH DAMAGE. -* -**************************************************************************** -* -* History: -* -* 18.12.06 mifi First Version -* The hardware initialization is based on the startup file -* crtat91sam7x256_rom.S from NutOS 4.2.1. -* Therefore partial copyright by egnite Software GmbH. -****************************************************************************/ - -/* - * Some defines for the program status registers - */ - ARM_MODE_USER = 0x10 /* Normal User Mode */ - ARM_MODE_FIQ = 0x11 /* FIQ Fast Interrupts Mode */ - ARM_MODE_IRQ = 0x12 /* IRQ Standard Interrupts Mode */ - ARM_MODE_SVC = 0x13 /* Supervisor Interrupts Mode */ - ARM_MODE_ABORT = 0x17 /* Abort Processing memory Faults Mode */ - ARM_MODE_UNDEF = 0x1B /* Undefined Instructions Mode */ - ARM_MODE_SYS = 0x1F /* System Running in Priviledged Operating Mode */ - ARM_MODE_MASK = 0x1F - - I_BIT = 0x80 /* disable IRQ when I bit is set */ - F_BIT = 0x40 /* disable IRQ when I bit is set */ - -/* - * Register Base Address - */ - AIC_BASE = 0xFFFFF000 - AIC_EOICR_OFF = 0x130 - AIC_IDCR_OFF = 0x124 - - RSTC_MR = 0xFFFFFD08 - RSTC_KEY = 0xA5000000 - RSTC_URSTEN = 0x00000001 - - WDT_BASE = 0xFFFFFD40 - WDT_MR_OFF = 0x00000004 - WDT_WDDIS = 0x00008000 - - MC_BASE = 0xFFFFFF00 - MC_FMR_OFF = 0x00000060 - MC_FWS_1FWS = 0x00480100 - - .section .vectors,"ax" - .code 32 - -/****************************************************************************/ -/* Vector table and reset entry */ -/****************************************************************************/ -_vectors: - ldr pc, ResetAddr /* Reset */ - ldr pc, UndefAddr /* Undefined instruction */ - ldr pc, SWIAddr /* Software interrupt */ - ldr pc, PAbortAddr /* Prefetch abort */ - ldr pc, DAbortAddr /* Data abort */ - ldr pc, ReservedAddr /* Reserved */ - ldr pc, IRQAddr /* IRQ interrupt */ - ldr pc, FIQAddr /* FIQ interrupt */ - - -ResetAddr: .word ResetHandler -UndefAddr: .word UndefHandler -SWIAddr: .word SWIHandler -PAbortAddr: .word PAbortHandler -DAbortAddr: .word DAbortHandler -ReservedAddr: .word 0 -IRQAddr: .word IRQHandler -FIQAddr: .word FIQHandler - - .ltorg - - .section .init, "ax" - .code 32 - - .global ResetHandler - .global ExitFunction - .extern main -/****************************************************************************/ -/* Reset handler */ -/****************************************************************************/ -ResetHandler: - /* - * The watchdog is enabled after processor reset. Disable it. - */ - ldr r1, =WDT_BASE - ldr r0, =WDT_WDDIS - str r0, [r1, #WDT_MR_OFF] - - - /* - * Enable user reset: assertion length programmed to 1ms - */ - ldr r0, =(RSTC_KEY | RSTC_URSTEN | (4 << 8)) - ldr r1, =RSTC_MR - str r0, [r1, #0] - - - /* - * Use 2 cycles for flash access. - */ - ldr r1, =MC_BASE - ldr r0, =MC_FWS_1FWS - str r0, [r1, #MC_FMR_OFF] - - - /* - * Disable all interrupts. Useful for debugging w/o target reset. - */ - ldr r1, =AIC_BASE - mvn r0, #0 - str r0, [r1, #AIC_EOICR_OFF] - str r0, [r1, #AIC_IDCR_OFF] - - - /* - * Setup a stack for each mode - */ - msr CPSR_c, #ARM_MODE_UNDEF | I_BIT | F_BIT /* Undefined Instruction Mode */ - ldr sp, =__stack_und_end - - msr CPSR_c, #ARM_MODE_ABORT | I_BIT | F_BIT /* Abort Mode */ - ldr sp, =__stack_abt_end - - msr CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT /* FIQ Mode */ - ldr sp, =__stack_fiq_end - - msr CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT /* IRQ Mode */ - ldr sp, =__stack_irq_end - - msr CPSR_c, #ARM_MODE_SVC | I_BIT | F_BIT /* Supervisor Mode */ - ldr sp, =__stack_svc_end - - - /* - * Clear .bss section - */ - ldr r1, =__bss_start - ldr r2, =__bss_end - ldr r3, =0 -bss_clear_loop: - cmp r1, r2 - strne r3, [r1], #+4 - bne bss_clear_loop - - - /* - * Jump to main - */ - mrs r0, cpsr - bic r0, r0, #I_BIT | F_BIT /* Enable FIQ and IRQ interrupt */ - msr cpsr, r0 - - mov r0, #0 /* No arguments */ - mov r1, #0 /* No arguments */ - ldr r2, =main - mov lr, pc - bx r2 /* And jump... */ - -ExitFunction: - nop - nop - nop - b ExitFunction - - -/****************************************************************************/ -/* Default interrupt handler */ -/****************************************************************************/ - -UndefHandler: - b UndefHandler - -SWIHandler: - b SWIHandler - -PAbortHandler: - b PAbortHandler - -DAbortHandler: - b DAbortHandler - -IRQHandler: - b IRQHandler - -FIQHandler: - b FIQHandler - - .weak ExitFunction - .weak UndefHandler, PAbortHandler, DAbortHandler - .weak IRQHandler, FIQHandler - - .ltorg -/*** EOF ***/ - - Index: src/flash/ocl/at91sam7x/dcc.c +/**************************************************************************** +* Copyright (c) 2006 by Michael Fischer. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* 1. Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* 3. Neither the name of the author nor the names of its contributors may +* be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL +* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +* SUCH DAMAGE. +* +**************************************************************************** +* +* History: +* +* 18.12.06 mifi First Version +* The hardware initialization is based on the startup file +* crtat91sam7x256_rom.S from NutOS 4.2.1. +* Therefore partial copyright by egnite Software GmbH. +****************************************************************************/ + +/* + * Some defines for the program status registers + */ + ARM_MODE_USER = 0x10 /* Normal User Mode */ + ARM_MODE_FIQ = 0x11 /* FIQ Fast Interrupts Mode */ + ARM_MODE_IRQ = 0x12 /* IRQ Standard Interrupts Mode */ + ARM_MODE_SVC = 0x13 /* Supervisor Interrupts Mode */ + ARM_MODE_ABORT = 0x17 /* Abort Processing memory Faults Mode */ + ARM_MODE_UNDEF = 0x1B /* Undefined Instructions Mode */ + ARM_MODE_SYS = 0x1F /* System Running in Priviledged Operating Mode */ + ARM_MODE_MASK = 0x1F + + I_BIT = 0x80 /* disable IRQ when I bit is set */ + F_BIT = 0x40 /* disable IRQ when I bit is set */ + +/* + * Register Base Address + */ + AIC_BASE = 0xFFFFF000 + AIC_EOICR_OFF = 0x130 + AIC_IDCR_OFF = 0x124 + + RSTC_MR = 0xFFFFFD08 + RSTC_KEY = 0xA5000000 + RSTC_URSTEN = 0x00000001 + + WDT_BASE = 0xFFFFFD40 + WDT_MR_OFF = 0x00000004 + WDT_WDDIS = 0x00008000 + + MC_BASE = 0xFFFFFF00 + MC_FMR_OFF = 0x00000060 + MC_FWS_1FWS = 0x00480100 + + .section .vectors,"ax" + .code 32 + +/****************************************************************************/ +/* Vector table and reset entry */ +/****************************************************************************/ +_vectors: + ldr pc, ResetAddr /* Reset */ + ldr pc, UndefAddr /* Undefined instruction */ + ldr pc, SWIAddr /* Software interrupt */ + ldr pc, PAbortAddr /* Prefetch abort */ + ldr pc, DAbortAddr /* Data abort */ + ldr pc, ReservedAddr /* Reserved */ + ldr pc, IRQAddr /* IRQ interrupt */ + ldr pc, FIQAddr /* FIQ interrupt */ + + +ResetAddr: .word ResetHandler +UndefAddr: .word UndefHandler +SWIAddr: .word SWIHandler +PAbortAddr: .word PAbortHandler +DAbortAddr: .word DAbortHandler +ReservedAddr: .word 0 +IRQAddr: .word IRQHandler +FIQAddr: .word FIQHandler + + .ltorg + + .section .init, "ax" + .code 32 + + .global ResetHandler + .global ExitFunction + .extern main +/****************************************************************************/ +/* Reset handler */ +/****************************************************************************/ +ResetHandler: + /* + * The watchdog is enabled after processor reset. Disable it. + */ + ldr r1, =WDT_BASE + ldr r0, =WDT_WDDIS + str r0, [r1, #WDT_MR_OFF] + + + /* + * Enable user reset: assertion length programmed to 1ms + */ + ldr r0, =(RSTC_KEY | RSTC_URSTEN | (4 << 8)) + ldr r1, =RSTC_MR + str r0, [r1, #0] + + + /* + * Use 2 cycles for flash access. + */ + ldr r1, =MC_BASE + ldr r0, =MC_FWS_1FWS + str r0, [r1, #MC_FMR_OFF] + + + /* + * Disable all interrupts. Useful for debugging w/o target reset. + */ + ldr r1, =AIC_BASE + mvn r0, #0 + str r0, [r1, #AIC_EOICR_OFF] + str r0, [r1, #AIC_IDCR_OFF] + + + /* + * Setup a stack for each mode + */ + msr CPSR_c, #ARM_MODE_UNDEF | I_BIT | F_BIT /* Undefined Instruction Mode */ + ldr sp, =__stack_und_end + + msr CPSR_c, #ARM_MODE_ABORT | I_BIT | F_BIT /* Abort Mode */ + ldr sp, =__stack_abt_end + + msr CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT /* FIQ Mode */ + ldr sp, =__stack_fiq_end + + msr CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT /* IRQ Mode */ + ldr sp, =__stack_irq_end + + msr CPSR_c, #ARM_MODE_SVC | I_BIT | F_BIT /* Supervisor Mode */ + ldr sp, =__stack_svc_end + + + /* + * Clear .bss section + */ + ldr r1, =__bss_start + ldr r2, =__bss_end + ldr r3, =0 +bss_clear_loop: + cmp r1, r2 + strne r3, [r1], #+4 + bne bss_clear_loop + + + /* + * Jump to main + */ + mrs r0, cpsr + bic r0, r0, #I_BIT | F_BIT /* Enable FIQ and IRQ interrupt */ + msr cpsr, r0 + + mov r0, #0 /* No arguments */ + mov r1, #0 /* No arguments */ + ldr r2, =main + mov lr, pc + bx r2 /* And jump... */ + +ExitFunction: + nop + nop + nop + b ExitFunction + + +/****************************************************************************/ +/* Default interrupt handler */ +/****************************************************************************/ + +UndefHandler: + b UndefHandler + +SWIHandler: + b SWIHandler + +PAbortHandler: + b PAbortHandler + +DAbortHandler: + b DAbortHandler + +IRQHandler: + b IRQHandler + +FIQHandler: + b FIQHandler + + .weak ExitFunction + .weak UndefHandler, PAbortHandler, DAbortHandler + .weak IRQHandler, FIQHandler + + .ltorg +/*** EOF ***/ diff --git a/src/flash/ocl/at91sam7x/dcc.c b/src/flash/ocl/at91sam7x/dcc.c index 2c352369..3507bbe5 100644 --- a/src/flash/ocl/at91sam7x/dcc.c +++ b/src/flash/ocl/at91sam7x/dcc.c @@ -1,51 +1,51 @@ -/*************************************************************************** - * Copyright (C) 2007 by Pavel Chromy * - * chromy@asix.cz * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * - ***************************************************************************/ -#include "dcc.h" - - -/* debug channel read (debugger->MCU) */ -uint32 dcc_rd(void) -{ - volatile uint32 dcc_reg; - - do { - asm volatile ("mrc p14, 0, %0, C0, C0" : "=r" (dcc_reg) : ); - } while ((dcc_reg&1)==0); - - asm volatile ("mrc p14, 0, %0, C1, C0" : "=r" (dcc_reg) : ); - return dcc_reg; -} - - -/* debug channel write (MCU->debugger) */ -int dcc_wr(uint32 data) -{ - volatile uint32 dcc_reg; - - do { - asm volatile ("mrc p14, 0, %0, C0, C0" : "=r" (dcc_reg) : ); - /* operation controled by master, cancel operation - upon reception of data for immediate response */ - if (dcc_reg&1) return -1; - } while (dcc_reg&2); - - asm volatile ("mcr p14, 0, %0, C1, C0" : : "r" (data)); - return 0; -} +/*************************************************************************** + * Copyright (C) 2007 by Pavel Chromy * + * chromy@asix.cz * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, write to the * + * Free Software Foundation, Inc., * + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * + ***************************************************************************/ +#include "dcc.h" + + +/* debug channel read (debugger->MCU) */ +uint32 dcc_rd(void) +{ + volatile uint32 dcc_reg; + + do { + asm volatile ("mrc p14, 0, %0, C0, C0" : "=r" (dcc_reg) : ); + } while ((dcc_reg&1)==0); + + asm volatile ("mrc p14, 0, %0, C1, C0" : "=r" (dcc_reg) : ); + return dcc_reg; +} + + +/* debug channel write (MCU->debugger) */ +int dcc_wr(uint32 data) +{ + volatile uint32 dcc_reg; + + do { + asm volatile ("mrc p14, 0, %0, C0, C0" : "=r" (dcc_reg) : ); + /* operation controled by master, cancel operation + upon reception of data for immediate response */ + if (dcc_reg&1) return -1; + } while (dcc_reg&2); + + asm volatile ("mcr p14, 0, %0, C1, C0" : : "r" (data)); + return 0; +} diff --git a/src/flash/ocl/at91sam7x/dcc.h b/src/flash/ocl/at91sam7x/dcc.h index 963df261..f41b1d27 100644 --- a/src/flash/ocl/at91sam7x/dcc.h +++ b/src/flash/ocl/at91sam7x/dcc.h @@ -1,31 +1,31 @@ -/*************************************************************************** - * Copyright (C) 2007 by Pavel Chromy * - * chromy@asix.cz * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * - ***************************************************************************/ -#ifndef dccH -#define dccH - -#include "platform.h" - -/* debug channel read (debugger->MCU) */ -extern uint32 dcc_rd(void); - -/* debug channel write (MCU->debugger) */ -extern int dcc_wr(uint32 data); - -#endif +/*************************************************************************** + * Copyright (C) 2007 by Pavel Chromy * + * chromy@asix.cz * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, write to the * + * Free Software Foundation, Inc., * + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * + ***************************************************************************/ +#ifndef dccH +#define dccH + +#include "platform.h" + +/* debug channel read (debugger->MCU) */ +extern uint32 dcc_rd(void); + +/* debug channel write (MCU->debugger) */ +extern int dcc_wr(uint32 data); + +#endif diff --git a/src/flash/ocl/at91sam7x/main.c b/src/flash/ocl/at91sam7x/main.c index c9e93ddb..2a4d28bb 100644 --- a/src/flash/ocl/at91sam7x/main.c +++ b/src/flash/ocl/at91sam7x/main.c @@ -1,107 +1,107 @@ -/*************************************************************************** - * Copyright (C) 2007 by Pavel Chromy * - * chromy@asix.cz * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * - ***************************************************************************/ -#include "platform.h" - -#include "ocl.h" -#include "dcc.h" -#include "samflash.h" - - -#define BUFSIZE 1024 /* words, i.e. 4 KiB */ -uint32 buffer[1024]; - -void cmd_flash(uint32 cmd) -{ - unsigned int len; - uint32 adr; - uint32 chksum; - unsigned int bi; /* buffer index */ - unsigned int bi_start; /* receive start mark */ - unsigned int bi_end; /* receive end mark */ - unsigned int ofs; - int pagenum; - int result; - - adr=dcc_rd(); - len=cmd&0xffff; - ofs=adr%flash_page_size; - bi_start=ofs/4; - bi_end=(ofs+len+3)/4; - - if (bi_end>BUFSIZE) { - dcc_wr(OCL_BUFF_OVER); - return; - } - - chksum=OCL_CHKS_INIT; - for (bi=0; biBUFSIZE) { + dcc_wr(OCL_BUFF_OVER); + return; + } + + chksum=OCL_CHKS_INIT; + for (bi=0; bi $@ - -clean: - -rm -f $(OBJS) - -rm -f $(PROJECT).elf - -rm -f $(PROJECT).map - -rm -f $(PROJECT).hex - -rm -f $(PROJECT).bin - -rm -f $(PROJECT).lst - -rm -f $(SRC:.c=.c.bak) - -rm -f $(SRC:.c=.lst) - -rm -f $(ASRC:.s=.s.bak) - -rm -f $(ASRC:.s=.lst) - -rm -fR .dep - -# -# Include the dependency files, should be the last of the makefile -# -#-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) - +############################################################################################## +# Start of default section +# + +TRGT = arm-elf- +CC = $(TRGT)gcc +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +HEX = $(CP) -O ihex +BIN = $(CP) -O binary +OBJDUMP = $(TRGT)objdump + +MCU = arm7tdmi + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################################## + +############################################################################################## +# Start of user section +# + +# Define project name here +PROJECT = at91sam7x_ocl + +# Define linker script file here +LDSCRIPT= at91sam7x_ram.ld + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List C source files here +SRC = main.c dcc.c samflash.c + +# List ASM source files here +ASRC = crt.s + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# Define optimisation level here +OPT = -O2 + +# +# End of user defines +############################################################################################## + + +INCDIR = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR)) +LIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) +DEFS = $(DDEFS) $(UDEFS) +ADEFS = $(DADEFS) $(UADEFS) +OBJS = $(ASRC:.s=.o) $(SRC:.c=.o) +LIBS = $(DLIBS) $(ULIBS) +MCFLAGS = -mcpu=$(MCU) + +ASFLAGS = $(MCFLAGS) -g -gdwarf-2 -Wa,-amhls=$(<:.s=.lst) $(ADEFS) +CPFLAGS = $(MCFLAGS) $(OPT) -gdwarf-2 -mthumb-interwork -fomit-frame-pointer -Wall -Wstrict-prototypes -fverbose-asm -Wa,-ahlms=$(<:.c=.lst) $(DEFS) +LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) + +# Generate dependency information +#CPFLAGS += -MD -MP -MF .dep/$(@F).d + +# +# makefile rules +# + +all: $(OBJS) $(PROJECT).elf $(PROJECT).hex $(PROJECT).bin $(PROJECT).lst + +%o : %c + $(CC) -c $(CPFLAGS) -I . $(INCDIR) $< -o $@ + +%o : %s + $(AS) -c $(ASFLAGS) $< -o $@ + +%elf: $(OBJS) + $(CC) $(OBJS) $(LDFLAGS) $(LIBS) -o $@ + +%hex: %elf + $(HEX) $< $@ + +%bin: %elf + $(BIN) $< $@ + +%.lst: %.elf + $(OBJDUMP) -h -S $< > $@ + +clean: + -rm -f $(OBJS) + -rm -f $(PROJECT).elf + -rm -f $(PROJECT).map + -rm -f $(PROJECT).hex + -rm -f $(PROJECT).bin + -rm -f $(PROJECT).lst + -rm -f $(SRC:.c=.c.bak) + -rm -f $(SRC:.c=.lst) + -rm -f $(ASRC:.s=.s.bak) + -rm -f $(ASRC:.s=.lst) + -rm -fR .dep + +# +# Include the dependency files, should be the last of the makefile +# +#-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) + # *** EOF *** \ No newline at end of file diff --git a/src/flash/ocl/at91sam7x/ocl.h b/src/flash/ocl/at91sam7x/ocl.h index 8c677b0e..d5c430be 100644 --- a/src/flash/ocl/at91sam7x/ocl.h +++ b/src/flash/ocl/at91sam7x/ocl.h @@ -1,40 +1,40 @@ -/*************************************************************************** - * Copyright (C) 2007 by Pavel Chromy * - * chromy@asix.cz * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * - ***************************************************************************/ -#ifndef OCL_H -#define OCL_H - -/* command/response mask */ -#define OCL_CMD_MASK 0xFFFF0000L - -/* commads */ -#define OCL_FLASH_BLOCK 0x0CFB0000L -#define OCL_ERASE_BLOCK 0x0CEB0000L -#define OCL_ERASE_ALL 0x0CEA0000L -#define OCL_PROBE 0x0CBE0000L - -/* responses */ -#define OCL_CMD_DONE 0x0ACD0000L -#define OCL_CMD_ERR 0x0ACE0000L -#define OCL_CHKS_FAIL 0x0ACF0000L -#define OCL_BUFF_OVER 0x0AB00000L - -#define OCL_CHKS_INIT 0xC100CD0CL - -#endif /* OCL_H */ +/*************************************************************************** + * Copyright (C) 2007 by Pavel Chromy * + * chromy@asix.cz * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, write to the * + * Free Software Foundation, Inc., * + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * + ***************************************************************************/ +#ifndef OCL_H +#define OCL_H + +/* command/response mask */ +#define OCL_CMD_MASK 0xFFFF0000L + +/* commads */ +#define OCL_FLASH_BLOCK 0x0CFB0000L +#define OCL_ERASE_BLOCK 0x0CEB0000L +#define OCL_ERASE_ALL 0x0CEA0000L +#define OCL_PROBE 0x0CBE0000L + +/* responses */ +#define OCL_CMD_DONE 0x0ACD0000L +#define OCL_CMD_ERR 0x0ACE0000L +#define OCL_CHKS_FAIL 0x0ACF0000L +#define OCL_BUFF_OVER 0x0AB00000L + +#define OCL_CHKS_INIT 0xC100CD0CL + +#endif /* OCL_H */ diff --git a/src/flash/ocl/at91sam7x/platform.h b/src/flash/ocl/at91sam7x/platform.h index c73544af..f1eea976 100644 --- a/src/flash/ocl/at91sam7x/platform.h +++ b/src/flash/ocl/at91sam7x/platform.h @@ -1,46 +1,46 @@ -/*************************************************************************** - * Copyright (C) 2007 by Pavel Chromy * - * chromy@asix.cz * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * - ***************************************************************************/ -#ifndef platformH -#define platformH - -#include "samregs.h" - - -#define outb(_reg, _val) (*((volatile unsigned char *)(_reg)) = (_val)) -#define outw(_reg, _val) (*((volatile unsigned short *)(_reg)) = (_val)) -#define outr(_reg, _val) (*((volatile unsigned int *)(_reg)) = (_val)) - -#define inb(_reg) (*((volatile unsigned char *)(_reg))) -#define inw(_reg) (*((volatile unsigned short *)(_reg))) -#define inr(_reg) (*((volatile unsigned int *)(_reg))) - -#define _BV(bit) (1 << (bit)) - - -typedef signed char int8; -typedef unsigned char uint8; - -typedef signed short int16; -typedef unsigned short uint16; - -typedef signed int int32; -typedef unsigned int uint32; - -#endif +/*************************************************************************** + * Copyright (C) 2007 by Pavel Chromy * + * chromy@asix.cz * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, write to the * + * Free Software Foundation, Inc., * + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * + ***************************************************************************/ +#ifndef platformH +#define platformH + +#include "samregs.h" + + +#define outb(_reg, _val) (*((volatile unsigned char *)(_reg)) = (_val)) +#define outw(_reg, _val) (*((volatile unsigned short *)(_reg)) = (_val)) +#define outr(_reg, _val) (*((volatile unsigned int *)(_reg)) = (_val)) + +#define inb(_reg) (*((volatile unsigned char *)(_reg))) +#define inw(_reg) (*((volatile unsigned short *)(_reg))) +#define inr(_reg) (*((volatile unsigned int *)(_reg))) + +#define _BV(bit) (1 << (bit)) + + +typedef signed char int8; +typedef unsigned char uint8; + +typedef signed short int16; +typedef unsigned short uint16; + +typedef signed int int32; +typedef unsigned int uint32; + +#endif diff --git a/src/flash/ocl/at91sam7x/samflash.c b/src/flash/ocl/at91sam7x/samflash.c index 253e410c..a48e6cfd 100644 --- a/src/flash/ocl/at91sam7x/samflash.c +++ b/src/flash/ocl/at91sam7x/samflash.c @@ -1,196 +1,196 @@ -/*************************************************************************** - * Copyright (C) 2007 by Pavel Chromy * - * chromy@asix.cz * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * - ***************************************************************************/ -#include "samflash.h" - - -unsigned int flash_page_count=1024; -unsigned int flash_page_size=256; - -/* pages per lock bit */ -unsigned int flash_lock_pages=1024/16; - - -/* detect chip and set loader parameters */ -int flash_init(void) -{ - unsigned int nvpsiz; - - nvpsiz=(inr(DBGU_CIDR)>>8)&0xf; - - switch (nvpsiz) { - case 3: - /* AT91SAM7x32 */ - flash_page_count=256; - flash_page_size=128; - flash_lock_pages=256/8; - break; - case 5: - /* AT91SAM7x64 */ - flash_page_count=512; - flash_page_size=128; - flash_lock_pages=512/16; - break; - case 7: - /* AT91SAM7x128*/ - flash_page_count=512; - flash_page_size=256; - flash_lock_pages=512/8; - break; - case 9: - /* AT91SAM7x256 */ - flash_page_count=1024; - flash_page_size=256; - flash_lock_pages=1024/16; - break; - case 10: - /* AT91SAM7x512 */ - flash_page_count=2048; - flash_page_size=256; - flash_lock_pages=2048/32; - break; - default: - return FLASH_STAT_INITE; - } - return FLASH_STAT_OK; -} - - -/* program single flash page */ -int flash_page_program(uint32 *data, int page_num) -{ - int i; - int efc_ofs; - - uint32 *flash_ptr; - uint32 *data_ptr; - - /* select proper controller */ - if (page_num>=1024) efc_ofs=0x10; - else efc_ofs=0; - - /* wait until FLASH is ready, just for sure */ - while ((inr(MC_FSR+efc_ofs)&MC_FRDY)==0); - - /* calculate page address, only lower 8 bits are used to address the latch, - but the upper part of address is needed for writing to proper EFC */ - flash_ptr=(uint32 *)(FLASH_AREA_ADDR+(page_num*flash_page_size)); - data_ptr=data; - - /* copy data to latch */ - for (i=flash_page_size/4; i; i--) { - /* we do not use memcpy to be sure that only 32 bit access is used */ - *(flash_ptr++)=*(data_ptr++); - } - - /* page number and page write command to FCR */ - outr(MC_FCR+efc_ofs, ((page_num&0x3ff)<<8) | MC_KEY | MC_FCMD_WP); - - /* wait until it's done */ - while ((inr(MC_FSR+efc_ofs)&MC_FRDY)==0); - - /* check for errors */ - if ((inr(MC_FSR+efc_ofs)&MC_PROGE)) return FLASH_STAT_PROGE; - if ((inr(MC_FSR+efc_ofs)&MC_LOCKE)) return FLASH_STAT_LOCKE; - -#if 0 - /* verify written data */ - flash_ptr=(uint32 *)(FLASH_AREA_ADDR+(page_num*flash_page_size)); - data_ptr=data; - - for (i=flash_page_size/4; i; i--) { - if (*(flash_ptr++)!=*(data_ptr++)) return FLASH_STAT_VERIFE; - } -#endif - - return FLASH_STAT_OK; -} - - -int flash_erase_plane(int efc_ofs) -{ - unsigned int lockbits; - int page_num; - - page_num=0; - lockbits=inr(MC_FSR+efc_ofs)>>16; - while (lockbits) { - if (lockbits&1) { - - /* wait until FLASH is ready, just for sure */ - while ((inr(MC_FSR+efc_ofs)&MC_FRDY)==0); - - outr(MC_FCR+efc_ofs, ((page_num&0x3ff)<<8) | 0x5a000004); - - /* wait until it's done */ - while ((inr(MC_FSR+efc_ofs)&MC_FRDY)==0); - - /* check for errors */ - if ((inr(MC_FSR+efc_ofs)&MC_PROGE)) return FLASH_STAT_PROGE; - if ((inr(MC_FSR+efc_ofs)&MC_LOCKE)) return FLASH_STAT_LOCKE; - - } - if ((page_num+=flash_lock_pages)>flash_page_count) break; - lockbits>>=1; - } - - /* wait until FLASH is ready, just for sure */ - while ((inr(MC_FSR+efc_ofs)&MC_FRDY)==0); - - /* erase all command to FCR */ - outr(MC_FCR+efc_ofs, 0x5a000008); - - /* wait until it's done */ - while ((inr(MC_FSR+efc_ofs)&MC_FRDY)==0); - - /* check for errors */ - if ((inr(MC_FSR+efc_ofs)&MC_PROGE)) return FLASH_STAT_PROGE; - if ((inr(MC_FSR+efc_ofs)&MC_LOCKE)) return FLASH_STAT_LOCKE; - - /* set no erase before programming */ - outr(MC_FMR+efc_ofs, inr(MC_FMR+efc_ofs)|0x80); - - return FLASH_STAT_OK; -} - - -/* erase whole chip */ -int flash_erase_all(void) -{ - int result; - - if ((result=flash_erase_plane(0))!=FLASH_STAT_OK) return result; - - /* the second flash controller, if any */ - if (flash_page_count>1024) result=flash_erase_plane(0x10); - - return result; -} - - -int flash_verify(uint32 adr, unsigned int len, uint8 *src) -{ - unsigned char *flash_ptr; - - flash_ptr=(uint8 *)FLASH_AREA_ADDR+adr; - for ( ;len; len--) { - if (*(flash_ptr++)!=*(src++)) return FLASH_STAT_VERIFE; - } - return FLASH_STAT_OK; -} +/*************************************************************************** + * Copyright (C) 2007 by Pavel Chromy * + * chromy@asix.cz * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, write to the * + * Free Software Foundation, Inc., * + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * + ***************************************************************************/ +#include "samflash.h" + + +unsigned int flash_page_count=1024; +unsigned int flash_page_size=256; + +/* pages per lock bit */ +unsigned int flash_lock_pages=1024/16; + + +/* detect chip and set loader parameters */ +int flash_init(void) +{ + unsigned int nvpsiz; + + nvpsiz=(inr(DBGU_CIDR)>>8)&0xf; + + switch (nvpsiz) { + case 3: + /* AT91SAM7x32 */ + flash_page_count=256; + flash_page_size=128; + flash_lock_pages=256/8; + break; + case 5: + /* AT91SAM7x64 */ + flash_page_count=512; + flash_page_size=128; + flash_lock_pages=512/16; + break; + case 7: + /* AT91SAM7x128*/ + flash_page_count=512; + flash_page_size=256; + flash_lock_pages=512/8; + break; + case 9: + /* AT91SAM7x256 */ + flash_page_count=1024; + flash_page_size=256; + flash_lock_pages=1024/16; + break; + case 10: + /* AT91SAM7x512 */ + flash_page_count=2048; + flash_page_size=256; + flash_lock_pages=2048/32; + break; + default: + return FLASH_STAT_INITE; + } + return FLASH_STAT_OK; +} + + +/* program single flash page */ +int flash_page_program(uint32 *data, int page_num) +{ + int i; + int efc_ofs; + + uint32 *flash_ptr; + uint32 *data_ptr; + + /* select proper controller */ + if (page_num>=1024) efc_ofs=0x10; + else efc_ofs=0; + + /* wait until FLASH is ready, just for sure */ + while ((inr(MC_FSR+efc_ofs)&MC_FRDY)==0); + + /* calculate page address, only lower 8 bits are used to address the latch, + but the upper part of address is needed for writing to proper EFC */ + flash_ptr=(uint32 *)(FLASH_AREA_ADDR+(page_num*flash_page_size)); + data_ptr=data; + + /* copy data to latch */ + for (i=flash_page_size/4; i; i--) { + /* we do not use memcpy to be sure that only 32 bit access is used */ + *(flash_ptr++)=*(data_ptr++); + } + + /* page number and page write command to FCR */ + outr(MC_FCR+efc_ofs, ((page_num&0x3ff)<<8) | MC_KEY | MC_FCMD_WP); + + /* wait until it's done */ + while ((inr(MC_FSR+efc_ofs)&MC_FRDY)==0); + + /* check for errors */ + if ((inr(MC_FSR+efc_ofs)&MC_PROGE)) return FLASH_STAT_PROGE; + if ((inr(MC_FSR+efc_ofs)&MC_LOCKE)) return FLASH_STAT_LOCKE; + +#if 0 + /* verify written data */ + flash_ptr=(uint32 *)(FLASH_AREA_ADDR+(page_num*flash_page_size)); + data_ptr=data; + + for (i=flash_page_size/4; i; i--) { + if (*(flash_ptr++)!=*(data_ptr++)) return FLASH_STAT_VERIFE; + } +#endif + + return FLASH_STAT_OK; +} + + +int flash_erase_plane(int efc_ofs) +{ + unsigned int lockbits; + int page_num; + + page_num=0; + lockbits=inr(MC_FSR+efc_ofs)>>16; + while (lockbits) { + if (lockbits&1) { + + /* wait until FLASH is ready, just for sure */ + while ((inr(MC_FSR+efc_ofs)&MC_FRDY)==0); + + outr(MC_FCR+efc_ofs, ((page_num&0x3ff)<<8) | 0x5a000004); + + /* wait until it's done */ + while ((inr(MC_FSR+efc_ofs)&MC_FRDY)==0); + + /* check for errors */ + if ((inr(MC_FSR+efc_ofs)&MC_PROGE)) return FLASH_STAT_PROGE; + if ((inr(MC_FSR+efc_ofs)&MC_LOCKE)) return FLASH_STAT_LOCKE; + + } + if ((page_num+=flash_lock_pages)>flash_page_count) break; + lockbits>>=1; + } + + /* wait until FLASH is ready, just for sure */ + while ((inr(MC_FSR+efc_ofs)&MC_FRDY)==0); + + /* erase all command to FCR */ + outr(MC_FCR+efc_ofs, 0x5a000008); + + /* wait until it's done */ + while ((inr(MC_FSR+efc_ofs)&MC_FRDY)==0); + + /* check for errors */ + if ((inr(MC_FSR+efc_ofs)&MC_PROGE)) return FLASH_STAT_PROGE; + if ((inr(MC_FSR+efc_ofs)&MC_LOCKE)) return FLASH_STAT_LOCKE; + + /* set no erase before programming */ + outr(MC_FMR+efc_ofs, inr(MC_FMR+efc_ofs)|0x80); + + return FLASH_STAT_OK; +} + + +/* erase whole chip */ +int flash_erase_all(void) +{ + int result; + + if ((result=flash_erase_plane(0))!=FLASH_STAT_OK) return result; + + /* the second flash controller, if any */ + if (flash_page_count>1024) result=flash_erase_plane(0x10); + + return result; +} + + +int flash_verify(uint32 adr, unsigned int len, uint8 *src) +{ + unsigned char *flash_ptr; + + flash_ptr=(uint8 *)FLASH_AREA_ADDR+adr; + for ( ;len; len--) { + if (*(flash_ptr++)!=*(src++)) return FLASH_STAT_VERIFE; + } + return FLASH_STAT_OK; +} diff --git a/src/flash/ocl/at91sam7x/samflash.h b/src/flash/ocl/at91sam7x/samflash.h index c793b9e8..136e3147 100644 --- a/src/flash/ocl/at91sam7x/samflash.h +++ b/src/flash/ocl/at91sam7x/samflash.h @@ -1,48 +1,48 @@ -/*************************************************************************** - * Copyright (C) 2007 by Pavel Chromy * - * chromy@asix.cz * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * - ***************************************************************************/ -#ifndef samflashH -#define samflashH - -#include "platform.h" - -#define FLASH_AREA_ADDR 0x100000 - -#define FLASH_STAT_OK 0 -#define FLASH_STAT_PROGE 1 -#define FLASH_STAT_LOCKE 2 -#define FLASH_STAT_VERIFE 3 -#define FLASH_STAT_INITE 4 - -extern unsigned int flash_page_count; -extern unsigned int flash_page_size; /* words */ - -/* detect chip and set loader parameters */ -extern int flash_init(void); - -/* program single flash page */ -extern int flash_page_program(uint32 *data, int page_num); - -/* erase whole chip */ -extern int flash_erase_all(void); - -/* verify written data */ -extern int flash_verify(uint32 adr, unsigned int len, uint8 *src); - -#endif +/*************************************************************************** + * Copyright (C) 2007 by Pavel Chromy * + * chromy@asix.cz * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, write to the * + * Free Software Foundation, Inc., * + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * + ***************************************************************************/ +#ifndef samflashH +#define samflashH + +#include "platform.h" + +#define FLASH_AREA_ADDR 0x100000 + +#define FLASH_STAT_OK 0 +#define FLASH_STAT_PROGE 1 +#define FLASH_STAT_LOCKE 2 +#define FLASH_STAT_VERIFE 3 +#define FLASH_STAT_INITE 4 + +extern unsigned int flash_page_count; +extern unsigned int flash_page_size; /* words */ + +/* detect chip and set loader parameters */ +extern int flash_init(void); + +/* program single flash page */ +extern int flash_page_program(uint32 *data, int page_num); + +/* erase whole chip */ +extern int flash_erase_all(void); + +/* verify written data */ +extern int flash_verify(uint32 adr, unsigned int len, uint8 *src); + +#endif diff --git a/src/flash/ocl/at91sam7x/samregs.h b/src/flash/ocl/at91sam7x/samregs.h index 7d3654fe..b206fd28 100644 --- a/src/flash/ocl/at91sam7x/samregs.h +++ b/src/flash/ocl/at91sam7x/samregs.h @@ -1,83 +1,83 @@ -/* - * Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holders nor the names of - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS - * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE - * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF - * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * For additional information see http://www.ethernut.de/ - */ - - -#ifndef samregsH -#define samregsH - - -/* - * Register definitions below copied from NutOS - */ - -#define DBGU_BASE 0xFFFFF200 /*!< \brief DBGU base address. */ - -#define DBGU_CIDR_OFF 0x00000040 /*!< \brief DBGU chip ID register offset. */ -#define DBGU_CIDR (DBGU_BASE + DBGU_CIDR_OFF) /*!< \brief DBGU chip ID register. */ - - -#define MC_BASE 0xFFFFFF00 /*!< \brief Memory controller base. */ - -#define MC_FMR_OFF 0x00000060 /*!< \brief MC flash mode register offset. */ -#define MC_FMR (MC_BASE + MC_FMR_OFF) /*!< \brief MC flash mode register address. */ -#define MC_FRDY 0x00000001 /*!< \brief Flash ready. */ -#define MC_LOCKE 0x00000004 /*!< \brief Lock error. */ -#define MC_PROGE 0x00000008 /*!< \brief Programming error. */ -#define MC_NEBP 0x00000080 /*!< \brief No erase before programming. */ -#define MC_FWS_MASK 0x00000300 /*!< \brief Flash wait state mask. */ -#define MC_FWS_1R2W 0x00000000 /*!< \brief 1 cycle for read, 2 for write operations. */ -#define MC_FWS_2R3W 0x00000100 /*!< \brief 2 cycles for read, 3 for write operations. */ -#define MC_FWS_3R4W 0x00000200 /*!< \brief 3 cycles for read, 4 for write operations. */ -#define MC_FWS_4R4W 0x00000300 /*!< \brief 4 cycles for read and write operations. */ -#define MC_FMCN_MASK 0x00FF0000 /*!< \brief Flash microsecond cycle number mask. */ - -#define MC_FCR_OFF 0x00000064 /*!< \brief MC flash command register offset. */ -#define MC_FCR (MC_BASE + MC_FCR_OFF) /*!< \brief MC flash command register address. */ -#define MC_FCMD_MASK 0x0000000F /*!< \brief Flash command mask. */ -#define MC_FCMD_NOP 0x00000000 /*!< \brief No command. */ -#define MC_FCMD_WP 0x00000001 /*!< \brief Write page. */ -#define MC_FCMD_SLB 0x00000002 /*!< \brief Set lock bit. */ -#define MC_FCMD_WPL 0x00000003 /*!< \brief Write page and lock. */ -#define MC_FCMD_CLB 0x00000004 /*!< \brief Clear lock bit. */ -#define MC_FCMD_EA 0x00000008 /*!< \brief Erase all. */ -#define MC_FCMD_SGPB 0x0000000B /*!< \brief Set general purpose NVM bit. */ -#define MC_FCMD_CGPB 0x0000000D /*!< \brief Clear general purpose NVM bit. */ -#define MC_FCMD_SSB 0x0000000F /*!< \brief Set security bit. */ -#define MC_PAGEN_MASK 0x0003FF00 /*!< \brief Page number mask. */ -#define MC_KEY 0x5A000000 /*!< \brief Writing protect key. */ - -#define MC_FSR_OFF 0x00000068 /*!< \brief MC flash status register offset. */ -#define MC_FSR (MC_BASE + MC_FSR_OFF) /*!< \brief MC flash status register address. */ -#define MC_SECURITY 0x00000010 /*!< \brief Security bit status. */ - - -#endif +/* + * Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holders nor the names of + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE + * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF + * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * For additional information see http://www.ethernut.de/ + */ + + +#ifndef samregsH +#define samregsH + + +/* + * Register definitions below copied from NutOS + */ + +#define DBGU_BASE 0xFFFFF200 /*!< \brief DBGU base address. */ + +#define DBGU_CIDR_OFF 0x00000040 /*!< \brief DBGU chip ID register offset. */ +#define DBGU_CIDR (DBGU_BASE + DBGU_CIDR_OFF) /*!< \brief DBGU chip ID register. */ + + +#define MC_BASE 0xFFFFFF00 /*!< \brief Memory controller base. */ + +#define MC_FMR_OFF 0x00000060 /*!< \brief MC flash mode register offset. */ +#define MC_FMR (MC_BASE + MC_FMR_OFF) /*!< \brief MC flash mode register address. */ +#define MC_FRDY 0x00000001 /*!< \brief Flash ready. */ +#define MC_LOCKE 0x00000004 /*!< \brief Lock error. */ +#define MC_PROGE 0x00000008 /*!< \brief Programming error. */ +#define MC_NEBP 0x00000080 /*!< \brief No erase before programming. */ +#define MC_FWS_MASK 0x00000300 /*!< \brief Flash wait state mask. */ +#define MC_FWS_1R2W 0x00000000 /*!< \brief 1 cycle for read, 2 for write operations. */ +#define MC_FWS_2R3W 0x00000100 /*!< \brief 2 cycles for read, 3 for write operations. */ +#define MC_FWS_3R4W 0x00000200 /*!< \brief 3 cycles for read, 4 for write operations. */ +#define MC_FWS_4R4W 0x00000300 /*!< \brief 4 cycles for read and write operations. */ +#define MC_FMCN_MASK 0x00FF0000 /*!< \brief Flash microsecond cycle number mask. */ + +#define MC_FCR_OFF 0x00000064 /*!< \brief MC flash command register offset. */ +#define MC_FCR (MC_BASE + MC_FCR_OFF) /*!< \brief MC flash command register address. */ +#define MC_FCMD_MASK 0x0000000F /*!< \brief Flash command mask. */ +#define MC_FCMD_NOP 0x00000000 /*!< \brief No command. */ +#define MC_FCMD_WP 0x00000001 /*!< \brief Write page. */ +#define MC_FCMD_SLB 0x00000002 /*!< \brief Set lock bit. */ +#define MC_FCMD_WPL 0x00000003 /*!< \brief Write page and lock. */ +#define MC_FCMD_CLB 0x00000004 /*!< \brief Clear lock bit. */ +#define MC_FCMD_EA 0x00000008 /*!< \brief Erase all. */ +#define MC_FCMD_SGPB 0x0000000B /*!< \brief Set general purpose NVM bit. */ +#define MC_FCMD_CGPB 0x0000000D /*!< \brief Clear general purpose NVM bit. */ +#define MC_FCMD_SSB 0x0000000F /*!< \brief Set security bit. */ +#define MC_PAGEN_MASK 0x0003FF00 /*!< \brief Page number mask. */ +#define MC_KEY 0x5A000000 /*!< \brief Writing protect key. */ + +#define MC_FSR_OFF 0x00000068 /*!< \brief MC flash status register offset. */ +#define MC_FSR (MC_BASE + MC_FSR_OFF) /*!< \brief MC flash status register address. */ +#define MC_SECURITY 0x00000010 /*!< \brief Security bit status. */ + + +#endif diff --git a/testing/examples/SAM7S256Test/results/607.html b/testing/examples/SAM7S256Test/results/607.html index 570b3b34..852c0ad6 100644 --- a/testing/examples/SAM7S256Test/results/607.html +++ b/testing/examples/SAM7S256Test/results/607.html @@ -1,698 +1,698 @@ - - -Test results for revision 607 - - - -

Test cases

-

Test case results

-The test results are stored in seperate documents. One document for -each subversion number. - - - - -
Test resultscomment
607
templateTest results template
- -

SAM7S64

- -

Connectivity

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
IDTargetInterfaceDescriptionInitial stateInputExpected outputActual outputPass/Fail
CON001SAM7S64ZY1000Telnet connectionPower on, jtag target attachedOn console, type
telnet ip port		Open On-Chip Debugger
>		Open On-Chip Debugger
>		PASS
CON002SAM7S64ZY1000GDB server connectionPower on, jtag target attachedOn GDB console, type
target remote ip:port		Remote debugging using 10.0.0.73:3333Remote debugging using 10.0.0.73:3333PASS
- -

Reset

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
IDTargetInterfaceDescriptionInitial stateInputExpected outputActual outputPass/Fail
RES001SAM7S64ZY1000Reset halt on a blank targetErase all the content of the flashConnect via the telnet interface and type
reset halt		Reset should return without error and the output should contain
target state: halted
pc = 0		 - - JTAG device found: 0x3f0f0f0f (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
- nSRST pulls nTRST, falling back to "reset run_and_halt"
- target state: halted
- target halted in ARM state due to debug request, current mode: Supervisor
- cpsr: 0x60000013 pc: 0x00100178 - - 		PASS
RES002SAM7S64ZY1000Reset init on a blank targetErase all the content of the flashConnect via the telnet interface and type
reset init		Reset should return without error and the output should contain
executing reset script 'name_of_the_script'		 - - JTAG device found: 0x3f0f0f0f (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
- nSRST pulls nTRST, falling back to "reset run_and_init"
- target state: halted
- target halted in ARM state due to debug request, current mode: Supervisor
- cpsr: 0x600000d3 pc: 0x00003e24
- executing reset script 'event/sam7s256_reset.script' - - 		PASS
RES003SAM7S64ZY1000Reset after a power cycle of the targetReset the target then power cycle the targetConnect via the telnet interface and type
reset halt after the power was detected		Reset should return without error and the output should contain
target state: halted		 - - JTAG device found: 0x3f0f0f0f (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
- nSRST pulls nTRST, falling back to "reset run_and_halt"
- target state: halted
- target halted in ARM state due to debug request, current mode: Supervisor
- cpsr: 0x300000d3 pc: 0x00003a38 - - 		PASS
- -

JTAG Speed

- - - - - - - - - - - - - - - - - - - - - - - -
IDTargetZY1000DescriptionInitial stateInputExpected outputActual outputPass/Fail
RES001SAM7S64ZY100016MHz on normal operationReset init the target according to RES002 Exercise a memory access over the JTAG, for example
mdw 0x0 32		The command should run without any errors. If any JTAG checking errors happen, the test failed - - > jtag_khz 16000
- > mdw 0 32
- 0x00000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
- 0x00000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
- 0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
- 0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff - - 		PASS
- -

Debugging

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
IDTargetInterfaceDescriptionInitial stateInputExpected outputActual outputPass/Fail
DBG001SAM7S64ZY1000Load is workingReset init is working, RAM is accesible, GDB server is startedOn the console of the OS:
- arm-elf-gdb test_ram.elf
- (gdb) target remote ip:port
- (gdb) load - 		Load should return without error, typical output looks like:
- - Loading section .text, size 0x14c lma 0x0
- Start address 0x40, load size 332
- Transfer rate: 180 bytes/sec, 332 bytes/write.
- - 		- (gdb) load
- Loading section .text, size 0x194 lma 0x200000
- Start address 0x200040, load size 404
- Transfer rate: 17470 bits/sec, 404 bytes/write. - 		PASS
DBG002SAM7S64ZY1000Software breakpointLoad the test_ram.elf application, use instructions from GDB001In the GDB console:
- - (gdb) monitor arm7_9 sw_bkpts enable
- software breakpoints enabled
- (gdb) break main
- Breakpoint 1 at 0xec: file src/main.c, line 71.
- (gdb) continue
- Continuing. - - 		The software breakpoint should be reached, a typical output looks like:
- - target state: halted
- target halted in ARM state due to breakpoint, current mode: Supervisor
- cpsr: 0x000000d3 pc: 0x000000ec
-
- Breakpoint 1, main () at src/main.c:71
- 71 DWORD a = 1; - - 		- - (gdb) break main
- Breakpoint 2 at 0x200134: file src/main.c, line 69.
- (gdb) c
- Continuing.
- target state: halted
- target halted in ARM state due to breakpoint, current mode: Supervisor
- cpsr: 0x60000013 pc: 0x00200134
-
- Breakpoint 2, main () at src/main.c:69
- 69 DWORD a = 1; - - 		PASS
DBG003SAM7S64ZY1000Single step in a RAM applicationLoad the test_ram.elf application, use instructions from GDB001, break in main using the instructions from GDB002In GDB, type
(gdb) step		The next instruction should be reached, typical output:
- - (gdb) step
- target state: halted
- target halted in ARM state due to single step, current mode: Abort
- cpsr: 0x20000097 pc: 0x000000f0
- target state: halted
- target halted in ARM state due to single step, current mode: Abort
- cpsr: 0x20000097 pc: 0x000000f4
- 72 DWORD b = 2; - - 		- - (gdb) step
- target state: halted
- target halted in ARM state due to single step, current mode: Abort
- cpsr: 0x20000097 pc: 0x000000f0
- target state: halted
- target halted in ARM state due to single step, current mode: Abort
- cpsr: 0x20000097 pc: 0x000000f4
- 72 DWORD b = 2; - - 		PASS
DBG004SAM7S64ZY1000Software break points are working after a resetLoad the test_ram.elf application, use instructions from GDB001, break in main using the instructions from GDB002In GDB, type
- (gdb) monitor reset
- (gdb) load
- (gdb) continue
- 		The breakpoint should be reached, typical output:
- - target state: halted
- target halted in ARM state due to breakpoint, current mode: Supervisor
- cpsr: 0x000000d3 pc: 0x000000ec
-
- Breakpoint 1, main () at src/main.c:71
- 71 DWORD a = 1; - - 		- (gdb) moni reset
- JTAG device found: 0x3f0f0f0f (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
- target state: halted
- target halted in ARM state due to debug request, current mode: Supervisor
- cpsr: 0x600000d3 pc: 0x00003e28
- executing reset script 'event/sam7s256_reset.script'
- (gdb) load
- Loading section .text, size 0x194 lma 0x200000
- Start address 0x200040, load size 404
- Transfer rate: 20455 bits/sec, 404 bytes/write.
- (gdb) continue
- Continuing.
- target state: halted
- target halted in ARM state due to breakpoint, current mode: Supervisor
- cpsr: 0x60000013 pc: 0x00200134
-
- Breakpoint 2, main () at src/main.c:69
- 69 DWORD a = 1; - 		PASS
DBG005SAM7S64ZY1000Hardware breakpointFlash the test_rom.elf application. Make this test after FLA004 has passedBe sure that gdb_memory_map and gdb_flash_program are enabled. In GDB, type
- - (gdb) monitor reset
- (gdb) load
- Loading section .text, size 0x194 lma 0x100000
- Start address 0x100040, load size 404
- Transfer rate: 179 bytes/sec, 404 bytes/write.
- (gdb) monitor arm7_9 force_hw_bkpts enable
- force hardware breakpoints enabled
- (gdb) break main
- Breakpoint 1 at 0x100134: file src/main.c, line 69.
- (gdb) continue
- - 		The breakpoint should be reached, typical output:
- - Continuing.
-
- Breakpoint 1, main () at src/main.c:69
- 69 DWORD a = 1;
- - 		- - (gdb) break main
- Breakpoint 1 at 0x100134: file src/main.c, line 69.
- (gdb) c
- Continuing.
- target state: halted
- target halted in ARM state due to breakpoint, current mode: Supervisor
- cpsr: 0x60000013 pc: 0x00100134
-
- Breakpoint 1, main () at src/main.c:69
- 69 DWORD a = 1; - - 		PASS
DBG006SAM7S64ZY1000Hardware breakpoint is set after a resetFollow the instructions to flash and insert a hardware breakpoint from DBG005In GDB, type
- - (gdb) monitor reset
- (gdb) monitor reg pc 0x100000
- pc (/32): 0x00100000
- (gdb) continue -
- where the value inserted in PC is the start address of the application - 		The breakpoint should be reached, typical output:
- - Continuing.
-
- Breakpoint 1, main () at src/main.c:69
- 69 DWORD a = 1;
- - 		- - Continuing.
- target state: halted
- target halted in ARM state due to single step, current mode: Supervisor
- cpsr: 0x60000013 pc: 0x00100040
- target state: halted
- target halted in ARM state due to breakpoint, current mode: Supervisor
- cpsr: 0x60000013 pc: 0x00100134
-
- Breakpoint 1, main () at src/main.c:69
- 69 DWORD a = 1; -
- Aren't there too many "halted" signs? - 		PASS
DBG007SAM7S64ZY1000Single step in ROMFlash the test_rom.elf application and set a breakpoint in main, use DBG005. Make this test after FLA004 has passedBe sure that gdb_memory_map and gdb_flash_program are enabled. In GDB, type
- - (gdb) monitor reset
- (gdb) load
- Loading section .text, size 0x194 lma 0x100000
- Start address 0x100040, load size 404
- Transfer rate: 179 bytes/sec, 404 bytes/write.
- (gdb) monitor arm7_9 force_hw_bkpts enable
- force hardware breakpoints enabled
- (gdb) break main
- Breakpoint 1 at 0x100134: file src/main.c, line 69.
- (gdb) continue
- Continuing.
-
- Breakpoint 1, main () at src/main.c:69
- 69 DWORD a = 1;
- (gdb) step - - 		The breakpoint should be reached, typical output:
- - target state: halted
- target halted in ARM state due to single step, current mode: Supervisor
- cpsr: 0x60000013 pc: 0x0010013c
- 70 DWORD b = 2;
- - 		- (gdb) step
- target state: halted
- target halted in ARM state due to single step, current mode: Supervisor
- cpsr: 0x60000013 pc: 0x00100138
- target state: halted
- target halted in ARM state due to single step, current mode: Supervisor
- cpsr: 0x60000013 pc: 0x0010013c
- 70 DWORD b = 2; - 		PASS
- -

RAM access

-Note: these tests are not designed to test/debug the target, but to test functionalities! - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
IDTargetInterfaceDescriptionInitial stateInputExpected outputActual outputPass/Fail
RAM001SAM7S64ZY100032 bit Write/read RAMReset init is workingOn the telnet interface
- > mww ram_address 0xdeadbeef 16
- > mdw ram_address 32 - - 		The commands should execute without error. A clear failure is a memory access exception. The result of running the commands should be a list of 16 locations 32bit long containing 0xdeadbeef.
- - > mww 0x0 0xdeadbeef 16
- > mdw 0x0 32
- 0x00000000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
- 0x00000020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
- 0x00000040: e1a00000 e59fa51c e59f051c e04aa000 00080017 00009388 00009388 00009388
- 0x00000060: 00009388 0002c2c0 0002c2c0 000094f8 000094f4 00009388 00009388 00009388
- - 		- - > mww 0x00200000 0xdeadbeef 16
- > mdw 0x00200000 32
- 0x00200000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
- 0x00200020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
- 0x00200040: e59f10b4 e3a00902 e5810004 e59f00ac e59f10ac e5810000 e3e010ff e59f00a4
- 0x00200060: e5810060 e59f10a0 e3e00000 e5810130 e5810124 e321f0db e59fd090 e321f0d7 - - 		PASS
RAM002SAM7S64ZY100016 bit Write/read RAMReset init is workingOn the telnet interface
- > mwh ram_address 0xbeef 16
- > mdh ram_address 32 - - 		The commands should execute without error. A clear failure is a memory access exception. The result of running the commands should be a list of 16 locations 16bit long containing 0xbeef.
- - > mwh 0x0 0xbeef 16
- > mdh 0x0 32
- 0x00000000: beef beef beef beef beef beef beef beef beef beef beef beef beef beef beef beef
- 0x00000020: 00e0 0000 021c 0000 0240 0000 026c 0000 0288 0000 0000 0000 0388 0000 0350 0000
- > - - 		- > mwh 0x00200000 0xbeef 16
- > mdh 0x00200000 32
- 0x00200000: beef beef beef beef beef beef beef beef beef beef beef beef beef beef beef beef
- 0x00200020: 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 - 		PASS
RAM003SAM7S64ZY10008 bit Write/read RAMReset init is workingOn the telnet interface
- > mwb ram_address 0xab 16
- > mdb ram_address 32 - - 		The commands should execute without error. A clear failure is a memory access exception. The result of running the commands should be a list of 16 locations 8bit long containing 0xab.
- - > mwb ram_address 0xab 16
- > mdb ram_address 32
- 0x00000000: ab ab ab ab ab ab ab ab ab ab ab ab ab ab ab ab 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
- > - - 		- > mwb 0x00200000 0xab 16
- > mdb 0x00200000 32
- 0x00200000: ab ab ab ab ab ab ab ab ab ab ab ab ab ab ab ab 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - 		PASS
- - - -

Flash access

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
IDTargetInterfaceDescriptionInitial stateInputExpected outputActual outputPass/Fail
FLA001SAM7S64ZY1000Flash probeReset init is workingOn the telnet interface:
- > flash probe 0 - 		The command should execute without error. The output should state the name of the flash and the starting address. An example of output:
- flash 'ecosflash' found at 0x01000000 - 		- - > flash probe 0
- flash 'at91sam7' found at 0x00100000 - - 		PASS
FLA002SAM7S64ZY1000flash fillwReset init is working, flash is probedOn the telnet interface
- > flash fillw 0x1000000 0xdeadbeef 16 - - 		The commands should execute without error. The output looks like:
- - wrote 64 bytes to 0x01000000 in 11.610000s (0.091516 kb/s) -
- To verify the contents of the flash:
- - > mdw 0x1000000 32
- 0x01000000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
- 0x01000020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
- 0x01000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
- 0x01000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff - - 		- > flash fillw 0x100000 0xdeadbeef 16
- wrote 64 bytes to 0x00100000 in 1.110000s (0.957207 kb/s)
- > mdw 0x100000 32
- 0x00100000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
- 0x00100020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
- 0x00100040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
- 0x00100060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff - 		PASS
FLA003SAM7S64ZY1000Flash eraseReset init is working, flash is probedOn the telnet interface
- > flash erase_address 0x1000000 0x2000 - - 		The commands should execute without error.
- - erased address 0x01000000 length 8192 in 4.970000s - - To check that the flash has been erased, read at different addresses. The result should always be 0xff. - - > mdw 0x1000000 32
- 0x01000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
- 0x01000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
- 0x01000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
- 0x01000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff - - 		- > flash erase_address 0x100000 0x2000
- erased address 0x00100000 length 8192 in 0.510000s
- > mdw 0x100000 32
- 0x00100000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
- 0x00100020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
- 0x00100040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
- 0x00100060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
- > - 		PASS
FLA004SAM7S64ZY1000Loading to flash from GDBReset init is working, flash is probed, connectivity to GDB server is workingStart GDB using a ROM elf image, eg: arm-elf-gdb test_rom.elf.
- - (gdb) target remote ip:port
- (gdb) monitor reset
- (gdb) load
- Loading section .text, size 0x194 lma 0x100000
- Start address 0x100040, load size 404
- Transfer rate: 179 bytes/sec, 404 bytes/write. - (gdb) monitor verify_image path_to_elf_file - - 		The output should look like:
- - verified 404 bytes in 5.060000s -
- The failure message is something like:
- Verify operation failed address 0x00200000. Was 0x00 instead of 0x18 - 		- - (gdb) load
- Loading section .text, size 0x194 lma 0x100000
- Start address 0x100040, load size 404
- Transfer rate: 1540 bits/sec, 404 bytes/write.
- (gdb) monitor verify_image /tftp/10.0.0.9/c:\workspace/ecosboard/ecosboard/phi/openocd/rep/testing/examples/SAM7S256Test/test_rom.elf
- verified 404 bytes in 4.860000s - - 		PASS
- - + + +Test results for revision 607 + + + +

Test cases

+

Test case results

+The test results are stored in seperate documents. One document for +each subversion number. + + + + +
Test resultscomment
607
templateTest results template
+ +

SAM7S64

+ +

Connectivity

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
IDTargetInterfaceDescriptionInitial stateInputExpected outputActual outputPass/Fail
CON001SAM7S64ZY1000Telnet connectionPower on, jtag target attachedOn console, type
telnet ip port		Open On-Chip Debugger
>		Open On-Chip Debugger
>		PASS
CON002SAM7S64ZY1000GDB server connectionPower on, jtag target attachedOn GDB console, type
target remote ip:port		Remote debugging using 10.0.0.73:3333Remote debugging using 10.0.0.73:3333PASS
+ +

Reset

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
IDTargetInterfaceDescriptionInitial stateInputExpected outputActual outputPass/Fail
RES001SAM7S64ZY1000Reset halt on a blank targetErase all the content of the flashConnect via the telnet interface and type
reset halt		Reset should return without error and the output should contain
target state: halted
pc = 0		 + + JTAG device found: 0x3f0f0f0f (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
+ nSRST pulls nTRST, falling back to "reset run_and_halt"
+ target state: halted
+ target halted in ARM state due to debug request, current mode: Supervisor
+ cpsr: 0x60000013 pc: 0x00100178 + + 		PASS
RES002SAM7S64ZY1000Reset init on a blank targetErase all the content of the flashConnect via the telnet interface and type
reset init		Reset should return without error and the output should contain
executing reset script 'name_of_the_script'		 + + JTAG device found: 0x3f0f0f0f (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
+ nSRST pulls nTRST, falling back to "reset run_and_init"
+ target state: halted
+ target halted in ARM state due to debug request, current mode: Supervisor
+ cpsr: 0x600000d3 pc: 0x00003e24
+ executing reset script 'event/sam7s256_reset.script' + + 		PASS
RES003SAM7S64ZY1000Reset after a power cycle of the targetReset the target then power cycle the targetConnect via the telnet interface and type
reset halt after the power was detected		Reset should return without error and the output should contain
target state: halted		 + + JTAG device found: 0x3f0f0f0f (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
+ nSRST pulls nTRST, falling back to "reset run_and_halt"
+ target state: halted
+ target halted in ARM state due to debug request, current mode: Supervisor
+ cpsr: 0x300000d3 pc: 0x00003a38 + + 		PASS
+ +

JTAG Speed

+ + + + + + + + + + + + + + + + + + + + + + + +
IDTargetZY1000DescriptionInitial stateInputExpected outputActual outputPass/Fail
RES001SAM7S64ZY100016MHz on normal operationReset init the target according to RES002 Exercise a memory access over the JTAG, for example
mdw 0x0 32		The command should run without any errors. If any JTAG checking errors happen, the test failed + + > jtag_khz 16000
+ > mdw 0 32
+ 0x00000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x00000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff + + 		PASS
+ +

Debugging

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
IDTargetInterfaceDescriptionInitial stateInputExpected outputActual outputPass/Fail
DBG001SAM7S64ZY1000Load is workingReset init is working, RAM is accesible, GDB server is startedOn the console of the OS:
+ arm-elf-gdb test_ram.elf
+ (gdb) target remote ip:port
+ (gdb) load + 		Load should return without error, typical output looks like:
+ + Loading section .text, size 0x14c lma 0x0
+ Start address 0x40, load size 332
+ Transfer rate: 180 bytes/sec, 332 bytes/write.
+ + 		+ (gdb) load
+ Loading section .text, size 0x194 lma 0x200000
+ Start address 0x200040, load size 404
+ Transfer rate: 17470 bits/sec, 404 bytes/write. + 		PASS
DBG002SAM7S64ZY1000Software breakpointLoad the test_ram.elf application, use instructions from GDB001In the GDB console:
+ + (gdb) monitor arm7_9 sw_bkpts enable
+ software breakpoints enabled
+ (gdb) break main
+ Breakpoint 1 at 0xec: file src/main.c, line 71.
+ (gdb) continue
+ Continuing. + + 		The software breakpoint should be reached, a typical output looks like:
+ + target state: halted
+ target halted in ARM state due to breakpoint, current mode: Supervisor
+ cpsr: 0x000000d3 pc: 0x000000ec
+
+ Breakpoint 1, main () at src/main.c:71
+ 71 DWORD a = 1; + + 		+ + (gdb) break main
+ Breakpoint 2 at 0x200134: file src/main.c, line 69.
+ (gdb) c
+ Continuing.
+ target state: halted
+ target halted in ARM state due to breakpoint, current mode: Supervisor
+ cpsr: 0x60000013 pc: 0x00200134
+
+ Breakpoint 2, main () at src/main.c:69
+ 69 DWORD a = 1; + + 		PASS
DBG003SAM7S64ZY1000Single step in a RAM applicationLoad the test_ram.elf application, use instructions from GDB001, break in main using the instructions from GDB002In GDB, type
(gdb) step		The next instruction should be reached, typical output:
+ + (gdb) step
+ target state: halted
+ target halted in ARM state due to single step, current mode: Abort
+ cpsr: 0x20000097 pc: 0x000000f0
+ target state: halted
+ target halted in ARM state due to single step, current mode: Abort
+ cpsr: 0x20000097 pc: 0x000000f4
+ 72 DWORD b = 2; + + 		+ + (gdb) step
+ target state: halted
+ target halted in ARM state due to single step, current mode: Abort
+ cpsr: 0x20000097 pc: 0x000000f0
+ target state: halted
+ target halted in ARM state due to single step, current mode: Abort
+ cpsr: 0x20000097 pc: 0x000000f4
+ 72 DWORD b = 2; + + 		PASS
DBG004SAM7S64ZY1000Software break points are working after a resetLoad the test_ram.elf application, use instructions from GDB001, break in main using the instructions from GDB002In GDB, type
+ (gdb) monitor reset
+ (gdb) load
+ (gdb) continue
+ 		The breakpoint should be reached, typical output:
+ + target state: halted
+ target halted in ARM state due to breakpoint, current mode: Supervisor
+ cpsr: 0x000000d3 pc: 0x000000ec
+
+ Breakpoint 1, main () at src/main.c:71
+ 71 DWORD a = 1; + + 		+ (gdb) moni reset
+ JTAG device found: 0x3f0f0f0f (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
+ target state: halted
+ target halted in ARM state due to debug request, current mode: Supervisor
+ cpsr: 0x600000d3 pc: 0x00003e28
+ executing reset script 'event/sam7s256_reset.script'
+ (gdb) load
+ Loading section .text, size 0x194 lma 0x200000
+ Start address 0x200040, load size 404
+ Transfer rate: 20455 bits/sec, 404 bytes/write.
+ (gdb) continue
+ Continuing.
+ target state: halted
+ target halted in ARM state due to breakpoint, current mode: Supervisor
+ cpsr: 0x60000013 pc: 0x00200134
+
+ Breakpoint 2, main () at src/main.c:69
+ 69 DWORD a = 1; + 		PASS
DBG005SAM7S64ZY1000Hardware breakpointFlash the test_rom.elf application. Make this test after FLA004 has passedBe sure that gdb_memory_map and gdb_flash_program are enabled. In GDB, type
+ + (gdb) monitor reset
+ (gdb) load
+ Loading section .text, size 0x194 lma 0x100000
+ Start address 0x100040, load size 404
+ Transfer rate: 179 bytes/sec, 404 bytes/write.
+ (gdb) monitor arm7_9 force_hw_bkpts enable
+ force hardware breakpoints enabled
+ (gdb) break main
+ Breakpoint 1 at 0x100134: file src/main.c, line 69.
+ (gdb) continue
+ + 		The breakpoint should be reached, typical output:
+ + Continuing.
+
+ Breakpoint 1, main () at src/main.c:69
+ 69 DWORD a = 1;
+ + 		+ + (gdb) break main
+ Breakpoint 1 at 0x100134: file src/main.c, line 69.
+ (gdb) c
+ Continuing.
+ target state: halted
+ target halted in ARM state due to breakpoint, current mode: Supervisor
+ cpsr: 0x60000013 pc: 0x00100134
+
+ Breakpoint 1, main () at src/main.c:69
+ 69 DWORD a = 1; + + 		PASS
DBG006SAM7S64ZY1000Hardware breakpoint is set after a resetFollow the instructions to flash and insert a hardware breakpoint from DBG005In GDB, type
+ + (gdb) monitor reset
+ (gdb) monitor reg pc 0x100000
+ pc (/32): 0x00100000
+ (gdb) continue +
+ where the value inserted in PC is the start address of the application + 		The breakpoint should be reached, typical output:
+ + Continuing.
+
+ Breakpoint 1, main () at src/main.c:69
+ 69 DWORD a = 1;
+ + 		+ + Continuing.
+ target state: halted
+ target halted in ARM state due to single step, current mode: Supervisor
+ cpsr: 0x60000013 pc: 0x00100040
+ target state: halted
+ target halted in ARM state due to breakpoint, current mode: Supervisor
+ cpsr: 0x60000013 pc: 0x00100134
+
+ Breakpoint 1, main () at src/main.c:69
+ 69 DWORD a = 1; +
+ Aren't there too many "halted" signs? + 		PASS
DBG007SAM7S64ZY1000Single step in ROMFlash the test_rom.elf application and set a breakpoint in main, use DBG005. Make this test after FLA004 has passedBe sure that gdb_memory_map and gdb_flash_program are enabled. In GDB, type
+ + (gdb) monitor reset
+ (gdb) load
+ Loading section .text, size 0x194 lma 0x100000
+ Start address 0x100040, load size 404
+ Transfer rate: 179 bytes/sec, 404 bytes/write.
+ (gdb) monitor arm7_9 force_hw_bkpts enable
+ force hardware breakpoints enabled
+ (gdb) break main
+ Breakpoint 1 at 0x100134: file src/main.c, line 69.
+ (gdb) continue
+ Continuing.
+
+ Breakpoint 1, main () at src/main.c:69
+ 69 DWORD a = 1;
+ (gdb) step + + 		The breakpoint should be reached, typical output:
+ + target state: halted
+ target halted in ARM state due to single step, current mode: Supervisor
+ cpsr: 0x60000013 pc: 0x0010013c
+ 70 DWORD b = 2;
+ + 		+ (gdb) step
+ target state: halted
+ target halted in ARM state due to single step, current mode: Supervisor
+ cpsr: 0x60000013 pc: 0x00100138
+ target state: halted
+ target halted in ARM state due to single step, current mode: Supervisor
+ cpsr: 0x60000013 pc: 0x0010013c
+ 70 DWORD b = 2; + 		PASS
+ +

RAM access

+Note: these tests are not designed to test/debug the target, but to test functionalities! + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
IDTargetInterfaceDescriptionInitial stateInputExpected outputActual outputPass/Fail
RAM001SAM7S64ZY100032 bit Write/read RAMReset init is workingOn the telnet interface
+ > mww ram_address 0xdeadbeef 16
+ > mdw ram_address 32 + + 		The commands should execute without error. A clear failure is a memory access exception. The result of running the commands should be a list of 16 locations 32bit long containing 0xdeadbeef.
+ + > mww 0x0 0xdeadbeef 16
+ > mdw 0x0 32
+ 0x00000000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
+ 0x00000020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
+ 0x00000040: e1a00000 e59fa51c e59f051c e04aa000 00080017 00009388 00009388 00009388
+ 0x00000060: 00009388 0002c2c0 0002c2c0 000094f8 000094f4 00009388 00009388 00009388
+ + 		+ + > mww 0x00200000 0xdeadbeef 16
+ > mdw 0x00200000 32
+ 0x00200000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
+ 0x00200020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
+ 0x00200040: e59f10b4 e3a00902 e5810004 e59f00ac e59f10ac e5810000 e3e010ff e59f00a4
+ 0x00200060: e5810060 e59f10a0 e3e00000 e5810130 e5810124 e321f0db e59fd090 e321f0d7 + + 		PASS
RAM002SAM7S64ZY100016 bit Write/read RAMReset init is workingOn the telnet interface
+ > mwh ram_address 0xbeef 16
+ > mdh ram_address 32 + + 		The commands should execute without error. A clear failure is a memory access exception. The result of running the commands should be a list of 16 locations 16bit long containing 0xbeef.
+ + > mwh 0x0 0xbeef 16
+ > mdh 0x0 32
+ 0x00000000: beef beef beef beef beef beef beef beef beef beef beef beef beef beef beef beef
+ 0x00000020: 00e0 0000 021c 0000 0240 0000 026c 0000 0288 0000 0000 0000 0388 0000 0350 0000
+ > + + 		+ > mwh 0x00200000 0xbeef 16
+ > mdh 0x00200000 32
+ 0x00200000: beef beef beef beef beef beef beef beef beef beef beef beef beef beef beef beef
+ 0x00200020: 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 + 		PASS
RAM003SAM7S64ZY10008 bit Write/read RAMReset init is workingOn the telnet interface
+ > mwb ram_address 0xab 16
+ > mdb ram_address 32 + + 		The commands should execute without error. A clear failure is a memory access exception. The result of running the commands should be a list of 16 locations 8bit long containing 0xab.
+ + > mwb ram_address 0xab 16
+ > mdb ram_address 32
+ 0x00000000: ab ab ab ab ab ab ab ab ab ab ab ab ab ab ab ab 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+ > + + 		+ > mwb 0x00200000 0xab 16
+ > mdb 0x00200000 32
+ 0x00200000: ab ab ab ab ab ab ab ab ab ab ab ab ab ab ab ab 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 		PASS
+ + + +

Flash access

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
IDTargetInterfaceDescriptionInitial stateInputExpected outputActual outputPass/Fail
FLA001SAM7S64ZY1000Flash probeReset init is workingOn the telnet interface:
+ > flash probe 0 + 		The command should execute without error. The output should state the name of the flash and the starting address. An example of output:
+ flash 'ecosflash' found at 0x01000000 + 		+ + > flash probe 0
+ flash 'at91sam7' found at 0x00100000 + + 		PASS
FLA002SAM7S64ZY1000flash fillwReset init is working, flash is probedOn the telnet interface
+ > flash fillw 0x1000000 0xdeadbeef 16 + + 		The commands should execute without error. The output looks like:
+ + wrote 64 bytes to 0x01000000 in 11.610000s (0.091516 kb/s) +
+ To verify the contents of the flash:
+ + > mdw 0x1000000 32
+ 0x01000000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
+ 0x01000020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
+ 0x01000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x01000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff + + 		+ > flash fillw 0x100000 0xdeadbeef 16
+ wrote 64 bytes to 0x00100000 in 1.110000s (0.957207 kb/s)
+ > mdw 0x100000 32
+ 0x00100000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
+ 0x00100020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
+ 0x00100040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x00100060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff + 		PASS
FLA003SAM7S64ZY1000Flash eraseReset init is working, flash is probedOn the telnet interface
+ > flash erase_address 0x1000000 0x2000 + + 		The commands should execute without error.
+ + erased address 0x01000000 length 8192 in 4.970000s + + To check that the flash has been erased, read at different addresses. The result should always be 0xff. + + > mdw 0x1000000 32
+ 0x01000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x01000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x01000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x01000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff + + 		+ > flash erase_address 0x100000 0x2000
+ erased address 0x00100000 length 8192 in 0.510000s
+ > mdw 0x100000 32
+ 0x00100000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x00100020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x00100040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x00100060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ > + 		PASS
FLA004SAM7S64ZY1000Loading to flash from GDBReset init is working, flash is probed, connectivity to GDB server is workingStart GDB using a ROM elf image, eg: arm-elf-gdb test_rom.elf.
+ + (gdb) target remote ip:port
+ (gdb) monitor reset
+ (gdb) load
+ Loading section .text, size 0x194 lma 0x100000
+ Start address 0x100040, load size 404
+ Transfer rate: 179 bytes/sec, 404 bytes/write. + (gdb) monitor verify_image path_to_elf_file + + 		The output should look like:
+ + verified 404 bytes in 5.060000s +
+ The failure message is something like:
+ Verify operation failed address 0x00200000. Was 0x00 instead of 0x18 + 		+ + (gdb) load
+ Loading section .text, size 0x194 lma 0x100000
+ Start address 0x100040, load size 404
+ Transfer rate: 1540 bits/sec, 404 bytes/write.
+ (gdb) monitor verify_image /tftp/10.0.0.9/c:\workspace/ecosboard/ecosboard/phi/openocd/rep/testing/examples/SAM7S256Test/test_rom.elf
+ verified 404 bytes in 4.860000s + + 		PASS
+ + \ No newline at end of file diff --git a/testing/results/template.html b/testing/results/template.html index 90692587..286bf2e3 100644 --- a/testing/results/template.html +++ b/testing/results/template.html @@ -1,18 +1,18 @@ - - - - - - Testcases - - - - - - - - -
TestInterfaceTargetResult
CON001 FILL IN! FILL IN!PASS/FAIL
CON002 FILL IN! FILL IN!PASS/FAIL
RES001 FILL IN! FILL IN!PASS/FAIL
RES002 FILL IN! FILL IN!PASS/FAIL
RES003 FILL IN! FILL IN!PASS/FAIL
DBG001 FILL IN! FILL IN!PASS/FAIL
- - + + + + + + Testcases + + + + + + + + +
TestInterfaceTargetResult
CON001 FILL IN! FILL IN!PASS/FAIL
CON002 FILL IN! FILL IN!PASS/FAIL
RES001 FILL IN! FILL IN!PASS/FAIL
RES002 FILL IN! FILL IN!PASS/FAIL
RES003 FILL IN! FILL IN!PASS/FAIL
DBG001 FILL IN! FILL IN!PASS/FAIL
+ + \ No newline at end of file diff --git a/testing/smoketests.html b/testing/smoketests.html index cc8a553e..3d5cd962 100644 --- a/testing/smoketests.html +++ b/testing/smoketests.html @@ -1,315 +1,315 @@ - - - - - -

OpenOCD smoketest results

- These tests can be performed on any JTAG device as long as they are executed using the unmodified code from SVN. -

The latest version in which the test is known to have passed is in the table below.

-

Vocabulary

- - - - - - - - - - - - - -
Passed versionThe latest branch and version on which the test is known to pass
Broken versionThe latest branch and version on which the test is known to fail. n/a when older than passed version.
IDA unqiue ID to refer to a test. The unique numbers are maintained in this file. Note that the same test can be run on different hardware/interface. Each combination yields a unique id.
-

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Unique IDSynopsisJTAG devicePassed versionBroken version
fill_mallocFill malloc() memory with garbagen/an/an/a
ocd1Telnet Windowsn/an/an/a
ocd2Telnet Linuxn/an/an/a
ocd3Telnet Cygwinn/an/an/a
ocd4ARM7 debuggingn/an/an/a
SAM9260SAM9260 debuggingft2232 500n/a
xscale1XScale debuggingbitbang505n/a
xscale2XScale debuggingFT2232202n/a
bdte-ram1str710 ram debuggingJTAGkey536n/a
bdte-rom2str710 rom debuggingJTAGkey536n/a
bdte-ram3str912 ram debuggingJTAGkey536n/a
bdte-rom4str912 rom debuggingJTAGkey536n/a
bdte-ram5lpc2148 ram debuggingJTAGkey536n/a
bdte-rom6lpc2148 rom debuggingJTAGkey536n/a
bdte-ram7lpc2294 ram debuggingJTAGkey536n/a
bdte-rom8lpc2294 rom debuggingJTAGkey536n/a
bdte-ram9sam7s256 ram debuggingJTAGkey536n/a
bdte-rom10sam7s256 rom debuggingJTAGkey536n/a
bdte-ram11sam7x256 ram debuggingJTAGkey517n/a
bdte-rom12sam7x256 rom debuggingJTAGkey517n/a
bdte-ram13at91r40008 ram debuggingJTAGkey536n/a
-

-
-

OpenOCD JTAG device test results

- Each JTAG device must be tested - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
IDSynopsisPassed versionBroken version
jtag1Parportn/an/a
jtag2JTAGkey536n/a
jtag3Turtelizer2536n/a
jtag4JTAGkey536n/a
jtag5add new onen/an/a
-

jtag1:

-

jtag2: Tested on Windows XP Prof. (SP2) with original FTDI driver.

-

jtag3: Tested on Windows XP Prof. (SP2) with original FTDI driver.

-

jtag4: Tested on Mac OS X (10.5.2, Intel) with libftdi-0.10 and libusb-0.1.12

-

jtag5:

-
-

OpenOCD JTAG device speed test result

-

The test result is in KB/sec.

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
IDSynopsisr320r420r423r459r517r536
speed1JTAGkey9364 93939393
speed2JTAGkeyn/an/an/an/a5252
speed3add new onen/an/an/an/an/an/a
-

-
-

Policy on removing features from OpenOCD

- If a feature in OpenOCD is known to be broken and nobody has submitted a fix and the feature is causing trouble for maintainence, it can be removed from OpenOCD trunk. The threshold for temporarily removing something from OpenOCD trunk is low to ease maintainence and place the burden of maintainence on those that care about a feature. -

Note that code is never deleted from OpenOCD svn, it remains in svn so if somebody sees a feature removed that they would like kept, they have but to port and fix that feature back up to main trunk. This document can be helpful in this regard in that the latest working version and the known broken version may be listed.

-

Policy on adding features from OpenOCD

- To add a feature to OpenOCD, generally it should not break any existing features and it should be functional and the code reasonably readable and useful to others in the OpenOCD community. The code does not have to be completed. Work in progress is fine for OpenOCD trunk. -

Also new tests should be defined. Note that the code does not have to pass all the tests. In fact it can be helpful to have tests to describe facets that really should be working, but aren't done yet.

-
-

ocd4 - ARM7 debugging

- Connect to ARM7 device(any), use GDB load to load a program into RAM and single halt, resume and single step. -
-

bdte-ram (Basic debugging test with Eclipse in RAM)

-

This test was made under Eclipse with the Zylin Embedded CDT plugin. For the GDB "Initialize commands" take a look in the examples/<target>/prj/eclipse_ram.gdb file.

-

Start debugging, the debugger should stop at main. set some breakpoints and "Resume". If the debugger hit a breakpoint check if the "Variables" looks correct. Remove some breakpoints and "Resume" again. If the target is running, use the "Suspend" function and use "Step Into" or "Step Over" through the source. Even open the "Disassembly" view and enable the "Instruction Stepping Mode". Now you can single step through the assembler source. Use "Resume" again to run the program, set a breakpoint while the target is running. Check if you can inspect the variables with the mouse over. Play a little with the target...

-
-

bdte-rom (Basic debugging test with Eclipse in ROM)

-

This test was made under Eclipse with the Zylin Embedded CDT plugin. For the GDB "Initialize commands" take a look in the examples/<target>/prj/eclipse_rom.gdb file.

-

Start debugging, the debugger should download and store the program in the flash of the target.

-

Now you can make some tests like described in the bdte-ram section above too.

-
-

speed1 - Download speed test

-

For this test a STR710 with external memory was used. The example project can be found under examples/STR710JtagSpeed. Here Eclipse or the arm-elf-gdb can be used to download the test.elf file into the RAM. The result of the GDB can look like:

-

Loading section .text, size 0x6019c lma 0x62000000
- Start address 0x62000040, load size 393628
- Transfer rate: 93 KB/sec, 2008 bytes/write.

-

In this example a speed of 93 KB/sec was reached. The hardware which was used for the test can be found here.

-

The test was made on Windows XP Prof. (SP2) with a JTAGkey and the original FTDI driver.

-
-

speed2 - Download speed test

-

For this test a STR710 with external memory was used. The example project can be found under examples/STR710JtagSpeed. Here Eclipse or the arm-elf-gdb can be used to download the test.elf file into the RAM. The result of the GDB can look like:

-

Loading section .text, size 0x6019c lma 0x62000000
- Start address 0x62000040, load size 393628
Transfer rate: 52 KB/sec, 2008 bytes/write.

-

In this example a speed of 52 KB/sec was reached. The hardware which was used for the test can be found here.

-

The test was made on Mac OS X (10.5.2, Intel) with a JTAGkey and the following driver:

-

- libftdi 0.10
- - libusb 0.1.12

-

-

- - + + + + + +

OpenOCD smoketest results

+ These tests can be performed on any JTAG device as long as they are executed using the unmodified code from SVN. +

The latest version in which the test is known to have passed is in the table below.

+

Vocabulary

+ + + + + + + + + + + + + +
Passed versionThe latest branch and version on which the test is known to pass
Broken versionThe latest branch and version on which the test is known to fail. n/a when older than passed version.
IDA unqiue ID to refer to a test. The unique numbers are maintained in this file. Note that the same test can be run on different hardware/interface. Each combination yields a unique id.
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Unique IDSynopsisJTAG devicePassed versionBroken version
fill_mallocFill malloc() memory with garbagen/an/an/a
ocd1Telnet Windowsn/an/an/a
ocd2Telnet Linuxn/an/an/a
ocd3Telnet Cygwinn/an/an/a
ocd4ARM7 debuggingn/an/an/a
SAM9260SAM9260 debuggingft2232 500n/a
xscale1XScale debuggingbitbang505n/a
xscale2XScale debuggingFT2232202n/a
bdte-ram1str710 ram debuggingJTAGkey536n/a
bdte-rom2str710 rom debuggingJTAGkey536n/a
bdte-ram3str912 ram debuggingJTAGkey536n/a
bdte-rom4str912 rom debuggingJTAGkey536n/a
bdte-ram5lpc2148 ram debuggingJTAGkey536n/a
bdte-rom6lpc2148 rom debuggingJTAGkey536n/a
bdte-ram7lpc2294 ram debuggingJTAGkey536n/a
bdte-rom8lpc2294 rom debuggingJTAGkey536n/a
bdte-ram9sam7s256 ram debuggingJTAGkey536n/a
bdte-rom10sam7s256 rom debuggingJTAGkey536n/a
bdte-ram11sam7x256 ram debuggingJTAGkey517n/a
bdte-rom12sam7x256 rom debuggingJTAGkey517n/a
bdte-ram13at91r40008 ram debuggingJTAGkey536n/a
+

+
+

OpenOCD JTAG device test results

+ Each JTAG device must be tested + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
IDSynopsisPassed versionBroken version
jtag1Parportn/an/a
jtag2JTAGkey536n/a
jtag3Turtelizer2536n/a
jtag4JTAGkey536n/a
jtag5add new onen/an/a
+

jtag1:

+

jtag2: Tested on Windows XP Prof. (SP2) with original FTDI driver.

+

jtag3: Tested on Windows XP Prof. (SP2) with original FTDI driver.

+

jtag4: Tested on Mac OS X (10.5.2, Intel) with libftdi-0.10 and libusb-0.1.12

+

jtag5:

+
+

OpenOCD JTAG device speed test result

+

The test result is in KB/sec.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
IDSynopsisr320r420r423r459r517r536
speed1JTAGkey9364 93939393
speed2JTAGkeyn/an/an/an/a5252
speed3add new onen/an/an/an/an/an/a
+

+
+

Policy on removing features from OpenOCD

+ If a feature in OpenOCD is known to be broken and nobody has submitted a fix and the feature is causing trouble for maintainence, it can be removed from OpenOCD trunk. The threshold for temporarily removing something from OpenOCD trunk is low to ease maintainence and place the burden of maintainence on those that care about a feature. +

Note that code is never deleted from OpenOCD svn, it remains in svn so if somebody sees a feature removed that they would like kept, they have but to port and fix that feature back up to main trunk. This document can be helpful in this regard in that the latest working version and the known broken version may be listed.

+

Policy on adding features from OpenOCD

+ To add a feature to OpenOCD, generally it should not break any existing features and it should be functional and the code reasonably readable and useful to others in the OpenOCD community. The code does not have to be completed. Work in progress is fine for OpenOCD trunk. +

Also new tests should be defined. Note that the code does not have to pass all the tests. In fact it can be helpful to have tests to describe facets that really should be working, but aren't done yet.

+
+

ocd4 - ARM7 debugging

+ Connect to ARM7 device(any), use GDB load to load a program into RAM and single halt, resume and single step. +
+

bdte-ram (Basic debugging test with Eclipse in RAM)

+

This test was made under Eclipse with the Zylin Embedded CDT plugin. For the GDB "Initialize commands" take a look in the examples/<target>/prj/eclipse_ram.gdb file.

+

Start debugging, the debugger should stop at main. set some breakpoints and "Resume". If the debugger hit a breakpoint check if the "Variables" looks correct. Remove some breakpoints and "Resume" again. If the target is running, use the "Suspend" function and use "Step Into" or "Step Over" through the source. Even open the "Disassembly" view and enable the "Instruction Stepping Mode". Now you can single step through the assembler source. Use "Resume" again to run the program, set a breakpoint while the target is running. Check if you can inspect the variables with the mouse over. Play a little with the target...

+
+

bdte-rom (Basic debugging test with Eclipse in ROM)

+

This test was made under Eclipse with the Zylin Embedded CDT plugin. For the GDB "Initialize commands" take a look in the examples/<target>/prj/eclipse_rom.gdb file.

+

Start debugging, the debugger should download and store the program in the flash of the target.

+

Now you can make some tests like described in the bdte-ram section above too.

+
+

speed1 - Download speed test

+

For this test a STR710 with external memory was used. The example project can be found under examples/STR710JtagSpeed. Here Eclipse or the arm-elf-gdb can be used to download the test.elf file into the RAM. The result of the GDB can look like:

+

Loading section .text, size 0x6019c lma 0x62000000
+ Start address 0x62000040, load size 393628
+ Transfer rate: 93 KB/sec, 2008 bytes/write.

+

In this example a speed of 93 KB/sec was reached. The hardware which was used for the test can be found here.

+

The test was made on Windows XP Prof. (SP2) with a JTAGkey and the original FTDI driver.

+
+

speed2 - Download speed test

+

For this test a STR710 with external memory was used. The example project can be found under examples/STR710JtagSpeed. Here Eclipse or the arm-elf-gdb can be used to download the test.elf file into the RAM. The result of the GDB can look like:

+

Loading section .text, size 0x6019c lma 0x62000000
+ Start address 0x62000040, load size 393628
Transfer rate: 52 KB/sec, 2008 bytes/write.

+

In this example a speed of 52 KB/sec was reached. The hardware which was used for the test can be found here.

+

The test was made on Mac OS X (10.5.2, Intel) with a JTAGkey and the following driver:

+

- libftdi 0.10
+ - libusb 0.1.12

+

+

+ + \ No newline at end of file diff --git a/testing/testcases.html b/testing/testcases.html index df8bfe71..a3cc9eb6 100644 --- a/testing/testcases.html +++ b/testing/testcases.html @@ -1,578 +1,578 @@ - - -Test cases - - - -

Test cases

-

Test case results

-The test results are stored in seperate documents. One document for -each subversion number. - - - - -
Test resultscomment
607
templateTest results template
- -

Vocabulary

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Passed versionThe latest branch and version on which the test is known to pass
Broken versionThe latest branch and version on which the test is known to fail. n/a when older than passed version.
IDA unqiue ID to refer to a test. The unique numbers are maintained in this file. Note that the same test can be run on different hardware/interface. Each combination yields a unique id.
Test caseAn atomic entity that describes the operations needed to test a feature or only a part of it. The test case should: -
    -
  • be uniquely identifiable
    • -
  • define the complete prerequisites of the test (eg: the target, the interface, the initial state of the system)
    • -
  • define the input to be applied to the system in order to execute the test
    • -
  • define the expected output
    • -
  • contain the output resulted by running the test case
    • -
  • contain the result of the test (pass/fail)
    • -
-
Test suiteA (completable) collection of test cases
TestingTesting refers to running the test suite for a specific revision of the software, - for one or many targets, using one or many JTAG interfaces. Testing should be be stored - along with all the other records for that specific revision. For releases, the results - can be stored along with the binaries
Target = ANYAny target can be used for this test
Interface = ANYAny interface can be used for this test
Target = "reset_config srst_and_trst"Any target which supports the reset_config above
- -

Test cases

- -

Connectivity

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
IDTargetInterfaceDescriptionInitial stateInputExpected outputPass/Fail
CON001ALLALLTelnet connectionPower on, jtag target attachedOn console, type
telnet ip port		Open On-Chip Debugger
>		PASS/FAIL
CON002ALLALLGDB server connectionPower on, jtag target attachedOn GDB console, type
target remote ip:port		Remote debugging using 10.0.0.73:3333PASS/FAIL
- -

Reset

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
IDTargetInterfaceDescriptionInitial stateInputExpected outputPass/Fail
RES001Fill in!Fill in!Reset halt on a blank targetErase all the content of the flashConnect via the telnet interface and type
reset halt		Reset should return without error and the output should contain
target state: halted
pc = 0		PASS/FAIL
RES002Fill in!Fill in!Reset init on a blank targetErase all the content of the flashConnect via the telnet interface and type
reset init		Reset should return without error and the output should contain
executing reset script 'name_of_the_script'		PASS/FAIL
RES003Fill in!Fill in!Reset after a power cycle of the targetReset the target then power cycle the targetConnect via the telnet interface and type
reset halt after the power was detected		Reset should return without error and the output should contain
target state: halted		PASS/FAIL
RES004ARM7/9,reset_config srst_and_trstANYReset halt on a blank target where reset halt is supportedErase all the content of the flashConnect via the telnet interface and type
reset halt		Reset should return without error and the output should contain
target state: halted
pc = 0		PASS/FAIL
RES005arm926ejs,reset_config srst_and_trstANYReset halt on a blank target where reset halt is supported. This target has problems with the reset vector catch being disabled by TRSTErase all the content of the flashConnect via the telnet interface and type
reset halt		Reset should return without error and the output should contain
target state: halted
pc = 0		PASS/FAIL
- -

JTAG Speed

- - - - - - - - - - - - - - - - - - - - - -
IDTargetInterfaceDescriptionInitial stateInputExpected outputPass/Fail
RES001Fill in!Fill in!16MHz on normal operationReset init the target according to RES002 Exercise a memory access over the JTAG, for example
mdw 0x0 32		The command should run without any errors. If any JTAG checking errors happen, the test failedPASS/FAIL
- -

Debugging

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
IDTargetInterfaceDescriptionInitial stateInputExpected outputPass/Fail
DBG001Fill in!Fill in!Load is workingReset init is working, RAM is accesible, GDB server is startedOn the console of the OS:
- arm-elf-gdb test_ram.elf
- (gdb) target remote ip:port
- (gdb) load - 		Load should return without error, typical output looks like:
- - Loading section .text, size 0x14c lma 0x0
- Start address 0x40, load size 332
- Transfer rate: 180 bytes/sec, 332 bytes/write.
- - 		PASS/FAIL
DBG002Fill in!Fill in!Software breakpointLoad the test_ram.elf application, use instructions from GDB001In the GDB console:
- - (gdb) monitor arm7_9 sw_bkpts enable
- software breakpoints enabled
- (gdb) break main
- Breakpoint 1 at 0xec: file src/main.c, line 71.
- (gdb) continue
- Continuing. - - 		The software breakpoint should be reached, a typical output looks like:
- - target state: halted
- target halted in ARM state due to breakpoint, current mode: Supervisor
- cpsr: 0x000000d3 pc: 0x000000ec
-
- Breakpoint 1, main () at src/main.c:71
- 71 DWORD a = 1; - - 		PASS/FAIL
DBG003Fill in!Fill in!Single step in a RAM applicationLoad the test_ram.elf application, use instructions from GDB001, break in main using the instructions from GDB002In GDB, type
(gdb) step		The next instruction should be reached, typical output:
- - (gdb) step
- target state: halted
- target halted in ARM state due to single step, current mode: Abort
- cpsr: 0x20000097 pc: 0x000000f0
- target state: halted
- target halted in ARM state due to single step, current mode: Abort
- cpsr: 0x20000097 pc: 0x000000f4
- 72 DWORD b = 2; - - 		PASS/FAIL
DBG004Fill in!Fill in!Software break points are working after a resetLoad the test_ram.elf application, use instructions from GDB001, break in main using the instructions from GDB002In GDB, type
- (gdb) monitor reset
- (gdb) load
- (gdb) continue
- 		The breakpoint should be reached, typical output:
- - target state: halted
- target halted in ARM state due to breakpoint, current mode: Supervisor
- cpsr: 0x000000d3 pc: 0x000000ec
-
- Breakpoint 1, main () at src/main.c:71
- 71 DWORD a = 1; - - 		PASS/FAIL
DBG005Fill in!Fill in!Hardware breakpointFlash the test_rom.elf application. Make this test after FLA004 has passedBe sure that gdb_memory_map and gdb_flash_program are enabled. In GDB, type
- - (gdb) monitor reset
- (gdb) load
- Loading section .text, size 0x194 lma 0x100000
- Start address 0x100040, load size 404
- Transfer rate: 179 bytes/sec, 404 bytes/write.
- (gdb) monitor arm7_9 force_hw_bkpts enable
- force hardware breakpoints enabled
- (gdb) break main
- Breakpoint 1 at 0x100134: file src/main.c, line 69.
- (gdb) continue
- - 		The breakpoint should be reached, typical output:
- - Continuing.
-
- Breakpoint 1, main () at src/main.c:69
- 69 DWORD a = 1;
- - 		PASS/FAIL
DBG006Fill in!Fill in!Hardware breakpoint is set after a resetFollow the instructions to flash and insert a hardware breakpoint from DBG005In GDB, type
- - (gdb) monitor reset
- (gdb) monitor reg pc 0x100000
- pc (/32): 0x00100000
- (gdb) continue - - 		The breakpoint should be reached, typical output:
- - Continuing.
-
- Breakpoint 1, main () at src/main.c:69
- 69 DWORD a = 1;
- - 		PASS/FAIL
DBG007Fill in!Fill in!Single step in ROMFlash the test_rom.elf application and set a breakpoint in main, use DBG005. Make this test after FLA004 has passedBe sure that gdb_memory_map and gdb_flash_program are enabled. In GDB, type
- - (gdb) monitor reset
- (gdb) load
- Loading section .text, size 0x194 lma 0x100000
- Start address 0x100040, load size 404
- Transfer rate: 179 bytes/sec, 404 bytes/write.
- (gdb) monitor arm7_9 force_hw_bkpts enable
- force hardware breakpoints enabled
- (gdb) break main
- Breakpoint 1 at 0x100134: file src/main.c, line 69.
- (gdb) continue
- Continuing.
-
- Breakpoint 1, main () at src/main.c:69
- 69 DWORD a = 1;
- (gdb) step - - 		The breakpoint should be reached, typical output:
- - target state: halted
- target halted in ARM state due to single step, current mode: Supervisor
- cpsr: 0x60000013 pc: 0x0010013c
- 70 DWORD b = 2;
- - 		PASS/FAIL
- -

RAM access

-Note: these tests are not designed to test/debug the target, but to test functionalities! - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
IDTargetInterfaceDescriptionInitial stateInputExpected outputPass/Fail
RAM001Fill in!Fill in!32 bit Write/read RAMReset init is workingOn the telnet interface
- > mww ram_address 0xdeadbeef 16
- > mdw ram_address 32 - - 		The commands should execute without error. A clear failure is a memory access exception. The result of running the commands should be a list of 16 locations 32bit long containing 0xdeadbeef.
- - > mww 0x0 0xdeadbeef 16
- > mdw 0x0 32
- 0x00000000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
- 0x00000020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
- 0x00000040: e1a00000 e59fa51c e59f051c e04aa000 00080017 00009388 00009388 00009388
- 0x00000060: 00009388 0002c2c0 0002c2c0 000094f8 000094f4 00009388 00009388 00009388
- - 		PASS/FAIL
RAM001Fill in!Fill in!16 bit Write/read RAMReset init is workingOn the telnet interface
- > mwh ram_address 0xbeef 16
- > mdh ram_address 32 - - 		The commands should execute without error. A clear failure is a memory access exception. The result of running the commands should be a list of 16 locations 16bit long containing 0xbeef.
- - > mwh 0x0 0xbeef 16
- > mdh 0x0 32
- 0x00000000: beef beef beef beef beef beef beef beef beef beef beef beef beef beef beef beef
- 0x00000020: 00e0 0000 021c 0000 0240 0000 026c 0000 0288 0000 0000 0000 0388 0000 0350 0000
- > - - 		PASS/FAIL
RAM003Fill in!Fill in!8 bit Write/read RAMReset init is workingOn the telnet interface
- > mwb ram_address 0xab 16
- > mdb ram_address 32 - - 		The commands should execute without error. A clear failure is a memory access exception. The result of running the commands should be a list of 16 locations 8bit long containing 0xab.
- - > mwh 0x0 0x0 16
- > mwb ram_address 0xab 16
- > mdb ram_address 32
- 0x00000000: ab ab ab ab ab ab ab ab ab ab ab ab ab ab ab ab 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
- > - - 		PASS/FAIL
- - - -

Flash access

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
IDTargetInterfaceDescriptionInitial stateInputExpected outputPass/Fail
FLA001Fill in!Fill in!Flash probeReset init is workingOn the telnet interface:
- > flash probe 0 - 		The command should execute without error. The output should state the name of the flash and the starting address. An example of output:
- flash 'ecosflash' found at 0x01000000 - 		PASS/FAIL
FLA002Fill in!Fill in!flash fillwReset init is working, flash is probedOn the telnet interface
- > flash fillw 0x1000000 0xdeadbeef 16 - - 		The commands should execute without error. The output looks like:
- - wrote 64 bytes to 0x01000000 in 11.610000s (0.091516 kb/s) -
- To verify the contents of the flash:
- - > mdw 0x1000000 32
- 0x01000000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
- 0x01000020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
- 0x01000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
- 0x01000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff - - 		PASS/FAIL
FLA003Fill in!Fill in!Flash eraseReset init is working, flash is probedOn the telnet interface
- > flash erase_address 0x1000000 0x2000 - - 		The commands should execute without error.
- - erased address 0x01000000 length 8192 in 4.970000s - - To check that the flash has been erased, read at different addresses. The result should always be 0xff. - - > mdw 0x1000000 32
- 0x01000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
- 0x01000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
- 0x01000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
- 0x01000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff - - 		PASS/FAIL
FLA004Fill in!Fill in!Loading to flash from GDBReset init is working, flash is probed, connectivity to GDB server is workingStart GDB using a ROM elf image, eg: arm-elf-gdb test_rom.elf.
- - (gdb) target remote ip:port
- (gdb) monitor reset
- (gdb) load
- Loading section .text, size 0x194 lma 0x100000
- Start address 0x100040, load size 404
- Transfer rate: 179 bytes/sec, 404 bytes/write. - (gdb) monitor verify_image path_to_elf_file - - 		The output should look like:
- - verified 404 bytes in 5.060000s -
- The failure message is something like:
- Verify operation failed address 0x00200000. Was 0x00 instead of 0x18 - 		PASS/FAIL
- - + + +Test cases + + + +

Test cases

+

Test case results

+The test results are stored in seperate documents. One document for +each subversion number. + + + + +
Test resultscomment
607
templateTest results template
+ +

Vocabulary

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Passed versionThe latest branch and version on which the test is known to pass
Broken versionThe latest branch and version on which the test is known to fail. n/a when older than passed version.
IDA unqiue ID to refer to a test. The unique numbers are maintained in this file. Note that the same test can be run on different hardware/interface. Each combination yields a unique id.
Test caseAn atomic entity that describes the operations needed to test a feature or only a part of it. The test case should: +
    +
  • be uniquely identifiable
    • +
  • define the complete prerequisites of the test (eg: the target, the interface, the initial state of the system)
    • +
  • define the input to be applied to the system in order to execute the test
    • +
  • define the expected output
    • +
  • contain the output resulted by running the test case
    • +
  • contain the result of the test (pass/fail)
    • +
+
Test suiteA (completable) collection of test cases
TestingTesting refers to running the test suite for a specific revision of the software, + for one or many targets, using one or many JTAG interfaces. Testing should be be stored + along with all the other records for that specific revision. For releases, the results + can be stored along with the binaries
Target = ANYAny target can be used for this test
Interface = ANYAny interface can be used for this test
Target = "reset_config srst_and_trst"Any target which supports the reset_config above
+ +

Test cases

+ +

Connectivity

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
IDTargetInterfaceDescriptionInitial stateInputExpected outputPass/Fail
CON001ALLALLTelnet connectionPower on, jtag target attachedOn console, type
telnet ip port		Open On-Chip Debugger
>		PASS/FAIL
CON002ALLALLGDB server connectionPower on, jtag target attachedOn GDB console, type
target remote ip:port		Remote debugging using 10.0.0.73:3333PASS/FAIL
+ +

Reset

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
IDTargetInterfaceDescriptionInitial stateInputExpected outputPass/Fail
RES001Fill in!Fill in!Reset halt on a blank targetErase all the content of the flashConnect via the telnet interface and type
reset halt		Reset should return without error and the output should contain
target state: halted
pc = 0		PASS/FAIL
RES002Fill in!Fill in!Reset init on a blank targetErase all the content of the flashConnect via the telnet interface and type
reset init		Reset should return without error and the output should contain
executing reset script 'name_of_the_script'		PASS/FAIL
RES003Fill in!Fill in!Reset after a power cycle of the targetReset the target then power cycle the targetConnect via the telnet interface and type
reset halt after the power was detected		Reset should return without error and the output should contain
target state: halted		PASS/FAIL
RES004ARM7/9,reset_config srst_and_trstANYReset halt on a blank target where reset halt is supportedErase all the content of the flashConnect via the telnet interface and type
reset halt		Reset should return without error and the output should contain
target state: halted
pc = 0		PASS/FAIL
RES005arm926ejs,reset_config srst_and_trstANYReset halt on a blank target where reset halt is supported. This target has problems with the reset vector catch being disabled by TRSTErase all the content of the flashConnect via the telnet interface and type
reset halt		Reset should return without error and the output should contain
target state: halted
pc = 0		PASS/FAIL
+ +

JTAG Speed

+ + + + + + + + + + + + + + + + + + + + + +
IDTargetInterfaceDescriptionInitial stateInputExpected outputPass/Fail
RES001Fill in!Fill in!16MHz on normal operationReset init the target according to RES002 Exercise a memory access over the JTAG, for example
mdw 0x0 32		The command should run without any errors. If any JTAG checking errors happen, the test failedPASS/FAIL
+ +

Debugging

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
IDTargetInterfaceDescriptionInitial stateInputExpected outputPass/Fail
DBG001Fill in!Fill in!Load is workingReset init is working, RAM is accesible, GDB server is startedOn the console of the OS:
+ arm-elf-gdb test_ram.elf
+ (gdb) target remote ip:port
+ (gdb) load + 		Load should return without error, typical output looks like:
+ + Loading section .text, size 0x14c lma 0x0
+ Start address 0x40, load size 332
+ Transfer rate: 180 bytes/sec, 332 bytes/write.
+ + 		PASS/FAIL
DBG002Fill in!Fill in!Software breakpointLoad the test_ram.elf application, use instructions from GDB001In the GDB console:
+ + (gdb) monitor arm7_9 sw_bkpts enable
+ software breakpoints enabled
+ (gdb) break main
+ Breakpoint 1 at 0xec: file src/main.c, line 71.
+ (gdb) continue
+ Continuing. + + 		The software breakpoint should be reached, a typical output looks like:
+ + target state: halted
+ target halted in ARM state due to breakpoint, current mode: Supervisor
+ cpsr: 0x000000d3 pc: 0x000000ec
+
+ Breakpoint 1, main () at src/main.c:71
+ 71 DWORD a = 1; + + 		PASS/FAIL
DBG003Fill in!Fill in!Single step in a RAM applicationLoad the test_ram.elf application, use instructions from GDB001, break in main using the instructions from GDB002In GDB, type
(gdb) step		The next instruction should be reached, typical output:
+ + (gdb) step
+ target state: halted
+ target halted in ARM state due to single step, current mode: Abort
+ cpsr: 0x20000097 pc: 0x000000f0
+ target state: halted
+ target halted in ARM state due to single step, current mode: Abort
+ cpsr: 0x20000097 pc: 0x000000f4
+ 72 DWORD b = 2; + + 		PASS/FAIL
DBG004Fill in!Fill in!Software break points are working after a resetLoad the test_ram.elf application, use instructions from GDB001, break in main using the instructions from GDB002In GDB, type
+ (gdb) monitor reset
+ (gdb) load
+ (gdb) continue
+ 		The breakpoint should be reached, typical output:
+ + target state: halted
+ target halted in ARM state due to breakpoint, current mode: Supervisor
+ cpsr: 0x000000d3 pc: 0x000000ec
+
+ Breakpoint 1, main () at src/main.c:71
+ 71 DWORD a = 1; + + 		PASS/FAIL
DBG005Fill in!Fill in!Hardware breakpointFlash the test_rom.elf application. Make this test after FLA004 has passedBe sure that gdb_memory_map and gdb_flash_program are enabled. In GDB, type
+ + (gdb) monitor reset
+ (gdb) load
+ Loading section .text, size 0x194 lma 0x100000
+ Start address 0x100040, load size 404
+ Transfer rate: 179 bytes/sec, 404 bytes/write.
+ (gdb) monitor arm7_9 force_hw_bkpts enable
+ force hardware breakpoints enabled
+ (gdb) break main
+ Breakpoint 1 at 0x100134: file src/main.c, line 69.
+ (gdb) continue
+ + 		The breakpoint should be reached, typical output:
+ + Continuing.
+
+ Breakpoint 1, main () at src/main.c:69
+ 69 DWORD a = 1;
+ + 		PASS/FAIL
DBG006Fill in!Fill in!Hardware breakpoint is set after a resetFollow the instructions to flash and insert a hardware breakpoint from DBG005In GDB, type
+ + (gdb) monitor reset
+ (gdb) monitor reg pc 0x100000
+ pc (/32): 0x00100000
+ (gdb) continue + + 		The breakpoint should be reached, typical output:
+ + Continuing.
+
+ Breakpoint 1, main () at src/main.c:69
+ 69 DWORD a = 1;
+ + 		PASS/FAIL
DBG007Fill in!Fill in!Single step in ROMFlash the test_rom.elf application and set a breakpoint in main, use DBG005. Make this test after FLA004 has passedBe sure that gdb_memory_map and gdb_flash_program are enabled. In GDB, type
+ + (gdb) monitor reset
+ (gdb) load
+ Loading section .text, size 0x194 lma 0x100000
+ Start address 0x100040, load size 404
+ Transfer rate: 179 bytes/sec, 404 bytes/write.
+ (gdb) monitor arm7_9 force_hw_bkpts enable
+ force hardware breakpoints enabled
+ (gdb) break main
+ Breakpoint 1 at 0x100134: file src/main.c, line 69.
+ (gdb) continue
+ Continuing.
+
+ Breakpoint 1, main () at src/main.c:69
+ 69 DWORD a = 1;
+ (gdb) step + + 		The breakpoint should be reached, typical output:
+ + target state: halted
+ target halted in ARM state due to single step, current mode: Supervisor
+ cpsr: 0x60000013 pc: 0x0010013c
+ 70 DWORD b = 2;
+ + 		PASS/FAIL
+ +

RAM access

+Note: these tests are not designed to test/debug the target, but to test functionalities! + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
IDTargetInterfaceDescriptionInitial stateInputExpected outputPass/Fail
RAM001Fill in!Fill in!32 bit Write/read RAMReset init is workingOn the telnet interface
+ > mww ram_address 0xdeadbeef 16
+ > mdw ram_address 32 + + 		The commands should execute without error. A clear failure is a memory access exception. The result of running the commands should be a list of 16 locations 32bit long containing 0xdeadbeef.
+ + > mww 0x0 0xdeadbeef 16
+ > mdw 0x0 32
+ 0x00000000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
+ 0x00000020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
+ 0x00000040: e1a00000 e59fa51c e59f051c e04aa000 00080017 00009388 00009388 00009388
+ 0x00000060: 00009388 0002c2c0 0002c2c0 000094f8 000094f4 00009388 00009388 00009388
+ + 		PASS/FAIL
RAM001Fill in!Fill in!16 bit Write/read RAMReset init is workingOn the telnet interface
+ > mwh ram_address 0xbeef 16
+ > mdh ram_address 32 + + 		The commands should execute without error. A clear failure is a memory access exception. The result of running the commands should be a list of 16 locations 16bit long containing 0xbeef.
+ + > mwh 0x0 0xbeef 16
+ > mdh 0x0 32
+ 0x00000000: beef beef beef beef beef beef beef beef beef beef beef beef beef beef beef beef
+ 0x00000020: 00e0 0000 021c 0000 0240 0000 026c 0000 0288 0000 0000 0000 0388 0000 0350 0000
+ > + + 		PASS/FAIL
RAM003Fill in!Fill in!8 bit Write/read RAMReset init is workingOn the telnet interface
+ > mwb ram_address 0xab 16
+ > mdb ram_address 32 + + 		The commands should execute without error. A clear failure is a memory access exception. The result of running the commands should be a list of 16 locations 8bit long containing 0xab.
+ + > mwh 0x0 0x0 16
+ > mwb ram_address 0xab 16
+ > mdb ram_address 32
+ 0x00000000: ab ab ab ab ab ab ab ab ab ab ab ab ab ab ab ab 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+ > + + 		PASS/FAIL
+ + + +

Flash access

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
IDTargetInterfaceDescriptionInitial stateInputExpected outputPass/Fail
FLA001Fill in!Fill in!Flash probeReset init is workingOn the telnet interface:
+ > flash probe 0 + 		The command should execute without error. The output should state the name of the flash and the starting address. An example of output:
+ flash 'ecosflash' found at 0x01000000 + 		PASS/FAIL
FLA002Fill in!Fill in!flash fillwReset init is working, flash is probedOn the telnet interface
+ > flash fillw 0x1000000 0xdeadbeef 16 + + 		The commands should execute without error. The output looks like:
+ + wrote 64 bytes to 0x01000000 in 11.610000s (0.091516 kb/s) +
+ To verify the contents of the flash:
+ + > mdw 0x1000000 32
+ 0x01000000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
+ 0x01000020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
+ 0x01000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x01000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff + + 		PASS/FAIL
FLA003Fill in!Fill in!Flash eraseReset init is working, flash is probedOn the telnet interface
+ > flash erase_address 0x1000000 0x2000 + + 		The commands should execute without error.
+ + erased address 0x01000000 length 8192 in 4.970000s + + To check that the flash has been erased, read at different addresses. The result should always be 0xff. + + > mdw 0x1000000 32
+ 0x01000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x01000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x01000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x01000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff + + 		PASS/FAIL
FLA004Fill in!Fill in!Loading to flash from GDBReset init is working, flash is probed, connectivity to GDB server is workingStart GDB using a ROM elf image, eg: arm-elf-gdb test_rom.elf.
+ + (gdb) target remote ip:port
+ (gdb) monitor reset
+ (gdb) load
+ Loading section .text, size 0x194 lma 0x100000
+ Start address 0x100040, load size 404
+ Transfer rate: 179 bytes/sec, 404 bytes/write. + (gdb) monitor verify_image path_to_elf_file + + 		The output should look like:
+ + verified 404 bytes in 5.060000s +
+ The failure message is something like:
+ Verify operation failed address 0x00200000. Was 0x00 instead of 0x18 + 		PASS/FAIL
+ + \ No newline at end of file