From: Wolfgang Denk <wd@denx.de>
Date: Sun, 14 Jun 2009 18:58:46 +0000 (+0200)
Subject: mecp5123: fix build error
X-Git-Tag: v2009.08-rc1~107
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=0549353a6ba5aa03420c0962b9072e9cf1fa49d9;p=u-boot

mecp5123: fix build error

The mecp5123 board did not compile because the MSCAN Clock Control
Registers were missing; these got added, but as an array instead
of 4 individual registers. Adapt the code so it builds.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
---

diff --git a/board/esd/mecp5123/mecp5123.c b/board/esd/mecp5123/mecp5123.c
index 909b45869e..bff96db72a 100644
--- a/board/esd/mecp5123/mecp5123.c
+++ b/board/esd/mecp5123/mecp5123.c
@@ -79,6 +79,7 @@ int board_early_init_f(void)
 {
 	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 	u32 spridr;
+	int i;
 
 	/*
 	 * Initialize Local Window for NOR FLASH access
@@ -129,14 +130,10 @@ int board_early_init_f(void)
 	/*
 	 * Configure MSCAN clocks
 	 */
-	out_be32(&im->clk.m1ccr, 0x00300000);
-	out_be32(&im->clk.m2ccr, 0x00300000);
-	out_be32(&im->clk.m3ccr, 0x00300000);
-	out_be32(&im->clk.m4ccr, 0x00300000);
-	out_be32(&im->clk.m1ccr, 0x00310000);
-	out_be32(&im->clk.m2ccr, 0x00310000);
-	out_be32(&im->clk.m3ccr, 0x00310000);
-	out_be32(&im->clk.m4ccr, 0x00310000);
+	for (i=0; i<4; ++i) {
+		out_be32(&im->clk.msccr[i], 0x00300000);
+		out_be32(&im->clk.msccr[i], 0x00310000);
+	}
 
 	/*
 	 * Configure GPIO's