From: Simon Glass Date: Sat, 12 Mar 2016 05:06:55 +0000 (-0700) Subject: x86: Create a common header for Intel register access X-Git-Tag: v2016.05-rc1~296 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=06d336cca284cc767a095ce40afca79b4aa0ecb0;p=u-boot x86: Create a common header for Intel register access There are several blocks of registers that are accessed from all over the code on Intel CPUs. These don't currently have their own driver and it is not clear whether having a driver makes sense. An example is the Memory Controller Hub (MCH). We map it to a known location on some Intel chips (mostly those without FSP - Firmware Support Package). Add a new header file for these registers, and move MCH into it. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c index f0e733bc33..796771c021 100644 --- a/arch/x86/cpu/ivybridge/cpu.c +++ b/arch/x86/cpu/ivybridge/cpu.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/x86/cpu/ivybridge/gma.c b/arch/x86/cpu/ivybridge/gma.c index 91a57f9847..37e2e6ead8 100644 --- a/arch/x86/cpu/ivybridge/gma.c +++ b/arch/x86/cpu/ivybridge/gma.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/x86/cpu/ivybridge/northbridge.c b/arch/x86/cpu/ivybridge/northbridge.c index a066607a18..f7e0bc3f18 100644 --- a/arch/x86/cpu/ivybridge/northbridge.c +++ b/arch/x86/cpu/ivybridge/northbridge.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -167,8 +168,8 @@ static void sandybridge_setup_northbridge_bars(struct udevice *dev) debug("Setting up static registers\n"); dm_pci_write_config32(dev, EPBAR, DEFAULT_EPBAR | 1); dm_pci_write_config32(dev, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32); - dm_pci_write_config32(dev, MCHBAR, DEFAULT_MCHBAR | 1); - dm_pci_write_config32(dev, MCHBAR + 4, (0LL + DEFAULT_MCHBAR) >> 32); + dm_pci_write_config32(dev, MCHBAR, MCH_BASE_ADDRESS | 1); + dm_pci_write_config32(dev, MCHBAR + 4, (0LL + MCH_BASE_ADDRESS) >> 32); /* 64MB - busses 0-63 */ dm_pci_write_config32(dev, PCIEXBAR, DEFAULT_PCIEXBAR | 5); dm_pci_write_config32(dev, PCIEXBAR + 4, diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c index 0ebcc2c257..f7dd61f045 100644 --- a/arch/x86/cpu/ivybridge/sdram.c +++ b/arch/x86/cpu/ivybridge/sdram.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include #include @@ -682,7 +683,7 @@ int dram_init(void) { struct pei_data pei_data __aligned(8) = { .pei_version = PEI_VERSION, - .mchbar = DEFAULT_MCHBAR, + .mchbar = MCH_BASE_ADDRESS, .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_PCIE_ECAM_BASE, diff --git a/arch/x86/include/asm/arch-ivybridge/sandybridge.h b/arch/x86/include/asm/arch-ivybridge/sandybridge.h index d137d6786a..59b05cc72e 100644 --- a/arch/x86/include/asm/arch-ivybridge/sandybridge.h +++ b/arch/x86/include/asm/arch-ivybridge/sandybridge.h @@ -38,7 +38,6 @@ #define IED_SIZE 0x400000 /* Northbridge BARs */ -#define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */ #define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ #define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ #define DEFAULT_RCBABASE 0xfed1c000 @@ -97,8 +96,6 @@ /* * MCHBAR */ -#define MCHBAR_REG(reg) (DEFAULT_MCHBAR + (reg)) - #define SSKPD 0x5d14 /* 16bit (scratchpad) */ #define BIOS_RESET_CPL 0x5da8 /* 8bit */ diff --git a/arch/x86/include/asm/intel_regs.h b/arch/x86/include/asm/intel_regs.h new file mode 100644 index 0000000000..9725738143 --- /dev/null +++ b/arch/x86/include/asm/intel_regs.h @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2016 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __ASM_INTEL_REGS_H +#define __ASM_INTEL_REGS_H + +/* Access the memory-controller hub */ +#define MCH_BASE_ADDRESS 0xfed10000 +#define MCH_BASE_SIZE 0x8000 +#define MCHBAR_REG(reg) (MCH_BASE_ADDRESS + (reg)) + +#endif