From: lintbe Date: Wed, 12 Feb 2014 22:48:10 +0000 (+0100) Subject: Fixing ca65 for 65816 jml and jmp opcodes X-Git-Tag: V2.15~151^2~1 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=07d49f143bd0b36192c5101d8040052c6de7847f;p=cc65 Fixing ca65 for 65816 jml and jmp opcodes added a missing addressing mode for jmp/jml : Absolute Indexed Long that opcode can be written like jmp[$1234] or jml[$1234] removed Absolute Inderect addressing mode for jml since it's not a long adressing mode --- diff --git a/src/ca65/ea65.c b/src/ca65/ea65.c index 48c4a2c07..21e9073ac 100644 --- a/src/ca65/ea65.c +++ b/src/ca65/ea65.c @@ -110,7 +110,7 @@ void GetEA (EffAddr* A) A->AddrModeSet = AM65_DIR_IND_LONG_Y; } else { /* [dir] */ - A->AddrModeSet = AM65_DIR_IND_LONG; + A->AddrModeSet = AM65_DIR_IND_LONG | AM65_ABS_IND_LONG; } } else if (CurTok.Tok == TOK_LPAREN) { diff --git a/src/ca65/instr.c b/src/ca65/instr.c index 277676614..73fd83a78 100644 --- a/src/ca65/instr.c +++ b/src/ca65/instr.c @@ -516,8 +516,8 @@ static const struct { { "INC", 0x000006F, 0x00, 4, PutAll }, { "INX", 0x0000001, 0xe8, 0, PutAll }, { "INY", 0x0000001, 0xc8, 0, PutAll }, - { "JML", 0x0000810, 0x5c, 1, PutAll }, - { "JMP", 0x0010818, 0x4c, 6, PutAll }, + { "JML", 0x4000010, 0x5c, 1, PutAll }, + { "JMP", 0x4010818, 0x4c, 6, PutAll }, { "JSL", 0x0000010, 0x20, 7, PutAll }, { "JSR", 0x0010018, 0x20, 7, PutAll }, { "LDA", 0x0b8f6fc, 0xa0, 0, PutAll }, @@ -800,61 +800,61 @@ static unsigned char EATab[10][AM65I_COUNT] = { 0x00, 0x00, 0x05, 0x0D, 0x0F, 0x15, 0x1D, 0x1F, 0x00, 0x19, 0x12, 0x00, 0x07, 0x11, 0x17, 0x01, 0x00, 0x00, 0x00, 0x03, 0x13, 0x09, 0x00, 0x09, - 0x00, 0x00 + 0x00, 0x00, 0x00 }, { /* Table 1 */ 0x08, 0x08, 0x04, 0x0C, 0x00, 0x14, 0x1C, 0x00, 0x14, 0x1C, 0x00, 0x80, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00 + 0x00, 0x00, 0x70 }, { /* Table 2 */ 0x00, 0x00, 0x24, 0x2C, 0x0F, 0x34, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x89, 0x00, 0x00, - 0x00, 0x00 + 0x00, 0x00, 0x00 }, { /* Table 3 */ 0x3A, 0x3A, 0xC6, 0xCE, 0x00, 0xD6, 0xDE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00 + 0x00, 0x00, 0x00 }, { /* Table 4 */ 0x1A, 0x1A, 0xE6, 0xEE, 0x00, 0xF6, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00 + 0x00, 0x00, 0x00 }, { /* Table 5 */ 0x00, 0x00, 0x60, 0x98, 0x00, 0x70, 0x9E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00 + 0x00, 0x00, 0x00 }, { /* Table 6 */ 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, - 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00 + 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x30, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x90 }, { /* Table 7 */ 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xDC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00 + 0x00, 0x00, 0x00 }, { /* Table 8 */ 0x00, 0x40, 0x01, 0x41, 0x00, 0x09, 0x49, 0x00, 0x00, 0x00, 0x00, 0x51, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, - 0x00, 0x00 + 0x00, 0x00, 0x00 }, { /* Table 9 */ 0x00, 0x00, 0x00, 0x10, 0x00, 0x20, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00 + 0x00, 0x00, 0x00 }, }; @@ -898,6 +898,7 @@ unsigned char ExtBytes[AM65I_COUNT] = { 1, /* Immidiate byte */ 2, /* Blockmove (65816) */ 7, /* Block transfer (HuC6280) */ + 2, /* Absolute Indirect long */ }; /* Table that encodes the additional bytes for each SWEET16 instruction */ diff --git a/src/ca65/instr.h b/src/ca65/instr.h index 9a219b424..201f03802 100644 --- a/src/ca65/instr.h +++ b/src/ca65/instr.h @@ -84,6 +84,7 @@ #define AM65_IMM_IMPLICIT 0x00800000UL #define AM65_BLOCKMOVE 0x01000000UL #define AM65_BLOCKXFER 0x02000000UL +#define AM65_ABS_IND_LONG 0x04000000UL /* Bitmask for all ZP operations that have correspondent ABS ops */ #define AM65_SET_ZP (AM65_DIR | AM65_DIR_X | AM65_DIR_Y | AM65_DIR_IND | AM65_DIR_X_IND) @@ -107,7 +108,7 @@ #define AM65I_IMM_ACCU 21 #define AM65I_IMM_INDEX 22 #define AM65I_IMM_IMPLICIT 23 -#define AM65I_COUNT 26 +#define AM65I_COUNT 27