From: Sriram Dash Date: Wed, 17 Aug 2016 06:17:52 +0000 (+0530) Subject: mpc85xx: powerpc: usb: Modified the erratum A006261 according to endianness X-Git-Tag: v2016.11-rc1~32 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=08efeac55f8c828973b66f0c8607d4505a9e6ceb;p=u-boot mpc85xx: powerpc: usb: Modified the erratum A006261 according to endianness Modifies erratum implementation due to the fact that P3041, P5020, and P5040 are all big endian for the USB PHY registers, but they were specified little endian. Signed-off-by: Sriram Dash Signed-off-by: Rajesh Bhagat Reviewed-by: York Sun --- diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index ace42799f7..53b3729f98 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -114,10 +114,10 @@ void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy) setbits_be32(&usb_phy->config2, CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL); - temp = squelch_prog_rd_0_2 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0; + temp = squelch_prog_rd_0_2 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3; out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp); - temp = squelch_prog_rd_3_5 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3; + temp = squelch_prog_rd_3_5 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0; out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp); #endif }