From: Matthias Welwarsky Date: Thu, 20 Oct 2016 13:39:30 +0000 (+0200) Subject: aarch64: cleanup context restore X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=0a53bae0ea4007f171802b7d5e65499d4aa18ad0;p=openocd aarch64: cleanup context restore Remove register cache invalidation and target state changes that are handled appropriately in other functions. Change-Id: Ic903f41ddc267f4b8765ea022bd4d6da1017e21f Signed-off-by: Matthias Welwarsky --- diff --git a/src/target/aarch64.c b/src/target/aarch64.c index d7d557dd..1220004e 100644 --- a/src/target/aarch64.c +++ b/src/target/aarch64.c @@ -504,25 +504,16 @@ static int aarch64_internal_restore(struct target *target, int current, LOG_ERROR("How do I resume into Jazelle state??"); return ERROR_FAIL; } - LOG_DEBUG("resume pc = 0x%16" PRIx64, resume_pc); + LOG_DEBUG("resume pc = 0x%016" PRIx64, resume_pc); buf_set_u64(arm->pc->value, 0, 64, resume_pc); arm->pc->dirty = 1; arm->pc->valid = 1; - armv8_dpm_modeswitch(&armv8->dpm, ARM_MODE_ANY); /* called it now before restoring context because it uses cpu * register r0 for restoring system control register */ retval = aarch64_restore_system_control_reg(target); - if (retval != ERROR_OK) - return retval; - retval = aarch64_restore_context(target, handle_breakpoints); - if (retval != ERROR_OK) - return retval; - target->debug_reason = DBG_REASON_NOTHALTED; - target->state = TARGET_RUNNING; - - /* registers are now invalid */ - register_cache_invalidate(arm->core_cache); + if (retval == ERROR_OK) + retval = aarch64_restore_context(target, handle_breakpoints); return retval; }