From: Marian Balakowicz <m8@semihalf.com>
Date: Sun, 27 Nov 2005 19:15:41 +0000 (+0100)
Subject: Increase IPB and PCI clocks for O2DNT board.
X-Git-Tag: LABEL_2006_03_12_0025~64
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=0a69b26ed6fe3184cab86872589c27b076e6cb8e;p=u-boot

Increase IPB and PCI clocks for O2DNT board.
---

diff --git a/include/configs/o2dnt.h b/include/configs/o2dnt.h
index 325f654776..981651ab07 100644
--- a/include/configs/o2dnt.h
+++ b/include/configs/o2dnt.h
@@ -137,8 +137,20 @@
 /*
  * IPB Bus clocking configuration.
  */
-#undef CFG_IPBSPEED_133   		/* define for 133MHz speed */
+#define CFG_IPBSPEED_133		/* define for 133MHz speed */
+
+#if defined(CFG_IPBSPEED_133)
+/*
+ * PCI Bus clocking configuration
+ *
+ * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
+ * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
+ * been tested with a IPB Bus Clock of 66 MHz.
+ */
+#define CFG_PCISPEED_66			/* define for 66MHz speed */
+#endif
 #endif
+
 /*
  * I2C configuration
  */
@@ -263,7 +275,16 @@
 
 #define CFG_BOOTCS_START	CFG_FLASH_BASE
 #define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
-#define CFG_BOOTCS_CFG		0x00047801
+
+#ifdef CFG_PCISPEED_66
+/* 
+ * For 66 MHz PCI clock additional Wait State is needed for CS0 (flash).
+ */
+#define CFG_BOOTCS_CFG		0x00057801 /* for pci_clk = 66 MHz */
+#else
+#define CFG_BOOTCS_CFG		0x00047801 /* for pci_clk = 33 MHz */
+#endif
+
 #define CFG_CS0_START		CFG_FLASH_BASE
 #define CFG_CS0_SIZE		CFG_FLASH_SIZE