From: Michal Simek <michal.simek@xilinx.com>
Date: Tue, 14 Feb 2017 16:40:21 +0000 (+0100)
Subject: arm: zynq: Label whole PL part as fpga_full region
X-Git-Tag: v2017.09-rc2~129^2~21
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=0b180d02a30191478ec8088661049e19930253f7;p=u-boot

arm: zynq: Label whole PL part as fpga_full region

This will simplify dt overlay structure for the whole PL.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Moritz Fischer <moritz.fischer@ettus.com>
---

diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
index 34fc6e5f89..f993e19ef2 100644
--- a/arch/arm/dts/zynq-7000.dtsi
+++ b/arch/arm/dts/zynq-7000.dtsi
@@ -38,6 +38,14 @@
 		};
 	};
 
+	fpga_full: fpga-full {
+		compatible = "fpga-region";
+		fpga-mgr = <&devcfg>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+	};
+
 	pmu@f8891000 {
 		compatible = "arm,cortex-a9-pmu";
 		interrupts = <0 5 4>, <0 6 4>;