From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Tue, 24 May 2016 12:13:57 +0000 (+0900)
Subject: ARM: uniphier: disable cache in SPL of PH1-LD20
X-Git-Tag: v2016.07-rc1~171^2~6
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=0bd20207ab2d874842161cab37c213310d785b24;p=u-boot

ARM: uniphier: disable cache in SPL of PH1-LD20

The Boot ROM has enabled D-cache and MMU setting DDR memory area
as Normal Memory in its page table.  Disable D-cache and MMU
before jumping to U-Boot proper.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---

diff --git a/arch/arm/mach-uniphier/init/init-ld20.c b/arch/arm/mach-uniphier/init/init-ld20.c
index 660ad457dc..7f66053e1f 100644
--- a/arch/arm/mach-uniphier/init/init-ld20.c
+++ b/arch/arm/mach-uniphier/init/init-ld20.c
@@ -51,5 +51,7 @@ int uniphier_ld20_init(const struct uniphier_board_data *bd)
 
 	led_puts("L5");
 
+	dcache_disable();
+
 	return 0;
 }