From: Lei Wen <[leiwen@marvell.com]> Date: Tue, 1 Nov 2011 10:55:56 +0000 (+0530) Subject: pantheon: define CONFIG_SYS_CACHELINE_SIZE X-Git-Tag: v2011.12-rc1~228^2~66 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=0caac5f4155a1db6c5ce921c7f9294b6b46e7744;p=u-boot pantheon: define CONFIG_SYS_CACHELINE_SIZE By default, on Pantheon SoC DCache Lnd ICache line lengths are 32 bytes long Signed-off-by: Lei Wen --- diff --git a/arch/arm/include/asm/arch-pantheon/config.h b/arch/arm/include/asm/arch-pantheon/config.h index d10583dec4..e4fce7da92 100644 --- a/arch/arm/include/asm/arch-pantheon/config.h +++ b/arch/arm/include/asm/arch-pantheon/config.h @@ -28,6 +28,8 @@ #include #define CONFIG_ARM926EJS 1 /* Basic Architecture */ +/* default Dcache Line length for pantheon */ +#define CONFIG_SYS_CACHELINE_SIZE 32 #define CONFIG_SYS_TCLK (14745600) /* NS16550 clk config */ #define CONFIG_SYS_HZ_CLOCK (3250000) /* Timer Freq. 3.25MHZ */